]>
Commit | Line | Data |
---|---|---|
ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
5ee3c60c | 28 | #include <linux/suspend.h> |
34ee32c9 | 29 | #include <linux/acpi.h> |
ac718b69 | 30 | |
d0942473 | 31 | /* Information for net-next */ |
32 | #define NETNEXT_VERSION "08" | |
33 | ||
34 | /* Information for net */ | |
b20cb60e | 35 | #define NET_VERSION "9" |
d0942473 | 36 | |
37 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 38 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 39 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 40 | #define MODULENAME "r8152" |
41 | ||
42 | #define R8152_PHY_ID 32 | |
43 | ||
44 | #define PLA_IDR 0xc000 | |
45 | #define PLA_RCR 0xc010 | |
46 | #define PLA_RMS 0xc016 | |
47 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
48 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
49 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 50 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 51 | #define PLA_FMC 0xc0b4 |
52 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 53 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 54 | #define PLA_MAR 0xcd00 |
43779f8d | 55 | #define PLA_BACKUP 0xd000 |
ac718b69 | 56 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 57 | #define PLA_TEREDO_TIMER 0xd2cc |
58 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 59 | #define PLA_LEDSEL 0xdd90 |
60 | #define PLA_LED_FEATURE 0xdd92 | |
61 | #define PLA_PHYAR 0xde00 | |
43779f8d | 62 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 63 | #define PLA_GPHY_INTR_IMR 0xe022 |
64 | #define PLA_EEE_CR 0xe040 | |
65 | #define PLA_EEEP_CR 0xe080 | |
66 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 67 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
68 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
69 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
70 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 71 | #define PLA_TCR0 0xe610 |
72 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 73 | #define PLA_MTPS 0xe615 |
ac718b69 | 74 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 75 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 76 | #define PLA_CR 0xe813 |
77 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 78 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
79 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 80 | #define PLA_CONFIG5 0xe822 |
81 | #define PLA_PHY_PWR 0xe84c | |
82 | #define PLA_OOB_CTRL 0xe84f | |
83 | #define PLA_CPCR 0xe854 | |
84 | #define PLA_MISC_0 0xe858 | |
85 | #define PLA_MISC_1 0xe85a | |
86 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 87 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 88 | #define PLA_SFF_STS_7 0xe8de |
89 | #define PLA_PHYSTATUS 0xe908 | |
90 | #define PLA_BP_BA 0xfc26 | |
91 | #define PLA_BP_0 0xfc28 | |
92 | #define PLA_BP_1 0xfc2a | |
93 | #define PLA_BP_2 0xfc2c | |
94 | #define PLA_BP_3 0xfc2e | |
95 | #define PLA_BP_4 0xfc30 | |
96 | #define PLA_BP_5 0xfc32 | |
97 | #define PLA_BP_6 0xfc34 | |
98 | #define PLA_BP_7 0xfc36 | |
43779f8d | 99 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 100 | |
65bab84c | 101 | #define USB_USB2PHY 0xb41e |
102 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 103 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 104 | #define USB_CSR_DUMMY1 0xb464 |
105 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 106 | #define USB_DEV_STAT 0xb808 |
65bab84c | 107 | #define USB_CONNECT_TIMER 0xcbf8 |
108 | #define USB_BURST_SIZE 0xcfc0 | |
ac718b69 | 109 | #define USB_USB_CTRL 0xd406 |
110 | #define USB_PHY_CTRL 0xd408 | |
111 | #define USB_TX_AGG 0xd40a | |
112 | #define USB_RX_BUF_TH 0xd40c | |
113 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 114 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
115 | #define USB_RX_EARLY_SIZE 0xd42e | |
ac718b69 | 116 | #define USB_PM_CTRL_STATUS 0xd432 |
117 | #define USB_TX_DMA 0xd434 | |
43779f8d | 118 | #define USB_TOLERANCE 0xd490 |
119 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 120 | #define USB_BMU_RESET 0xd4b0 |
ac718b69 | 121 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 122 | #define USB_MISC_0 0xd81a |
123 | #define USB_POWER_CUT 0xd80a | |
124 | #define USB_AFE_CTRL2 0xd824 | |
125 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 126 | #define USB_BP_BA 0xfc26 |
127 | #define USB_BP_0 0xfc28 | |
128 | #define USB_BP_1 0xfc2a | |
129 | #define USB_BP_2 0xfc2c | |
130 | #define USB_BP_3 0xfc2e | |
131 | #define USB_BP_4 0xfc30 | |
132 | #define USB_BP_5 0xfc32 | |
133 | #define USB_BP_6 0xfc34 | |
134 | #define USB_BP_7 0xfc36 | |
43779f8d | 135 | #define USB_BP_EN 0xfc38 |
ac718b69 | 136 | |
137 | /* OCP Registers */ | |
138 | #define OCP_ALDPS_CONFIG 0x2010 | |
139 | #define OCP_EEE_CONFIG1 0x2080 | |
140 | #define OCP_EEE_CONFIG2 0x2092 | |
141 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 142 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 143 | #define OCP_EEE_AR 0xa41a |
144 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 145 | #define OCP_PHY_STATUS 0xa420 |
146 | #define OCP_POWER_CFG 0xa430 | |
147 | #define OCP_EEE_CFG 0xa432 | |
148 | #define OCP_SRAM_ADDR 0xa436 | |
149 | #define OCP_SRAM_DATA 0xa438 | |
150 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 151 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 152 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 153 | #define OCP_EEE_LPABLE 0xa5d2 |
2dd49e0f | 154 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
43779f8d | 155 | #define OCP_ADC_CFG 0xbc06 |
156 | ||
157 | /* SRAM Register */ | |
158 | #define SRAM_LPF_CFG 0x8012 | |
159 | #define SRAM_10M_AMP1 0x8080 | |
160 | #define SRAM_10M_AMP2 0x8082 | |
161 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 162 | |
163 | /* PLA_RCR */ | |
164 | #define RCR_AAP 0x00000001 | |
165 | #define RCR_APM 0x00000002 | |
166 | #define RCR_AM 0x00000004 | |
167 | #define RCR_AB 0x00000008 | |
168 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
169 | ||
170 | /* PLA_RXFIFO_CTRL0 */ | |
171 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
172 | #define RXFIFO_THR1_OOB 0x01800003 | |
173 | ||
174 | /* PLA_RXFIFO_CTRL1 */ | |
175 | #define RXFIFO_THR2_FULL 0x00000060 | |
176 | #define RXFIFO_THR2_HIGH 0x00000038 | |
177 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 178 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 179 | |
180 | /* PLA_RXFIFO_CTRL2 */ | |
181 | #define RXFIFO_THR3_FULL 0x00000078 | |
182 | #define RXFIFO_THR3_HIGH 0x00000048 | |
183 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 184 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 185 | |
186 | /* PLA_TXFIFO_CTRL */ | |
187 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 188 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 189 | |
65bab84c | 190 | /* PLA_DMY_REG0 */ |
191 | #define ECM_ALDPS 0x0002 | |
192 | ||
ac718b69 | 193 | /* PLA_FMC */ |
194 | #define FMC_FCR_MCU_EN 0x0001 | |
195 | ||
196 | /* PLA_EEEP_CR */ | |
197 | #define EEEP_CR_EEEP_TX 0x0002 | |
198 | ||
43779f8d | 199 | /* PLA_WDT6_CTRL */ |
200 | #define WDT6_SET_MODE 0x0010 | |
201 | ||
ac718b69 | 202 | /* PLA_TCR0 */ |
203 | #define TCR0_TX_EMPTY 0x0800 | |
204 | #define TCR0_AUTO_FIFO 0x0080 | |
205 | ||
206 | /* PLA_TCR1 */ | |
207 | #define VERSION_MASK 0x7cf0 | |
208 | ||
69b4b7a4 | 209 | /* PLA_MTPS */ |
210 | #define MTPS_JUMBO (12 * 1024 / 64) | |
211 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
212 | ||
4f1d4d54 | 213 | /* PLA_RSTTALLY */ |
214 | #define TALLY_RESET 0x0001 | |
215 | ||
ac718b69 | 216 | /* PLA_CR */ |
217 | #define CR_RST 0x10 | |
218 | #define CR_RE 0x08 | |
219 | #define CR_TE 0x04 | |
220 | ||
221 | /* PLA_CRWECR */ | |
222 | #define CRWECR_NORAML 0x00 | |
223 | #define CRWECR_CONFIG 0xc0 | |
224 | ||
225 | /* PLA_OOB_CTRL */ | |
226 | #define NOW_IS_OOB 0x80 | |
227 | #define TXFIFO_EMPTY 0x20 | |
228 | #define RXFIFO_EMPTY 0x10 | |
229 | #define LINK_LIST_READY 0x02 | |
230 | #define DIS_MCU_CLROOB 0x01 | |
231 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
232 | ||
233 | /* PLA_MISC_1 */ | |
234 | #define RXDY_GATED_EN 0x0008 | |
235 | ||
236 | /* PLA_SFF_STS_7 */ | |
237 | #define RE_INIT_LL 0x8000 | |
238 | #define MCU_BORW_EN 0x4000 | |
239 | ||
240 | /* PLA_CPCR */ | |
241 | #define CPCR_RX_VLAN 0x0040 | |
242 | ||
243 | /* PLA_CFG_WOL */ | |
244 | #define MAGIC_EN 0x0001 | |
245 | ||
43779f8d | 246 | /* PLA_TEREDO_CFG */ |
247 | #define TEREDO_SEL 0x8000 | |
248 | #define TEREDO_WAKE_MASK 0x7f00 | |
249 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
250 | #define OOB_TEREDO_EN 0x0001 | |
251 | ||
ac718b69 | 252 | /* PAL_BDC_CR */ |
253 | #define ALDPS_PROXY_MODE 0x0001 | |
254 | ||
21ff2e89 | 255 | /* PLA_CONFIG34 */ |
256 | #define LINK_ON_WAKE_EN 0x0010 | |
257 | #define LINK_OFF_WAKE_EN 0x0008 | |
258 | ||
ac718b69 | 259 | /* PLA_CONFIG5 */ |
21ff2e89 | 260 | #define BWF_EN 0x0040 |
261 | #define MWF_EN 0x0020 | |
262 | #define UWF_EN 0x0010 | |
ac718b69 | 263 | #define LAN_WAKE_EN 0x0002 |
264 | ||
265 | /* PLA_LED_FEATURE */ | |
266 | #define LED_MODE_MASK 0x0700 | |
267 | ||
268 | /* PLA_PHY_PWR */ | |
269 | #define TX_10M_IDLE_EN 0x0080 | |
270 | #define PFM_PWM_SWITCH 0x0040 | |
271 | ||
272 | /* PLA_MAC_PWR_CTRL */ | |
273 | #define D3_CLK_GATED_EN 0x00004000 | |
274 | #define MCU_CLK_RATIO 0x07010f07 | |
275 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 276 | #define ALDPS_SPDWN_RATIO 0x0f87 |
277 | ||
278 | /* PLA_MAC_PWR_CTRL2 */ | |
279 | #define EEE_SPDWN_RATIO 0x8007 | |
280 | ||
281 | /* PLA_MAC_PWR_CTRL3 */ | |
282 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
283 | #define SUSPEND_SPDWN_EN 0x0004 | |
284 | #define U1U2_SPDWN_EN 0x0002 | |
285 | #define L1_SPDWN_EN 0x0001 | |
286 | ||
287 | /* PLA_MAC_PWR_CTRL4 */ | |
288 | #define PWRSAVE_SPDWN_EN 0x1000 | |
289 | #define RXDV_SPDWN_EN 0x0800 | |
290 | #define TX10MIDLE_EN 0x0100 | |
291 | #define TP100_SPDWN_EN 0x0020 | |
292 | #define TP500_SPDWN_EN 0x0010 | |
293 | #define TP1000_SPDWN_EN 0x0008 | |
294 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 295 | |
296 | /* PLA_GPHY_INTR_IMR */ | |
297 | #define GPHY_STS_MSK 0x0001 | |
298 | #define SPEED_DOWN_MSK 0x0002 | |
299 | #define SPDWN_RXDV_MSK 0x0004 | |
300 | #define SPDWN_LINKCHG_MSK 0x0008 | |
301 | ||
302 | /* PLA_PHYAR */ | |
303 | #define PHYAR_FLAG 0x80000000 | |
304 | ||
305 | /* PLA_EEE_CR */ | |
306 | #define EEE_RX_EN 0x0001 | |
307 | #define EEE_TX_EN 0x0002 | |
308 | ||
43779f8d | 309 | /* PLA_BOOT_CTRL */ |
310 | #define AUTOLOAD_DONE 0x0002 | |
311 | ||
65bab84c | 312 | /* USB_USB2PHY */ |
313 | #define USB2PHY_SUSPEND 0x0001 | |
314 | #define USB2PHY_L1 0x0002 | |
315 | ||
316 | /* USB_SSPHYLINK2 */ | |
317 | #define pwd_dn_scale_mask 0x3ffe | |
318 | #define pwd_dn_scale(x) ((x) << 1) | |
319 | ||
320 | /* USB_CSR_DUMMY1 */ | |
321 | #define DYNAMIC_BURST 0x0001 | |
322 | ||
323 | /* USB_CSR_DUMMY2 */ | |
324 | #define EP4_FULL_FC 0x0001 | |
325 | ||
ac718b69 | 326 | /* USB_DEV_STAT */ |
327 | #define STAT_SPEED_MASK 0x0006 | |
328 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 329 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 330 | |
331 | /* USB_TX_AGG */ | |
332 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
333 | ||
334 | /* USB_RX_BUF_TH */ | |
43779f8d | 335 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 336 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 337 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 338 | |
339 | /* USB_TX_DMA */ | |
340 | #define TEST_MODE_DISABLE 0x00000001 | |
341 | #define TX_SIZE_ADJUST1 0x00000100 | |
342 | ||
93fe9b18 | 343 | /* USB_BMU_RESET */ |
344 | #define BMU_RESET_EP_IN 0x01 | |
345 | #define BMU_RESET_EP_OUT 0x02 | |
346 | ||
ac718b69 | 347 | /* USB_UPS_CTRL */ |
348 | #define POWER_CUT 0x0100 | |
349 | ||
350 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 351 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 352 | |
353 | /* USB_USB_CTRL */ | |
354 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 355 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 356 | |
43779f8d | 357 | /* USB_U2P3_CTRL */ |
358 | #define U2P3_ENABLE 0x0001 | |
359 | ||
360 | /* USB_POWER_CUT */ | |
361 | #define PWR_EN 0x0001 | |
362 | #define PHASE2_EN 0x0008 | |
363 | ||
364 | /* USB_MISC_0 */ | |
365 | #define PCUT_STATUS 0x0001 | |
366 | ||
464ec10a | 367 | /* USB_RX_EARLY_TIMEOUT */ |
368 | #define COALESCE_SUPER 85000U | |
369 | #define COALESCE_HIGH 250000U | |
370 | #define COALESCE_SLOW 524280U | |
43779f8d | 371 | |
372 | /* USB_WDT11_CTRL */ | |
373 | #define TIMER11_EN 0x0001 | |
374 | ||
375 | /* USB_LPM_CTRL */ | |
65bab84c | 376 | /* bit 4 ~ 5: fifo empty boundary */ |
377 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
378 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 379 | #define LPM_TIMER_MASK 0x0c |
380 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
381 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 382 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 383 | |
384 | /* USB_AFE_CTRL2 */ | |
385 | #define SEN_VAL_MASK 0xf800 | |
386 | #define SEN_VAL_NORMAL 0xa000 | |
387 | #define SEL_RXIDLE 0x0100 | |
388 | ||
ac718b69 | 389 | /* OCP_ALDPS_CONFIG */ |
390 | #define ENPWRSAVE 0x8000 | |
391 | #define ENPDNPS 0x0200 | |
392 | #define LINKENA 0x0100 | |
393 | #define DIS_SDSAVE 0x0010 | |
394 | ||
43779f8d | 395 | /* OCP_PHY_STATUS */ |
396 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 397 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 398 | #define PHY_STAT_LAN_ON 3 |
399 | #define PHY_STAT_PWRDN 5 | |
400 | ||
401 | /* OCP_POWER_CFG */ | |
402 | #define EEE_CLKDIV_EN 0x8000 | |
403 | #define EN_ALDPS 0x0004 | |
404 | #define EN_10M_PLLOFF 0x0001 | |
405 | ||
ac718b69 | 406 | /* OCP_EEE_CONFIG1 */ |
407 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
408 | #define RG_MATCLR_EN 0x4000 | |
409 | #define EEE_10_CAP 0x2000 | |
410 | #define EEE_NWAY_EN 0x1000 | |
411 | #define TX_QUIET_EN 0x0200 | |
412 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 413 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 414 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 415 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
416 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
417 | ||
418 | /* OCP_EEE_CONFIG2 */ | |
419 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
420 | #define RG_DACQUIET_EN 0x0400 | |
421 | #define RG_LDVQUIET_EN 0x0200 | |
422 | #define RG_CKRSEL 0x0020 | |
423 | #define RG_EEEPRG_EN 0x0010 | |
424 | ||
425 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 426 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 427 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 428 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
429 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
430 | ||
431 | /* OCP_EEE_AR */ | |
432 | /* bit[15:14] function */ | |
433 | #define FUN_ADDR 0x0000 | |
434 | #define FUN_DATA 0x4000 | |
435 | /* bit[4:0] device addr */ | |
ac718b69 | 436 | |
43779f8d | 437 | /* OCP_EEE_CFG */ |
438 | #define CTAP_SHORT_EN 0x0040 | |
439 | #define EEE10_EN 0x0010 | |
440 | ||
441 | /* OCP_DOWN_SPEED */ | |
442 | #define EN_10M_BGOFF 0x0080 | |
443 | ||
2dd49e0f | 444 | /* OCP_PHY_STATE */ |
445 | #define TXDIS_STATE 0x01 | |
446 | #define ABD_STATE 0x02 | |
447 | ||
43779f8d | 448 | /* OCP_ADC_CFG */ |
449 | #define CKADSEL_L 0x0100 | |
450 | #define ADC_EN 0x0080 | |
451 | #define EN_EMI_L 0x0040 | |
452 | ||
453 | /* SRAM_LPF_CFG */ | |
454 | #define LPF_AUTO_TUNE 0x8000 | |
455 | ||
456 | /* SRAM_10M_AMP1 */ | |
457 | #define GDAC_IB_UPALL 0x0008 | |
458 | ||
459 | /* SRAM_10M_AMP2 */ | |
460 | #define AMP_DN 0x0200 | |
461 | ||
462 | /* SRAM_IMPEDANCE */ | |
463 | #define RX_DRIVING_MASK 0x6000 | |
464 | ||
34ee32c9 ML |
465 | /* MAC PASSTHRU */ |
466 | #define AD_MASK 0xfee0 | |
467 | #define EFUSE 0xcfdb | |
468 | #define PASS_THRU_MASK 0x1 | |
469 | ||
ac718b69 | 470 | enum rtl_register_content { |
43779f8d | 471 | _1000bps = 0x10, |
ac718b69 | 472 | _100bps = 0x08, |
473 | _10bps = 0x04, | |
474 | LINK_STATUS = 0x02, | |
475 | FULL_DUP = 0x01, | |
476 | }; | |
477 | ||
1764bcd9 | 478 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 479 | #define RTL8152_MAX_RX 10 |
40a82917 | 480 | #define INTBUFSIZE 2 |
8e1f51bd | 481 | #define CRC_SIZE 4 |
482 | #define TX_ALIGN 4 | |
483 | #define RX_ALIGN 8 | |
40a82917 | 484 | |
485 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 486 | |
ac718b69 | 487 | #define RTL8152_REQT_READ 0xc0 |
488 | #define RTL8152_REQT_WRITE 0x40 | |
489 | #define RTL8152_REQ_GET_REGS 0x05 | |
490 | #define RTL8152_REQ_SET_REGS 0x05 | |
491 | ||
492 | #define BYTE_EN_DWORD 0xff | |
493 | #define BYTE_EN_WORD 0x33 | |
494 | #define BYTE_EN_BYTE 0x11 | |
495 | #define BYTE_EN_SIX_BYTES 0x3f | |
496 | #define BYTE_EN_START_MASK 0x0f | |
497 | #define BYTE_EN_END_MASK 0xf0 | |
498 | ||
69b4b7a4 | 499 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
500 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 501 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 502 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 503 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 504 | #define RTL8152_NAPI_WEIGHT 64 |
b20cb60e | 505 | #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \ |
506 | sizeof(struct rx_desc) + RX_ALIGN) | |
ac718b69 | 507 | |
508 | /* rtl8152 flags */ | |
509 | enum rtl8152_flags { | |
510 | RTL8152_UNPLUG = 0, | |
ac718b69 | 511 | RTL8152_SET_RX_MODE, |
40a82917 | 512 | WORK_ENABLE, |
513 | RTL8152_LINK_CHG, | |
9a4be1bd | 514 | SELECTIVE_SUSPEND, |
aa66a5f1 | 515 | PHY_RESET, |
d823ab68 | 516 | SCHEDULE_NAPI, |
ac718b69 | 517 | }; |
518 | ||
519 | /* Define these values to match your device */ | |
520 | #define VENDOR_ID_REALTEK 0x0bda | |
d5b07ccc | 521 | #define VENDOR_ID_MICROSOFT 0x045e |
43779f8d | 522 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 523 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 524 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 525 | |
526 | #define MCU_TYPE_PLA 0x0100 | |
527 | #define MCU_TYPE_USB 0x0000 | |
528 | ||
4f1d4d54 | 529 | struct tally_counter { |
530 | __le64 tx_packets; | |
531 | __le64 rx_packets; | |
532 | __le64 tx_errors; | |
533 | __le32 rx_errors; | |
534 | __le16 rx_missed; | |
535 | __le16 align_errors; | |
536 | __le32 tx_one_collision; | |
537 | __le32 tx_multi_collision; | |
538 | __le64 rx_unicast; | |
539 | __le64 rx_broadcast; | |
540 | __le32 rx_multicast; | |
541 | __le16 tx_aborted; | |
f37119c5 | 542 | __le16 tx_underrun; |
4f1d4d54 | 543 | }; |
544 | ||
ac718b69 | 545 | struct rx_desc { |
500b6d7e | 546 | __le32 opts1; |
ac718b69 | 547 | #define RX_LEN_MASK 0x7fff |
565cab0a | 548 | |
500b6d7e | 549 | __le32 opts2; |
f5aaaa6d | 550 | #define RD_UDP_CS BIT(23) |
551 | #define RD_TCP_CS BIT(22) | |
552 | #define RD_IPV6_CS BIT(20) | |
553 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 554 | |
500b6d7e | 555 | __le32 opts3; |
f5aaaa6d | 556 | #define IPF BIT(23) /* IP checksum fail */ |
557 | #define UDPF BIT(22) /* UDP checksum fail */ | |
558 | #define TCPF BIT(21) /* TCP checksum fail */ | |
559 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 560 | |
500b6d7e | 561 | __le32 opts4; |
562 | __le32 opts5; | |
563 | __le32 opts6; | |
ac718b69 | 564 | }; |
565 | ||
566 | struct tx_desc { | |
500b6d7e | 567 | __le32 opts1; |
f5aaaa6d | 568 | #define TX_FS BIT(31) /* First segment of a packet */ |
569 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
570 | #define GTSENDV4 BIT(28) | |
571 | #define GTSENDV6 BIT(27) | |
60c89071 | 572 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 573 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 574 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 575 | |
500b6d7e | 576 | __le32 opts2; |
f5aaaa6d | 577 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
578 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
579 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
580 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 581 | #define MSS_SHIFT 17 |
582 | #define MSS_MAX 0x7ffU | |
583 | #define TCPHO_SHIFT 17 | |
6128d1bb | 584 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 585 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 586 | }; |
587 | ||
dff4e8ad | 588 | struct r8152; |
589 | ||
ebc2ec48 | 590 | struct rx_agg { |
591 | struct list_head list; | |
592 | struct urb *urb; | |
dff4e8ad | 593 | struct r8152 *context; |
ebc2ec48 | 594 | void *buffer; |
595 | void *head; | |
596 | }; | |
597 | ||
598 | struct tx_agg { | |
599 | struct list_head list; | |
600 | struct urb *urb; | |
dff4e8ad | 601 | struct r8152 *context; |
ebc2ec48 | 602 | void *buffer; |
603 | void *head; | |
604 | u32 skb_num; | |
605 | u32 skb_len; | |
606 | }; | |
607 | ||
ac718b69 | 608 | struct r8152 { |
609 | unsigned long flags; | |
610 | struct usb_device *udev; | |
d823ab68 | 611 | struct napi_struct napi; |
40a82917 | 612 | struct usb_interface *intf; |
ac718b69 | 613 | struct net_device *netdev; |
40a82917 | 614 | struct urb *intr_urb; |
ebc2ec48 | 615 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
616 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
617 | struct list_head rx_done, tx_free; | |
d823ab68 | 618 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 619 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 620 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 621 | struct mii_if_info mii; |
b5403273 | 622 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 623 | #ifdef CONFIG_PM_SLEEP |
624 | struct notifier_block pm_notifier; | |
625 | #endif | |
c81229c9 | 626 | |
627 | struct rtl_ops { | |
628 | void (*init)(struct r8152 *); | |
629 | int (*enable)(struct r8152 *); | |
630 | void (*disable)(struct r8152 *); | |
7e9da481 | 631 | void (*up)(struct r8152 *); |
c81229c9 | 632 | void (*down)(struct r8152 *); |
633 | void (*unload)(struct r8152 *); | |
df35d283 | 634 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
635 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
2dd49e0f | 636 | bool (*in_nway)(struct r8152 *); |
a028a9e0 | 637 | void (*hw_phy_cfg)(struct r8152 *); |
2609af19 | 638 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
c81229c9 | 639 | } rtl_ops; |
640 | ||
40a82917 | 641 | int intr_interval; |
21ff2e89 | 642 | u32 saved_wolopts; |
ac718b69 | 643 | u32 msg_enable; |
dd1b119c | 644 | u32 tx_qlen; |
464ec10a | 645 | u32 coalesce; |
ac718b69 | 646 | u16 ocp_base; |
aa7e26b6 | 647 | u16 speed; |
40a82917 | 648 | u8 *intr_buff; |
ac718b69 | 649 | u8 version; |
aa7e26b6 | 650 | u8 duplex; |
651 | u8 autoneg; | |
ac718b69 | 652 | }; |
653 | ||
654 | enum rtl_version { | |
655 | RTL_VER_UNKNOWN = 0, | |
656 | RTL_VER_01, | |
43779f8d | 657 | RTL_VER_02, |
658 | RTL_VER_03, | |
659 | RTL_VER_04, | |
660 | RTL_VER_05, | |
fb02eb4a | 661 | RTL_VER_06, |
c27b32c2 | 662 | RTL_VER_07, |
43779f8d | 663 | RTL_VER_MAX |
ac718b69 | 664 | }; |
665 | ||
60c89071 | 666 | enum tx_csum_stat { |
667 | TX_CSUM_SUCCESS = 0, | |
668 | TX_CSUM_TSO, | |
669 | TX_CSUM_NONE | |
670 | }; | |
671 | ||
ac718b69 | 672 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
673 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
674 | */ | |
675 | static const int multicast_filter_limit = 32; | |
52aec126 | 676 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 677 | |
52aec126 | 678 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 679 | VLAN_ETH_HLEN - VLAN_HLEN) |
680 | ||
ac718b69 | 681 | static |
682 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
683 | { | |
31787f53 | 684 | int ret; |
685 | void *tmp; | |
686 | ||
687 | tmp = kmalloc(size, GFP_KERNEL); | |
688 | if (!tmp) | |
689 | return -ENOMEM; | |
690 | ||
691 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 692 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
693 | value, index, tmp, size, 500); | |
31787f53 | 694 | |
695 | memcpy(data, tmp, size); | |
696 | kfree(tmp); | |
697 | ||
698 | return ret; | |
ac718b69 | 699 | } |
700 | ||
701 | static | |
702 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
703 | { | |
31787f53 | 704 | int ret; |
705 | void *tmp; | |
706 | ||
c4438f03 | 707 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 708 | if (!tmp) |
709 | return -ENOMEM; | |
710 | ||
31787f53 | 711 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 712 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
713 | value, index, tmp, size, 500); | |
31787f53 | 714 | |
715 | kfree(tmp); | |
db8515ef | 716 | |
31787f53 | 717 | return ret; |
ac718b69 | 718 | } |
719 | ||
720 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 721 | void *data, u16 type) |
ac718b69 | 722 | { |
45f4a19f | 723 | u16 limit = 64; |
724 | int ret = 0; | |
ac718b69 | 725 | |
726 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
727 | return -ENODEV; | |
728 | ||
729 | /* both size and indix must be 4 bytes align */ | |
730 | if ((size & 3) || !size || (index & 3) || !data) | |
731 | return -EPERM; | |
732 | ||
733 | if ((u32)index + (u32)size > 0xffff) | |
734 | return -EPERM; | |
735 | ||
736 | while (size) { | |
737 | if (size > limit) { | |
738 | ret = get_registers(tp, index, type, limit, data); | |
739 | if (ret < 0) | |
740 | break; | |
741 | ||
742 | index += limit; | |
743 | data += limit; | |
744 | size -= limit; | |
745 | } else { | |
746 | ret = get_registers(tp, index, type, size, data); | |
747 | if (ret < 0) | |
748 | break; | |
749 | ||
750 | index += size; | |
751 | data += size; | |
752 | size = 0; | |
753 | break; | |
754 | } | |
755 | } | |
756 | ||
67610496 | 757 | if (ret == -ENODEV) |
758 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
759 | ||
ac718b69 | 760 | return ret; |
761 | } | |
762 | ||
763 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 764 | u16 size, void *data, u16 type) |
ac718b69 | 765 | { |
45f4a19f | 766 | int ret; |
767 | u16 byteen_start, byteen_end, byen; | |
768 | u16 limit = 512; | |
ac718b69 | 769 | |
770 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
771 | return -ENODEV; | |
772 | ||
773 | /* both size and indix must be 4 bytes align */ | |
774 | if ((size & 3) || !size || (index & 3) || !data) | |
775 | return -EPERM; | |
776 | ||
777 | if ((u32)index + (u32)size > 0xffff) | |
778 | return -EPERM; | |
779 | ||
780 | byteen_start = byteen & BYTE_EN_START_MASK; | |
781 | byteen_end = byteen & BYTE_EN_END_MASK; | |
782 | ||
783 | byen = byteen_start | (byteen_start << 4); | |
784 | ret = set_registers(tp, index, type | byen, 4, data); | |
785 | if (ret < 0) | |
786 | goto error1; | |
787 | ||
788 | index += 4; | |
789 | data += 4; | |
790 | size -= 4; | |
791 | ||
792 | if (size) { | |
793 | size -= 4; | |
794 | ||
795 | while (size) { | |
796 | if (size > limit) { | |
797 | ret = set_registers(tp, index, | |
b209af99 | 798 | type | BYTE_EN_DWORD, |
799 | limit, data); | |
ac718b69 | 800 | if (ret < 0) |
801 | goto error1; | |
802 | ||
803 | index += limit; | |
804 | data += limit; | |
805 | size -= limit; | |
806 | } else { | |
807 | ret = set_registers(tp, index, | |
b209af99 | 808 | type | BYTE_EN_DWORD, |
809 | size, data); | |
ac718b69 | 810 | if (ret < 0) |
811 | goto error1; | |
812 | ||
813 | index += size; | |
814 | data += size; | |
815 | size = 0; | |
816 | break; | |
817 | } | |
818 | } | |
819 | ||
820 | byen = byteen_end | (byteen_end >> 4); | |
821 | ret = set_registers(tp, index, type | byen, 4, data); | |
822 | if (ret < 0) | |
823 | goto error1; | |
824 | } | |
825 | ||
826 | error1: | |
67610496 | 827 | if (ret == -ENODEV) |
828 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
829 | ||
ac718b69 | 830 | return ret; |
831 | } | |
832 | ||
833 | static inline | |
834 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
835 | { | |
836 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
837 | } | |
838 | ||
839 | static inline | |
840 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
841 | { | |
842 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
843 | } | |
844 | ||
ac718b69 | 845 | static inline |
846 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
847 | { | |
848 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
849 | } | |
850 | ||
851 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
852 | { | |
c8826de8 | 853 | __le32 data; |
ac718b69 | 854 | |
c8826de8 | 855 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 856 | |
857 | return __le32_to_cpu(data); | |
858 | } | |
859 | ||
860 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
861 | { | |
c8826de8 | 862 | __le32 tmp = __cpu_to_le32(data); |
863 | ||
864 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 865 | } |
866 | ||
867 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
868 | { | |
869 | u32 data; | |
c8826de8 | 870 | __le32 tmp; |
ac718b69 | 871 | u8 shift = index & 2; |
872 | ||
873 | index &= ~3; | |
874 | ||
c8826de8 | 875 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 876 | |
c8826de8 | 877 | data = __le32_to_cpu(tmp); |
ac718b69 | 878 | data >>= (shift * 8); |
879 | data &= 0xffff; | |
880 | ||
881 | return (u16)data; | |
882 | } | |
883 | ||
884 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
885 | { | |
c8826de8 | 886 | u32 mask = 0xffff; |
887 | __le32 tmp; | |
ac718b69 | 888 | u16 byen = BYTE_EN_WORD; |
889 | u8 shift = index & 2; | |
890 | ||
891 | data &= mask; | |
892 | ||
893 | if (index & 2) { | |
894 | byen <<= shift; | |
895 | mask <<= (shift * 8); | |
896 | data <<= (shift * 8); | |
897 | index &= ~3; | |
898 | } | |
899 | ||
c8826de8 | 900 | tmp = __cpu_to_le32(data); |
ac718b69 | 901 | |
c8826de8 | 902 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 903 | } |
904 | ||
905 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
906 | { | |
907 | u32 data; | |
c8826de8 | 908 | __le32 tmp; |
ac718b69 | 909 | u8 shift = index & 3; |
910 | ||
911 | index &= ~3; | |
912 | ||
c8826de8 | 913 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 914 | |
c8826de8 | 915 | data = __le32_to_cpu(tmp); |
ac718b69 | 916 | data >>= (shift * 8); |
917 | data &= 0xff; | |
918 | ||
919 | return (u8)data; | |
920 | } | |
921 | ||
922 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
923 | { | |
c8826de8 | 924 | u32 mask = 0xff; |
925 | __le32 tmp; | |
ac718b69 | 926 | u16 byen = BYTE_EN_BYTE; |
927 | u8 shift = index & 3; | |
928 | ||
929 | data &= mask; | |
930 | ||
931 | if (index & 3) { | |
932 | byen <<= shift; | |
933 | mask <<= (shift * 8); | |
934 | data <<= (shift * 8); | |
935 | index &= ~3; | |
936 | } | |
937 | ||
c8826de8 | 938 | tmp = __cpu_to_le32(data); |
ac718b69 | 939 | |
c8826de8 | 940 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 941 | } |
942 | ||
ac244d3e | 943 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 944 | { |
945 | u16 ocp_base, ocp_index; | |
946 | ||
947 | ocp_base = addr & 0xf000; | |
948 | if (ocp_base != tp->ocp_base) { | |
949 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
950 | tp->ocp_base = ocp_base; | |
951 | } | |
952 | ||
953 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 954 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 955 | } |
956 | ||
ac244d3e | 957 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 958 | { |
ac244d3e | 959 | u16 ocp_base, ocp_index; |
ac718b69 | 960 | |
ac244d3e | 961 | ocp_base = addr & 0xf000; |
962 | if (ocp_base != tp->ocp_base) { | |
963 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
964 | tp->ocp_base = ocp_base; | |
ac718b69 | 965 | } |
ac244d3e | 966 | |
967 | ocp_index = (addr & 0x0fff) | 0xb000; | |
968 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 969 | } |
970 | ||
ac244d3e | 971 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 972 | { |
ac244d3e | 973 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
974 | } | |
ac718b69 | 975 | |
ac244d3e | 976 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
977 | { | |
978 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 979 | } |
980 | ||
43779f8d | 981 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
982 | { | |
983 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
984 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
985 | } | |
986 | ||
ac718b69 | 987 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
988 | { | |
989 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 990 | int ret; |
ac718b69 | 991 | |
6871438c | 992 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
993 | return -ENODEV; | |
994 | ||
ac718b69 | 995 | if (phy_id != R8152_PHY_ID) |
996 | return -EINVAL; | |
997 | ||
9a4be1bd | 998 | ret = r8152_mdio_read(tp, reg); |
999 | ||
9a4be1bd | 1000 | return ret; |
ac718b69 | 1001 | } |
1002 | ||
1003 | static | |
1004 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1005 | { | |
1006 | struct r8152 *tp = netdev_priv(netdev); | |
1007 | ||
6871438c | 1008 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1009 | return; | |
1010 | ||
ac718b69 | 1011 | if (phy_id != R8152_PHY_ID) |
1012 | return; | |
1013 | ||
1014 | r8152_mdio_write(tp, reg, val); | |
1015 | } | |
1016 | ||
b209af99 | 1017 | static int |
1018 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1019 | |
8ba789ab | 1020 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1021 | { | |
1022 | struct r8152 *tp = netdev_priv(netdev); | |
1023 | struct sockaddr *addr = p; | |
ea6a7112 | 1024 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1025 | |
1026 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1027 | goto out1; |
1028 | ||
1029 | ret = usb_autopm_get_interface(tp->intf); | |
1030 | if (ret < 0) | |
1031 | goto out1; | |
8ba789ab | 1032 | |
b5403273 | 1033 | mutex_lock(&tp->control); |
1034 | ||
8ba789ab | 1035 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1036 | ||
1037 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1038 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1039 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1040 | ||
b5403273 | 1041 | mutex_unlock(&tp->control); |
1042 | ||
ea6a7112 | 1043 | usb_autopm_put_interface(tp->intf); |
1044 | out1: | |
1045 | return ret; | |
8ba789ab | 1046 | } |
1047 | ||
34ee32c9 ML |
1048 | /* Devices containing RTL8153-AD can support a persistent |
1049 | * host system provided MAC address. | |
1050 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1051 | */ | |
1052 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1053 | { | |
1054 | acpi_status status; | |
1055 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1056 | union acpi_object *obj; | |
1057 | int ret = -EINVAL; | |
1058 | u32 ocp_data; | |
1059 | unsigned char buf[6]; | |
1060 | ||
1061 | /* test for -AD variant of RTL8153 */ | |
1062 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1063 | if ((ocp_data & AD_MASK) != 0x1000) | |
1064 | return -ENODEV; | |
1065 | ||
1066 | /* test for MAC address pass-through bit */ | |
1067 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1068 | if ((ocp_data & PASS_THRU_MASK) != 1) | |
1069 | return -ENODEV; | |
1070 | ||
1071 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
1072 | status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); | |
1073 | obj = (union acpi_object *)buffer.pointer; | |
1074 | if (!ACPI_SUCCESS(status)) | |
1075 | return -ENODEV; | |
1076 | if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { | |
1077 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1078 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1079 | obj->type, obj->string.length); |
1080 | goto amacout; | |
1081 | } | |
1082 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || | |
1083 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1084 | netif_warn(tp, probe, tp->netdev, | |
1085 | "Invalid header when reading pass-thru MAC addr\n"); | |
1086 | goto amacout; | |
1087 | } | |
1088 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1089 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1090 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1091 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1092 | ret, buf); | |
34ee32c9 ML |
1093 | ret = -EINVAL; |
1094 | goto amacout; | |
1095 | } | |
1096 | memcpy(sa->sa_data, buf, 6); | |
1097 | ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); | |
1098 | netif_info(tp, probe, tp->netdev, | |
1099 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1100 | ||
1101 | amacout: | |
1102 | kfree(obj); | |
1103 | return ret; | |
1104 | } | |
1105 | ||
179bb6d7 | 1106 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1107 | { |
1108 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1109 | struct sockaddr sa; |
8a91c824 | 1110 | int ret; |
ac718b69 | 1111 | |
53700f0c | 1112 | if (tp->version == RTL_VER_01) { |
179bb6d7 | 1113 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
53700f0c | 1114 | } else { |
34ee32c9 ML |
1115 | /* if this is not an RTL8153-AD, no eFuse mac pass thru set, |
1116 | * or system doesn't provide valid _SB.AMAC this will be | |
1117 | * be expected to non-zero | |
1118 | */ | |
1119 | ret = vendor_mac_passthru_addr_read(tp, &sa); | |
1120 | if (ret < 0) | |
1121 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); | |
1122 | } | |
8a91c824 | 1123 | |
1124 | if (ret < 0) { | |
179bb6d7 | 1125 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1126 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1127 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1128 | sa.sa_data); | |
1129 | eth_hw_addr_random(dev); | |
1130 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1131 | ret = rtl8152_set_mac_address(dev, &sa); | |
1132 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1133 | sa.sa_data); | |
8a91c824 | 1134 | } else { |
179bb6d7 | 1135 | if (tp->version == RTL_VER_01) |
1136 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1137 | else | |
1138 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1139 | } |
179bb6d7 | 1140 | |
1141 | return ret; | |
ac718b69 | 1142 | } |
1143 | ||
ac718b69 | 1144 | static void read_bulk_callback(struct urb *urb) |
1145 | { | |
ac718b69 | 1146 | struct net_device *netdev; |
ac718b69 | 1147 | int status = urb->status; |
ebc2ec48 | 1148 | struct rx_agg *agg; |
1149 | struct r8152 *tp; | |
ac718b69 | 1150 | |
ebc2ec48 | 1151 | agg = urb->context; |
1152 | if (!agg) | |
1153 | return; | |
1154 | ||
1155 | tp = agg->context; | |
ac718b69 | 1156 | if (!tp) |
1157 | return; | |
ebc2ec48 | 1158 | |
ac718b69 | 1159 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1160 | return; | |
ebc2ec48 | 1161 | |
1162 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1163 | return; | |
1164 | ||
ac718b69 | 1165 | netdev = tp->netdev; |
7559fb2f | 1166 | |
1167 | /* When link down, the driver would cancel all bulks. */ | |
1168 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1169 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1170 | return; |
1171 | ||
9a4be1bd | 1172 | usb_mark_last_busy(tp->udev); |
1173 | ||
ac718b69 | 1174 | switch (status) { |
1175 | case 0: | |
ebc2ec48 | 1176 | if (urb->actual_length < ETH_ZLEN) |
1177 | break; | |
1178 | ||
2685d410 | 1179 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1180 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1181 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1182 | napi_schedule(&tp->napi); |
ebc2ec48 | 1183 | return; |
ac718b69 | 1184 | case -ESHUTDOWN: |
1185 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1186 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1187 | return; |
ac718b69 | 1188 | case -ENOENT: |
1189 | return; /* the urb is in unlink state */ | |
1190 | case -ETIME: | |
4a8deae2 HW |
1191 | if (net_ratelimit()) |
1192 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1193 | break; |
ac718b69 | 1194 | default: |
4a8deae2 HW |
1195 | if (net_ratelimit()) |
1196 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1197 | break; |
ac718b69 | 1198 | } |
1199 | ||
a0fccd48 | 1200 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1201 | } |
1202 | ||
ebc2ec48 | 1203 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1204 | { |
ebc2ec48 | 1205 | struct net_device_stats *stats; |
d104eafa | 1206 | struct net_device *netdev; |
ebc2ec48 | 1207 | struct tx_agg *agg; |
ac718b69 | 1208 | struct r8152 *tp; |
ebc2ec48 | 1209 | int status = urb->status; |
ac718b69 | 1210 | |
ebc2ec48 | 1211 | agg = urb->context; |
1212 | if (!agg) | |
ac718b69 | 1213 | return; |
1214 | ||
ebc2ec48 | 1215 | tp = agg->context; |
1216 | if (!tp) | |
1217 | return; | |
1218 | ||
d104eafa | 1219 | netdev = tp->netdev; |
05e0f1aa | 1220 | stats = &netdev->stats; |
ebc2ec48 | 1221 | if (status) { |
4a8deae2 | 1222 | if (net_ratelimit()) |
d104eafa | 1223 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1224 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1225 | } else { |
ebc2ec48 | 1226 | stats->tx_packets += agg->skb_num; |
1227 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1228 | } |
1229 | ||
2685d410 | 1230 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1231 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1232 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1233 | |
9a4be1bd | 1234 | usb_autopm_put_interface_async(tp->intf); |
1235 | ||
d104eafa | 1236 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1237 | return; |
1238 | ||
1239 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1240 | return; | |
1241 | ||
1242 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1243 | return; | |
1244 | ||
1245 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1246 | napi_schedule(&tp->napi); |
ac718b69 | 1247 | } |
1248 | ||
40a82917 | 1249 | static void intr_callback(struct urb *urb) |
1250 | { | |
1251 | struct r8152 *tp; | |
500b6d7e | 1252 | __le16 *d; |
40a82917 | 1253 | int status = urb->status; |
1254 | int res; | |
1255 | ||
1256 | tp = urb->context; | |
1257 | if (!tp) | |
1258 | return; | |
1259 | ||
1260 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1261 | return; | |
1262 | ||
1263 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1264 | return; | |
1265 | ||
1266 | switch (status) { | |
1267 | case 0: /* success */ | |
1268 | break; | |
1269 | case -ECONNRESET: /* unlink */ | |
1270 | case -ESHUTDOWN: | |
1271 | netif_device_detach(tp->netdev); | |
1272 | case -ENOENT: | |
d59c876d | 1273 | case -EPROTO: |
1274 | netif_info(tp, intr, tp->netdev, | |
1275 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1276 | return; |
1277 | case -EOVERFLOW: | |
1278 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1279 | goto resubmit; | |
1280 | /* -EPIPE: should clear the halt */ | |
1281 | default: | |
1282 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1283 | goto resubmit; | |
1284 | } | |
1285 | ||
1286 | d = urb->transfer_buffer; | |
1287 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1288 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1289 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1290 | schedule_delayed_work(&tp->schedule, 0); | |
1291 | } | |
1292 | } else { | |
51d979fa | 1293 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 1294 | netif_stop_queue(tp->netdev); |
40a82917 | 1295 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1296 | schedule_delayed_work(&tp->schedule, 0); | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | resubmit: | |
1301 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1302 | if (res == -ENODEV) { |
1303 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1304 | netif_device_detach(tp->netdev); |
67610496 | 1305 | } else if (res) { |
40a82917 | 1306 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1307 | "can't resubmit intr, status %d\n", res); |
67610496 | 1308 | } |
40a82917 | 1309 | } |
1310 | ||
ebc2ec48 | 1311 | static inline void *rx_agg_align(void *data) |
1312 | { | |
8e1f51bd | 1313 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1314 | } |
1315 | ||
1316 | static inline void *tx_agg_align(void *data) | |
1317 | { | |
8e1f51bd | 1318 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1319 | } |
1320 | ||
1321 | static void free_all_mem(struct r8152 *tp) | |
1322 | { | |
1323 | int i; | |
1324 | ||
1325 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1326 | usb_free_urb(tp->rx_info[i].urb); |
1327 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1328 | |
9629e3c0 | 1329 | kfree(tp->rx_info[i].buffer); |
1330 | tp->rx_info[i].buffer = NULL; | |
1331 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1332 | } |
1333 | ||
1334 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1335 | usb_free_urb(tp->tx_info[i].urb); |
1336 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1337 | |
9629e3c0 | 1338 | kfree(tp->tx_info[i].buffer); |
1339 | tp->tx_info[i].buffer = NULL; | |
1340 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1341 | } |
40a82917 | 1342 | |
9629e3c0 | 1343 | usb_free_urb(tp->intr_urb); |
1344 | tp->intr_urb = NULL; | |
40a82917 | 1345 | |
9629e3c0 | 1346 | kfree(tp->intr_buff); |
1347 | tp->intr_buff = NULL; | |
ebc2ec48 | 1348 | } |
1349 | ||
1350 | static int alloc_all_mem(struct r8152 *tp) | |
1351 | { | |
1352 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1353 | struct usb_interface *intf = tp->intf; |
1354 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1355 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1356 | struct urb *urb; |
1357 | int node, i; | |
1358 | u8 *buf; | |
1359 | ||
1360 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1361 | ||
1362 | spin_lock_init(&tp->rx_lock); | |
1363 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1364 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 1365 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 1366 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 1367 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1368 | |
1369 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1370 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1371 | if (!buf) |
1372 | goto err1; | |
1373 | ||
1374 | if (buf != rx_agg_align(buf)) { | |
1375 | kfree(buf); | |
52aec126 | 1376 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1377 | node); |
ebc2ec48 | 1378 | if (!buf) |
1379 | goto err1; | |
1380 | } | |
1381 | ||
1382 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1383 | if (!urb) { | |
1384 | kfree(buf); | |
1385 | goto err1; | |
1386 | } | |
1387 | ||
1388 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1389 | tp->rx_info[i].context = tp; | |
1390 | tp->rx_info[i].urb = urb; | |
1391 | tp->rx_info[i].buffer = buf; | |
1392 | tp->rx_info[i].head = rx_agg_align(buf); | |
1393 | } | |
1394 | ||
1395 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1396 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1397 | if (!buf) |
1398 | goto err1; | |
1399 | ||
1400 | if (buf != tx_agg_align(buf)) { | |
1401 | kfree(buf); | |
52aec126 | 1402 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1403 | node); |
ebc2ec48 | 1404 | if (!buf) |
1405 | goto err1; | |
1406 | } | |
1407 | ||
1408 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1409 | if (!urb) { | |
1410 | kfree(buf); | |
1411 | goto err1; | |
1412 | } | |
1413 | ||
1414 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1415 | tp->tx_info[i].context = tp; | |
1416 | tp->tx_info[i].urb = urb; | |
1417 | tp->tx_info[i].buffer = buf; | |
1418 | tp->tx_info[i].head = tx_agg_align(buf); | |
1419 | ||
1420 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1421 | } | |
1422 | ||
40a82917 | 1423 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1424 | if (!tp->intr_urb) | |
1425 | goto err1; | |
1426 | ||
1427 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1428 | if (!tp->intr_buff) | |
1429 | goto err1; | |
1430 | ||
1431 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1432 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1433 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1434 | tp, tp->intr_interval); | |
40a82917 | 1435 | |
ebc2ec48 | 1436 | return 0; |
1437 | ||
1438 | err1: | |
1439 | free_all_mem(tp); | |
1440 | return -ENOMEM; | |
1441 | } | |
1442 | ||
0de98f6c | 1443 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1444 | { | |
1445 | struct tx_agg *agg = NULL; | |
1446 | unsigned long flags; | |
1447 | ||
21949ab7 | 1448 | if (list_empty(&tp->tx_free)) |
1449 | return NULL; | |
1450 | ||
0de98f6c | 1451 | spin_lock_irqsave(&tp->tx_lock, flags); |
1452 | if (!list_empty(&tp->tx_free)) { | |
1453 | struct list_head *cursor; | |
1454 | ||
1455 | cursor = tp->tx_free.next; | |
1456 | list_del_init(cursor); | |
1457 | agg = list_entry(cursor, struct tx_agg, list); | |
1458 | } | |
1459 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1460 | ||
1461 | return agg; | |
1462 | } | |
1463 | ||
b209af99 | 1464 | /* r8152_csum_workaround() |
6128d1bb | 1465 | * The hw limites the value the transport offset. When the offset is out of the |
1466 | * range, calculate the checksum by sw. | |
1467 | */ | |
1468 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1469 | struct sk_buff_head *list) | |
1470 | { | |
1471 | if (skb_shinfo(skb)->gso_size) { | |
1472 | netdev_features_t features = tp->netdev->features; | |
1473 | struct sk_buff_head seg_list; | |
1474 | struct sk_buff *segs, *nskb; | |
1475 | ||
a91d45f1 | 1476 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1477 | segs = skb_gso_segment(skb, features); |
1478 | if (IS_ERR(segs) || !segs) | |
1479 | goto drop; | |
1480 | ||
1481 | __skb_queue_head_init(&seg_list); | |
1482 | ||
1483 | do { | |
1484 | nskb = segs; | |
1485 | segs = segs->next; | |
1486 | nskb->next = NULL; | |
1487 | __skb_queue_tail(&seg_list, nskb); | |
1488 | } while (segs); | |
1489 | ||
1490 | skb_queue_splice(&seg_list, list); | |
1491 | dev_kfree_skb(skb); | |
1492 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1493 | if (skb_checksum_help(skb) < 0) | |
1494 | goto drop; | |
1495 | ||
1496 | __skb_queue_head(list, skb); | |
1497 | } else { | |
1498 | struct net_device_stats *stats; | |
1499 | ||
1500 | drop: | |
1501 | stats = &tp->netdev->stats; | |
1502 | stats->tx_dropped++; | |
1503 | dev_kfree_skb(skb); | |
1504 | } | |
1505 | } | |
1506 | ||
b209af99 | 1507 | /* msdn_giant_send_check() |
6128d1bb | 1508 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1509 | * packet length for IPv6 TCP large packets. | |
1510 | */ | |
1511 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1512 | { | |
1513 | const struct ipv6hdr *ipv6h; | |
1514 | struct tcphdr *th; | |
fcb308d5 | 1515 | int ret; |
1516 | ||
1517 | ret = skb_cow_head(skb, 0); | |
1518 | if (ret) | |
1519 | return ret; | |
6128d1bb | 1520 | |
1521 | ipv6h = ipv6_hdr(skb); | |
1522 | th = tcp_hdr(skb); | |
1523 | ||
1524 | th->check = 0; | |
1525 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1526 | ||
fcb308d5 | 1527 | return ret; |
6128d1bb | 1528 | } |
1529 | ||
c5554298 | 1530 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1531 | { | |
df8a39de | 1532 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1533 | u32 opts2; |
1534 | ||
df8a39de | 1535 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1536 | desc->opts2 |= cpu_to_le32(opts2); |
1537 | } | |
1538 | } | |
1539 | ||
1540 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1541 | { | |
1542 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1543 | ||
1544 | if (opts2 & RX_VLAN_TAG) | |
1545 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1546 | swab16(opts2 & 0xffff)); | |
1547 | } | |
1548 | ||
60c89071 | 1549 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1550 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1551 | { | |
1552 | u32 mss = skb_shinfo(skb)->gso_size; | |
1553 | u32 opts1, opts2 = 0; | |
1554 | int ret = TX_CSUM_SUCCESS; | |
1555 | ||
1556 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1557 | ||
1558 | opts1 = len | TX_FS | TX_LS; | |
1559 | ||
1560 | if (mss) { | |
6128d1bb | 1561 | if (transport_offset > GTTCPHO_MAX) { |
1562 | netif_warn(tp, tx_err, tp->netdev, | |
1563 | "Invalid transport offset 0x%x for TSO\n", | |
1564 | transport_offset); | |
1565 | ret = TX_CSUM_TSO; | |
1566 | goto unavailable; | |
1567 | } | |
1568 | ||
6e74d174 | 1569 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1570 | case htons(ETH_P_IP): |
1571 | opts1 |= GTSENDV4; | |
1572 | break; | |
1573 | ||
6128d1bb | 1574 | case htons(ETH_P_IPV6): |
fcb308d5 | 1575 | if (msdn_giant_send_check(skb)) { |
1576 | ret = TX_CSUM_TSO; | |
1577 | goto unavailable; | |
1578 | } | |
6128d1bb | 1579 | opts1 |= GTSENDV6; |
6128d1bb | 1580 | break; |
1581 | ||
60c89071 | 1582 | default: |
1583 | WARN_ON_ONCE(1); | |
1584 | break; | |
1585 | } | |
1586 | ||
1587 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1588 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1589 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1590 | u8 ip_protocol; | |
5bd23881 | 1591 | |
6128d1bb | 1592 | if (transport_offset > TCPHO_MAX) { |
1593 | netif_warn(tp, tx_err, tp->netdev, | |
1594 | "Invalid transport offset 0x%x\n", | |
1595 | transport_offset); | |
1596 | ret = TX_CSUM_NONE; | |
1597 | goto unavailable; | |
1598 | } | |
1599 | ||
6e74d174 | 1600 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1601 | case htons(ETH_P_IP): |
1602 | opts2 |= IPV4_CS; | |
1603 | ip_protocol = ip_hdr(skb)->protocol; | |
1604 | break; | |
1605 | ||
1606 | case htons(ETH_P_IPV6): | |
1607 | opts2 |= IPV6_CS; | |
1608 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1609 | break; | |
1610 | ||
1611 | default: | |
1612 | ip_protocol = IPPROTO_RAW; | |
1613 | break; | |
1614 | } | |
1615 | ||
60c89071 | 1616 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1617 | opts2 |= TCP_CS; |
60c89071 | 1618 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1619 | opts2 |= UDP_CS; |
60c89071 | 1620 | else |
5bd23881 | 1621 | WARN_ON_ONCE(1); |
5bd23881 | 1622 | |
60c89071 | 1623 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1624 | } |
60c89071 | 1625 | |
1626 | desc->opts2 = cpu_to_le32(opts2); | |
1627 | desc->opts1 = cpu_to_le32(opts1); | |
1628 | ||
6128d1bb | 1629 | unavailable: |
60c89071 | 1630 | return ret; |
5bd23881 | 1631 | } |
1632 | ||
b1379d9a | 1633 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1634 | { | |
d84130a1 | 1635 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1636 | int remain, ret; |
b1379d9a | 1637 | u8 *tx_data; |
1638 | ||
d84130a1 | 1639 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1640 | spin_lock(&tx_queue->lock); |
d84130a1 | 1641 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1642 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1643 | |
b1379d9a | 1644 | tx_data = agg->head; |
b209af99 | 1645 | agg->skb_num = 0; |
1646 | agg->skb_len = 0; | |
52aec126 | 1647 | remain = agg_buf_sz; |
b1379d9a | 1648 | |
7937f9e5 | 1649 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1650 | struct tx_desc *tx_desc; |
1651 | struct sk_buff *skb; | |
1652 | unsigned int len; | |
60c89071 | 1653 | u32 offset; |
b1379d9a | 1654 | |
d84130a1 | 1655 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1656 | if (!skb) |
1657 | break; | |
1658 | ||
60c89071 | 1659 | len = skb->len + sizeof(*tx_desc); |
1660 | ||
1661 | if (len > remain) { | |
d84130a1 | 1662 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1663 | break; |
1664 | } | |
1665 | ||
7937f9e5 | 1666 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1667 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1668 | |
1669 | offset = (u32)skb_transport_offset(skb); | |
1670 | ||
6128d1bb | 1671 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1672 | r8152_csum_workaround(tp, skb, &skb_head); | |
1673 | continue; | |
1674 | } | |
60c89071 | 1675 | |
c5554298 | 1676 | rtl_tx_vlan_tag(tx_desc, skb); |
1677 | ||
b1379d9a | 1678 | tx_data += sizeof(*tx_desc); |
1679 | ||
60c89071 | 1680 | len = skb->len; |
1681 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1682 | struct net_device_stats *stats = &tp->netdev->stats; | |
1683 | ||
1684 | stats->tx_dropped++; | |
1685 | dev_kfree_skb_any(skb); | |
1686 | tx_data -= sizeof(*tx_desc); | |
1687 | continue; | |
1688 | } | |
1689 | ||
1690 | tx_data += len; | |
b1379d9a | 1691 | agg->skb_len += len; |
60c89071 | 1692 | agg->skb_num++; |
1693 | ||
b1379d9a | 1694 | dev_kfree_skb_any(skb); |
1695 | ||
52aec126 | 1696 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1697 | } |
1698 | ||
d84130a1 | 1699 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1700 | spin_lock(&tx_queue->lock); |
d84130a1 | 1701 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1702 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1703 | } |
1704 | ||
0c3121fc | 1705 | netif_tx_lock(tp->netdev); |
dd1b119c | 1706 | |
1707 | if (netif_queue_stopped(tp->netdev) && | |
1708 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1709 | netif_wake_queue(tp->netdev); | |
1710 | ||
0c3121fc | 1711 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1712 | |
0c3121fc | 1713 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1714 | if (ret < 0) |
1715 | goto out_tx_fill; | |
dd1b119c | 1716 | |
b1379d9a | 1717 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1718 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1719 | (usb_complete_t)write_bulk_callback, agg); | |
1720 | ||
0c3121fc | 1721 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1722 | if (ret < 0) |
0c3121fc | 1723 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1724 | |
1725 | out_tx_fill: | |
1726 | return ret; | |
b1379d9a | 1727 | } |
1728 | ||
565cab0a | 1729 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1730 | { | |
1731 | u8 checksum = CHECKSUM_NONE; | |
1732 | u32 opts2, opts3; | |
1733 | ||
19c0f40d | 1734 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 1735 | goto return_result; |
1736 | ||
1737 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1738 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1739 | ||
1740 | if (opts2 & RD_IPV4_CS) { | |
1741 | if (opts3 & IPF) | |
1742 | checksum = CHECKSUM_NONE; | |
1743 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1744 | checksum = CHECKSUM_NONE; | |
1745 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1746 | checksum = CHECKSUM_NONE; | |
1747 | else | |
1748 | checksum = CHECKSUM_UNNECESSARY; | |
b9a321b4 | 1749 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 1750 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
1751 | checksum = CHECKSUM_UNNECESSARY; | |
1752 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1753 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1754 | } |
1755 | ||
1756 | return_result: | |
1757 | return checksum; | |
1758 | } | |
1759 | ||
d823ab68 | 1760 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1761 | { |
a5a4f468 | 1762 | unsigned long flags; |
d84130a1 | 1763 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1764 | int ret = 0, work_done = 0; |
ce594e98 | 1765 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 1766 | |
1767 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1768 | while (work_done < budget) { | |
1769 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1770 | struct net_device *netdev = tp->netdev; | |
1771 | struct net_device_stats *stats = &netdev->stats; | |
1772 | unsigned int pkt_len; | |
1773 | ||
1774 | if (!skb) | |
1775 | break; | |
1776 | ||
1777 | pkt_len = skb->len; | |
ce594e98 | 1778 | napi_gro_receive(napi, skb); |
d823ab68 | 1779 | work_done++; |
1780 | stats->rx_packets++; | |
1781 | stats->rx_bytes += pkt_len; | |
1782 | } | |
1783 | } | |
ebc2ec48 | 1784 | |
d84130a1 | 1785 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1786 | goto out1; |
d84130a1 | 1787 | |
1788 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1789 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1790 | list_splice_init(&tp->rx_done, &rx_queue); |
1791 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1792 | ||
1793 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1794 | struct rx_desc *rx_desc; |
1795 | struct rx_agg *agg; | |
43a4478d | 1796 | int len_used = 0; |
1797 | struct urb *urb; | |
1798 | u8 *rx_data; | |
43a4478d | 1799 | |
ebc2ec48 | 1800 | list_del_init(cursor); |
ebc2ec48 | 1801 | |
1802 | agg = list_entry(cursor, struct rx_agg, list); | |
1803 | urb = agg->urb; | |
0de98f6c | 1804 | if (urb->actual_length < ETH_ZLEN) |
1805 | goto submit; | |
ebc2ec48 | 1806 | |
ebc2ec48 | 1807 | rx_desc = agg->head; |
1808 | rx_data = agg->head; | |
7937f9e5 | 1809 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1810 | |
7937f9e5 | 1811 | while (urb->actual_length > len_used) { |
43a4478d | 1812 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1813 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1814 | unsigned int pkt_len; |
43a4478d | 1815 | struct sk_buff *skb; |
1816 | ||
74544458 | 1817 | /* limite the skb numbers for rx_queue */ |
1818 | if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) | |
1819 | break; | |
1820 | ||
7937f9e5 | 1821 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1822 | if (pkt_len < ETH_ZLEN) |
1823 | break; | |
1824 | ||
7937f9e5 | 1825 | len_used += pkt_len; |
1826 | if (urb->actual_length < len_used) | |
1827 | break; | |
1828 | ||
8e1f51bd | 1829 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1830 | rx_data += sizeof(struct rx_desc); |
1831 | ||
ce594e98 | 1832 | skb = napi_alloc_skb(napi, pkt_len); |
ebc2ec48 | 1833 | if (!skb) { |
1834 | stats->rx_dropped++; | |
5e2f7485 | 1835 | goto find_next_rx; |
ebc2ec48 | 1836 | } |
565cab0a | 1837 | |
1838 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1839 | memcpy(skb->data, rx_data, pkt_len); |
1840 | skb_put(skb, pkt_len); | |
1841 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1842 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1843 | if (work_done < budget) { |
ce594e98 | 1844 | napi_gro_receive(napi, skb); |
d823ab68 | 1845 | work_done++; |
1846 | stats->rx_packets++; | |
1847 | stats->rx_bytes += pkt_len; | |
1848 | } else { | |
1849 | __skb_queue_tail(&tp->rx_queue, skb); | |
1850 | } | |
ebc2ec48 | 1851 | |
5e2f7485 | 1852 | find_next_rx: |
8e1f51bd | 1853 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1854 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1855 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1856 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1857 | } |
1858 | ||
0de98f6c | 1859 | submit: |
e1a2ca92 | 1860 | if (!ret) { |
1861 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1862 | } else { | |
1863 | urb->actual_length = 0; | |
1864 | list_add_tail(&agg->list, next); | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | if (!list_empty(&rx_queue)) { | |
1869 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1870 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1871 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1872 | } |
d823ab68 | 1873 | |
1874 | out1: | |
1875 | return work_done; | |
ebc2ec48 | 1876 | } |
1877 | ||
1878 | static void tx_bottom(struct r8152 *tp) | |
1879 | { | |
ebc2ec48 | 1880 | int res; |
1881 | ||
b1379d9a | 1882 | do { |
1883 | struct tx_agg *agg; | |
ebc2ec48 | 1884 | |
b1379d9a | 1885 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1886 | break; |
1887 | ||
b1379d9a | 1888 | agg = r8152_get_tx_agg(tp); |
1889 | if (!agg) | |
ebc2ec48 | 1890 | break; |
ebc2ec48 | 1891 | |
b1379d9a | 1892 | res = r8152_tx_agg_fill(tp, agg); |
1893 | if (res) { | |
05e0f1aa | 1894 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1895 | |
b1379d9a | 1896 | if (res == -ENODEV) { |
67610496 | 1897 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1898 | netif_device_detach(netdev); |
1899 | } else { | |
05e0f1aa | 1900 | struct net_device_stats *stats = &netdev->stats; |
1901 | unsigned long flags; | |
1902 | ||
b1379d9a | 1903 | netif_warn(tp, tx_err, netdev, |
1904 | "failed tx_urb %d\n", res); | |
1905 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1906 | |
b1379d9a | 1907 | spin_lock_irqsave(&tp->tx_lock, flags); |
1908 | list_add_tail(&agg->list, &tp->tx_free); | |
1909 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1910 | } | |
ebc2ec48 | 1911 | } |
b1379d9a | 1912 | } while (res == 0); |
ebc2ec48 | 1913 | } |
1914 | ||
d823ab68 | 1915 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 1916 | { |
ebc2ec48 | 1917 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1918 | return; | |
1919 | ||
1920 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1921 | return; |
ebc2ec48 | 1922 | |
7559fb2f | 1923 | /* When link down, the driver would cancel all bulks. */ |
1924 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1925 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1926 | return; |
ebc2ec48 | 1927 | |
d823ab68 | 1928 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 1929 | |
0c3121fc | 1930 | tx_bottom(tp); |
ebc2ec48 | 1931 | } |
1932 | ||
d823ab68 | 1933 | static int r8152_poll(struct napi_struct *napi, int budget) |
1934 | { | |
1935 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
1936 | int work_done; | |
1937 | ||
1938 | work_done = rx_bottom(tp, budget); | |
1939 | bottom_half(tp); | |
1940 | ||
1941 | if (work_done < budget) { | |
a3307f9b | 1942 | if (!napi_complete_done(napi, work_done)) |
1943 | goto out; | |
d823ab68 | 1944 | if (!list_empty(&tp->rx_done)) |
1945 | napi_schedule(napi); | |
248b213a | 1946 | else if (!skb_queue_empty(&tp->tx_queue) && |
1947 | !list_empty(&tp->tx_free)) | |
1948 | napi_schedule(napi); | |
d823ab68 | 1949 | } |
1950 | ||
a3307f9b | 1951 | out: |
d823ab68 | 1952 | return work_done; |
1953 | } | |
1954 | ||
ebc2ec48 | 1955 | static |
1956 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1957 | { | |
a0fccd48 | 1958 | int ret; |
1959 | ||
ef827a5b | 1960 | /* The rx would be stopped, so skip submitting */ |
1961 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
1962 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
1963 | return 0; | |
1964 | ||
ebc2ec48 | 1965 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 1966 | agg->head, agg_buf_sz, |
b209af99 | 1967 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1968 | |
a0fccd48 | 1969 | ret = usb_submit_urb(agg->urb, mem_flags); |
1970 | if (ret == -ENODEV) { | |
1971 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1972 | netif_device_detach(tp->netdev); | |
1973 | } else if (ret) { | |
1974 | struct urb *urb = agg->urb; | |
1975 | unsigned long flags; | |
1976 | ||
1977 | urb->actual_length = 0; | |
1978 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1979 | list_add_tail(&agg->list, &tp->rx_done); | |
1980 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 1981 | |
1982 | netif_err(tp, rx_err, tp->netdev, | |
1983 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
1984 | ||
1985 | napi_schedule(&tp->napi); | |
a0fccd48 | 1986 | } |
1987 | ||
1988 | return ret; | |
ac718b69 | 1989 | } |
1990 | ||
00a5e360 | 1991 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1992 | { | |
1993 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1994 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1995 | struct sk_buff *skb; |
1996 | ||
d84130a1 | 1997 | if (skb_queue_empty(tx_queue)) |
1998 | return; | |
1999 | ||
2000 | __skb_queue_head_init(&skb_head); | |
2685d410 | 2001 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 2002 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 2003 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 2004 | |
2005 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 2006 | dev_kfree_skb(skb); |
2007 | stats->tx_dropped++; | |
2008 | } | |
2009 | } | |
2010 | ||
ac718b69 | 2011 | static void rtl8152_tx_timeout(struct net_device *netdev) |
2012 | { | |
2013 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2014 | |
4a8deae2 | 2015 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2016 | |
2017 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2018 | } |
2019 | ||
2020 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2021 | { | |
2022 | struct r8152 *tp = netdev_priv(netdev); | |
2023 | ||
51d979fa | 2024 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2025 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2026 | schedule_delayed_work(&tp->schedule, 0); |
2027 | } | |
ac718b69 | 2028 | } |
2029 | ||
2030 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2031 | { | |
2032 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2033 | u32 mc_filter[2]; /* Multicast hash filter */ |
2034 | __le32 tmp[2]; | |
ac718b69 | 2035 | u32 ocp_data; |
2036 | ||
ac718b69 | 2037 | netif_stop_queue(netdev); |
2038 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2039 | ocp_data &= ~RCR_ACPT_ALL; | |
2040 | ocp_data |= RCR_AB | RCR_APM; | |
2041 | ||
2042 | if (netdev->flags & IFF_PROMISC) { | |
2043 | /* Unconditionally log net taps. */ | |
2044 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2045 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2046 | mc_filter[1] = 0xffffffff; |
2047 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2048 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
2049 | (netdev->flags & IFF_ALLMULTI)) { | |
2050 | /* Too many to filter perfectly -- accept all multicasts. */ | |
2051 | ocp_data |= RCR_AM; | |
b209af99 | 2052 | mc_filter[1] = 0xffffffff; |
2053 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2054 | } else { |
2055 | struct netdev_hw_addr *ha; | |
2056 | ||
b209af99 | 2057 | mc_filter[1] = 0; |
2058 | mc_filter[0] = 0; | |
ac718b69 | 2059 | netdev_for_each_mc_addr(ha, netdev) { |
2060 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 2061 | |
ac718b69 | 2062 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
2063 | ocp_data |= RCR_AM; | |
2064 | } | |
2065 | } | |
2066 | ||
31787f53 | 2067 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2068 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2069 | |
31787f53 | 2070 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2071 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2072 | netif_wake_queue(netdev); | |
ac718b69 | 2073 | } |
2074 | ||
a5e31255 | 2075 | static netdev_features_t |
2076 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2077 | netdev_features_t features) | |
2078 | { | |
2079 | u32 mss = skb_shinfo(skb)->gso_size; | |
2080 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
2081 | int offset = skb_transport_offset(skb); | |
2082 | ||
2083 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
a188222b | 2084 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2085 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2086 | features &= ~NETIF_F_GSO_MASK; | |
2087 | ||
2088 | return features; | |
2089 | } | |
2090 | ||
ac718b69 | 2091 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2092 | struct net_device *netdev) |
ac718b69 | 2093 | { |
2094 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2095 | |
ebc2ec48 | 2096 | skb_tx_timestamp(skb); |
ac718b69 | 2097 | |
61598788 | 2098 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2099 | |
0c3121fc | 2100 | if (!list_empty(&tp->tx_free)) { |
2101 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 2102 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 2103 | schedule_delayed_work(&tp->schedule, 0); |
2104 | } else { | |
2105 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2106 | napi_schedule(&tp->napi); |
0c3121fc | 2107 | } |
b209af99 | 2108 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2109 | netif_stop_queue(netdev); |
b209af99 | 2110 | } |
dd1b119c | 2111 | |
ac718b69 | 2112 | return NETDEV_TX_OK; |
2113 | } | |
2114 | ||
2115 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2116 | { | |
2117 | u32 ocp_data; | |
2118 | ||
2119 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2120 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2121 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2122 | ocp_data |= FMC_FCR_MCU_EN; | |
2123 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2124 | } | |
2125 | ||
2126 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2127 | { | |
2128 | int i; | |
2129 | ||
2130 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2131 | ||
2132 | for (i = 0; i < 1000; i++) { | |
2133 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2134 | break; | |
b209af99 | 2135 | usleep_range(100, 400); |
ac718b69 | 2136 | } |
2137 | } | |
2138 | ||
dd1b119c | 2139 | static void set_tx_qlen(struct r8152 *tp) |
2140 | { | |
2141 | struct net_device *netdev = tp->netdev; | |
2142 | ||
52aec126 | 2143 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2144 | sizeof(struct tx_desc)); | |
dd1b119c | 2145 | } |
2146 | ||
ac718b69 | 2147 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2148 | { | |
2149 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2150 | } | |
2151 | ||
507605a8 | 2152 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2153 | { |
ebc2ec48 | 2154 | u32 ocp_data; |
ac718b69 | 2155 | u8 speed; |
2156 | ||
2157 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2158 | if (speed & _10bps) { |
ac718b69 | 2159 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2160 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2161 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2162 | } else { | |
2163 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2164 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2165 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2166 | } | |
507605a8 | 2167 | } |
2168 | ||
00a5e360 | 2169 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2170 | { | |
2171 | u32 ocp_data; | |
2172 | ||
2173 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2174 | if (enable) | |
2175 | ocp_data |= RXDY_GATED_EN; | |
2176 | else | |
2177 | ocp_data &= ~RXDY_GATED_EN; | |
2178 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2179 | } | |
2180 | ||
445f7f4d | 2181 | static int rtl_start_rx(struct r8152 *tp) |
2182 | { | |
2183 | int i, ret = 0; | |
2184 | ||
2185 | INIT_LIST_HEAD(&tp->rx_done); | |
2186 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2187 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2188 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2189 | if (ret) | |
2190 | break; | |
2191 | } | |
2192 | ||
7bcf4f60 | 2193 | if (ret && ++i < RTL8152_MAX_RX) { |
2194 | struct list_head rx_queue; | |
2195 | unsigned long flags; | |
2196 | ||
2197 | INIT_LIST_HEAD(&rx_queue); | |
2198 | ||
2199 | do { | |
2200 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2201 | struct urb *urb = agg->urb; | |
2202 | ||
2203 | urb->actual_length = 0; | |
2204 | list_add_tail(&agg->list, &rx_queue); | |
2205 | } while (i < RTL8152_MAX_RX); | |
2206 | ||
2207 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2208 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2209 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2210 | } | |
2211 | ||
445f7f4d | 2212 | return ret; |
2213 | } | |
2214 | ||
2215 | static int rtl_stop_rx(struct r8152 *tp) | |
2216 | { | |
2217 | int i; | |
2218 | ||
2219 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2220 | usb_kill_urb(tp->rx_info[i].urb); | |
2221 | ||
d823ab68 | 2222 | while (!skb_queue_empty(&tp->rx_queue)) |
2223 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2224 | ||
445f7f4d | 2225 | return 0; |
2226 | } | |
2227 | ||
507605a8 | 2228 | static int rtl_enable(struct r8152 *tp) |
2229 | { | |
2230 | u32 ocp_data; | |
ac718b69 | 2231 | |
2232 | r8152b_reset_packet_filter(tp); | |
2233 | ||
2234 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2235 | ocp_data |= CR_RE | CR_TE; | |
2236 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2237 | ||
00a5e360 | 2238 | rxdy_gated_en(tp, false); |
ac718b69 | 2239 | |
aa2e0926 | 2240 | return 0; |
ac718b69 | 2241 | } |
2242 | ||
507605a8 | 2243 | static int rtl8152_enable(struct r8152 *tp) |
2244 | { | |
6871438c | 2245 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2246 | return -ENODEV; | |
2247 | ||
507605a8 | 2248 | set_tx_qlen(tp); |
2249 | rtl_set_eee_plus(tp); | |
2250 | ||
2251 | return rtl_enable(tp); | |
2252 | } | |
2253 | ||
464ec10a | 2254 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2255 | { |
464ec10a | 2256 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2257 | |
464ec10a | 2258 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); |
2259 | } | |
2260 | ||
2261 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2262 | { | |
b20cb60e | 2263 | u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4; |
464ec10a | 2264 | |
2265 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); | |
43779f8d | 2266 | } |
2267 | ||
2268 | static int rtl8153_enable(struct r8152 *tp) | |
2269 | { | |
6871438c | 2270 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2271 | return -ENODEV; | |
2272 | ||
43779f8d | 2273 | set_tx_qlen(tp); |
2274 | rtl_set_eee_plus(tp); | |
464ec10a | 2275 | r8153_set_rx_early_timeout(tp); |
2276 | r8153_set_rx_early_size(tp); | |
43779f8d | 2277 | |
2278 | return rtl_enable(tp); | |
2279 | } | |
2280 | ||
d70b1137 | 2281 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2282 | { |
ebc2ec48 | 2283 | u32 ocp_data; |
2284 | int i; | |
ac718b69 | 2285 | |
6871438c | 2286 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2287 | rtl_drop_queued_tx(tp); | |
2288 | return; | |
2289 | } | |
2290 | ||
ac718b69 | 2291 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2292 | ocp_data &= ~RCR_ACPT_ALL; | |
2293 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2294 | ||
00a5e360 | 2295 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2296 | |
2297 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2298 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2299 | |
00a5e360 | 2300 | rxdy_gated_en(tp, true); |
ac718b69 | 2301 | |
2302 | for (i = 0; i < 1000; i++) { | |
2303 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2304 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2305 | break; | |
8ddfa077 | 2306 | usleep_range(1000, 2000); |
ac718b69 | 2307 | } |
2308 | ||
2309 | for (i = 0; i < 1000; i++) { | |
2310 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2311 | break; | |
8ddfa077 | 2312 | usleep_range(1000, 2000); |
ac718b69 | 2313 | } |
2314 | ||
445f7f4d | 2315 | rtl_stop_rx(tp); |
ac718b69 | 2316 | |
2317 | rtl8152_nic_reset(tp); | |
2318 | } | |
2319 | ||
00a5e360 | 2320 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2321 | { | |
2322 | u32 ocp_data; | |
2323 | ||
2324 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2325 | if (enable) | |
2326 | ocp_data |= POWER_CUT; | |
2327 | else | |
2328 | ocp_data &= ~POWER_CUT; | |
2329 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2330 | ||
2331 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2332 | ocp_data &= ~RESUME_INDICATE; | |
2333 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2334 | } |
2335 | ||
c5554298 | 2336 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2337 | { | |
2338 | u32 ocp_data; | |
2339 | ||
2340 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2341 | if (enable) | |
2342 | ocp_data |= CPCR_RX_VLAN; | |
2343 | else | |
2344 | ocp_data &= ~CPCR_RX_VLAN; | |
2345 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2346 | } | |
2347 | ||
2348 | static int rtl8152_set_features(struct net_device *dev, | |
2349 | netdev_features_t features) | |
2350 | { | |
2351 | netdev_features_t changed = features ^ dev->features; | |
2352 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2353 | int ret; |
2354 | ||
2355 | ret = usb_autopm_get_interface(tp->intf); | |
2356 | if (ret < 0) | |
2357 | goto out; | |
c5554298 | 2358 | |
b5403273 | 2359 | mutex_lock(&tp->control); |
2360 | ||
c5554298 | 2361 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2362 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2363 | rtl_rx_vlan_en(tp, true); | |
2364 | else | |
2365 | rtl_rx_vlan_en(tp, false); | |
2366 | } | |
2367 | ||
b5403273 | 2368 | mutex_unlock(&tp->control); |
2369 | ||
405f8a0e | 2370 | usb_autopm_put_interface(tp->intf); |
2371 | ||
2372 | out: | |
2373 | return ret; | |
c5554298 | 2374 | } |
2375 | ||
21ff2e89 | 2376 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2377 | ||
2378 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2379 | { | |
2380 | u32 ocp_data; | |
2381 | u32 wolopts = 0; | |
2382 | ||
21ff2e89 | 2383 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
2384 | if (ocp_data & LINK_ON_WAKE_EN) | |
2385 | wolopts |= WAKE_PHY; | |
2386 | ||
2387 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2388 | if (ocp_data & UWF_EN) | |
2389 | wolopts |= WAKE_UCAST; | |
2390 | if (ocp_data & BWF_EN) | |
2391 | wolopts |= WAKE_BCAST; | |
2392 | if (ocp_data & MWF_EN) | |
2393 | wolopts |= WAKE_MCAST; | |
2394 | ||
2395 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2396 | if (ocp_data & MAGIC_EN) | |
2397 | wolopts |= WAKE_MAGIC; | |
2398 | ||
2399 | return wolopts; | |
2400 | } | |
2401 | ||
2402 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2403 | { | |
2404 | u32 ocp_data; | |
2405 | ||
2406 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2407 | ||
2408 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2409 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2410 | if (wolopts & WAKE_PHY) | |
2411 | ocp_data |= LINK_ON_WAKE_EN; | |
2412 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2413 | ||
2414 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 2415 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 2416 | if (wolopts & WAKE_UCAST) |
2417 | ocp_data |= UWF_EN; | |
2418 | if (wolopts & WAKE_BCAST) | |
2419 | ocp_data |= BWF_EN; | |
2420 | if (wolopts & WAKE_MCAST) | |
2421 | ocp_data |= MWF_EN; | |
21ff2e89 | 2422 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
2423 | ||
2424 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2425 | ||
2426 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2427 | ocp_data &= ~MAGIC_EN; | |
2428 | if (wolopts & WAKE_MAGIC) | |
2429 | ocp_data |= MAGIC_EN; | |
2430 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2431 | ||
2432 | if (wolopts & WAKE_ANY) | |
2433 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2434 | else | |
2435 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2436 | } | |
2437 | ||
134f98bc | 2438 | static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) |
2439 | { | |
2440 | /* MAC clock speed down */ | |
2441 | if (enable) { | |
2442 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
2443 | ALDPS_SPDWN_RATIO); | |
2444 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, | |
2445 | EEE_SPDWN_RATIO); | |
2446 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2447 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2448 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2449 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2450 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2451 | TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | | |
2452 | TP1000_SPDWN_EN); | |
2453 | } else { | |
2454 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); | |
2455 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); | |
2456 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); | |
2457 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); | |
2458 | } | |
2459 | } | |
2460 | ||
b214396f | 2461 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2462 | { | |
2463 | u8 u1u2[8]; | |
2464 | ||
2465 | if (enable) | |
2466 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2467 | else | |
2468 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2469 | ||
2470 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2471 | } | |
2472 | ||
2473 | static void r8153_u2p3en(struct r8152 *tp, bool enable) | |
2474 | { | |
2475 | u32 ocp_data; | |
2476 | ||
2477 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
3cb3234e | 2478 | if (enable) |
b214396f | 2479 | ocp_data |= U2P3_ENABLE; |
2480 | else | |
2481 | ocp_data &= ~U2P3_ENABLE; | |
2482 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2483 | } | |
2484 | ||
c564b871 | 2485 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
2486 | { | |
2487 | u16 data; | |
2488 | int i; | |
2489 | ||
2490 | for (i = 0; i < 500; i++) { | |
2491 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
2492 | data &= PHY_STAT_MASK; | |
2493 | if (desired) { | |
2494 | if (data == desired) | |
2495 | break; | |
2496 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
2497 | data == PHY_STAT_EXT_INIT) { | |
2498 | break; | |
2499 | } | |
2500 | ||
2501 | msleep(20); | |
2502 | } | |
2503 | ||
2504 | return data; | |
2505 | } | |
2506 | ||
b214396f | 2507 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
2508 | { | |
2509 | u32 ocp_data; | |
2510 | ||
2511 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2512 | if (enable) | |
2513 | ocp_data |= PWR_EN | PHASE2_EN; | |
2514 | else | |
2515 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2516 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2517 | ||
2518 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2519 | ocp_data &= ~PCUT_STATUS; | |
2520 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2521 | } | |
2522 | ||
7daed8dc | 2523 | static bool rtl_can_wakeup(struct r8152 *tp) |
2524 | { | |
2525 | struct usb_device *udev = tp->udev; | |
2526 | ||
2527 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2528 | } | |
2529 | ||
9a4be1bd | 2530 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2531 | { | |
2532 | if (enable) { | |
2533 | u32 ocp_data; | |
2534 | ||
2535 | __rtl_set_wol(tp, WAKE_ANY); | |
2536 | ||
2537 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2538 | ||
2539 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2540 | ocp_data |= LINK_OFF_WAKE_EN; | |
2541 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2542 | ||
2543 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2544 | } else { | |
f95ae8a0 | 2545 | u32 ocp_data; |
2546 | ||
9a4be1bd | 2547 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 2548 | |
2549 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2550 | ||
2551 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2552 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
2553 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2554 | ||
2555 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 2556 | } |
2557 | } | |
f95ae8a0 | 2558 | |
2609af19 | 2559 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
2560 | { | |
2609af19 | 2561 | if (enable) { |
2562 | r8153_u1u2en(tp, false); | |
2563 | r8153_u2p3en(tp, false); | |
134f98bc | 2564 | r8153_mac_clk_spd(tp, true); |
02552754 | 2565 | rtl_runtime_suspend_enable(tp, true); |
2609af19 | 2566 | } else { |
02552754 | 2567 | rtl_runtime_suspend_enable(tp, false); |
134f98bc | 2568 | r8153_mac_clk_spd(tp, false); |
3cb3234e | 2569 | |
2570 | switch (tp->version) { | |
2571 | case RTL_VER_03: | |
2572 | case RTL_VER_04: | |
2573 | break; | |
2574 | case RTL_VER_05: | |
2575 | case RTL_VER_06: | |
2576 | default: | |
2577 | r8153_u2p3en(tp, true); | |
2578 | break; | |
2579 | } | |
2580 | ||
b214396f | 2581 | r8153_u1u2en(tp, true); |
9a4be1bd | 2582 | } |
2583 | } | |
2584 | ||
4349968a | 2585 | static void r8153_teredo_off(struct r8152 *tp) |
2586 | { | |
2587 | u32 ocp_data; | |
2588 | ||
2589 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2590 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2591 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2592 | ||
2593 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2594 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2595 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2596 | } | |
2597 | ||
93fe9b18 | 2598 | static void rtl_reset_bmu(struct r8152 *tp) |
2599 | { | |
2600 | u32 ocp_data; | |
2601 | ||
2602 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2603 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
2604 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2605 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
2606 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2607 | } | |
2608 | ||
cda9fb01 | 2609 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 2610 | { |
cda9fb01 | 2611 | if (enable) { |
2612 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2613 | LINKENA | DIS_SDSAVE); | |
2614 | } else { | |
2615 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
2616 | DIS_SDSAVE); | |
2617 | msleep(20); | |
2618 | } | |
4349968a | 2619 | } |
2620 | ||
e6449539 | 2621 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
2622 | { | |
2623 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
2624 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
2625 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
2626 | } | |
2627 | ||
2628 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
2629 | { | |
2630 | u16 data; | |
2631 | ||
2632 | r8152_mmd_indirect(tp, dev, reg); | |
2633 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
2634 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2635 | ||
2636 | return data; | |
2637 | } | |
2638 | ||
2639 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
2640 | { | |
2641 | r8152_mmd_indirect(tp, dev, reg); | |
2642 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
2643 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2644 | } | |
2645 | ||
2646 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
2647 | { | |
2648 | u16 config1, config2, config3; | |
2649 | u32 ocp_data; | |
2650 | ||
2651 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2652 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
2653 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
2654 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
2655 | ||
2656 | if (enable) { | |
2657 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2658 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
2659 | config1 |= sd_rise_time(1); | |
2660 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
2661 | config3 |= fast_snr(42); | |
2662 | } else { | |
2663 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2664 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
2665 | RX_QUIET_EN); | |
2666 | config1 |= sd_rise_time(7); | |
2667 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
2668 | config3 |= fast_snr(511); | |
2669 | } | |
2670 | ||
2671 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2672 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
2673 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
2674 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
2675 | } | |
2676 | ||
2677 | static void r8152b_enable_eee(struct r8152 *tp) | |
2678 | { | |
2679 | r8152_eee_en(tp, true); | |
2680 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
2681 | } | |
2682 | ||
2683 | static void r8152b_enable_fc(struct r8152 *tp) | |
2684 | { | |
2685 | u16 anar; | |
2686 | ||
2687 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2688 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2689 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2690 | } | |
2691 | ||
d70b1137 | 2692 | static void rtl8152_disable(struct r8152 *tp) |
2693 | { | |
cda9fb01 | 2694 | r8152_aldps_en(tp, false); |
d70b1137 | 2695 | rtl_disable(tp); |
cda9fb01 | 2696 | r8152_aldps_en(tp, true); |
d70b1137 | 2697 | } |
2698 | ||
4349968a | 2699 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2700 | { | |
ef39df8e | 2701 | r8152b_enable_eee(tp); |
2702 | r8152_aldps_en(tp, true); | |
2703 | r8152b_enable_fc(tp); | |
f0cbe0ac | 2704 | |
aa66a5f1 | 2705 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2706 | } |
2707 | ||
ac718b69 | 2708 | static void r8152b_exit_oob(struct r8152 *tp) |
2709 | { | |
db8515ef | 2710 | u32 ocp_data; |
2711 | int i; | |
ac718b69 | 2712 | |
2713 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2714 | ocp_data &= ~RCR_ACPT_ALL; | |
2715 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2716 | ||
00a5e360 | 2717 | rxdy_gated_en(tp, true); |
da9bd117 | 2718 | r8153_teredo_off(tp); |
ac718b69 | 2719 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
2720 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2721 | ||
2722 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2723 | ocp_data &= ~NOW_IS_OOB; | |
2724 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2725 | ||
2726 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2727 | ocp_data &= ~MCU_BORW_EN; | |
2728 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2729 | ||
2730 | for (i = 0; i < 1000; i++) { | |
2731 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2732 | if (ocp_data & LINK_LIST_READY) | |
2733 | break; | |
8ddfa077 | 2734 | usleep_range(1000, 2000); |
ac718b69 | 2735 | } |
2736 | ||
2737 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2738 | ocp_data |= RE_INIT_LL; | |
2739 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2740 | ||
2741 | for (i = 0; i < 1000; i++) { | |
2742 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2743 | if (ocp_data & LINK_LIST_READY) | |
2744 | break; | |
8ddfa077 | 2745 | usleep_range(1000, 2000); |
ac718b69 | 2746 | } |
2747 | ||
2748 | rtl8152_nic_reset(tp); | |
2749 | ||
2750 | /* rx share fifo credit full threshold */ | |
2751 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2752 | ||
a3cc465d | 2753 | if (tp->udev->speed == USB_SPEED_FULL || |
2754 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2755 | /* rx share fifo credit near full threshold */ |
2756 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2757 | RXFIFO_THR2_FULL); | |
2758 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2759 | RXFIFO_THR3_FULL); | |
2760 | } else { | |
2761 | /* rx share fifo credit near full threshold */ | |
2762 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2763 | RXFIFO_THR2_HIGH); | |
2764 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2765 | RXFIFO_THR3_HIGH); | |
2766 | } | |
2767 | ||
2768 | /* TX share fifo free credit full threshold */ | |
2769 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2770 | ||
2771 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2772 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2773 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2774 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2775 | ||
c5554298 | 2776 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2777 | |
2778 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2779 | ||
2780 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2781 | ocp_data |= TCR0_AUTO_FIFO; | |
2782 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2783 | } | |
2784 | ||
2785 | static void r8152b_enter_oob(struct r8152 *tp) | |
2786 | { | |
45f4a19f | 2787 | u32 ocp_data; |
2788 | int i; | |
ac718b69 | 2789 | |
2790 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2791 | ocp_data &= ~NOW_IS_OOB; | |
2792 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2793 | ||
2794 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2795 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2796 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2797 | ||
d70b1137 | 2798 | rtl_disable(tp); |
ac718b69 | 2799 | |
2800 | for (i = 0; i < 1000; i++) { | |
2801 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2802 | if (ocp_data & LINK_LIST_READY) | |
2803 | break; | |
8ddfa077 | 2804 | usleep_range(1000, 2000); |
ac718b69 | 2805 | } |
2806 | ||
2807 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2808 | ocp_data |= RE_INIT_LL; | |
2809 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2810 | ||
2811 | for (i = 0; i < 1000; i++) { | |
2812 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2813 | if (ocp_data & LINK_LIST_READY) | |
2814 | break; | |
8ddfa077 | 2815 | usleep_range(1000, 2000); |
ac718b69 | 2816 | } |
2817 | ||
2818 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2819 | ||
c5554298 | 2820 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2821 | |
2822 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2823 | ocp_data |= ALDPS_PROXY_MODE; | |
2824 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2825 | ||
2826 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2827 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2828 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2829 | ||
00a5e360 | 2830 | rxdy_gated_en(tp, false); |
ac718b69 | 2831 | |
2832 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2833 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2834 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2835 | } | |
2836 | ||
e6449539 | 2837 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
2838 | { | |
2839 | u16 data; | |
2840 | ||
2841 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2842 | if (enable) { | |
2843 | data |= EN_ALDPS; | |
2844 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2845 | } else { | |
4214cc55 | 2846 | int i; |
2847 | ||
e6449539 | 2848 | data &= ~EN_ALDPS; |
2849 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
4214cc55 | 2850 | for (i = 0; i < 20; i++) { |
2851 | usleep_range(1000, 2000); | |
2852 | if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) | |
2853 | break; | |
2854 | } | |
e6449539 | 2855 | } |
2856 | } | |
2857 | ||
2858 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
2859 | { | |
2860 | u32 ocp_data; | |
2861 | u16 config; | |
2862 | ||
2863 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2864 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
2865 | ||
2866 | if (enable) { | |
2867 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2868 | config |= EEE10_EN; | |
2869 | } else { | |
2870 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2871 | config &= ~EEE10_EN; | |
2872 | } | |
2873 | ||
2874 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2875 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
2876 | } | |
2877 | ||
43779f8d | 2878 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2879 | { | |
2880 | u32 ocp_data; | |
2881 | u16 data; | |
2882 | ||
d768c61b | 2883 | /* disable ALDPS before updating the PHY parameters */ |
2884 | r8153_aldps_en(tp, false); | |
fb02eb4a | 2885 | |
d768c61b | 2886 | /* disable EEE before updating the PHY parameters */ |
2887 | r8153_eee_en(tp, false); | |
2888 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
43779f8d | 2889 | |
2890 | if (tp->version == RTL_VER_03) { | |
2891 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2892 | data &= ~CTAP_SHORT_EN; | |
2893 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2894 | } | |
2895 | ||
2896 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2897 | data |= EEE_CLKDIV_EN; | |
2898 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2899 | ||
2900 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2901 | data |= EN_10M_BGOFF; | |
2902 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2903 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2904 | data |= EN_10M_PLLOFF; | |
2905 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 2906 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 2907 | |
2908 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2909 | ocp_data |= PFM_PWM_SWITCH; | |
2910 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2911 | ||
b4d99def | 2912 | /* Enable LPF corner auto tune */ |
2913 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 2914 | |
b4d99def | 2915 | /* Adjust 10M Amplitude */ |
2916 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
2917 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 2918 | |
af0287ec | 2919 | r8153_eee_en(tp, true); |
2920 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
2921 | ||
ef39df8e | 2922 | r8153_aldps_en(tp, true); |
2923 | r8152b_enable_fc(tp); | |
2924 | ||
3cb3234e | 2925 | switch (tp->version) { |
2926 | case RTL_VER_03: | |
2927 | case RTL_VER_04: | |
2928 | break; | |
2929 | case RTL_VER_05: | |
2930 | case RTL_VER_06: | |
2931 | default: | |
2932 | r8153_u2p3en(tp, true); | |
2933 | break; | |
2934 | } | |
2935 | ||
aa66a5f1 | 2936 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 2937 | } |
2938 | ||
43779f8d | 2939 | static void r8153_first_init(struct r8152 *tp) |
2940 | { | |
2941 | u32 ocp_data; | |
2942 | int i; | |
2943 | ||
134f98bc | 2944 | r8153_mac_clk_spd(tp, false); |
00a5e360 | 2945 | rxdy_gated_en(tp, true); |
43779f8d | 2946 | r8153_teredo_off(tp); |
2947 | ||
2948 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2949 | ocp_data &= ~RCR_ACPT_ALL; | |
2950 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2951 | ||
43779f8d | 2952 | rtl8152_nic_reset(tp); |
93fe9b18 | 2953 | rtl_reset_bmu(tp); |
43779f8d | 2954 | |
2955 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2956 | ocp_data &= ~NOW_IS_OOB; | |
2957 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2958 | ||
2959 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2960 | ocp_data &= ~MCU_BORW_EN; | |
2961 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2962 | ||
2963 | for (i = 0; i < 1000; i++) { | |
2964 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2965 | if (ocp_data & LINK_LIST_READY) | |
2966 | break; | |
8ddfa077 | 2967 | usleep_range(1000, 2000); |
43779f8d | 2968 | } |
2969 | ||
2970 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2971 | ocp_data |= RE_INIT_LL; | |
2972 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2973 | ||
2974 | for (i = 0; i < 1000; i++) { | |
2975 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2976 | if (ocp_data & LINK_LIST_READY) | |
2977 | break; | |
8ddfa077 | 2978 | usleep_range(1000, 2000); |
43779f8d | 2979 | } |
2980 | ||
c5554298 | 2981 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2982 | |
210c4f70 | 2983 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
2984 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
69b4b7a4 | 2985 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); |
43779f8d | 2986 | |
2987 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2988 | ocp_data |= TCR0_AUTO_FIFO; | |
2989 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2990 | ||
2991 | rtl8152_nic_reset(tp); | |
2992 | ||
2993 | /* rx share fifo credit full threshold */ | |
2994 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2995 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2996 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2997 | /* TX share fifo free credit full threshold */ | |
2998 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
43779f8d | 2999 | } |
3000 | ||
3001 | static void r8153_enter_oob(struct r8152 *tp) | |
3002 | { | |
3003 | u32 ocp_data; | |
3004 | int i; | |
3005 | ||
134f98bc | 3006 | r8153_mac_clk_spd(tp, true); |
3007 | ||
43779f8d | 3008 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
3009 | ocp_data &= ~NOW_IS_OOB; | |
3010 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3011 | ||
d70b1137 | 3012 | rtl_disable(tp); |
93fe9b18 | 3013 | rtl_reset_bmu(tp); |
43779f8d | 3014 | |
3015 | for (i = 0; i < 1000; i++) { | |
3016 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3017 | if (ocp_data & LINK_LIST_READY) | |
3018 | break; | |
8ddfa077 | 3019 | usleep_range(1000, 2000); |
43779f8d | 3020 | } |
3021 | ||
3022 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3023 | ocp_data |= RE_INIT_LL; | |
3024 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3025 | ||
3026 | for (i = 0; i < 1000; i++) { | |
3027 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3028 | if (ocp_data & LINK_LIST_READY) | |
3029 | break; | |
8ddfa077 | 3030 | usleep_range(1000, 2000); |
43779f8d | 3031 | } |
3032 | ||
210c4f70 | 3033 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
3034 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
43779f8d | 3035 | |
43779f8d | 3036 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
3037 | ocp_data &= ~TEREDO_WAKE_MASK; | |
3038 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
3039 | ||
c5554298 | 3040 | rtl_rx_vlan_en(tp, true); |
43779f8d | 3041 | |
3042 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3043 | ocp_data |= ALDPS_PROXY_MODE; | |
3044 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3045 | ||
3046 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3047 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3048 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3049 | ||
00a5e360 | 3050 | rxdy_gated_en(tp, false); |
43779f8d | 3051 | |
3052 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3053 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3054 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3055 | } | |
3056 | ||
d70b1137 | 3057 | static void rtl8153_disable(struct r8152 *tp) |
3058 | { | |
cda9fb01 | 3059 | r8153_aldps_en(tp, false); |
d70b1137 | 3060 | rtl_disable(tp); |
93fe9b18 | 3061 | rtl_reset_bmu(tp); |
cda9fb01 | 3062 | r8153_aldps_en(tp, true); |
d70b1137 | 3063 | } |
3064 | ||
ac718b69 | 3065 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
3066 | { | |
43779f8d | 3067 | u16 bmcr, anar, gbcr; |
ac718b69 | 3068 | int ret = 0; |
3069 | ||
ac718b69 | 3070 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
3071 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
3072 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 3073 | if (tp->mii.supports_gmii) { |
3074 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
3075 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
3076 | } else { | |
3077 | gbcr = 0; | |
3078 | } | |
ac718b69 | 3079 | |
3080 | if (autoneg == AUTONEG_DISABLE) { | |
3081 | if (speed == SPEED_10) { | |
3082 | bmcr = 0; | |
3083 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3084 | } else if (speed == SPEED_100) { | |
3085 | bmcr = BMCR_SPEED100; | |
3086 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 3087 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3088 | bmcr = BMCR_SPEED1000; | |
3089 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 3090 | } else { |
3091 | ret = -EINVAL; | |
3092 | goto out; | |
3093 | } | |
3094 | ||
3095 | if (duplex == DUPLEX_FULL) | |
3096 | bmcr |= BMCR_FULLDPLX; | |
3097 | } else { | |
3098 | if (speed == SPEED_10) { | |
3099 | if (duplex == DUPLEX_FULL) | |
3100 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3101 | else | |
3102 | anar |= ADVERTISE_10HALF; | |
3103 | } else if (speed == SPEED_100) { | |
3104 | if (duplex == DUPLEX_FULL) { | |
3105 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3106 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3107 | } else { | |
3108 | anar |= ADVERTISE_10HALF; | |
3109 | anar |= ADVERTISE_100HALF; | |
3110 | } | |
43779f8d | 3111 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3112 | if (duplex == DUPLEX_FULL) { | |
3113 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3114 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3115 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
3116 | } else { | |
3117 | anar |= ADVERTISE_10HALF; | |
3118 | anar |= ADVERTISE_100HALF; | |
3119 | gbcr |= ADVERTISE_1000HALF; | |
3120 | } | |
ac718b69 | 3121 | } else { |
3122 | ret = -EINVAL; | |
3123 | goto out; | |
3124 | } | |
3125 | ||
3126 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
3127 | } | |
3128 | ||
fae56178 | 3129 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 3130 | bmcr |= BMCR_RESET; |
3131 | ||
43779f8d | 3132 | if (tp->mii.supports_gmii) |
3133 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
3134 | ||
ac718b69 | 3135 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
3136 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
3137 | ||
fae56178 | 3138 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 3139 | int i; |
3140 | ||
aa66a5f1 | 3141 | for (i = 0; i < 50; i++) { |
3142 | msleep(20); | |
3143 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
3144 | break; | |
3145 | } | |
3146 | } | |
3147 | ||
ac718b69 | 3148 | out: |
ac718b69 | 3149 | return ret; |
3150 | } | |
3151 | ||
d70b1137 | 3152 | static void rtl8152_up(struct r8152 *tp) |
3153 | { | |
3154 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3155 | return; | |
3156 | ||
cda9fb01 | 3157 | r8152_aldps_en(tp, false); |
d70b1137 | 3158 | r8152b_exit_oob(tp); |
cda9fb01 | 3159 | r8152_aldps_en(tp, true); |
d70b1137 | 3160 | } |
3161 | ||
ac718b69 | 3162 | static void rtl8152_down(struct r8152 *tp) |
3163 | { | |
6871438c | 3164 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3165 | rtl_drop_queued_tx(tp); | |
3166 | return; | |
3167 | } | |
3168 | ||
00a5e360 | 3169 | r8152_power_cut_en(tp, false); |
cda9fb01 | 3170 | r8152_aldps_en(tp, false); |
ac718b69 | 3171 | r8152b_enter_oob(tp); |
cda9fb01 | 3172 | r8152_aldps_en(tp, true); |
ac718b69 | 3173 | } |
3174 | ||
d70b1137 | 3175 | static void rtl8153_up(struct r8152 *tp) |
3176 | { | |
3177 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3178 | return; | |
3179 | ||
b214396f | 3180 | r8153_u1u2en(tp, false); |
3cb3234e | 3181 | r8153_u2p3en(tp, false); |
cda9fb01 | 3182 | r8153_aldps_en(tp, false); |
d70b1137 | 3183 | r8153_first_init(tp); |
cda9fb01 | 3184 | r8153_aldps_en(tp, true); |
3cb3234e | 3185 | |
3186 | switch (tp->version) { | |
3187 | case RTL_VER_03: | |
3188 | case RTL_VER_04: | |
3189 | break; | |
3190 | case RTL_VER_05: | |
3191 | case RTL_VER_06: | |
3192 | default: | |
3193 | r8153_u2p3en(tp, true); | |
3194 | break; | |
3195 | } | |
3196 | ||
b214396f | 3197 | r8153_u1u2en(tp, true); |
d70b1137 | 3198 | } |
3199 | ||
43779f8d | 3200 | static void rtl8153_down(struct r8152 *tp) |
3201 | { | |
6871438c | 3202 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3203 | rtl_drop_queued_tx(tp); | |
3204 | return; | |
3205 | } | |
3206 | ||
b9702723 | 3207 | r8153_u1u2en(tp, false); |
b214396f | 3208 | r8153_u2p3en(tp, false); |
b9702723 | 3209 | r8153_power_cut_en(tp, false); |
cda9fb01 | 3210 | r8153_aldps_en(tp, false); |
43779f8d | 3211 | r8153_enter_oob(tp); |
cda9fb01 | 3212 | r8153_aldps_en(tp, true); |
43779f8d | 3213 | } |
3214 | ||
2dd49e0f | 3215 | static bool rtl8152_in_nway(struct r8152 *tp) |
3216 | { | |
3217 | u16 nway_state; | |
3218 | ||
3219 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
3220 | tp->ocp_base = 0x2000; | |
3221 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
3222 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
3223 | ||
3224 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
3225 | if (nway_state & 0xc000) | |
3226 | return false; | |
3227 | else | |
3228 | return true; | |
3229 | } | |
3230 | ||
3231 | static bool rtl8153_in_nway(struct r8152 *tp) | |
3232 | { | |
3233 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
3234 | ||
3235 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
3236 | return false; | |
3237 | else | |
3238 | return true; | |
3239 | } | |
3240 | ||
ac718b69 | 3241 | static void set_carrier(struct r8152 *tp) |
3242 | { | |
3243 | struct net_device *netdev = tp->netdev; | |
ce594e98 | 3244 | struct napi_struct *napi = &tp->napi; |
ac718b69 | 3245 | u8 speed; |
3246 | ||
3247 | speed = rtl8152_get_speed(tp); | |
3248 | ||
3249 | if (speed & LINK_STATUS) { | |
51d979fa | 3250 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 3251 | tp->rtl_ops.enable(tp); |
ac718b69 | 3252 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
de9bf29d | 3253 | netif_stop_queue(netdev); |
ce594e98 | 3254 | napi_disable(napi); |
ac718b69 | 3255 | netif_carrier_on(netdev); |
aa2e0926 | 3256 | rtl_start_rx(tp); |
41cec84c | 3257 | napi_enable(&tp->napi); |
de9bf29d | 3258 | netif_wake_queue(netdev); |
3259 | netif_info(tp, link, netdev, "carrier on\n"); | |
2f25abe6 | 3260 | } else if (netif_queue_stopped(netdev) && |
3261 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
3262 | netif_wake_queue(netdev); | |
ac718b69 | 3263 | } |
3264 | } else { | |
51d979fa | 3265 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 3266 | netif_carrier_off(netdev); |
ce594e98 | 3267 | napi_disable(napi); |
c81229c9 | 3268 | tp->rtl_ops.disable(tp); |
ce594e98 | 3269 | napi_enable(napi); |
de9bf29d | 3270 | netif_info(tp, link, netdev, "carrier off\n"); |
ac718b69 | 3271 | } |
3272 | } | |
ac718b69 | 3273 | } |
3274 | ||
3275 | static void rtl_work_func_t(struct work_struct *work) | |
3276 | { | |
3277 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
3278 | ||
a1f83fee | 3279 | /* If the device is unplugged or !netif_running(), the workqueue |
3280 | * doesn't need to wake the device, and could return directly. | |
3281 | */ | |
3282 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
3283 | return; | |
3284 | ||
9a4be1bd | 3285 | if (usb_autopm_get_interface(tp->intf) < 0) |
3286 | return; | |
3287 | ||
ac718b69 | 3288 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
3289 | goto out1; | |
3290 | ||
b5403273 | 3291 | if (!mutex_trylock(&tp->control)) { |
3292 | schedule_delayed_work(&tp->schedule, 0); | |
3293 | goto out1; | |
3294 | } | |
3295 | ||
216a8349 | 3296 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) |
40a82917 | 3297 | set_carrier(tp); |
ac718b69 | 3298 | |
216a8349 | 3299 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
ac718b69 | 3300 | _rtl8152_set_rx_mode(tp->netdev); |
3301 | ||
d823ab68 | 3302 | /* don't schedule napi before linking */ |
216a8349 | 3303 | if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && |
3304 | netif_carrier_ok(tp->netdev)) | |
d823ab68 | 3305 | napi_schedule(&tp->napi); |
aa66a5f1 | 3306 | |
b5403273 | 3307 | mutex_unlock(&tp->control); |
3308 | ||
ac718b69 | 3309 | out1: |
9a4be1bd | 3310 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3311 | } |
3312 | ||
a028a9e0 | 3313 | static void rtl_hw_phy_work_func_t(struct work_struct *work) |
3314 | { | |
3315 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
3316 | ||
3317 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3318 | return; | |
3319 | ||
3320 | if (usb_autopm_get_interface(tp->intf) < 0) | |
3321 | return; | |
3322 | ||
3323 | mutex_lock(&tp->control); | |
3324 | ||
3325 | tp->rtl_ops.hw_phy_cfg(tp); | |
3326 | ||
aa7e26b6 | 3327 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); |
9d21c0d8 | 3328 | |
a028a9e0 | 3329 | mutex_unlock(&tp->control); |
3330 | ||
3331 | usb_autopm_put_interface(tp->intf); | |
3332 | } | |
3333 | ||
5ee3c60c | 3334 | #ifdef CONFIG_PM_SLEEP |
3335 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
3336 | void *data) | |
3337 | { | |
3338 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
3339 | ||
3340 | switch (action) { | |
3341 | case PM_HIBERNATION_PREPARE: | |
3342 | case PM_SUSPEND_PREPARE: | |
3343 | usb_autopm_get_interface(tp->intf); | |
3344 | break; | |
3345 | ||
3346 | case PM_POST_HIBERNATION: | |
3347 | case PM_POST_SUSPEND: | |
3348 | usb_autopm_put_interface(tp->intf); | |
3349 | break; | |
3350 | ||
3351 | case PM_POST_RESTORE: | |
3352 | case PM_RESTORE_PREPARE: | |
3353 | default: | |
3354 | break; | |
3355 | } | |
3356 | ||
3357 | return NOTIFY_DONE; | |
3358 | } | |
3359 | #endif | |
3360 | ||
ac718b69 | 3361 | static int rtl8152_open(struct net_device *netdev) |
3362 | { | |
3363 | struct r8152 *tp = netdev_priv(netdev); | |
3364 | int res = 0; | |
3365 | ||
7e9da481 | 3366 | res = alloc_all_mem(tp); |
3367 | if (res) | |
3368 | goto out; | |
3369 | ||
9a4be1bd | 3370 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
3371 | if (res < 0) |
3372 | goto out_free; | |
9a4be1bd | 3373 | |
b5403273 | 3374 | mutex_lock(&tp->control); |
3375 | ||
7e9da481 | 3376 | tp->rtl_ops.up(tp); |
3377 | ||
3d55f44f | 3378 | netif_carrier_off(netdev); |
3379 | netif_start_queue(netdev); | |
3380 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3381 | |
40a82917 | 3382 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3383 | if (res) { | |
3384 | if (res == -ENODEV) | |
3385 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3386 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3387 | res); | |
ca0a7531 | 3388 | goto out_unlock; |
ac718b69 | 3389 | } |
ca0a7531 | 3390 | napi_enable(&tp->napi); |
ac718b69 | 3391 | |
b5403273 | 3392 | mutex_unlock(&tp->control); |
3393 | ||
9a4be1bd | 3394 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 3395 | #ifdef CONFIG_PM_SLEEP |
3396 | tp->pm_notifier.notifier_call = rtl_notifier; | |
3397 | register_pm_notifier(&tp->pm_notifier); | |
3398 | #endif | |
ca0a7531 | 3399 | return 0; |
ac718b69 | 3400 | |
ca0a7531 GR |
3401 | out_unlock: |
3402 | mutex_unlock(&tp->control); | |
3403 | usb_autopm_put_interface(tp->intf); | |
3404 | out_free: | |
3405 | free_all_mem(tp); | |
7e9da481 | 3406 | out: |
ac718b69 | 3407 | return res; |
3408 | } | |
3409 | ||
3410 | static int rtl8152_close(struct net_device *netdev) | |
3411 | { | |
3412 | struct r8152 *tp = netdev_priv(netdev); | |
3413 | int res = 0; | |
3414 | ||
5ee3c60c | 3415 | #ifdef CONFIG_PM_SLEEP |
3416 | unregister_pm_notifier(&tp->pm_notifier); | |
3417 | #endif | |
d823ab68 | 3418 | napi_disable(&tp->napi); |
ac718b69 | 3419 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3420 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3421 | cancel_delayed_work_sync(&tp->schedule); |
3422 | netif_stop_queue(netdev); | |
9a4be1bd | 3423 | |
3424 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3425 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3426 | rtl_drop_queued_tx(tp); |
d823ab68 | 3427 | rtl_stop_rx(tp); |
9a4be1bd | 3428 | } else { |
b5403273 | 3429 | mutex_lock(&tp->control); |
3430 | ||
9a4be1bd | 3431 | tp->rtl_ops.down(tp); |
b5403273 | 3432 | |
3433 | mutex_unlock(&tp->control); | |
3434 | ||
9a4be1bd | 3435 | usb_autopm_put_interface(tp->intf); |
3436 | } | |
ac718b69 | 3437 | |
7e9da481 | 3438 | free_all_mem(tp); |
3439 | ||
ac718b69 | 3440 | return res; |
3441 | } | |
3442 | ||
4f1d4d54 | 3443 | static void rtl_tally_reset(struct r8152 *tp) |
3444 | { | |
3445 | u32 ocp_data; | |
3446 | ||
3447 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3448 | ocp_data |= TALLY_RESET; | |
3449 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3450 | } | |
3451 | ||
ac718b69 | 3452 | static void r8152b_init(struct r8152 *tp) |
3453 | { | |
ebc2ec48 | 3454 | u32 ocp_data; |
2dd436da | 3455 | u16 data; |
ac718b69 | 3456 | |
6871438c | 3457 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3458 | return; | |
3459 | ||
2dd436da | 3460 | data = r8152_mdio_read(tp, MII_BMCR); |
3461 | if (data & BMCR_PDOWN) { | |
3462 | data &= ~BMCR_PDOWN; | |
3463 | r8152_mdio_write(tp, MII_BMCR, data); | |
3464 | } | |
3465 | ||
cda9fb01 | 3466 | r8152_aldps_en(tp, false); |
d70b1137 | 3467 | |
ac718b69 | 3468 | if (tp->version == RTL_VER_01) { |
3469 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3470 | ocp_data &= ~LED_MODE_MASK; | |
3471 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3472 | } | |
3473 | ||
00a5e360 | 3474 | r8152_power_cut_en(tp, false); |
ac718b69 | 3475 | |
ac718b69 | 3476 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3477 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3478 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3479 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3480 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3481 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3482 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3483 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3484 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3485 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3486 | ||
4f1d4d54 | 3487 | rtl_tally_reset(tp); |
ac718b69 | 3488 | |
ebc2ec48 | 3489 | /* enable rx aggregation */ |
ac718b69 | 3490 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 3491 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 3492 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3493 | } | |
3494 | ||
43779f8d | 3495 | static void r8153_init(struct r8152 *tp) |
3496 | { | |
3497 | u32 ocp_data; | |
2dd436da | 3498 | u16 data; |
43779f8d | 3499 | int i; |
3500 | ||
6871438c | 3501 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3502 | return; | |
3503 | ||
b9702723 | 3504 | r8153_u1u2en(tp, false); |
43779f8d | 3505 | |
3506 | for (i = 0; i < 500; i++) { | |
3507 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3508 | AUTOLOAD_DONE) | |
3509 | break; | |
3510 | msleep(20); | |
3511 | } | |
3512 | ||
c564b871 | 3513 | data = r8153_phy_status(tp, 0); |
43779f8d | 3514 | |
2dd436da | 3515 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
3516 | tp->version == RTL_VER_05) | |
3517 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
3518 | ||
3519 | data = r8152_mdio_read(tp, MII_BMCR); | |
3520 | if (data & BMCR_PDOWN) { | |
3521 | data &= ~BMCR_PDOWN; | |
3522 | r8152_mdio_write(tp, MII_BMCR, data); | |
3523 | } | |
3524 | ||
c564b871 | 3525 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
2dd436da | 3526 | |
b9702723 | 3527 | r8153_u2p3en(tp, false); |
43779f8d | 3528 | |
65bab84c | 3529 | if (tp->version == RTL_VER_04) { |
3530 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
3531 | ocp_data &= ~pwd_dn_scale_mask; | |
3532 | ocp_data |= pwd_dn_scale(96); | |
3533 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
3534 | ||
3535 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
3536 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
3537 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
3538 | } else if (tp->version == RTL_VER_05) { | |
3539 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
3540 | ocp_data &= ~ECM_ALDPS; | |
3541 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
3542 | ||
fb02eb4a | 3543 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3544 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3545 | ocp_data &= ~DYNAMIC_BURST; | |
3546 | else | |
3547 | ocp_data |= DYNAMIC_BURST; | |
3548 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3549 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 3550 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3551 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3552 | ocp_data &= ~DYNAMIC_BURST; | |
3553 | else | |
3554 | ocp_data |= DYNAMIC_BURST; | |
3555 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3556 | } | |
3557 | ||
3558 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
3559 | ocp_data |= EP4_FULL_FC; | |
3560 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
3561 | ||
43779f8d | 3562 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
3563 | ocp_data &= ~TIMER11_EN; | |
3564 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3565 | ||
43779f8d | 3566 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3567 | ocp_data &= ~LED_MODE_MASK; | |
3568 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3569 | ||
65bab84c | 3570 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
2b84af94 | 3571 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) |
43779f8d | 3572 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 3573 | else |
3574 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 3575 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
3576 | ||
3577 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3578 | ocp_data &= ~SEN_VAL_MASK; | |
3579 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3580 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3581 | ||
65bab84c | 3582 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
3583 | ||
b9702723 | 3584 | r8153_power_cut_en(tp, false); |
3585 | r8153_u1u2en(tp, true); | |
134f98bc | 3586 | r8153_mac_clk_spd(tp, false); |
ee4761c1 | 3587 | usb_enable_lpm(tp->udev); |
43779f8d | 3588 | |
e31f6367 | 3589 | /* rx aggregation */ |
3590 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
3591 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
3592 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
43779f8d | 3593 | |
4f1d4d54 | 3594 | rtl_tally_reset(tp); |
49d10347 | 3595 | |
3596 | switch (tp->udev->speed) { | |
3597 | case USB_SPEED_SUPER: | |
3598 | case USB_SPEED_SUPER_PLUS: | |
3599 | tp->coalesce = COALESCE_SUPER; | |
3600 | break; | |
3601 | case USB_SPEED_HIGH: | |
3602 | tp->coalesce = COALESCE_HIGH; | |
3603 | break; | |
3604 | default: | |
3605 | tp->coalesce = COALESCE_SLOW; | |
3606 | break; | |
3607 | } | |
43779f8d | 3608 | } |
3609 | ||
e501139a | 3610 | static int rtl8152_pre_reset(struct usb_interface *intf) |
3611 | { | |
3612 | struct r8152 *tp = usb_get_intfdata(intf); | |
3613 | struct net_device *netdev; | |
3614 | ||
3615 | if (!tp) | |
3616 | return 0; | |
3617 | ||
3618 | netdev = tp->netdev; | |
3619 | if (!netif_running(netdev)) | |
3620 | return 0; | |
3621 | ||
de9bf29d | 3622 | netif_stop_queue(netdev); |
e501139a | 3623 | napi_disable(&tp->napi); |
3624 | clear_bit(WORK_ENABLE, &tp->flags); | |
3625 | usb_kill_urb(tp->intr_urb); | |
3626 | cancel_delayed_work_sync(&tp->schedule); | |
3627 | if (netif_carrier_ok(netdev)) { | |
e501139a | 3628 | mutex_lock(&tp->control); |
3629 | tp->rtl_ops.disable(tp); | |
3630 | mutex_unlock(&tp->control); | |
3631 | } | |
3632 | ||
3633 | return 0; | |
3634 | } | |
3635 | ||
3636 | static int rtl8152_post_reset(struct usb_interface *intf) | |
3637 | { | |
3638 | struct r8152 *tp = usb_get_intfdata(intf); | |
3639 | struct net_device *netdev; | |
3640 | ||
3641 | if (!tp) | |
3642 | return 0; | |
3643 | ||
3644 | netdev = tp->netdev; | |
3645 | if (!netif_running(netdev)) | |
3646 | return 0; | |
3647 | ||
3648 | set_bit(WORK_ENABLE, &tp->flags); | |
3649 | if (netif_carrier_ok(netdev)) { | |
3650 | mutex_lock(&tp->control); | |
3651 | tp->rtl_ops.enable(tp); | |
2c561b2b | 3652 | rtl_start_rx(tp); |
e501139a | 3653 | rtl8152_set_rx_mode(netdev); |
3654 | mutex_unlock(&tp->control); | |
e501139a | 3655 | } |
3656 | ||
3657 | napi_enable(&tp->napi); | |
de9bf29d | 3658 | netif_wake_queue(netdev); |
2c561b2b | 3659 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 3660 | |
7489bdad | 3661 | if (!list_empty(&tp->rx_done)) |
3662 | napi_schedule(&tp->napi); | |
e501139a | 3663 | |
3664 | return 0; | |
43779f8d | 3665 | } |
3666 | ||
2dd49e0f | 3667 | static bool delay_autosuspend(struct r8152 *tp) |
3668 | { | |
3669 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
3670 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
3671 | ||
3672 | /* This means a linking change occurs and the driver doesn't detect it, | |
3673 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
3674 | * device wouldn't wake up by receiving any packet. | |
3675 | */ | |
3676 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
3677 | return true; | |
3678 | ||
3679 | /* If the linking down is occurred by nway, the device may miss the | |
3680 | * linking change event. And it wouldn't wake when linking on. | |
3681 | */ | |
3682 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
3683 | return true; | |
6a0b76c0 | 3684 | else if (!skb_queue_empty(&tp->tx_queue)) |
3685 | return true; | |
2dd49e0f | 3686 | else |
3687 | return false; | |
3688 | } | |
3689 | ||
a9c54ad2 | 3690 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 3691 | { |
6cc69f2a | 3692 | struct net_device *netdev = tp->netdev; |
3693 | int ret = 0; | |
ac718b69 | 3694 | |
26afec39 | 3695 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
3696 | smp_mb__after_atomic(); | |
3697 | ||
8fb28061 | 3698 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 3699 | u32 rcr = 0; |
3700 | ||
8fb28061 | 3701 | if (delay_autosuspend(tp)) { |
26afec39 | 3702 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3703 | smp_mb__after_atomic(); | |
6cc69f2a | 3704 | ret = -EBUSY; |
3705 | goto out1; | |
3706 | } | |
3707 | ||
75dc692e | 3708 | if (netif_carrier_ok(netdev)) { |
3709 | u32 ocp_data; | |
3710 | ||
3711 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3712 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
3713 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3714 | rxdy_gated_en(tp, true); | |
3715 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
3716 | PLA_OOB_CTRL); | |
3717 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
3718 | rxdy_gated_en(tp, false); | |
3719 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 3720 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3721 | smp_mb__after_atomic(); | |
75dc692e | 3722 | ret = -EBUSY; |
3723 | goto out1; | |
3724 | } | |
3725 | } | |
3726 | ||
8fb28061 | 3727 | clear_bit(WORK_ENABLE, &tp->flags); |
3728 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 3729 | |
8fb28061 | 3730 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 3731 | |
3732 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 3733 | struct napi_struct *napi = &tp->napi; |
3734 | ||
3735 | napi_disable(napi); | |
75dc692e | 3736 | rtl_stop_rx(tp); |
3737 | rxdy_gated_en(tp, false); | |
3738 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 3739 | napi_enable(napi); |
75dc692e | 3740 | } |
6cc69f2a | 3741 | } |
ac718b69 | 3742 | |
8fb28061 | 3743 | out1: |
3744 | return ret; | |
3745 | } | |
3746 | ||
3747 | static int rtl8152_system_suspend(struct r8152 *tp) | |
3748 | { | |
3749 | struct net_device *netdev = tp->netdev; | |
3750 | int ret = 0; | |
3751 | ||
3752 | netif_device_detach(netdev); | |
3753 | ||
e3bd1a81 | 3754 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 3755 | struct napi_struct *napi = &tp->napi; |
3756 | ||
ac718b69 | 3757 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3758 | usb_kill_urb(tp->intr_urb); |
ce594e98 | 3759 | napi_disable(napi); |
8fb28061 | 3760 | cancel_delayed_work_sync(&tp->schedule); |
3761 | tp->rtl_ops.down(tp); | |
ce594e98 | 3762 | napi_enable(napi); |
ac718b69 | 3763 | } |
8fb28061 | 3764 | |
3765 | return ret; | |
3766 | } | |
3767 | ||
3768 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
3769 | { | |
3770 | struct r8152 *tp = usb_get_intfdata(intf); | |
3771 | int ret; | |
3772 | ||
3773 | mutex_lock(&tp->control); | |
3774 | ||
3775 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 3776 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 3777 | else |
3778 | ret = rtl8152_system_suspend(tp); | |
3779 | ||
b5403273 | 3780 | mutex_unlock(&tp->control); |
3781 | ||
6cc69f2a | 3782 | return ret; |
ac718b69 | 3783 | } |
3784 | ||
3785 | static int rtl8152_resume(struct usb_interface *intf) | |
3786 | { | |
3787 | struct r8152 *tp = usb_get_intfdata(intf); | |
ce594e98 | 3788 | struct net_device *netdev = tp->netdev; |
ac718b69 | 3789 | |
b5403273 | 3790 | mutex_lock(&tp->control); |
3791 | ||
befb2de1 | 3792 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) |
ce594e98 | 3793 | netif_device_attach(netdev); |
9a4be1bd | 3794 | |
ce594e98 | 3795 | if (netif_running(netdev) && netdev->flags & IFF_UP) { |
9a4be1bd | 3796 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 3797 | struct napi_struct *napi = &tp->napi; |
3798 | ||
2609af19 | 3799 | tp->rtl_ops.autosuspend_en(tp, false); |
ce594e98 | 3800 | napi_disable(napi); |
445f7f4d | 3801 | set_bit(WORK_ENABLE, &tp->flags); |
6f14f443 | 3802 | if (netif_carrier_ok(netdev)) { |
2f25abe6 | 3803 | if (rtl8152_get_speed(tp) & LINK_STATUS) { |
3804 | rtl_start_rx(tp); | |
3805 | } else { | |
6f14f443 | 3806 | netif_carrier_off(netdev); |
2f25abe6 | 3807 | tp->rtl_ops.disable(tp); |
6f14f443 | 3808 | netif_info(tp, link, netdev, |
2f25abe6 | 3809 | "linking down\n"); |
3810 | } | |
3811 | } | |
ce594e98 | 3812 | napi_enable(napi); |
26afec39 | 3813 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3814 | smp_mb__after_atomic(); | |
7489bdad | 3815 | if (!list_empty(&tp->rx_done)) |
3816 | napi_schedule(&tp->napi); | |
9a4be1bd | 3817 | } else { |
3818 | tp->rtl_ops.up(tp); | |
ce594e98 | 3819 | netif_carrier_off(netdev); |
445f7f4d | 3820 | set_bit(WORK_ENABLE, &tp->flags); |
9a4be1bd | 3821 | } |
40a82917 | 3822 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 3823 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 3824 | if (netdev->flags & IFF_UP) |
2609af19 | 3825 | tp->rtl_ops.autosuspend_en(tp, false); |
923e1ee3 | 3826 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
ac718b69 | 3827 | } |
3828 | ||
b5403273 | 3829 | mutex_unlock(&tp->control); |
3830 | ||
ac718b69 | 3831 | return 0; |
3832 | } | |
3833 | ||
7ec2541a | 3834 | static int rtl8152_reset_resume(struct usb_interface *intf) |
3835 | { | |
3836 | struct r8152 *tp = usb_get_intfdata(intf); | |
3837 | ||
3838 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
befb2de1 | 3839 | mutex_lock(&tp->control); |
3840 | tp->rtl_ops.init(tp); | |
3841 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); | |
3842 | mutex_unlock(&tp->control); | |
7ec2541a | 3843 | return rtl8152_resume(intf); |
3844 | } | |
3845 | ||
21ff2e89 | 3846 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3847 | { | |
3848 | struct r8152 *tp = netdev_priv(dev); | |
3849 | ||
9a4be1bd | 3850 | if (usb_autopm_get_interface(tp->intf) < 0) |
3851 | return; | |
3852 | ||
7daed8dc | 3853 | if (!rtl_can_wakeup(tp)) { |
3854 | wol->supported = 0; | |
3855 | wol->wolopts = 0; | |
3856 | } else { | |
3857 | mutex_lock(&tp->control); | |
3858 | wol->supported = WAKE_ANY; | |
3859 | wol->wolopts = __rtl_get_wol(tp); | |
3860 | mutex_unlock(&tp->control); | |
3861 | } | |
b5403273 | 3862 | |
9a4be1bd | 3863 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 3864 | } |
3865 | ||
3866 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3867 | { | |
3868 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3869 | int ret; |
3870 | ||
7daed8dc | 3871 | if (!rtl_can_wakeup(tp)) |
3872 | return -EOPNOTSUPP; | |
3873 | ||
9a4be1bd | 3874 | ret = usb_autopm_get_interface(tp->intf); |
3875 | if (ret < 0) | |
3876 | goto out_set_wol; | |
21ff2e89 | 3877 | |
b5403273 | 3878 | mutex_lock(&tp->control); |
3879 | ||
21ff2e89 | 3880 | __rtl_set_wol(tp, wol->wolopts); |
3881 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3882 | ||
b5403273 | 3883 | mutex_unlock(&tp->control); |
3884 | ||
9a4be1bd | 3885 | usb_autopm_put_interface(tp->intf); |
3886 | ||
3887 | out_set_wol: | |
3888 | return ret; | |
21ff2e89 | 3889 | } |
3890 | ||
a5ec27c1 | 3891 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3892 | { | |
3893 | struct r8152 *tp = netdev_priv(dev); | |
3894 | ||
3895 | return tp->msg_enable; | |
3896 | } | |
3897 | ||
3898 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3899 | { | |
3900 | struct r8152 *tp = netdev_priv(dev); | |
3901 | ||
3902 | tp->msg_enable = value; | |
3903 | } | |
3904 | ||
ac718b69 | 3905 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3906 | struct ethtool_drvinfo *info) | |
3907 | { | |
3908 | struct r8152 *tp = netdev_priv(netdev); | |
3909 | ||
b0b46c77 | 3910 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3911 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3912 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3913 | } | |
3914 | ||
3915 | static | |
06144dcf PR |
3916 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
3917 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 3918 | { |
3919 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 3920 | int ret; |
ac718b69 | 3921 | |
3922 | if (!tp->mii.mdio_read) | |
3923 | return -EOPNOTSUPP; | |
3924 | ||
8d4a4d72 | 3925 | ret = usb_autopm_get_interface(tp->intf); |
3926 | if (ret < 0) | |
3927 | goto out; | |
3928 | ||
b5403273 | 3929 | mutex_lock(&tp->control); |
3930 | ||
82c01a84 | 3931 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 3932 | |
b5403273 | 3933 | mutex_unlock(&tp->control); |
3934 | ||
8d4a4d72 | 3935 | usb_autopm_put_interface(tp->intf); |
3936 | ||
3937 | out: | |
3938 | return ret; | |
ac718b69 | 3939 | } |
3940 | ||
06144dcf PR |
3941 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
3942 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 3943 | { |
3944 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3945 | int ret; |
3946 | ||
3947 | ret = usb_autopm_get_interface(tp->intf); | |
3948 | if (ret < 0) | |
3949 | goto out; | |
ac718b69 | 3950 | |
b5403273 | 3951 | mutex_lock(&tp->control); |
3952 | ||
06144dcf PR |
3953 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
3954 | cmd->base.duplex); | |
aa7e26b6 | 3955 | if (!ret) { |
06144dcf PR |
3956 | tp->autoneg = cmd->base.autoneg; |
3957 | tp->speed = cmd->base.speed; | |
3958 | tp->duplex = cmd->base.duplex; | |
aa7e26b6 | 3959 | } |
9a4be1bd | 3960 | |
b5403273 | 3961 | mutex_unlock(&tp->control); |
3962 | ||
9a4be1bd | 3963 | usb_autopm_put_interface(tp->intf); |
3964 | ||
3965 | out: | |
3966 | return ret; | |
ac718b69 | 3967 | } |
3968 | ||
4f1d4d54 | 3969 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3970 | "tx_packets", | |
3971 | "rx_packets", | |
3972 | "tx_errors", | |
3973 | "rx_errors", | |
3974 | "rx_missed", | |
3975 | "align_errors", | |
3976 | "tx_single_collisions", | |
3977 | "tx_multi_collisions", | |
3978 | "rx_unicast", | |
3979 | "rx_broadcast", | |
3980 | "rx_multicast", | |
3981 | "tx_aborted", | |
3982 | "tx_underrun", | |
3983 | }; | |
3984 | ||
3985 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3986 | { | |
3987 | switch (sset) { | |
3988 | case ETH_SS_STATS: | |
3989 | return ARRAY_SIZE(rtl8152_gstrings); | |
3990 | default: | |
3991 | return -EOPNOTSUPP; | |
3992 | } | |
3993 | } | |
3994 | ||
3995 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3996 | struct ethtool_stats *stats, u64 *data) | |
3997 | { | |
3998 | struct r8152 *tp = netdev_priv(dev); | |
3999 | struct tally_counter tally; | |
4000 | ||
0b030244 | 4001 | if (usb_autopm_get_interface(tp->intf) < 0) |
4002 | return; | |
4003 | ||
4f1d4d54 | 4004 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
4005 | ||
0b030244 | 4006 | usb_autopm_put_interface(tp->intf); |
4007 | ||
4f1d4d54 | 4008 | data[0] = le64_to_cpu(tally.tx_packets); |
4009 | data[1] = le64_to_cpu(tally.rx_packets); | |
4010 | data[2] = le64_to_cpu(tally.tx_errors); | |
4011 | data[3] = le32_to_cpu(tally.rx_errors); | |
4012 | data[4] = le16_to_cpu(tally.rx_missed); | |
4013 | data[5] = le16_to_cpu(tally.align_errors); | |
4014 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
4015 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
4016 | data[8] = le64_to_cpu(tally.rx_unicast); | |
4017 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
4018 | data[10] = le32_to_cpu(tally.rx_multicast); | |
4019 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 4020 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 4021 | } |
4022 | ||
4023 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
4024 | { | |
4025 | switch (stringset) { | |
4026 | case ETH_SS_STATS: | |
4027 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
4028 | break; | |
4029 | } | |
4030 | } | |
4031 | ||
df35d283 | 4032 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
4033 | { | |
4034 | u32 ocp_data, lp, adv, supported = 0; | |
4035 | u16 val; | |
4036 | ||
4037 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
4038 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4039 | ||
4040 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
4041 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4042 | ||
4043 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
4044 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4045 | ||
4046 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4047 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4048 | ||
4049 | eee->eee_enabled = !!ocp_data; | |
4050 | eee->eee_active = !!(supported & adv & lp); | |
4051 | eee->supported = supported; | |
4052 | eee->advertised = adv; | |
4053 | eee->lp_advertised = lp; | |
4054 | ||
4055 | return 0; | |
4056 | } | |
4057 | ||
4058 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4059 | { | |
4060 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4061 | ||
4062 | r8152_eee_en(tp, eee->eee_enabled); | |
4063 | ||
4064 | if (!eee->eee_enabled) | |
4065 | val = 0; | |
4066 | ||
4067 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4068 | ||
4069 | return 0; | |
4070 | } | |
4071 | ||
4072 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4073 | { | |
4074 | u32 ocp_data, lp, adv, supported = 0; | |
4075 | u16 val; | |
4076 | ||
4077 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
4078 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4079 | ||
4080 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
4081 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4082 | ||
4083 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
4084 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4085 | ||
4086 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4087 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4088 | ||
4089 | eee->eee_enabled = !!ocp_data; | |
4090 | eee->eee_active = !!(supported & adv & lp); | |
4091 | eee->supported = supported; | |
4092 | eee->advertised = adv; | |
4093 | eee->lp_advertised = lp; | |
4094 | ||
4095 | return 0; | |
4096 | } | |
4097 | ||
4098 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4099 | { | |
4100 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4101 | ||
4102 | r8153_eee_en(tp, eee->eee_enabled); | |
4103 | ||
4104 | if (!eee->eee_enabled) | |
4105 | val = 0; | |
4106 | ||
4107 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4108 | ||
4109 | return 0; | |
4110 | } | |
4111 | ||
4112 | static int | |
4113 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
4114 | { | |
4115 | struct r8152 *tp = netdev_priv(net); | |
4116 | int ret; | |
4117 | ||
4118 | ret = usb_autopm_get_interface(tp->intf); | |
4119 | if (ret < 0) | |
4120 | goto out; | |
4121 | ||
b5403273 | 4122 | mutex_lock(&tp->control); |
4123 | ||
df35d283 | 4124 | ret = tp->rtl_ops.eee_get(tp, edata); |
4125 | ||
b5403273 | 4126 | mutex_unlock(&tp->control); |
4127 | ||
df35d283 | 4128 | usb_autopm_put_interface(tp->intf); |
4129 | ||
4130 | out: | |
4131 | return ret; | |
4132 | } | |
4133 | ||
4134 | static int | |
4135 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
4136 | { | |
4137 | struct r8152 *tp = netdev_priv(net); | |
4138 | int ret; | |
4139 | ||
4140 | ret = usb_autopm_get_interface(tp->intf); | |
4141 | if (ret < 0) | |
4142 | goto out; | |
4143 | ||
b5403273 | 4144 | mutex_lock(&tp->control); |
4145 | ||
df35d283 | 4146 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 4147 | if (!ret) |
4148 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 4149 | |
b5403273 | 4150 | mutex_unlock(&tp->control); |
4151 | ||
df35d283 | 4152 | usb_autopm_put_interface(tp->intf); |
4153 | ||
4154 | out: | |
4155 | return ret; | |
4156 | } | |
4157 | ||
8884f507 | 4158 | static int rtl8152_nway_reset(struct net_device *dev) |
4159 | { | |
4160 | struct r8152 *tp = netdev_priv(dev); | |
4161 | int ret; | |
4162 | ||
4163 | ret = usb_autopm_get_interface(tp->intf); | |
4164 | if (ret < 0) | |
4165 | goto out; | |
4166 | ||
4167 | mutex_lock(&tp->control); | |
4168 | ||
4169 | ret = mii_nway_restart(&tp->mii); | |
4170 | ||
4171 | mutex_unlock(&tp->control); | |
4172 | ||
4173 | usb_autopm_put_interface(tp->intf); | |
4174 | ||
4175 | out: | |
4176 | return ret; | |
4177 | } | |
4178 | ||
efb3dd88 | 4179 | static int rtl8152_get_coalesce(struct net_device *netdev, |
4180 | struct ethtool_coalesce *coalesce) | |
4181 | { | |
4182 | struct r8152 *tp = netdev_priv(netdev); | |
4183 | ||
4184 | switch (tp->version) { | |
4185 | case RTL_VER_01: | |
4186 | case RTL_VER_02: | |
c27b32c2 | 4187 | case RTL_VER_07: |
efb3dd88 | 4188 | return -EOPNOTSUPP; |
4189 | default: | |
4190 | break; | |
4191 | } | |
4192 | ||
4193 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
4194 | ||
4195 | return 0; | |
4196 | } | |
4197 | ||
4198 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
4199 | struct ethtool_coalesce *coalesce) | |
4200 | { | |
4201 | struct r8152 *tp = netdev_priv(netdev); | |
4202 | int ret; | |
4203 | ||
4204 | switch (tp->version) { | |
4205 | case RTL_VER_01: | |
4206 | case RTL_VER_02: | |
c27b32c2 | 4207 | case RTL_VER_07: |
efb3dd88 | 4208 | return -EOPNOTSUPP; |
4209 | default: | |
4210 | break; | |
4211 | } | |
4212 | ||
4213 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
4214 | return -EINVAL; | |
4215 | ||
4216 | ret = usb_autopm_get_interface(tp->intf); | |
4217 | if (ret < 0) | |
4218 | return ret; | |
4219 | ||
4220 | mutex_lock(&tp->control); | |
4221 | ||
4222 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
4223 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
4224 | ||
4225 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
4226 | r8153_set_rx_early_timeout(tp); | |
4227 | } | |
4228 | ||
4229 | mutex_unlock(&tp->control); | |
4230 | ||
4231 | usb_autopm_put_interface(tp->intf); | |
4232 | ||
4233 | return ret; | |
4234 | } | |
4235 | ||
407a471d | 4236 | static const struct ethtool_ops ops = { |
ac718b69 | 4237 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 4238 | .get_link = ethtool_op_get_link, |
8884f507 | 4239 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 4240 | .get_msglevel = rtl8152_get_msglevel, |
4241 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 4242 | .get_wol = rtl8152_get_wol, |
4243 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 4244 | .get_strings = rtl8152_get_strings, |
4245 | .get_sset_count = rtl8152_get_sset_count, | |
4246 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 4247 | .get_coalesce = rtl8152_get_coalesce, |
4248 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 4249 | .get_eee = rtl_ethtool_get_eee, |
4250 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
4251 | .get_link_ksettings = rtl8152_get_link_ksettings, |
4252 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
ac718b69 | 4253 | }; |
4254 | ||
4255 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
4256 | { | |
4257 | struct r8152 *tp = netdev_priv(netdev); | |
4258 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 4259 | int res; |
4260 | ||
6871438c | 4261 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4262 | return -ENODEV; | |
4263 | ||
9a4be1bd | 4264 | res = usb_autopm_get_interface(tp->intf); |
4265 | if (res < 0) | |
4266 | goto out; | |
ac718b69 | 4267 | |
4268 | switch (cmd) { | |
4269 | case SIOCGMIIPHY: | |
4270 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
4271 | break; | |
4272 | ||
4273 | case SIOCGMIIREG: | |
b5403273 | 4274 | mutex_lock(&tp->control); |
ac718b69 | 4275 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 4276 | mutex_unlock(&tp->control); |
ac718b69 | 4277 | break; |
4278 | ||
4279 | case SIOCSMIIREG: | |
4280 | if (!capable(CAP_NET_ADMIN)) { | |
4281 | res = -EPERM; | |
4282 | break; | |
4283 | } | |
b5403273 | 4284 | mutex_lock(&tp->control); |
ac718b69 | 4285 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 4286 | mutex_unlock(&tp->control); |
ac718b69 | 4287 | break; |
4288 | ||
4289 | default: | |
4290 | res = -EOPNOTSUPP; | |
4291 | } | |
4292 | ||
9a4be1bd | 4293 | usb_autopm_put_interface(tp->intf); |
4294 | ||
4295 | out: | |
ac718b69 | 4296 | return res; |
4297 | } | |
4298 | ||
69b4b7a4 | 4299 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
4300 | { | |
4301 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 4302 | int ret; |
69b4b7a4 | 4303 | |
4304 | switch (tp->version) { | |
4305 | case RTL_VER_01: | |
4306 | case RTL_VER_02: | |
c27b32c2 | 4307 | case RTL_VER_07: |
a52ad514 JW |
4308 | dev->mtu = new_mtu; |
4309 | return 0; | |
69b4b7a4 | 4310 | default: |
4311 | break; | |
4312 | } | |
4313 | ||
396e2e23 | 4314 | ret = usb_autopm_get_interface(tp->intf); |
4315 | if (ret < 0) | |
4316 | return ret; | |
4317 | ||
4318 | mutex_lock(&tp->control); | |
4319 | ||
69b4b7a4 | 4320 | dev->mtu = new_mtu; |
4321 | ||
210c4f70 | 4322 | if (netif_running(dev)) { |
4323 | u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE; | |
4324 | ||
4325 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); | |
4326 | ||
4327 | if (netif_carrier_ok(dev)) | |
4328 | r8153_set_rx_early_size(tp); | |
4329 | } | |
396e2e23 | 4330 | |
4331 | mutex_unlock(&tp->control); | |
4332 | ||
4333 | usb_autopm_put_interface(tp->intf); | |
4334 | ||
4335 | return ret; | |
69b4b7a4 | 4336 | } |
4337 | ||
ac718b69 | 4338 | static const struct net_device_ops rtl8152_netdev_ops = { |
4339 | .ndo_open = rtl8152_open, | |
4340 | .ndo_stop = rtl8152_close, | |
4341 | .ndo_do_ioctl = rtl8152_ioctl, | |
4342 | .ndo_start_xmit = rtl8152_start_xmit, | |
4343 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 4344 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 4345 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
4346 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 4347 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 4348 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 4349 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 4350 | }; |
4351 | ||
e3fe0b1a | 4352 | static void rtl8152_unload(struct r8152 *tp) |
4353 | { | |
6871438c | 4354 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4355 | return; | |
4356 | ||
00a5e360 | 4357 | if (tp->version != RTL_VER_01) |
4358 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 4359 | } |
4360 | ||
43779f8d | 4361 | static void rtl8153_unload(struct r8152 *tp) |
4362 | { | |
6871438c | 4363 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4364 | return; | |
4365 | ||
49be1723 | 4366 | r8153_power_cut_en(tp, false); |
43779f8d | 4367 | } |
4368 | ||
55b65475 | 4369 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 4370 | { |
4371 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 4372 | int ret = 0; |
4373 | ||
4374 | switch (tp->version) { | |
4375 | case RTL_VER_01: | |
4376 | case RTL_VER_02: | |
c27b32c2 | 4377 | case RTL_VER_07: |
55b65475 | 4378 | ops->init = r8152b_init; |
4379 | ops->enable = rtl8152_enable; | |
4380 | ops->disable = rtl8152_disable; | |
4381 | ops->up = rtl8152_up; | |
4382 | ops->down = rtl8152_down; | |
4383 | ops->unload = rtl8152_unload; | |
4384 | ops->eee_get = r8152_get_eee; | |
4385 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 4386 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 4387 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 4388 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
43779f8d | 4389 | break; |
4390 | ||
55b65475 | 4391 | case RTL_VER_03: |
4392 | case RTL_VER_04: | |
4393 | case RTL_VER_05: | |
fb02eb4a | 4394 | case RTL_VER_06: |
55b65475 | 4395 | ops->init = r8153_init; |
4396 | ops->enable = rtl8153_enable; | |
4397 | ops->disable = rtl8153_disable; | |
4398 | ops->up = rtl8153_up; | |
4399 | ops->down = rtl8153_down; | |
4400 | ops->unload = rtl8153_unload; | |
4401 | ops->eee_get = r8153_get_eee; | |
4402 | ops->eee_set = r8153_set_eee; | |
2dd49e0f | 4403 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 4404 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 4405 | ops->autosuspend_en = rtl8153_runtime_enable; |
c81229c9 | 4406 | break; |
4407 | ||
4408 | default: | |
55b65475 | 4409 | ret = -ENODEV; |
4410 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 4411 | break; |
4412 | } | |
4413 | ||
4414 | return ret; | |
4415 | } | |
4416 | ||
33928eed | 4417 | static u8 rtl_get_version(struct usb_interface *intf) |
4418 | { | |
4419 | struct usb_device *udev = interface_to_usbdev(intf); | |
4420 | u32 ocp_data = 0; | |
4421 | __le32 *tmp; | |
4422 | u8 version; | |
4423 | int ret; | |
4424 | ||
4425 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
4426 | if (!tmp) | |
4427 | return 0; | |
4428 | ||
4429 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
4430 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
4431 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); | |
4432 | if (ret > 0) | |
4433 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
4434 | ||
4435 | kfree(tmp); | |
4436 | ||
4437 | switch (ocp_data) { | |
4438 | case 0x4c00: | |
4439 | version = RTL_VER_01; | |
4440 | break; | |
4441 | case 0x4c10: | |
4442 | version = RTL_VER_02; | |
4443 | break; | |
4444 | case 0x5c00: | |
4445 | version = RTL_VER_03; | |
4446 | break; | |
4447 | case 0x5c10: | |
4448 | version = RTL_VER_04; | |
4449 | break; | |
4450 | case 0x5c20: | |
4451 | version = RTL_VER_05; | |
4452 | break; | |
4453 | case 0x5c30: | |
4454 | version = RTL_VER_06; | |
4455 | break; | |
c27b32c2 | 4456 | case 0x4800: |
4457 | version = RTL_VER_07; | |
4458 | break; | |
33928eed | 4459 | default: |
4460 | version = RTL_VER_UNKNOWN; | |
4461 | dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); | |
4462 | break; | |
4463 | } | |
4464 | ||
eb3c28c1 ON |
4465 | dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); |
4466 | ||
33928eed | 4467 | return version; |
4468 | } | |
4469 | ||
ac718b69 | 4470 | static int rtl8152_probe(struct usb_interface *intf, |
4471 | const struct usb_device_id *id) | |
4472 | { | |
4473 | struct usb_device *udev = interface_to_usbdev(intf); | |
33928eed | 4474 | u8 version = rtl_get_version(intf); |
ac718b69 | 4475 | struct r8152 *tp; |
4476 | struct net_device *netdev; | |
ebc2ec48 | 4477 | int ret; |
ac718b69 | 4478 | |
33928eed | 4479 | if (version == RTL_VER_UNKNOWN) |
4480 | return -ENODEV; | |
4481 | ||
10c32717 | 4482 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
4483 | usb_driver_set_configuration(udev, 1); | |
4484 | return -ENODEV; | |
4485 | } | |
4486 | ||
4487 | usb_reset_device(udev); | |
ac718b69 | 4488 | netdev = alloc_etherdev(sizeof(struct r8152)); |
4489 | if (!netdev) { | |
4a8deae2 | 4490 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 4491 | return -ENOMEM; |
4492 | } | |
4493 | ||
ebc2ec48 | 4494 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 4495 | tp = netdev_priv(netdev); |
4496 | tp->msg_enable = 0x7FFF; | |
4497 | ||
e3ad412a | 4498 | tp->udev = udev; |
4499 | tp->netdev = netdev; | |
4500 | tp->intf = intf; | |
33928eed | 4501 | tp->version = version; |
4502 | ||
4503 | switch (version) { | |
4504 | case RTL_VER_01: | |
4505 | case RTL_VER_02: | |
c27b32c2 | 4506 | case RTL_VER_07: |
33928eed | 4507 | tp->mii.supports_gmii = 0; |
4508 | break; | |
4509 | default: | |
4510 | tp->mii.supports_gmii = 1; | |
4511 | break; | |
4512 | } | |
e3ad412a | 4513 | |
55b65475 | 4514 | ret = rtl_ops_init(tp); |
31ca1dec | 4515 | if (ret) |
4516 | goto out; | |
c81229c9 | 4517 | |
b5403273 | 4518 | mutex_init(&tp->control); |
ac718b69 | 4519 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 4520 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
ac718b69 | 4521 | |
ac718b69 | 4522 | netdev->netdev_ops = &rtl8152_netdev_ops; |
4523 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 4524 | |
60c89071 | 4525 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4526 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 4527 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
4528 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 4529 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4530 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 4531 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 4532 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 4533 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
4534 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
4535 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 4536 | |
19c0f40d | 4537 | if (tp->version == RTL_VER_01) { |
4538 | netdev->features &= ~NETIF_F_RXCSUM; | |
4539 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
4540 | } | |
4541 | ||
7ad24ea4 | 4542 | netdev->ethtool_ops = &ops; |
60c89071 | 4543 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 4544 | |
f77f0aee JW |
4545 | /* MTU range: 68 - 1500 or 9194 */ |
4546 | netdev->min_mtu = ETH_MIN_MTU; | |
4547 | switch (tp->version) { | |
4548 | case RTL_VER_01: | |
4549 | case RTL_VER_02: | |
4550 | netdev->max_mtu = ETH_DATA_LEN; | |
4551 | break; | |
4552 | default: | |
4553 | netdev->max_mtu = RTL8153_MAX_MTU; | |
4554 | break; | |
4555 | } | |
4556 | ||
ac718b69 | 4557 | tp->mii.dev = netdev; |
4558 | tp->mii.mdio_read = read_mii_word; | |
4559 | tp->mii.mdio_write = write_mii_word; | |
4560 | tp->mii.phy_id_mask = 0x3f; | |
4561 | tp->mii.reg_num_mask = 0x1f; | |
4562 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 4563 | |
aa7e26b6 | 4564 | tp->autoneg = AUTONEG_ENABLE; |
4565 | tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; | |
4566 | tp->duplex = DUPLEX_FULL; | |
4567 | ||
9a4be1bd | 4568 | intf->needs_remote_wakeup = 1; |
4569 | ||
c81229c9 | 4570 | tp->rtl_ops.init(tp); |
a028a9e0 | 4571 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
ac718b69 | 4572 | set_ethernet_addr(tp); |
4573 | ||
ac718b69 | 4574 | usb_set_intfdata(intf, tp); |
d823ab68 | 4575 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 4576 | |
ebc2ec48 | 4577 | ret = register_netdev(netdev); |
4578 | if (ret != 0) { | |
4a8deae2 | 4579 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 4580 | goto out1; |
ac718b69 | 4581 | } |
4582 | ||
7daed8dc | 4583 | if (!rtl_can_wakeup(tp)) |
4584 | __rtl_set_wol(tp, 0); | |
4585 | ||
21ff2e89 | 4586 | tp->saved_wolopts = __rtl_get_wol(tp); |
4587 | if (tp->saved_wolopts) | |
4588 | device_set_wakeup_enable(&udev->dev, true); | |
4589 | else | |
4590 | device_set_wakeup_enable(&udev->dev, false); | |
4591 | ||
4a8deae2 | 4592 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 4593 | |
4594 | return 0; | |
4595 | ||
ac718b69 | 4596 | out1: |
d823ab68 | 4597 | netif_napi_del(&tp->napi); |
ebc2ec48 | 4598 | usb_set_intfdata(intf, NULL); |
ac718b69 | 4599 | out: |
4600 | free_netdev(netdev); | |
ebc2ec48 | 4601 | return ret; |
ac718b69 | 4602 | } |
4603 | ||
ac718b69 | 4604 | static void rtl8152_disconnect(struct usb_interface *intf) |
4605 | { | |
4606 | struct r8152 *tp = usb_get_intfdata(intf); | |
4607 | ||
4608 | usb_set_intfdata(intf, NULL); | |
4609 | if (tp) { | |
f561de33 | 4610 | struct usb_device *udev = tp->udev; |
4611 | ||
4612 | if (udev->state == USB_STATE_NOTATTACHED) | |
4613 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
4614 | ||
d823ab68 | 4615 | netif_napi_del(&tp->napi); |
ac718b69 | 4616 | unregister_netdev(tp->netdev); |
a028a9e0 | 4617 | cancel_delayed_work_sync(&tp->hw_phy_work); |
c81229c9 | 4618 | tp->rtl_ops.unload(tp); |
ac718b69 | 4619 | free_netdev(tp->netdev); |
4620 | } | |
4621 | } | |
4622 | ||
d9a28c5b | 4623 | #define REALTEK_USB_DEVICE(vend, prod) \ |
4624 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
4625 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
4626 | .idVendor = (vend), \ | |
4627 | .idProduct = (prod), \ | |
4628 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
4629 | }, \ | |
4630 | { \ | |
4631 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
4632 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
4633 | .idVendor = (vend), \ | |
4634 | .idProduct = (prod), \ | |
4635 | .bInterfaceClass = USB_CLASS_COMM, \ | |
4636 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
4637 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
4638 | ||
ac718b69 | 4639 | /* table of devices that work with this driver */ |
4640 | static struct usb_device_id rtl8152_table[] = { | |
c27b32c2 | 4641 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, |
d9a28c5b | 4642 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
4643 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
d5b07ccc RR |
4644 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, |
4645 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, | |
d9a28c5b | 4646 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, |
1006da19 | 4647 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d248cafc | 4648 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, |
4649 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, | |
4650 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, | |
4651 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, | |
4652 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, | |
d065c3c1 | 4653 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 4654 | {} |
4655 | }; | |
4656 | ||
4657 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
4658 | ||
4659 | static struct usb_driver rtl8152_driver = { | |
4660 | .name = MODULENAME, | |
ebc2ec48 | 4661 | .id_table = rtl8152_table, |
ac718b69 | 4662 | .probe = rtl8152_probe, |
4663 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 4664 | .suspend = rtl8152_suspend, |
ebc2ec48 | 4665 | .resume = rtl8152_resume, |
7ec2541a | 4666 | .reset_resume = rtl8152_reset_resume, |
e501139a | 4667 | .pre_reset = rtl8152_pre_reset, |
4668 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 4669 | .supports_autosuspend = 1, |
a634782f | 4670 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 4671 | }; |
4672 | ||
b4236daa | 4673 | module_usb_driver(rtl8152_driver); |
ac718b69 | 4674 | |
4675 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4676 | MODULE_DESCRIPTION(DRIVER_DESC); | |
4677 | MODULE_LICENSE("GPL"); | |
c961e877 | 4678 | MODULE_VERSION(DRIVER_VERSION); |