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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
ac718b69 | 27 | |
28 | /* Version Information */ | |
204c8704 | 29 | #define DRIVER_VERSION "v1.06.1 (2014/10/01)" |
ac718b69 | 30 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 31 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 32 | #define MODULENAME "r8152" |
33 | ||
34 | #define R8152_PHY_ID 32 | |
35 | ||
36 | #define PLA_IDR 0xc000 | |
37 | #define PLA_RCR 0xc010 | |
38 | #define PLA_RMS 0xc016 | |
39 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
40 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
41 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
42 | #define PLA_FMC 0xc0b4 | |
43 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 44 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 45 | #define PLA_MAR 0xcd00 |
43779f8d | 46 | #define PLA_BACKUP 0xd000 |
ac718b69 | 47 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 48 | #define PLA_TEREDO_TIMER 0xd2cc |
49 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 50 | #define PLA_LEDSEL 0xdd90 |
51 | #define PLA_LED_FEATURE 0xdd92 | |
52 | #define PLA_PHYAR 0xde00 | |
43779f8d | 53 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 54 | #define PLA_GPHY_INTR_IMR 0xe022 |
55 | #define PLA_EEE_CR 0xe040 | |
56 | #define PLA_EEEP_CR 0xe080 | |
57 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 58 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
59 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
60 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
61 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 62 | #define PLA_TCR0 0xe610 |
63 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 64 | #define PLA_MTPS 0xe615 |
ac718b69 | 65 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 66 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 67 | #define PLA_CR 0xe813 |
68 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 69 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
70 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 71 | #define PLA_CONFIG5 0xe822 |
72 | #define PLA_PHY_PWR 0xe84c | |
73 | #define PLA_OOB_CTRL 0xe84f | |
74 | #define PLA_CPCR 0xe854 | |
75 | #define PLA_MISC_0 0xe858 | |
76 | #define PLA_MISC_1 0xe85a | |
77 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 78 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 79 | #define PLA_SFF_STS_7 0xe8de |
80 | #define PLA_PHYSTATUS 0xe908 | |
81 | #define PLA_BP_BA 0xfc26 | |
82 | #define PLA_BP_0 0xfc28 | |
83 | #define PLA_BP_1 0xfc2a | |
84 | #define PLA_BP_2 0xfc2c | |
85 | #define PLA_BP_3 0xfc2e | |
86 | #define PLA_BP_4 0xfc30 | |
87 | #define PLA_BP_5 0xfc32 | |
88 | #define PLA_BP_6 0xfc34 | |
89 | #define PLA_BP_7 0xfc36 | |
43779f8d | 90 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 91 | |
43779f8d | 92 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 93 | #define USB_DEV_STAT 0xb808 |
94 | #define USB_USB_CTRL 0xd406 | |
95 | #define USB_PHY_CTRL 0xd408 | |
96 | #define USB_TX_AGG 0xd40a | |
97 | #define USB_RX_BUF_TH 0xd40c | |
98 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 99 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 100 | #define USB_PM_CTRL_STATUS 0xd432 |
101 | #define USB_TX_DMA 0xd434 | |
43779f8d | 102 | #define USB_TOLERANCE 0xd490 |
103 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 104 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 105 | #define USB_MISC_0 0xd81a |
106 | #define USB_POWER_CUT 0xd80a | |
107 | #define USB_AFE_CTRL2 0xd824 | |
108 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 109 | #define USB_BP_BA 0xfc26 |
110 | #define USB_BP_0 0xfc28 | |
111 | #define USB_BP_1 0xfc2a | |
112 | #define USB_BP_2 0xfc2c | |
113 | #define USB_BP_3 0xfc2e | |
114 | #define USB_BP_4 0xfc30 | |
115 | #define USB_BP_5 0xfc32 | |
116 | #define USB_BP_6 0xfc34 | |
117 | #define USB_BP_7 0xfc36 | |
43779f8d | 118 | #define USB_BP_EN 0xfc38 |
ac718b69 | 119 | |
120 | /* OCP Registers */ | |
121 | #define OCP_ALDPS_CONFIG 0x2010 | |
122 | #define OCP_EEE_CONFIG1 0x2080 | |
123 | #define OCP_EEE_CONFIG2 0x2092 | |
124 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 125 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 126 | #define OCP_EEE_AR 0xa41a |
127 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 128 | #define OCP_PHY_STATUS 0xa420 |
129 | #define OCP_POWER_CFG 0xa430 | |
130 | #define OCP_EEE_CFG 0xa432 | |
131 | #define OCP_SRAM_ADDR 0xa436 | |
132 | #define OCP_SRAM_DATA 0xa438 | |
133 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 134 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 135 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 136 | #define OCP_EEE_LPABLE 0xa5d2 |
43779f8d | 137 | #define OCP_ADC_CFG 0xbc06 |
138 | ||
139 | /* SRAM Register */ | |
140 | #define SRAM_LPF_CFG 0x8012 | |
141 | #define SRAM_10M_AMP1 0x8080 | |
142 | #define SRAM_10M_AMP2 0x8082 | |
143 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 144 | |
145 | /* PLA_RCR */ | |
146 | #define RCR_AAP 0x00000001 | |
147 | #define RCR_APM 0x00000002 | |
148 | #define RCR_AM 0x00000004 | |
149 | #define RCR_AB 0x00000008 | |
150 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
151 | ||
152 | /* PLA_RXFIFO_CTRL0 */ | |
153 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
154 | #define RXFIFO_THR1_OOB 0x01800003 | |
155 | ||
156 | /* PLA_RXFIFO_CTRL1 */ | |
157 | #define RXFIFO_THR2_FULL 0x00000060 | |
158 | #define RXFIFO_THR2_HIGH 0x00000038 | |
159 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 160 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 161 | |
162 | /* PLA_RXFIFO_CTRL2 */ | |
163 | #define RXFIFO_THR3_FULL 0x00000078 | |
164 | #define RXFIFO_THR3_HIGH 0x00000048 | |
165 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 166 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 167 | |
168 | /* PLA_TXFIFO_CTRL */ | |
169 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 170 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 171 | |
172 | /* PLA_FMC */ | |
173 | #define FMC_FCR_MCU_EN 0x0001 | |
174 | ||
175 | /* PLA_EEEP_CR */ | |
176 | #define EEEP_CR_EEEP_TX 0x0002 | |
177 | ||
43779f8d | 178 | /* PLA_WDT6_CTRL */ |
179 | #define WDT6_SET_MODE 0x0010 | |
180 | ||
ac718b69 | 181 | /* PLA_TCR0 */ |
182 | #define TCR0_TX_EMPTY 0x0800 | |
183 | #define TCR0_AUTO_FIFO 0x0080 | |
184 | ||
185 | /* PLA_TCR1 */ | |
186 | #define VERSION_MASK 0x7cf0 | |
187 | ||
69b4b7a4 | 188 | /* PLA_MTPS */ |
189 | #define MTPS_JUMBO (12 * 1024 / 64) | |
190 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
191 | ||
4f1d4d54 | 192 | /* PLA_RSTTALLY */ |
193 | #define TALLY_RESET 0x0001 | |
194 | ||
ac718b69 | 195 | /* PLA_CR */ |
196 | #define CR_RST 0x10 | |
197 | #define CR_RE 0x08 | |
198 | #define CR_TE 0x04 | |
199 | ||
200 | /* PLA_CRWECR */ | |
201 | #define CRWECR_NORAML 0x00 | |
202 | #define CRWECR_CONFIG 0xc0 | |
203 | ||
204 | /* PLA_OOB_CTRL */ | |
205 | #define NOW_IS_OOB 0x80 | |
206 | #define TXFIFO_EMPTY 0x20 | |
207 | #define RXFIFO_EMPTY 0x10 | |
208 | #define LINK_LIST_READY 0x02 | |
209 | #define DIS_MCU_CLROOB 0x01 | |
210 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
211 | ||
212 | /* PLA_MISC_1 */ | |
213 | #define RXDY_GATED_EN 0x0008 | |
214 | ||
215 | /* PLA_SFF_STS_7 */ | |
216 | #define RE_INIT_LL 0x8000 | |
217 | #define MCU_BORW_EN 0x4000 | |
218 | ||
219 | /* PLA_CPCR */ | |
220 | #define CPCR_RX_VLAN 0x0040 | |
221 | ||
222 | /* PLA_CFG_WOL */ | |
223 | #define MAGIC_EN 0x0001 | |
224 | ||
43779f8d | 225 | /* PLA_TEREDO_CFG */ |
226 | #define TEREDO_SEL 0x8000 | |
227 | #define TEREDO_WAKE_MASK 0x7f00 | |
228 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
229 | #define OOB_TEREDO_EN 0x0001 | |
230 | ||
ac718b69 | 231 | /* PAL_BDC_CR */ |
232 | #define ALDPS_PROXY_MODE 0x0001 | |
233 | ||
21ff2e89 | 234 | /* PLA_CONFIG34 */ |
235 | #define LINK_ON_WAKE_EN 0x0010 | |
236 | #define LINK_OFF_WAKE_EN 0x0008 | |
237 | ||
ac718b69 | 238 | /* PLA_CONFIG5 */ |
21ff2e89 | 239 | #define BWF_EN 0x0040 |
240 | #define MWF_EN 0x0020 | |
241 | #define UWF_EN 0x0010 | |
ac718b69 | 242 | #define LAN_WAKE_EN 0x0002 |
243 | ||
244 | /* PLA_LED_FEATURE */ | |
245 | #define LED_MODE_MASK 0x0700 | |
246 | ||
247 | /* PLA_PHY_PWR */ | |
248 | #define TX_10M_IDLE_EN 0x0080 | |
249 | #define PFM_PWM_SWITCH 0x0040 | |
250 | ||
251 | /* PLA_MAC_PWR_CTRL */ | |
252 | #define D3_CLK_GATED_EN 0x00004000 | |
253 | #define MCU_CLK_RATIO 0x07010f07 | |
254 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 255 | #define ALDPS_SPDWN_RATIO 0x0f87 |
256 | ||
257 | /* PLA_MAC_PWR_CTRL2 */ | |
258 | #define EEE_SPDWN_RATIO 0x8007 | |
259 | ||
260 | /* PLA_MAC_PWR_CTRL3 */ | |
261 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
262 | #define SUSPEND_SPDWN_EN 0x0004 | |
263 | #define U1U2_SPDWN_EN 0x0002 | |
264 | #define L1_SPDWN_EN 0x0001 | |
265 | ||
266 | /* PLA_MAC_PWR_CTRL4 */ | |
267 | #define PWRSAVE_SPDWN_EN 0x1000 | |
268 | #define RXDV_SPDWN_EN 0x0800 | |
269 | #define TX10MIDLE_EN 0x0100 | |
270 | #define TP100_SPDWN_EN 0x0020 | |
271 | #define TP500_SPDWN_EN 0x0010 | |
272 | #define TP1000_SPDWN_EN 0x0008 | |
273 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 274 | |
275 | /* PLA_GPHY_INTR_IMR */ | |
276 | #define GPHY_STS_MSK 0x0001 | |
277 | #define SPEED_DOWN_MSK 0x0002 | |
278 | #define SPDWN_RXDV_MSK 0x0004 | |
279 | #define SPDWN_LINKCHG_MSK 0x0008 | |
280 | ||
281 | /* PLA_PHYAR */ | |
282 | #define PHYAR_FLAG 0x80000000 | |
283 | ||
284 | /* PLA_EEE_CR */ | |
285 | #define EEE_RX_EN 0x0001 | |
286 | #define EEE_TX_EN 0x0002 | |
287 | ||
43779f8d | 288 | /* PLA_BOOT_CTRL */ |
289 | #define AUTOLOAD_DONE 0x0002 | |
290 | ||
ac718b69 | 291 | /* USB_DEV_STAT */ |
292 | #define STAT_SPEED_MASK 0x0006 | |
293 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 294 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 295 | |
296 | /* USB_TX_AGG */ | |
297 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
298 | ||
299 | /* USB_RX_BUF_TH */ | |
43779f8d | 300 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 301 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 302 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 303 | |
304 | /* USB_TX_DMA */ | |
305 | #define TEST_MODE_DISABLE 0x00000001 | |
306 | #define TX_SIZE_ADJUST1 0x00000100 | |
307 | ||
308 | /* USB_UPS_CTRL */ | |
309 | #define POWER_CUT 0x0100 | |
310 | ||
311 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 312 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 313 | |
314 | /* USB_USB_CTRL */ | |
315 | #define RX_AGG_DISABLE 0x0010 | |
316 | ||
43779f8d | 317 | /* USB_U2P3_CTRL */ |
318 | #define U2P3_ENABLE 0x0001 | |
319 | ||
320 | /* USB_POWER_CUT */ | |
321 | #define PWR_EN 0x0001 | |
322 | #define PHASE2_EN 0x0008 | |
323 | ||
324 | /* USB_MISC_0 */ | |
325 | #define PCUT_STATUS 0x0001 | |
326 | ||
327 | /* USB_RX_EARLY_AGG */ | |
328 | #define EARLY_AGG_SUPPER 0x0e832981 | |
329 | #define EARLY_AGG_HIGH 0x0e837a12 | |
330 | #define EARLY_AGG_SLOW 0x0e83ffff | |
331 | ||
332 | /* USB_WDT11_CTRL */ | |
333 | #define TIMER11_EN 0x0001 | |
334 | ||
335 | /* USB_LPM_CTRL */ | |
336 | #define LPM_TIMER_MASK 0x0c | |
337 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
338 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
339 | ||
340 | /* USB_AFE_CTRL2 */ | |
341 | #define SEN_VAL_MASK 0xf800 | |
342 | #define SEN_VAL_NORMAL 0xa000 | |
343 | #define SEL_RXIDLE 0x0100 | |
344 | ||
ac718b69 | 345 | /* OCP_ALDPS_CONFIG */ |
346 | #define ENPWRSAVE 0x8000 | |
347 | #define ENPDNPS 0x0200 | |
348 | #define LINKENA 0x0100 | |
349 | #define DIS_SDSAVE 0x0010 | |
350 | ||
43779f8d | 351 | /* OCP_PHY_STATUS */ |
352 | #define PHY_STAT_MASK 0x0007 | |
353 | #define PHY_STAT_LAN_ON 3 | |
354 | #define PHY_STAT_PWRDN 5 | |
355 | ||
356 | /* OCP_POWER_CFG */ | |
357 | #define EEE_CLKDIV_EN 0x8000 | |
358 | #define EN_ALDPS 0x0004 | |
359 | #define EN_10M_PLLOFF 0x0001 | |
360 | ||
ac718b69 | 361 | /* OCP_EEE_CONFIG1 */ |
362 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
363 | #define RG_MATCLR_EN 0x4000 | |
364 | #define EEE_10_CAP 0x2000 | |
365 | #define EEE_NWAY_EN 0x1000 | |
366 | #define TX_QUIET_EN 0x0200 | |
367 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 368 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 369 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 370 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
371 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
372 | ||
373 | /* OCP_EEE_CONFIG2 */ | |
374 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
375 | #define RG_DACQUIET_EN 0x0400 | |
376 | #define RG_LDVQUIET_EN 0x0200 | |
377 | #define RG_CKRSEL 0x0020 | |
378 | #define RG_EEEPRG_EN 0x0010 | |
379 | ||
380 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 381 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 382 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 383 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
384 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
385 | ||
386 | /* OCP_EEE_AR */ | |
387 | /* bit[15:14] function */ | |
388 | #define FUN_ADDR 0x0000 | |
389 | #define FUN_DATA 0x4000 | |
390 | /* bit[4:0] device addr */ | |
ac718b69 | 391 | |
43779f8d | 392 | /* OCP_EEE_CFG */ |
393 | #define CTAP_SHORT_EN 0x0040 | |
394 | #define EEE10_EN 0x0010 | |
395 | ||
396 | /* OCP_DOWN_SPEED */ | |
397 | #define EN_10M_BGOFF 0x0080 | |
398 | ||
43779f8d | 399 | /* OCP_ADC_CFG */ |
400 | #define CKADSEL_L 0x0100 | |
401 | #define ADC_EN 0x0080 | |
402 | #define EN_EMI_L 0x0040 | |
403 | ||
404 | /* SRAM_LPF_CFG */ | |
405 | #define LPF_AUTO_TUNE 0x8000 | |
406 | ||
407 | /* SRAM_10M_AMP1 */ | |
408 | #define GDAC_IB_UPALL 0x0008 | |
409 | ||
410 | /* SRAM_10M_AMP2 */ | |
411 | #define AMP_DN 0x0200 | |
412 | ||
413 | /* SRAM_IMPEDANCE */ | |
414 | #define RX_DRIVING_MASK 0x6000 | |
415 | ||
ac718b69 | 416 | enum rtl_register_content { |
43779f8d | 417 | _1000bps = 0x10, |
ac718b69 | 418 | _100bps = 0x08, |
419 | _10bps = 0x04, | |
420 | LINK_STATUS = 0x02, | |
421 | FULL_DUP = 0x01, | |
422 | }; | |
423 | ||
1764bcd9 | 424 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 425 | #define RTL8152_MAX_RX 10 |
40a82917 | 426 | #define INTBUFSIZE 2 |
8e1f51bd | 427 | #define CRC_SIZE 4 |
428 | #define TX_ALIGN 4 | |
429 | #define RX_ALIGN 8 | |
40a82917 | 430 | |
431 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 432 | |
ac718b69 | 433 | #define RTL8152_REQT_READ 0xc0 |
434 | #define RTL8152_REQT_WRITE 0x40 | |
435 | #define RTL8152_REQ_GET_REGS 0x05 | |
436 | #define RTL8152_REQ_SET_REGS 0x05 | |
437 | ||
438 | #define BYTE_EN_DWORD 0xff | |
439 | #define BYTE_EN_WORD 0x33 | |
440 | #define BYTE_EN_BYTE 0x11 | |
441 | #define BYTE_EN_SIX_BYTES 0x3f | |
442 | #define BYTE_EN_START_MASK 0x0f | |
443 | #define BYTE_EN_END_MASK 0xf0 | |
444 | ||
69b4b7a4 | 445 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
446 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 447 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 448 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 449 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
ac718b69 | 450 | |
451 | /* rtl8152 flags */ | |
452 | enum rtl8152_flags { | |
453 | RTL8152_UNPLUG = 0, | |
ac718b69 | 454 | RTL8152_SET_RX_MODE, |
40a82917 | 455 | WORK_ENABLE, |
456 | RTL8152_LINK_CHG, | |
9a4be1bd | 457 | SELECTIVE_SUSPEND, |
aa66a5f1 | 458 | PHY_RESET, |
0c3121fc | 459 | SCHEDULE_TASKLET, |
ac718b69 | 460 | }; |
461 | ||
462 | /* Define these values to match your device */ | |
463 | #define VENDOR_ID_REALTEK 0x0bda | |
464 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 465 | #define PRODUCT_ID_RTL8153 0x8153 |
466 | ||
467 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
468 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 469 | |
470 | #define MCU_TYPE_PLA 0x0100 | |
471 | #define MCU_TYPE_USB 0x0000 | |
472 | ||
c7de7dec | 473 | #define REALTEK_USB_DEVICE(vend, prod) \ |
474 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
475 | ||
4f1d4d54 | 476 | struct tally_counter { |
477 | __le64 tx_packets; | |
478 | __le64 rx_packets; | |
479 | __le64 tx_errors; | |
480 | __le32 rx_errors; | |
481 | __le16 rx_missed; | |
482 | __le16 align_errors; | |
483 | __le32 tx_one_collision; | |
484 | __le32 tx_multi_collision; | |
485 | __le64 rx_unicast; | |
486 | __le64 rx_broadcast; | |
487 | __le32 rx_multicast; | |
488 | __le16 tx_aborted; | |
489 | __le16 tx_underun; | |
490 | }; | |
491 | ||
ac718b69 | 492 | struct rx_desc { |
500b6d7e | 493 | __le32 opts1; |
ac718b69 | 494 | #define RX_LEN_MASK 0x7fff |
565cab0a | 495 | |
500b6d7e | 496 | __le32 opts2; |
565cab0a | 497 | #define RD_UDP_CS (1 << 23) |
498 | #define RD_TCP_CS (1 << 22) | |
6128d1bb | 499 | #define RD_IPV6_CS (1 << 20) |
565cab0a | 500 | #define RD_IPV4_CS (1 << 19) |
501 | ||
500b6d7e | 502 | __le32 opts3; |
565cab0a | 503 | #define IPF (1 << 23) /* IP checksum fail */ |
504 | #define UDPF (1 << 22) /* UDP checksum fail */ | |
505 | #define TCPF (1 << 21) /* TCP checksum fail */ | |
c5554298 | 506 | #define RX_VLAN_TAG (1 << 16) |
565cab0a | 507 | |
500b6d7e | 508 | __le32 opts4; |
509 | __le32 opts5; | |
510 | __le32 opts6; | |
ac718b69 | 511 | }; |
512 | ||
513 | struct tx_desc { | |
500b6d7e | 514 | __le32 opts1; |
ac718b69 | 515 | #define TX_FS (1 << 31) /* First segment of a packet */ |
516 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
60c89071 | 517 | #define GTSENDV4 (1 << 28) |
6128d1bb | 518 | #define GTSENDV6 (1 << 27) |
60c89071 | 519 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 520 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 521 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 522 | |
500b6d7e | 523 | __le32 opts2; |
5bd23881 | 524 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
525 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
526 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
527 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
60c89071 | 528 | #define MSS_SHIFT 17 |
529 | #define MSS_MAX 0x7ffU | |
530 | #define TCPHO_SHIFT 17 | |
6128d1bb | 531 | #define TCPHO_MAX 0x7ffU |
c5554298 | 532 | #define TX_VLAN_TAG (1 << 16) |
ac718b69 | 533 | }; |
534 | ||
dff4e8ad | 535 | struct r8152; |
536 | ||
ebc2ec48 | 537 | struct rx_agg { |
538 | struct list_head list; | |
539 | struct urb *urb; | |
dff4e8ad | 540 | struct r8152 *context; |
ebc2ec48 | 541 | void *buffer; |
542 | void *head; | |
543 | }; | |
544 | ||
545 | struct tx_agg { | |
546 | struct list_head list; | |
547 | struct urb *urb; | |
dff4e8ad | 548 | struct r8152 *context; |
ebc2ec48 | 549 | void *buffer; |
550 | void *head; | |
551 | u32 skb_num; | |
552 | u32 skb_len; | |
553 | }; | |
554 | ||
ac718b69 | 555 | struct r8152 { |
556 | unsigned long flags; | |
557 | struct usb_device *udev; | |
558 | struct tasklet_struct tl; | |
40a82917 | 559 | struct usb_interface *intf; |
ac718b69 | 560 | struct net_device *netdev; |
40a82917 | 561 | struct urb *intr_urb; |
ebc2ec48 | 562 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
563 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
564 | struct list_head rx_done, tx_free; | |
565 | struct sk_buff_head tx_queue; | |
566 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 567 | struct delayed_work schedule; |
568 | struct mii_if_info mii; | |
c81229c9 | 569 | |
570 | struct rtl_ops { | |
571 | void (*init)(struct r8152 *); | |
572 | int (*enable)(struct r8152 *); | |
573 | void (*disable)(struct r8152 *); | |
7e9da481 | 574 | void (*up)(struct r8152 *); |
c81229c9 | 575 | void (*down)(struct r8152 *); |
576 | void (*unload)(struct r8152 *); | |
df35d283 | 577 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
578 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
c81229c9 | 579 | } rtl_ops; |
580 | ||
40a82917 | 581 | int intr_interval; |
21ff2e89 | 582 | u32 saved_wolopts; |
ac718b69 | 583 | u32 msg_enable; |
dd1b119c | 584 | u32 tx_qlen; |
ac718b69 | 585 | u16 ocp_base; |
40a82917 | 586 | u8 *intr_buff; |
ac718b69 | 587 | u8 version; |
588 | u8 speed; | |
589 | }; | |
590 | ||
591 | enum rtl_version { | |
592 | RTL_VER_UNKNOWN = 0, | |
593 | RTL_VER_01, | |
43779f8d | 594 | RTL_VER_02, |
595 | RTL_VER_03, | |
596 | RTL_VER_04, | |
597 | RTL_VER_05, | |
598 | RTL_VER_MAX | |
ac718b69 | 599 | }; |
600 | ||
60c89071 | 601 | enum tx_csum_stat { |
602 | TX_CSUM_SUCCESS = 0, | |
603 | TX_CSUM_TSO, | |
604 | TX_CSUM_NONE | |
605 | }; | |
606 | ||
ac718b69 | 607 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
608 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
609 | */ | |
610 | static const int multicast_filter_limit = 32; | |
52aec126 | 611 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 612 | |
52aec126 | 613 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 614 | VLAN_ETH_HLEN - VLAN_HLEN) |
615 | ||
ac718b69 | 616 | static |
617 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
618 | { | |
31787f53 | 619 | int ret; |
620 | void *tmp; | |
621 | ||
622 | tmp = kmalloc(size, GFP_KERNEL); | |
623 | if (!tmp) | |
624 | return -ENOMEM; | |
625 | ||
626 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 627 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
628 | value, index, tmp, size, 500); | |
31787f53 | 629 | |
630 | memcpy(data, tmp, size); | |
631 | kfree(tmp); | |
632 | ||
633 | return ret; | |
ac718b69 | 634 | } |
635 | ||
636 | static | |
637 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
638 | { | |
31787f53 | 639 | int ret; |
640 | void *tmp; | |
641 | ||
c4438f03 | 642 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 643 | if (!tmp) |
644 | return -ENOMEM; | |
645 | ||
31787f53 | 646 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 647 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
648 | value, index, tmp, size, 500); | |
31787f53 | 649 | |
650 | kfree(tmp); | |
db8515ef | 651 | |
31787f53 | 652 | return ret; |
ac718b69 | 653 | } |
654 | ||
655 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 656 | void *data, u16 type) |
ac718b69 | 657 | { |
45f4a19f | 658 | u16 limit = 64; |
659 | int ret = 0; | |
ac718b69 | 660 | |
661 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
662 | return -ENODEV; | |
663 | ||
664 | /* both size and indix must be 4 bytes align */ | |
665 | if ((size & 3) || !size || (index & 3) || !data) | |
666 | return -EPERM; | |
667 | ||
668 | if ((u32)index + (u32)size > 0xffff) | |
669 | return -EPERM; | |
670 | ||
671 | while (size) { | |
672 | if (size > limit) { | |
673 | ret = get_registers(tp, index, type, limit, data); | |
674 | if (ret < 0) | |
675 | break; | |
676 | ||
677 | index += limit; | |
678 | data += limit; | |
679 | size -= limit; | |
680 | } else { | |
681 | ret = get_registers(tp, index, type, size, data); | |
682 | if (ret < 0) | |
683 | break; | |
684 | ||
685 | index += size; | |
686 | data += size; | |
687 | size = 0; | |
688 | break; | |
689 | } | |
690 | } | |
691 | ||
692 | return ret; | |
693 | } | |
694 | ||
695 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 696 | u16 size, void *data, u16 type) |
ac718b69 | 697 | { |
45f4a19f | 698 | int ret; |
699 | u16 byteen_start, byteen_end, byen; | |
700 | u16 limit = 512; | |
ac718b69 | 701 | |
702 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
703 | return -ENODEV; | |
704 | ||
705 | /* both size and indix must be 4 bytes align */ | |
706 | if ((size & 3) || !size || (index & 3) || !data) | |
707 | return -EPERM; | |
708 | ||
709 | if ((u32)index + (u32)size > 0xffff) | |
710 | return -EPERM; | |
711 | ||
712 | byteen_start = byteen & BYTE_EN_START_MASK; | |
713 | byteen_end = byteen & BYTE_EN_END_MASK; | |
714 | ||
715 | byen = byteen_start | (byteen_start << 4); | |
716 | ret = set_registers(tp, index, type | byen, 4, data); | |
717 | if (ret < 0) | |
718 | goto error1; | |
719 | ||
720 | index += 4; | |
721 | data += 4; | |
722 | size -= 4; | |
723 | ||
724 | if (size) { | |
725 | size -= 4; | |
726 | ||
727 | while (size) { | |
728 | if (size > limit) { | |
729 | ret = set_registers(tp, index, | |
b209af99 | 730 | type | BYTE_EN_DWORD, |
731 | limit, data); | |
ac718b69 | 732 | if (ret < 0) |
733 | goto error1; | |
734 | ||
735 | index += limit; | |
736 | data += limit; | |
737 | size -= limit; | |
738 | } else { | |
739 | ret = set_registers(tp, index, | |
b209af99 | 740 | type | BYTE_EN_DWORD, |
741 | size, data); | |
ac718b69 | 742 | if (ret < 0) |
743 | goto error1; | |
744 | ||
745 | index += size; | |
746 | data += size; | |
747 | size = 0; | |
748 | break; | |
749 | } | |
750 | } | |
751 | ||
752 | byen = byteen_end | (byteen_end >> 4); | |
753 | ret = set_registers(tp, index, type | byen, 4, data); | |
754 | if (ret < 0) | |
755 | goto error1; | |
756 | } | |
757 | ||
758 | error1: | |
759 | return ret; | |
760 | } | |
761 | ||
762 | static inline | |
763 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
764 | { | |
765 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
766 | } | |
767 | ||
768 | static inline | |
769 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
770 | { | |
771 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
772 | } | |
773 | ||
774 | static inline | |
775 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
776 | { | |
777 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
778 | } | |
779 | ||
780 | static inline | |
781 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
782 | { | |
783 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
784 | } | |
785 | ||
786 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
787 | { | |
c8826de8 | 788 | __le32 data; |
ac718b69 | 789 | |
c8826de8 | 790 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 791 | |
792 | return __le32_to_cpu(data); | |
793 | } | |
794 | ||
795 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
796 | { | |
c8826de8 | 797 | __le32 tmp = __cpu_to_le32(data); |
798 | ||
799 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 800 | } |
801 | ||
802 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
803 | { | |
804 | u32 data; | |
c8826de8 | 805 | __le32 tmp; |
ac718b69 | 806 | u8 shift = index & 2; |
807 | ||
808 | index &= ~3; | |
809 | ||
c8826de8 | 810 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 811 | |
c8826de8 | 812 | data = __le32_to_cpu(tmp); |
ac718b69 | 813 | data >>= (shift * 8); |
814 | data &= 0xffff; | |
815 | ||
816 | return (u16)data; | |
817 | } | |
818 | ||
819 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
820 | { | |
c8826de8 | 821 | u32 mask = 0xffff; |
822 | __le32 tmp; | |
ac718b69 | 823 | u16 byen = BYTE_EN_WORD; |
824 | u8 shift = index & 2; | |
825 | ||
826 | data &= mask; | |
827 | ||
828 | if (index & 2) { | |
829 | byen <<= shift; | |
830 | mask <<= (shift * 8); | |
831 | data <<= (shift * 8); | |
832 | index &= ~3; | |
833 | } | |
834 | ||
c8826de8 | 835 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 836 | |
c8826de8 | 837 | data |= __le32_to_cpu(tmp) & ~mask; |
838 | tmp = __cpu_to_le32(data); | |
ac718b69 | 839 | |
c8826de8 | 840 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 841 | } |
842 | ||
843 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
844 | { | |
845 | u32 data; | |
c8826de8 | 846 | __le32 tmp; |
ac718b69 | 847 | u8 shift = index & 3; |
848 | ||
849 | index &= ~3; | |
850 | ||
c8826de8 | 851 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 852 | |
c8826de8 | 853 | data = __le32_to_cpu(tmp); |
ac718b69 | 854 | data >>= (shift * 8); |
855 | data &= 0xff; | |
856 | ||
857 | return (u8)data; | |
858 | } | |
859 | ||
860 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
861 | { | |
c8826de8 | 862 | u32 mask = 0xff; |
863 | __le32 tmp; | |
ac718b69 | 864 | u16 byen = BYTE_EN_BYTE; |
865 | u8 shift = index & 3; | |
866 | ||
867 | data &= mask; | |
868 | ||
869 | if (index & 3) { | |
870 | byen <<= shift; | |
871 | mask <<= (shift * 8); | |
872 | data <<= (shift * 8); | |
873 | index &= ~3; | |
874 | } | |
875 | ||
c8826de8 | 876 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 877 | |
c8826de8 | 878 | data |= __le32_to_cpu(tmp) & ~mask; |
879 | tmp = __cpu_to_le32(data); | |
ac718b69 | 880 | |
c8826de8 | 881 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 882 | } |
883 | ||
ac244d3e | 884 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 885 | { |
886 | u16 ocp_base, ocp_index; | |
887 | ||
888 | ocp_base = addr & 0xf000; | |
889 | if (ocp_base != tp->ocp_base) { | |
890 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
891 | tp->ocp_base = ocp_base; | |
892 | } | |
893 | ||
894 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 895 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 896 | } |
897 | ||
ac244d3e | 898 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 899 | { |
ac244d3e | 900 | u16 ocp_base, ocp_index; |
ac718b69 | 901 | |
ac244d3e | 902 | ocp_base = addr & 0xf000; |
903 | if (ocp_base != tp->ocp_base) { | |
904 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
905 | tp->ocp_base = ocp_base; | |
ac718b69 | 906 | } |
ac244d3e | 907 | |
908 | ocp_index = (addr & 0x0fff) | 0xb000; | |
909 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 910 | } |
911 | ||
ac244d3e | 912 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 913 | { |
ac244d3e | 914 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
915 | } | |
ac718b69 | 916 | |
ac244d3e | 917 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
918 | { | |
919 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 920 | } |
921 | ||
43779f8d | 922 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
923 | { | |
924 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
925 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
926 | } | |
927 | ||
928 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
929 | { | |
930 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
931 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
932 | } | |
933 | ||
ac718b69 | 934 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
935 | { | |
936 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 937 | int ret; |
ac718b69 | 938 | |
6871438c | 939 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
940 | return -ENODEV; | |
941 | ||
ac718b69 | 942 | if (phy_id != R8152_PHY_ID) |
943 | return -EINVAL; | |
944 | ||
9a4be1bd | 945 | ret = usb_autopm_get_interface(tp->intf); |
946 | if (ret < 0) | |
947 | goto out; | |
948 | ||
949 | ret = r8152_mdio_read(tp, reg); | |
950 | ||
951 | usb_autopm_put_interface(tp->intf); | |
952 | ||
953 | out: | |
954 | return ret; | |
ac718b69 | 955 | } |
956 | ||
957 | static | |
958 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
959 | { | |
960 | struct r8152 *tp = netdev_priv(netdev); | |
961 | ||
6871438c | 962 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
963 | return; | |
964 | ||
ac718b69 | 965 | if (phy_id != R8152_PHY_ID) |
966 | return; | |
967 | ||
9a4be1bd | 968 | if (usb_autopm_get_interface(tp->intf) < 0) |
969 | return; | |
970 | ||
ac718b69 | 971 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 972 | |
973 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 974 | } |
975 | ||
b209af99 | 976 | static int |
977 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 978 | |
8ba789ab | 979 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
980 | { | |
981 | struct r8152 *tp = netdev_priv(netdev); | |
982 | struct sockaddr *addr = p; | |
ea6a7112 | 983 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 984 | |
985 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 986 | goto out1; |
987 | ||
988 | ret = usb_autopm_get_interface(tp->intf); | |
989 | if (ret < 0) | |
990 | goto out1; | |
8ba789ab | 991 | |
992 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
993 | ||
994 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
995 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
996 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
997 | ||
ea6a7112 | 998 | usb_autopm_put_interface(tp->intf); |
999 | out1: | |
1000 | return ret; | |
8ba789ab | 1001 | } |
1002 | ||
179bb6d7 | 1003 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1004 | { |
1005 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1006 | struct sockaddr sa; |
8a91c824 | 1007 | int ret; |
ac718b69 | 1008 | |
8a91c824 | 1009 | if (tp->version == RTL_VER_01) |
179bb6d7 | 1010 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 1011 | else |
179bb6d7 | 1012 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1013 | |
1014 | if (ret < 0) { | |
179bb6d7 | 1015 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1016 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1017 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1018 | sa.sa_data); | |
1019 | eth_hw_addr_random(dev); | |
1020 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1021 | ret = rtl8152_set_mac_address(dev, &sa); | |
1022 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1023 | sa.sa_data); | |
8a91c824 | 1024 | } else { |
179bb6d7 | 1025 | if (tp->version == RTL_VER_01) |
1026 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1027 | else | |
1028 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1029 | } |
179bb6d7 | 1030 | |
1031 | return ret; | |
ac718b69 | 1032 | } |
1033 | ||
ac718b69 | 1034 | static void read_bulk_callback(struct urb *urb) |
1035 | { | |
ac718b69 | 1036 | struct net_device *netdev; |
ac718b69 | 1037 | int status = urb->status; |
ebc2ec48 | 1038 | struct rx_agg *agg; |
1039 | struct r8152 *tp; | |
ac718b69 | 1040 | int result; |
ac718b69 | 1041 | |
ebc2ec48 | 1042 | agg = urb->context; |
1043 | if (!agg) | |
1044 | return; | |
1045 | ||
1046 | tp = agg->context; | |
ac718b69 | 1047 | if (!tp) |
1048 | return; | |
ebc2ec48 | 1049 | |
ac718b69 | 1050 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1051 | return; | |
ebc2ec48 | 1052 | |
1053 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1054 | return; | |
1055 | ||
ac718b69 | 1056 | netdev = tp->netdev; |
7559fb2f | 1057 | |
1058 | /* When link down, the driver would cancel all bulks. */ | |
1059 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1060 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1061 | return; |
1062 | ||
9a4be1bd | 1063 | usb_mark_last_busy(tp->udev); |
1064 | ||
ac718b69 | 1065 | switch (status) { |
1066 | case 0: | |
ebc2ec48 | 1067 | if (urb->actual_length < ETH_ZLEN) |
1068 | break; | |
1069 | ||
2685d410 | 1070 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1071 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1072 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1073 | tasklet_schedule(&tp->tl); |
1074 | return; | |
ac718b69 | 1075 | case -ESHUTDOWN: |
1076 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1077 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1078 | return; |
ac718b69 | 1079 | case -ENOENT: |
1080 | return; /* the urb is in unlink state */ | |
1081 | case -ETIME: | |
4a8deae2 HW |
1082 | if (net_ratelimit()) |
1083 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1084 | break; |
ac718b69 | 1085 | default: |
4a8deae2 HW |
1086 | if (net_ratelimit()) |
1087 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1088 | break; |
ac718b69 | 1089 | } |
1090 | ||
ebc2ec48 | 1091 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1092 | if (result == -ENODEV) { |
1093 | netif_device_detach(tp->netdev); | |
1094 | } else if (result) { | |
2685d410 | 1095 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1096 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1097 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1098 | tasklet_schedule(&tp->tl); |
ac718b69 | 1099 | } |
ac718b69 | 1100 | } |
1101 | ||
ebc2ec48 | 1102 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1103 | { |
ebc2ec48 | 1104 | struct net_device_stats *stats; |
d104eafa | 1105 | struct net_device *netdev; |
ebc2ec48 | 1106 | struct tx_agg *agg; |
ac718b69 | 1107 | struct r8152 *tp; |
ebc2ec48 | 1108 | int status = urb->status; |
ac718b69 | 1109 | |
ebc2ec48 | 1110 | agg = urb->context; |
1111 | if (!agg) | |
ac718b69 | 1112 | return; |
1113 | ||
ebc2ec48 | 1114 | tp = agg->context; |
1115 | if (!tp) | |
1116 | return; | |
1117 | ||
d104eafa | 1118 | netdev = tp->netdev; |
05e0f1aa | 1119 | stats = &netdev->stats; |
ebc2ec48 | 1120 | if (status) { |
4a8deae2 | 1121 | if (net_ratelimit()) |
d104eafa | 1122 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1123 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1124 | } else { |
ebc2ec48 | 1125 | stats->tx_packets += agg->skb_num; |
1126 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1127 | } |
1128 | ||
2685d410 | 1129 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1130 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1131 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1132 | |
9a4be1bd | 1133 | usb_autopm_put_interface_async(tp->intf); |
1134 | ||
d104eafa | 1135 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1136 | return; |
1137 | ||
1138 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1139 | return; | |
1140 | ||
1141 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1142 | return; | |
1143 | ||
1144 | if (!skb_queue_empty(&tp->tx_queue)) | |
0c3121fc | 1145 | tasklet_schedule(&tp->tl); |
ac718b69 | 1146 | } |
1147 | ||
40a82917 | 1148 | static void intr_callback(struct urb *urb) |
1149 | { | |
1150 | struct r8152 *tp; | |
500b6d7e | 1151 | __le16 *d; |
40a82917 | 1152 | int status = urb->status; |
1153 | int res; | |
1154 | ||
1155 | tp = urb->context; | |
1156 | if (!tp) | |
1157 | return; | |
1158 | ||
1159 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1160 | return; | |
1161 | ||
1162 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1163 | return; | |
1164 | ||
1165 | switch (status) { | |
1166 | case 0: /* success */ | |
1167 | break; | |
1168 | case -ECONNRESET: /* unlink */ | |
1169 | case -ESHUTDOWN: | |
1170 | netif_device_detach(tp->netdev); | |
1171 | case -ENOENT: | |
1172 | return; | |
1173 | case -EOVERFLOW: | |
1174 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1175 | goto resubmit; | |
1176 | /* -EPIPE: should clear the halt */ | |
1177 | default: | |
1178 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1179 | goto resubmit; | |
1180 | } | |
1181 | ||
1182 | d = urb->transfer_buffer; | |
1183 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1184 | if (!(tp->speed & LINK_STATUS)) { | |
1185 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1186 | schedule_delayed_work(&tp->schedule, 0); | |
1187 | } | |
1188 | } else { | |
1189 | if (tp->speed & LINK_STATUS) { | |
1190 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1191 | schedule_delayed_work(&tp->schedule, 0); | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | resubmit: | |
1196 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1197 | if (res == -ENODEV) | |
1198 | netif_device_detach(tp->netdev); | |
1199 | else if (res) | |
1200 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1201 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1202 | } |
1203 | ||
ebc2ec48 | 1204 | static inline void *rx_agg_align(void *data) |
1205 | { | |
8e1f51bd | 1206 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1207 | } |
1208 | ||
1209 | static inline void *tx_agg_align(void *data) | |
1210 | { | |
8e1f51bd | 1211 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1212 | } |
1213 | ||
1214 | static void free_all_mem(struct r8152 *tp) | |
1215 | { | |
1216 | int i; | |
1217 | ||
1218 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1219 | usb_free_urb(tp->rx_info[i].urb); |
1220 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1221 | |
9629e3c0 | 1222 | kfree(tp->rx_info[i].buffer); |
1223 | tp->rx_info[i].buffer = NULL; | |
1224 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1225 | } |
1226 | ||
1227 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1228 | usb_free_urb(tp->tx_info[i].urb); |
1229 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1230 | |
9629e3c0 | 1231 | kfree(tp->tx_info[i].buffer); |
1232 | tp->tx_info[i].buffer = NULL; | |
1233 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1234 | } |
40a82917 | 1235 | |
9629e3c0 | 1236 | usb_free_urb(tp->intr_urb); |
1237 | tp->intr_urb = NULL; | |
40a82917 | 1238 | |
9629e3c0 | 1239 | kfree(tp->intr_buff); |
1240 | tp->intr_buff = NULL; | |
ebc2ec48 | 1241 | } |
1242 | ||
1243 | static int alloc_all_mem(struct r8152 *tp) | |
1244 | { | |
1245 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1246 | struct usb_interface *intf = tp->intf; |
1247 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1248 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1249 | struct urb *urb; |
1250 | int node, i; | |
1251 | u8 *buf; | |
1252 | ||
1253 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1254 | ||
1255 | spin_lock_init(&tp->rx_lock); | |
1256 | spin_lock_init(&tp->tx_lock); | |
1257 | INIT_LIST_HEAD(&tp->rx_done); | |
1258 | INIT_LIST_HEAD(&tp->tx_free); | |
1259 | skb_queue_head_init(&tp->tx_queue); | |
1260 | ||
1261 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1262 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1263 | if (!buf) |
1264 | goto err1; | |
1265 | ||
1266 | if (buf != rx_agg_align(buf)) { | |
1267 | kfree(buf); | |
52aec126 | 1268 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1269 | node); |
ebc2ec48 | 1270 | if (!buf) |
1271 | goto err1; | |
1272 | } | |
1273 | ||
1274 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1275 | if (!urb) { | |
1276 | kfree(buf); | |
1277 | goto err1; | |
1278 | } | |
1279 | ||
1280 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1281 | tp->rx_info[i].context = tp; | |
1282 | tp->rx_info[i].urb = urb; | |
1283 | tp->rx_info[i].buffer = buf; | |
1284 | tp->rx_info[i].head = rx_agg_align(buf); | |
1285 | } | |
1286 | ||
1287 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1288 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1289 | if (!buf) |
1290 | goto err1; | |
1291 | ||
1292 | if (buf != tx_agg_align(buf)) { | |
1293 | kfree(buf); | |
52aec126 | 1294 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1295 | node); |
ebc2ec48 | 1296 | if (!buf) |
1297 | goto err1; | |
1298 | } | |
1299 | ||
1300 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1301 | if (!urb) { | |
1302 | kfree(buf); | |
1303 | goto err1; | |
1304 | } | |
1305 | ||
1306 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1307 | tp->tx_info[i].context = tp; | |
1308 | tp->tx_info[i].urb = urb; | |
1309 | tp->tx_info[i].buffer = buf; | |
1310 | tp->tx_info[i].head = tx_agg_align(buf); | |
1311 | ||
1312 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1313 | } | |
1314 | ||
40a82917 | 1315 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1316 | if (!tp->intr_urb) | |
1317 | goto err1; | |
1318 | ||
1319 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1320 | if (!tp->intr_buff) | |
1321 | goto err1; | |
1322 | ||
1323 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1324 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1325 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1326 | tp, tp->intr_interval); | |
40a82917 | 1327 | |
ebc2ec48 | 1328 | return 0; |
1329 | ||
1330 | err1: | |
1331 | free_all_mem(tp); | |
1332 | return -ENOMEM; | |
1333 | } | |
1334 | ||
0de98f6c | 1335 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1336 | { | |
1337 | struct tx_agg *agg = NULL; | |
1338 | unsigned long flags; | |
1339 | ||
21949ab7 | 1340 | if (list_empty(&tp->tx_free)) |
1341 | return NULL; | |
1342 | ||
0de98f6c | 1343 | spin_lock_irqsave(&tp->tx_lock, flags); |
1344 | if (!list_empty(&tp->tx_free)) { | |
1345 | struct list_head *cursor; | |
1346 | ||
1347 | cursor = tp->tx_free.next; | |
1348 | list_del_init(cursor); | |
1349 | agg = list_entry(cursor, struct tx_agg, list); | |
1350 | } | |
1351 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1352 | ||
1353 | return agg; | |
1354 | } | |
1355 | ||
60c89071 | 1356 | static inline __be16 get_protocol(struct sk_buff *skb) |
5bd23881 | 1357 | { |
60c89071 | 1358 | __be16 protocol; |
5bd23881 | 1359 | |
60c89071 | 1360 | if (skb->protocol == htons(ETH_P_8021Q)) |
1361 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1362 | else | |
1363 | protocol = skb->protocol; | |
5bd23881 | 1364 | |
60c89071 | 1365 | return protocol; |
1366 | } | |
5bd23881 | 1367 | |
b209af99 | 1368 | /* r8152_csum_workaround() |
6128d1bb | 1369 | * The hw limites the value the transport offset. When the offset is out of the |
1370 | * range, calculate the checksum by sw. | |
1371 | */ | |
1372 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1373 | struct sk_buff_head *list) | |
1374 | { | |
1375 | if (skb_shinfo(skb)->gso_size) { | |
1376 | netdev_features_t features = tp->netdev->features; | |
1377 | struct sk_buff_head seg_list; | |
1378 | struct sk_buff *segs, *nskb; | |
1379 | ||
a91d45f1 | 1380 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1381 | segs = skb_gso_segment(skb, features); |
1382 | if (IS_ERR(segs) || !segs) | |
1383 | goto drop; | |
1384 | ||
1385 | __skb_queue_head_init(&seg_list); | |
1386 | ||
1387 | do { | |
1388 | nskb = segs; | |
1389 | segs = segs->next; | |
1390 | nskb->next = NULL; | |
1391 | __skb_queue_tail(&seg_list, nskb); | |
1392 | } while (segs); | |
1393 | ||
1394 | skb_queue_splice(&seg_list, list); | |
1395 | dev_kfree_skb(skb); | |
1396 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1397 | if (skb_checksum_help(skb) < 0) | |
1398 | goto drop; | |
1399 | ||
1400 | __skb_queue_head(list, skb); | |
1401 | } else { | |
1402 | struct net_device_stats *stats; | |
1403 | ||
1404 | drop: | |
1405 | stats = &tp->netdev->stats; | |
1406 | stats->tx_dropped++; | |
1407 | dev_kfree_skb(skb); | |
1408 | } | |
1409 | } | |
1410 | ||
b209af99 | 1411 | /* msdn_giant_send_check() |
6128d1bb | 1412 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1413 | * packet length for IPv6 TCP large packets. | |
1414 | */ | |
1415 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1416 | { | |
1417 | const struct ipv6hdr *ipv6h; | |
1418 | struct tcphdr *th; | |
fcb308d5 | 1419 | int ret; |
1420 | ||
1421 | ret = skb_cow_head(skb, 0); | |
1422 | if (ret) | |
1423 | return ret; | |
6128d1bb | 1424 | |
1425 | ipv6h = ipv6_hdr(skb); | |
1426 | th = tcp_hdr(skb); | |
1427 | ||
1428 | th->check = 0; | |
1429 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1430 | ||
fcb308d5 | 1431 | return ret; |
6128d1bb | 1432 | } |
1433 | ||
c5554298 | 1434 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1435 | { | |
1436 | if (vlan_tx_tag_present(skb)) { | |
1437 | u32 opts2; | |
1438 | ||
1439 | opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb)); | |
1440 | desc->opts2 |= cpu_to_le32(opts2); | |
1441 | } | |
1442 | } | |
1443 | ||
1444 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1445 | { | |
1446 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1447 | ||
1448 | if (opts2 & RX_VLAN_TAG) | |
1449 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1450 | swab16(opts2 & 0xffff)); | |
1451 | } | |
1452 | ||
60c89071 | 1453 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1454 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1455 | { | |
1456 | u32 mss = skb_shinfo(skb)->gso_size; | |
1457 | u32 opts1, opts2 = 0; | |
1458 | int ret = TX_CSUM_SUCCESS; | |
1459 | ||
1460 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1461 | ||
1462 | opts1 = len | TX_FS | TX_LS; | |
1463 | ||
1464 | if (mss) { | |
6128d1bb | 1465 | if (transport_offset > GTTCPHO_MAX) { |
1466 | netif_warn(tp, tx_err, tp->netdev, | |
1467 | "Invalid transport offset 0x%x for TSO\n", | |
1468 | transport_offset); | |
1469 | ret = TX_CSUM_TSO; | |
1470 | goto unavailable; | |
1471 | } | |
1472 | ||
60c89071 | 1473 | switch (get_protocol(skb)) { |
1474 | case htons(ETH_P_IP): | |
1475 | opts1 |= GTSENDV4; | |
1476 | break; | |
1477 | ||
6128d1bb | 1478 | case htons(ETH_P_IPV6): |
fcb308d5 | 1479 | if (msdn_giant_send_check(skb)) { |
1480 | ret = TX_CSUM_TSO; | |
1481 | goto unavailable; | |
1482 | } | |
6128d1bb | 1483 | opts1 |= GTSENDV6; |
6128d1bb | 1484 | break; |
1485 | ||
60c89071 | 1486 | default: |
1487 | WARN_ON_ONCE(1); | |
1488 | break; | |
1489 | } | |
1490 | ||
1491 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1492 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1493 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1494 | u8 ip_protocol; | |
5bd23881 | 1495 | |
6128d1bb | 1496 | if (transport_offset > TCPHO_MAX) { |
1497 | netif_warn(tp, tx_err, tp->netdev, | |
1498 | "Invalid transport offset 0x%x\n", | |
1499 | transport_offset); | |
1500 | ret = TX_CSUM_NONE; | |
1501 | goto unavailable; | |
1502 | } | |
1503 | ||
60c89071 | 1504 | switch (get_protocol(skb)) { |
5bd23881 | 1505 | case htons(ETH_P_IP): |
1506 | opts2 |= IPV4_CS; | |
1507 | ip_protocol = ip_hdr(skb)->protocol; | |
1508 | break; | |
1509 | ||
1510 | case htons(ETH_P_IPV6): | |
1511 | opts2 |= IPV6_CS; | |
1512 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1513 | break; | |
1514 | ||
1515 | default: | |
1516 | ip_protocol = IPPROTO_RAW; | |
1517 | break; | |
1518 | } | |
1519 | ||
60c89071 | 1520 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1521 | opts2 |= TCP_CS; |
60c89071 | 1522 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1523 | opts2 |= UDP_CS; |
60c89071 | 1524 | else |
5bd23881 | 1525 | WARN_ON_ONCE(1); |
5bd23881 | 1526 | |
60c89071 | 1527 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1528 | } |
60c89071 | 1529 | |
1530 | desc->opts2 = cpu_to_le32(opts2); | |
1531 | desc->opts1 = cpu_to_le32(opts1); | |
1532 | ||
6128d1bb | 1533 | unavailable: |
60c89071 | 1534 | return ret; |
5bd23881 | 1535 | } |
1536 | ||
b1379d9a | 1537 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1538 | { | |
d84130a1 | 1539 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1540 | int remain, ret; |
b1379d9a | 1541 | u8 *tx_data; |
1542 | ||
d84130a1 | 1543 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1544 | spin_lock(&tx_queue->lock); |
d84130a1 | 1545 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1546 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1547 | |
b1379d9a | 1548 | tx_data = agg->head; |
b209af99 | 1549 | agg->skb_num = 0; |
1550 | agg->skb_len = 0; | |
52aec126 | 1551 | remain = agg_buf_sz; |
b1379d9a | 1552 | |
7937f9e5 | 1553 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1554 | struct tx_desc *tx_desc; |
1555 | struct sk_buff *skb; | |
1556 | unsigned int len; | |
60c89071 | 1557 | u32 offset; |
b1379d9a | 1558 | |
d84130a1 | 1559 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1560 | if (!skb) |
1561 | break; | |
1562 | ||
60c89071 | 1563 | len = skb->len + sizeof(*tx_desc); |
1564 | ||
1565 | if (len > remain) { | |
d84130a1 | 1566 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1567 | break; |
1568 | } | |
1569 | ||
7937f9e5 | 1570 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1571 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1572 | |
1573 | offset = (u32)skb_transport_offset(skb); | |
1574 | ||
6128d1bb | 1575 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1576 | r8152_csum_workaround(tp, skb, &skb_head); | |
1577 | continue; | |
1578 | } | |
60c89071 | 1579 | |
c5554298 | 1580 | rtl_tx_vlan_tag(tx_desc, skb); |
1581 | ||
b1379d9a | 1582 | tx_data += sizeof(*tx_desc); |
1583 | ||
60c89071 | 1584 | len = skb->len; |
1585 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1586 | struct net_device_stats *stats = &tp->netdev->stats; | |
1587 | ||
1588 | stats->tx_dropped++; | |
1589 | dev_kfree_skb_any(skb); | |
1590 | tx_data -= sizeof(*tx_desc); | |
1591 | continue; | |
1592 | } | |
1593 | ||
1594 | tx_data += len; | |
b1379d9a | 1595 | agg->skb_len += len; |
60c89071 | 1596 | agg->skb_num++; |
1597 | ||
b1379d9a | 1598 | dev_kfree_skb_any(skb); |
1599 | ||
52aec126 | 1600 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1601 | } |
1602 | ||
d84130a1 | 1603 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1604 | spin_lock(&tx_queue->lock); |
d84130a1 | 1605 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1606 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1607 | } |
1608 | ||
0c3121fc | 1609 | netif_tx_lock(tp->netdev); |
dd1b119c | 1610 | |
1611 | if (netif_queue_stopped(tp->netdev) && | |
1612 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1613 | netif_wake_queue(tp->netdev); | |
1614 | ||
0c3121fc | 1615 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1616 | |
0c3121fc | 1617 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1618 | if (ret < 0) |
1619 | goto out_tx_fill; | |
dd1b119c | 1620 | |
b1379d9a | 1621 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1622 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1623 | (usb_complete_t)write_bulk_callback, agg); | |
1624 | ||
0c3121fc | 1625 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1626 | if (ret < 0) |
0c3121fc | 1627 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1628 | |
1629 | out_tx_fill: | |
1630 | return ret; | |
b1379d9a | 1631 | } |
1632 | ||
565cab0a | 1633 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1634 | { | |
1635 | u8 checksum = CHECKSUM_NONE; | |
1636 | u32 opts2, opts3; | |
1637 | ||
1638 | if (tp->version == RTL_VER_01) | |
1639 | goto return_result; | |
1640 | ||
1641 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1642 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1643 | ||
1644 | if (opts2 & RD_IPV4_CS) { | |
1645 | if (opts3 & IPF) | |
1646 | checksum = CHECKSUM_NONE; | |
1647 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1648 | checksum = CHECKSUM_NONE; | |
1649 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1650 | checksum = CHECKSUM_NONE; | |
1651 | else | |
1652 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1653 | } else if (RD_IPV6_CS) { |
1654 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1655 | checksum = CHECKSUM_UNNECESSARY; | |
1656 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1657 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1658 | } |
1659 | ||
1660 | return_result: | |
1661 | return checksum; | |
1662 | } | |
1663 | ||
ebc2ec48 | 1664 | static void rx_bottom(struct r8152 *tp) |
1665 | { | |
a5a4f468 | 1666 | unsigned long flags; |
d84130a1 | 1667 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1668 | |
d84130a1 | 1669 | if (list_empty(&tp->rx_done)) |
1670 | return; | |
1671 | ||
1672 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1673 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1674 | list_splice_init(&tp->rx_done, &rx_queue); |
1675 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1676 | ||
1677 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1678 | struct rx_desc *rx_desc; |
1679 | struct rx_agg *agg; | |
43a4478d | 1680 | int len_used = 0; |
1681 | struct urb *urb; | |
1682 | u8 *rx_data; | |
1683 | int ret; | |
1684 | ||
ebc2ec48 | 1685 | list_del_init(cursor); |
ebc2ec48 | 1686 | |
1687 | agg = list_entry(cursor, struct rx_agg, list); | |
1688 | urb = agg->urb; | |
0de98f6c | 1689 | if (urb->actual_length < ETH_ZLEN) |
1690 | goto submit; | |
ebc2ec48 | 1691 | |
ebc2ec48 | 1692 | rx_desc = agg->head; |
1693 | rx_data = agg->head; | |
7937f9e5 | 1694 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1695 | |
7937f9e5 | 1696 | while (urb->actual_length > len_used) { |
43a4478d | 1697 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1698 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1699 | unsigned int pkt_len; |
43a4478d | 1700 | struct sk_buff *skb; |
1701 | ||
7937f9e5 | 1702 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1703 | if (pkt_len < ETH_ZLEN) |
1704 | break; | |
1705 | ||
7937f9e5 | 1706 | len_used += pkt_len; |
1707 | if (urb->actual_length < len_used) | |
1708 | break; | |
1709 | ||
8e1f51bd | 1710 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1711 | rx_data += sizeof(struct rx_desc); |
1712 | ||
1713 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1714 | if (!skb) { | |
1715 | stats->rx_dropped++; | |
5e2f7485 | 1716 | goto find_next_rx; |
ebc2ec48 | 1717 | } |
565cab0a | 1718 | |
1719 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1720 | memcpy(skb->data, rx_data, pkt_len); |
1721 | skb_put(skb, pkt_len); | |
1722 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1723 | rtl_rx_vlan_tag(rx_desc, skb); |
9d9aafa1 | 1724 | netif_receive_skb(skb); |
ebc2ec48 | 1725 | stats->rx_packets++; |
1726 | stats->rx_bytes += pkt_len; | |
1727 | ||
5e2f7485 | 1728 | find_next_rx: |
8e1f51bd | 1729 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1730 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1731 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1732 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1733 | } |
1734 | ||
0de98f6c | 1735 | submit: |
ebc2ec48 | 1736 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1737 | if (ret && ret != -ENODEV) { |
d84130a1 | 1738 | spin_lock_irqsave(&tp->rx_lock, flags); |
1739 | list_add_tail(&agg->list, &tp->rx_done); | |
1740 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1741 | tasklet_schedule(&tp->tl); |
1742 | } | |
1743 | } | |
ebc2ec48 | 1744 | } |
1745 | ||
1746 | static void tx_bottom(struct r8152 *tp) | |
1747 | { | |
ebc2ec48 | 1748 | int res; |
1749 | ||
b1379d9a | 1750 | do { |
1751 | struct tx_agg *agg; | |
ebc2ec48 | 1752 | |
b1379d9a | 1753 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1754 | break; |
1755 | ||
b1379d9a | 1756 | agg = r8152_get_tx_agg(tp); |
1757 | if (!agg) | |
ebc2ec48 | 1758 | break; |
ebc2ec48 | 1759 | |
b1379d9a | 1760 | res = r8152_tx_agg_fill(tp, agg); |
1761 | if (res) { | |
05e0f1aa | 1762 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1763 | |
b1379d9a | 1764 | if (res == -ENODEV) { |
1765 | netif_device_detach(netdev); | |
1766 | } else { | |
05e0f1aa | 1767 | struct net_device_stats *stats = &netdev->stats; |
1768 | unsigned long flags; | |
1769 | ||
b1379d9a | 1770 | netif_warn(tp, tx_err, netdev, |
1771 | "failed tx_urb %d\n", res); | |
1772 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1773 | |
b1379d9a | 1774 | spin_lock_irqsave(&tp->tx_lock, flags); |
1775 | list_add_tail(&agg->list, &tp->tx_free); | |
1776 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1777 | } | |
ebc2ec48 | 1778 | } |
b1379d9a | 1779 | } while (res == 0); |
ebc2ec48 | 1780 | } |
1781 | ||
1782 | static void bottom_half(unsigned long data) | |
ac718b69 | 1783 | { |
1784 | struct r8152 *tp; | |
ac718b69 | 1785 | |
ebc2ec48 | 1786 | tp = (struct r8152 *)data; |
1787 | ||
1788 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1789 | return; | |
1790 | ||
1791 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1792 | return; |
ebc2ec48 | 1793 | |
7559fb2f | 1794 | /* When link down, the driver would cancel all bulks. */ |
1795 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1796 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1797 | return; |
ebc2ec48 | 1798 | |
1799 | rx_bottom(tp); | |
0c3121fc | 1800 | tx_bottom(tp); |
ebc2ec48 | 1801 | } |
1802 | ||
1803 | static | |
1804 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1805 | { | |
1806 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
52aec126 | 1807 | agg->head, agg_buf_sz, |
b209af99 | 1808 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1809 | |
1810 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1811 | } |
1812 | ||
00a5e360 | 1813 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1814 | { | |
1815 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1816 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1817 | struct sk_buff *skb; |
1818 | ||
d84130a1 | 1819 | if (skb_queue_empty(tx_queue)) |
1820 | return; | |
1821 | ||
1822 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1823 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1824 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1825 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1826 | |
1827 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1828 | dev_kfree_skb(skb); |
1829 | stats->tx_dropped++; | |
1830 | } | |
1831 | } | |
1832 | ||
ac718b69 | 1833 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1834 | { | |
1835 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1836 | int i; |
1837 | ||
4a8deae2 | 1838 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1839 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1840 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1841 | } |
1842 | ||
1843 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1844 | { | |
1845 | struct r8152 *tp = netdev_priv(netdev); | |
1846 | ||
40a82917 | 1847 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1848 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1849 | schedule_delayed_work(&tp->schedule, 0); |
1850 | } | |
ac718b69 | 1851 | } |
1852 | ||
1853 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1854 | { | |
1855 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1856 | u32 mc_filter[2]; /* Multicast hash filter */ |
1857 | __le32 tmp[2]; | |
ac718b69 | 1858 | u32 ocp_data; |
1859 | ||
ac718b69 | 1860 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1861 | netif_stop_queue(netdev); | |
1862 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1863 | ocp_data &= ~RCR_ACPT_ALL; | |
1864 | ocp_data |= RCR_AB | RCR_APM; | |
1865 | ||
1866 | if (netdev->flags & IFF_PROMISC) { | |
1867 | /* Unconditionally log net taps. */ | |
1868 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1869 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1870 | mc_filter[1] = 0xffffffff; |
1871 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1872 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1873 | (netdev->flags & IFF_ALLMULTI)) { | |
1874 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1875 | ocp_data |= RCR_AM; | |
b209af99 | 1876 | mc_filter[1] = 0xffffffff; |
1877 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1878 | } else { |
1879 | struct netdev_hw_addr *ha; | |
1880 | ||
b209af99 | 1881 | mc_filter[1] = 0; |
1882 | mc_filter[0] = 0; | |
ac718b69 | 1883 | netdev_for_each_mc_addr(ha, netdev) { |
1884 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1885 | |
ac718b69 | 1886 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1887 | ocp_data |= RCR_AM; | |
1888 | } | |
1889 | } | |
1890 | ||
31787f53 | 1891 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1892 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1893 | |
31787f53 | 1894 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1895 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1896 | netif_wake_queue(netdev); | |
ac718b69 | 1897 | } |
1898 | ||
1899 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
b209af99 | 1900 | struct net_device *netdev) |
ac718b69 | 1901 | { |
1902 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1903 | |
ebc2ec48 | 1904 | skb_tx_timestamp(skb); |
ac718b69 | 1905 | |
61598788 | 1906 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1907 | |
0c3121fc | 1908 | if (!list_empty(&tp->tx_free)) { |
1909 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
1910 | set_bit(SCHEDULE_TASKLET, &tp->flags); | |
1911 | schedule_delayed_work(&tp->schedule, 0); | |
1912 | } else { | |
1913 | usb_mark_last_busy(tp->udev); | |
1914 | tasklet_schedule(&tp->tl); | |
1915 | } | |
b209af99 | 1916 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 1917 | netif_stop_queue(netdev); |
b209af99 | 1918 | } |
dd1b119c | 1919 | |
ac718b69 | 1920 | return NETDEV_TX_OK; |
1921 | } | |
1922 | ||
1923 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1924 | { | |
1925 | u32 ocp_data; | |
1926 | ||
1927 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1928 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1929 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1930 | ocp_data |= FMC_FCR_MCU_EN; | |
1931 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1932 | } | |
1933 | ||
1934 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1935 | { | |
1936 | int i; | |
1937 | ||
1938 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1939 | ||
1940 | for (i = 0; i < 1000; i++) { | |
1941 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1942 | break; | |
b209af99 | 1943 | usleep_range(100, 400); |
ac718b69 | 1944 | } |
1945 | } | |
1946 | ||
dd1b119c | 1947 | static void set_tx_qlen(struct r8152 *tp) |
1948 | { | |
1949 | struct net_device *netdev = tp->netdev; | |
1950 | ||
52aec126 | 1951 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
1952 | sizeof(struct tx_desc)); | |
dd1b119c | 1953 | } |
1954 | ||
ac718b69 | 1955 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1956 | { | |
1957 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1958 | } | |
1959 | ||
507605a8 | 1960 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1961 | { |
ebc2ec48 | 1962 | u32 ocp_data; |
ac718b69 | 1963 | u8 speed; |
1964 | ||
1965 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1966 | if (speed & _10bps) { |
ac718b69 | 1967 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1968 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1969 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1970 | } else { | |
1971 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1972 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1973 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1974 | } | |
507605a8 | 1975 | } |
1976 | ||
00a5e360 | 1977 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1978 | { | |
1979 | u32 ocp_data; | |
1980 | ||
1981 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1982 | if (enable) | |
1983 | ocp_data |= RXDY_GATED_EN; | |
1984 | else | |
1985 | ocp_data &= ~RXDY_GATED_EN; | |
1986 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1987 | } | |
1988 | ||
445f7f4d | 1989 | static int rtl_start_rx(struct r8152 *tp) |
1990 | { | |
1991 | int i, ret = 0; | |
1992 | ||
1993 | INIT_LIST_HEAD(&tp->rx_done); | |
1994 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1995 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1996 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1997 | if (ret) | |
1998 | break; | |
1999 | } | |
2000 | ||
2001 | return ret; | |
2002 | } | |
2003 | ||
2004 | static int rtl_stop_rx(struct r8152 *tp) | |
2005 | { | |
2006 | int i; | |
2007 | ||
2008 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2009 | usb_kill_urb(tp->rx_info[i].urb); | |
2010 | ||
2011 | return 0; | |
2012 | } | |
2013 | ||
507605a8 | 2014 | static int rtl_enable(struct r8152 *tp) |
2015 | { | |
2016 | u32 ocp_data; | |
ac718b69 | 2017 | |
2018 | r8152b_reset_packet_filter(tp); | |
2019 | ||
2020 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2021 | ocp_data |= CR_RE | CR_TE; | |
2022 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2023 | ||
00a5e360 | 2024 | rxdy_gated_en(tp, false); |
ac718b69 | 2025 | |
445f7f4d | 2026 | return rtl_start_rx(tp); |
ac718b69 | 2027 | } |
2028 | ||
507605a8 | 2029 | static int rtl8152_enable(struct r8152 *tp) |
2030 | { | |
6871438c | 2031 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2032 | return -ENODEV; | |
2033 | ||
507605a8 | 2034 | set_tx_qlen(tp); |
2035 | rtl_set_eee_plus(tp); | |
2036 | ||
2037 | return rtl_enable(tp); | |
2038 | } | |
2039 | ||
43779f8d | 2040 | static void r8153_set_rx_agg(struct r8152 *tp) |
2041 | { | |
2042 | u8 speed; | |
2043 | ||
2044 | speed = rtl8152_get_speed(tp); | |
2045 | if (speed & _1000bps) { | |
2046 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
2047 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2048 | RX_THR_SUPPER); | |
2049 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2050 | EARLY_AGG_SUPPER); | |
2051 | } else { | |
2052 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2053 | RX_THR_HIGH); | |
2054 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2055 | EARLY_AGG_HIGH); | |
2056 | } | |
2057 | } else { | |
2058 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
2059 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2060 | EARLY_AGG_SLOW); | |
2061 | } | |
2062 | } | |
2063 | ||
2064 | static int rtl8153_enable(struct r8152 *tp) | |
2065 | { | |
6871438c | 2066 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2067 | return -ENODEV; | |
2068 | ||
43779f8d | 2069 | set_tx_qlen(tp); |
2070 | rtl_set_eee_plus(tp); | |
2071 | r8153_set_rx_agg(tp); | |
2072 | ||
2073 | return rtl_enable(tp); | |
2074 | } | |
2075 | ||
d70b1137 | 2076 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2077 | { |
ebc2ec48 | 2078 | u32 ocp_data; |
2079 | int i; | |
ac718b69 | 2080 | |
6871438c | 2081 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2082 | rtl_drop_queued_tx(tp); | |
2083 | return; | |
2084 | } | |
2085 | ||
ac718b69 | 2086 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2087 | ocp_data &= ~RCR_ACPT_ALL; | |
2088 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2089 | ||
00a5e360 | 2090 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2091 | |
2092 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2093 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2094 | |
00a5e360 | 2095 | rxdy_gated_en(tp, true); |
ac718b69 | 2096 | |
2097 | for (i = 0; i < 1000; i++) { | |
2098 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2099 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2100 | break; | |
8ddfa077 | 2101 | usleep_range(1000, 2000); |
ac718b69 | 2102 | } |
2103 | ||
2104 | for (i = 0; i < 1000; i++) { | |
2105 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2106 | break; | |
8ddfa077 | 2107 | usleep_range(1000, 2000); |
ac718b69 | 2108 | } |
2109 | ||
445f7f4d | 2110 | rtl_stop_rx(tp); |
ac718b69 | 2111 | |
2112 | rtl8152_nic_reset(tp); | |
2113 | } | |
2114 | ||
00a5e360 | 2115 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2116 | { | |
2117 | u32 ocp_data; | |
2118 | ||
2119 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2120 | if (enable) | |
2121 | ocp_data |= POWER_CUT; | |
2122 | else | |
2123 | ocp_data &= ~POWER_CUT; | |
2124 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2125 | ||
2126 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2127 | ocp_data &= ~RESUME_INDICATE; | |
2128 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2129 | } |
2130 | ||
c5554298 | 2131 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2132 | { | |
2133 | u32 ocp_data; | |
2134 | ||
2135 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2136 | if (enable) | |
2137 | ocp_data |= CPCR_RX_VLAN; | |
2138 | else | |
2139 | ocp_data &= ~CPCR_RX_VLAN; | |
2140 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2141 | } | |
2142 | ||
2143 | static int rtl8152_set_features(struct net_device *dev, | |
2144 | netdev_features_t features) | |
2145 | { | |
2146 | netdev_features_t changed = features ^ dev->features; | |
2147 | struct r8152 *tp = netdev_priv(dev); | |
2148 | ||
2149 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { | |
2150 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2151 | rtl_rx_vlan_en(tp, true); | |
2152 | else | |
2153 | rtl_rx_vlan_en(tp, false); | |
2154 | } | |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
21ff2e89 | 2159 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2160 | ||
2161 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2162 | { | |
2163 | u32 ocp_data; | |
2164 | u32 wolopts = 0; | |
2165 | ||
2166 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2167 | if (!(ocp_data & LAN_WAKE_EN)) | |
2168 | return 0; | |
2169 | ||
2170 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2171 | if (ocp_data & LINK_ON_WAKE_EN) | |
2172 | wolopts |= WAKE_PHY; | |
2173 | ||
2174 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2175 | if (ocp_data & UWF_EN) | |
2176 | wolopts |= WAKE_UCAST; | |
2177 | if (ocp_data & BWF_EN) | |
2178 | wolopts |= WAKE_BCAST; | |
2179 | if (ocp_data & MWF_EN) | |
2180 | wolopts |= WAKE_MCAST; | |
2181 | ||
2182 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2183 | if (ocp_data & MAGIC_EN) | |
2184 | wolopts |= WAKE_MAGIC; | |
2185 | ||
2186 | return wolopts; | |
2187 | } | |
2188 | ||
2189 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2190 | { | |
2191 | u32 ocp_data; | |
2192 | ||
2193 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2194 | ||
2195 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2196 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2197 | if (wolopts & WAKE_PHY) | |
2198 | ocp_data |= LINK_ON_WAKE_EN; | |
2199 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2200 | ||
2201 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2202 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2203 | if (wolopts & WAKE_UCAST) | |
2204 | ocp_data |= UWF_EN; | |
2205 | if (wolopts & WAKE_BCAST) | |
2206 | ocp_data |= BWF_EN; | |
2207 | if (wolopts & WAKE_MCAST) | |
2208 | ocp_data |= MWF_EN; | |
2209 | if (wolopts & WAKE_ANY) | |
2210 | ocp_data |= LAN_WAKE_EN; | |
2211 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2212 | ||
2213 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2214 | ||
2215 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2216 | ocp_data &= ~MAGIC_EN; | |
2217 | if (wolopts & WAKE_MAGIC) | |
2218 | ocp_data |= MAGIC_EN; | |
2219 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2220 | ||
2221 | if (wolopts & WAKE_ANY) | |
2222 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2223 | else | |
2224 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2225 | } | |
2226 | ||
9a4be1bd | 2227 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2228 | { | |
2229 | if (enable) { | |
2230 | u32 ocp_data; | |
2231 | ||
2232 | __rtl_set_wol(tp, WAKE_ANY); | |
2233 | ||
2234 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2235 | ||
2236 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2237 | ocp_data |= LINK_OFF_WAKE_EN; | |
2238 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2239 | ||
2240 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2241 | } else { | |
2242 | __rtl_set_wol(tp, tp->saved_wolopts); | |
2243 | } | |
2244 | } | |
2245 | ||
aa66a5f1 | 2246 | static void rtl_phy_reset(struct r8152 *tp) |
2247 | { | |
2248 | u16 data; | |
2249 | int i; | |
2250 | ||
2251 | clear_bit(PHY_RESET, &tp->flags); | |
2252 | ||
2253 | data = r8152_mdio_read(tp, MII_BMCR); | |
2254 | ||
2255 | /* don't reset again before the previous one complete */ | |
2256 | if (data & BMCR_RESET) | |
2257 | return; | |
2258 | ||
2259 | data |= BMCR_RESET; | |
2260 | r8152_mdio_write(tp, MII_BMCR, data); | |
2261 | ||
2262 | for (i = 0; i < 50; i++) { | |
2263 | msleep(20); | |
2264 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2265 | break; | |
2266 | } | |
2267 | } | |
2268 | ||
4349968a | 2269 | static void r8153_teredo_off(struct r8152 *tp) |
2270 | { | |
2271 | u32 ocp_data; | |
2272 | ||
2273 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2274 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2275 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2276 | ||
2277 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2278 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2279 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2280 | } | |
2281 | ||
2282 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2283 | { | |
2284 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2285 | msleep(20); | |
2286 | } | |
2287 | ||
2288 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2289 | { | |
2290 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2291 | LINKENA | DIS_SDSAVE); | |
2292 | } | |
2293 | ||
d70b1137 | 2294 | static void rtl8152_disable(struct r8152 *tp) |
2295 | { | |
2296 | r8152b_disable_aldps(tp); | |
2297 | rtl_disable(tp); | |
2298 | r8152b_enable_aldps(tp); | |
2299 | } | |
2300 | ||
4349968a | 2301 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2302 | { | |
f0cbe0ac | 2303 | u16 data; |
2304 | ||
2305 | data = r8152_mdio_read(tp, MII_BMCR); | |
2306 | if (data & BMCR_PDOWN) { | |
2307 | data &= ~BMCR_PDOWN; | |
2308 | r8152_mdio_write(tp, MII_BMCR, data); | |
2309 | } | |
2310 | ||
aa66a5f1 | 2311 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2312 | } |
2313 | ||
ac718b69 | 2314 | static void r8152b_exit_oob(struct r8152 *tp) |
2315 | { | |
db8515ef | 2316 | u32 ocp_data; |
2317 | int i; | |
ac718b69 | 2318 | |
2319 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2320 | ocp_data &= ~RCR_ACPT_ALL; | |
2321 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2322 | ||
00a5e360 | 2323 | rxdy_gated_en(tp, true); |
da9bd117 | 2324 | r8153_teredo_off(tp); |
7e9da481 | 2325 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2326 | |
2327 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2328 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2329 | ||
2330 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2331 | ocp_data &= ~NOW_IS_OOB; | |
2332 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2333 | ||
2334 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2335 | ocp_data &= ~MCU_BORW_EN; | |
2336 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2337 | ||
2338 | for (i = 0; i < 1000; i++) { | |
2339 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2340 | if (ocp_data & LINK_LIST_READY) | |
2341 | break; | |
8ddfa077 | 2342 | usleep_range(1000, 2000); |
ac718b69 | 2343 | } |
2344 | ||
2345 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2346 | ocp_data |= RE_INIT_LL; | |
2347 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2348 | ||
2349 | for (i = 0; i < 1000; i++) { | |
2350 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2351 | if (ocp_data & LINK_LIST_READY) | |
2352 | break; | |
8ddfa077 | 2353 | usleep_range(1000, 2000); |
ac718b69 | 2354 | } |
2355 | ||
2356 | rtl8152_nic_reset(tp); | |
2357 | ||
2358 | /* rx share fifo credit full threshold */ | |
2359 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2360 | ||
a3cc465d | 2361 | if (tp->udev->speed == USB_SPEED_FULL || |
2362 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2363 | /* rx share fifo credit near full threshold */ |
2364 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2365 | RXFIFO_THR2_FULL); | |
2366 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2367 | RXFIFO_THR3_FULL); | |
2368 | } else { | |
2369 | /* rx share fifo credit near full threshold */ | |
2370 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2371 | RXFIFO_THR2_HIGH); | |
2372 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2373 | RXFIFO_THR3_HIGH); | |
2374 | } | |
2375 | ||
2376 | /* TX share fifo free credit full threshold */ | |
2377 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2378 | ||
2379 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2380 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2381 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2382 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2383 | ||
c5554298 | 2384 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2385 | |
2386 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2387 | ||
2388 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2389 | ocp_data |= TCR0_AUTO_FIFO; | |
2390 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2391 | } | |
2392 | ||
2393 | static void r8152b_enter_oob(struct r8152 *tp) | |
2394 | { | |
45f4a19f | 2395 | u32 ocp_data; |
2396 | int i; | |
ac718b69 | 2397 | |
2398 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2399 | ocp_data &= ~NOW_IS_OOB; | |
2400 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2401 | ||
2402 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2403 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2404 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2405 | ||
d70b1137 | 2406 | rtl_disable(tp); |
ac718b69 | 2407 | |
2408 | for (i = 0; i < 1000; i++) { | |
2409 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2410 | if (ocp_data & LINK_LIST_READY) | |
2411 | break; | |
8ddfa077 | 2412 | usleep_range(1000, 2000); |
ac718b69 | 2413 | } |
2414 | ||
2415 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2416 | ocp_data |= RE_INIT_LL; | |
2417 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2418 | ||
2419 | for (i = 0; i < 1000; i++) { | |
2420 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2421 | if (ocp_data & LINK_LIST_READY) | |
2422 | break; | |
8ddfa077 | 2423 | usleep_range(1000, 2000); |
ac718b69 | 2424 | } |
2425 | ||
2426 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2427 | ||
c5554298 | 2428 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2429 | |
2430 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2431 | ocp_data |= ALDPS_PROXY_MODE; | |
2432 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2433 | ||
2434 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2435 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2436 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2437 | ||
00a5e360 | 2438 | rxdy_gated_en(tp, false); |
ac718b69 | 2439 | |
2440 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2441 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2442 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2443 | } | |
2444 | ||
43779f8d | 2445 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2446 | { | |
2447 | u32 ocp_data; | |
2448 | u16 data; | |
2449 | ||
2450 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2451 | data = r8152_mdio_read(tp, MII_BMCR); |
2452 | if (data & BMCR_PDOWN) { | |
2453 | data &= ~BMCR_PDOWN; | |
2454 | r8152_mdio_write(tp, MII_BMCR, data); | |
2455 | } | |
43779f8d | 2456 | |
2457 | if (tp->version == RTL_VER_03) { | |
2458 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2459 | data &= ~CTAP_SHORT_EN; | |
2460 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2461 | } | |
2462 | ||
2463 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2464 | data |= EEE_CLKDIV_EN; | |
2465 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2466 | ||
2467 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2468 | data |= EN_10M_BGOFF; | |
2469 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2470 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2471 | data |= EN_10M_PLLOFF; | |
2472 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2473 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2474 | data &= ~RX_DRIVING_MASK; | |
2475 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2476 | ||
2477 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2478 | ocp_data |= PFM_PWM_SWITCH; | |
2479 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2480 | ||
2481 | data = sram_read(tp, SRAM_LPF_CFG); | |
2482 | data |= LPF_AUTO_TUNE; | |
2483 | sram_write(tp, SRAM_LPF_CFG, data); | |
2484 | ||
2485 | data = sram_read(tp, SRAM_10M_AMP1); | |
2486 | data |= GDAC_IB_UPALL; | |
2487 | sram_write(tp, SRAM_10M_AMP1, data); | |
2488 | data = sram_read(tp, SRAM_10M_AMP2); | |
2489 | data |= AMP_DN; | |
2490 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2491 | |
2492 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2493 | } |
2494 | ||
b9702723 | 2495 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2496 | { |
2497 | u8 u1u2[8]; | |
2498 | ||
2499 | if (enable) | |
2500 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2501 | else | |
2502 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2503 | ||
2504 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2505 | } | |
2506 | ||
b9702723 | 2507 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2508 | { |
2509 | u32 ocp_data; | |
2510 | ||
2511 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2512 | if (enable) | |
2513 | ocp_data |= U2P3_ENABLE; | |
2514 | else | |
2515 | ocp_data &= ~U2P3_ENABLE; | |
2516 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2517 | } | |
2518 | ||
b9702723 | 2519 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2520 | { |
2521 | u32 ocp_data; | |
2522 | ||
2523 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2524 | if (enable) | |
2525 | ocp_data |= PWR_EN | PHASE2_EN; | |
2526 | else | |
2527 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2528 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2529 | ||
2530 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2531 | ocp_data &= ~PCUT_STATUS; | |
2532 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2533 | } | |
2534 | ||
43779f8d | 2535 | static void r8153_first_init(struct r8152 *tp) |
2536 | { | |
2537 | u32 ocp_data; | |
2538 | int i; | |
2539 | ||
00a5e360 | 2540 | rxdy_gated_en(tp, true); |
43779f8d | 2541 | r8153_teredo_off(tp); |
2542 | ||
2543 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2544 | ocp_data &= ~RCR_ACPT_ALL; | |
2545 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2546 | ||
2547 | r8153_hw_phy_cfg(tp); | |
2548 | ||
2549 | rtl8152_nic_reset(tp); | |
2550 | ||
2551 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2552 | ocp_data &= ~NOW_IS_OOB; | |
2553 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2554 | ||
2555 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2556 | ocp_data &= ~MCU_BORW_EN; | |
2557 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2558 | ||
2559 | for (i = 0; i < 1000; i++) { | |
2560 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2561 | if (ocp_data & LINK_LIST_READY) | |
2562 | break; | |
8ddfa077 | 2563 | usleep_range(1000, 2000); |
43779f8d | 2564 | } |
2565 | ||
2566 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2567 | ocp_data |= RE_INIT_LL; | |
2568 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2569 | ||
2570 | for (i = 0; i < 1000; i++) { | |
2571 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2572 | if (ocp_data & LINK_LIST_READY) | |
2573 | break; | |
8ddfa077 | 2574 | usleep_range(1000, 2000); |
43779f8d | 2575 | } |
2576 | ||
c5554298 | 2577 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2578 | |
69b4b7a4 | 2579 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2580 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2581 | |
2582 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2583 | ocp_data |= TCR0_AUTO_FIFO; | |
2584 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2585 | ||
2586 | rtl8152_nic_reset(tp); | |
2587 | ||
2588 | /* rx share fifo credit full threshold */ | |
2589 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2590 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2591 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2592 | /* TX share fifo free credit full threshold */ | |
2593 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2594 | ||
9629e3c0 | 2595 | /* rx aggregation */ |
43779f8d | 2596 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2597 | ocp_data &= ~RX_AGG_DISABLE; | |
2598 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2599 | } | |
2600 | ||
2601 | static void r8153_enter_oob(struct r8152 *tp) | |
2602 | { | |
2603 | u32 ocp_data; | |
2604 | int i; | |
2605 | ||
2606 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2607 | ocp_data &= ~NOW_IS_OOB; | |
2608 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2609 | ||
d70b1137 | 2610 | rtl_disable(tp); |
43779f8d | 2611 | |
2612 | for (i = 0; i < 1000; i++) { | |
2613 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2614 | if (ocp_data & LINK_LIST_READY) | |
2615 | break; | |
8ddfa077 | 2616 | usleep_range(1000, 2000); |
43779f8d | 2617 | } |
2618 | ||
2619 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2620 | ocp_data |= RE_INIT_LL; | |
2621 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2622 | ||
2623 | for (i = 0; i < 1000; i++) { | |
2624 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2625 | if (ocp_data & LINK_LIST_READY) | |
2626 | break; | |
8ddfa077 | 2627 | usleep_range(1000, 2000); |
43779f8d | 2628 | } |
2629 | ||
69b4b7a4 | 2630 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2631 | |
43779f8d | 2632 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2633 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2634 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2635 | ||
c5554298 | 2636 | rtl_rx_vlan_en(tp, true); |
43779f8d | 2637 | |
2638 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2639 | ocp_data |= ALDPS_PROXY_MODE; | |
2640 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2641 | ||
2642 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2643 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2644 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2645 | ||
00a5e360 | 2646 | rxdy_gated_en(tp, false); |
43779f8d | 2647 | |
2648 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2649 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2650 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2651 | } | |
2652 | ||
2653 | static void r8153_disable_aldps(struct r8152 *tp) | |
2654 | { | |
2655 | u16 data; | |
2656 | ||
2657 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2658 | data &= ~EN_ALDPS; | |
2659 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2660 | msleep(20); | |
2661 | } | |
2662 | ||
2663 | static void r8153_enable_aldps(struct r8152 *tp) | |
2664 | { | |
2665 | u16 data; | |
2666 | ||
2667 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2668 | data |= EN_ALDPS; | |
2669 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2670 | } | |
2671 | ||
d70b1137 | 2672 | static void rtl8153_disable(struct r8152 *tp) |
2673 | { | |
2674 | r8153_disable_aldps(tp); | |
2675 | rtl_disable(tp); | |
2676 | r8153_enable_aldps(tp); | |
2677 | } | |
2678 | ||
ac718b69 | 2679 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2680 | { | |
43779f8d | 2681 | u16 bmcr, anar, gbcr; |
ac718b69 | 2682 | int ret = 0; |
2683 | ||
2684 | cancel_delayed_work_sync(&tp->schedule); | |
2685 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2686 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2687 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2688 | if (tp->mii.supports_gmii) { |
2689 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2690 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2691 | } else { | |
2692 | gbcr = 0; | |
2693 | } | |
ac718b69 | 2694 | |
2695 | if (autoneg == AUTONEG_DISABLE) { | |
2696 | if (speed == SPEED_10) { | |
2697 | bmcr = 0; | |
2698 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2699 | } else if (speed == SPEED_100) { | |
2700 | bmcr = BMCR_SPEED100; | |
2701 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2702 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2703 | bmcr = BMCR_SPEED1000; | |
2704 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2705 | } else { |
2706 | ret = -EINVAL; | |
2707 | goto out; | |
2708 | } | |
2709 | ||
2710 | if (duplex == DUPLEX_FULL) | |
2711 | bmcr |= BMCR_FULLDPLX; | |
2712 | } else { | |
2713 | if (speed == SPEED_10) { | |
2714 | if (duplex == DUPLEX_FULL) | |
2715 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2716 | else | |
2717 | anar |= ADVERTISE_10HALF; | |
2718 | } else if (speed == SPEED_100) { | |
2719 | if (duplex == DUPLEX_FULL) { | |
2720 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2721 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2722 | } else { | |
2723 | anar |= ADVERTISE_10HALF; | |
2724 | anar |= ADVERTISE_100HALF; | |
2725 | } | |
43779f8d | 2726 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2727 | if (duplex == DUPLEX_FULL) { | |
2728 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2729 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2730 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2731 | } else { | |
2732 | anar |= ADVERTISE_10HALF; | |
2733 | anar |= ADVERTISE_100HALF; | |
2734 | gbcr |= ADVERTISE_1000HALF; | |
2735 | } | |
ac718b69 | 2736 | } else { |
2737 | ret = -EINVAL; | |
2738 | goto out; | |
2739 | } | |
2740 | ||
2741 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2742 | } | |
2743 | ||
aa66a5f1 | 2744 | if (test_bit(PHY_RESET, &tp->flags)) |
2745 | bmcr |= BMCR_RESET; | |
2746 | ||
43779f8d | 2747 | if (tp->mii.supports_gmii) |
2748 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2749 | ||
ac718b69 | 2750 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2751 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2752 | ||
aa66a5f1 | 2753 | if (test_bit(PHY_RESET, &tp->flags)) { |
2754 | int i; | |
2755 | ||
2756 | clear_bit(PHY_RESET, &tp->flags); | |
2757 | for (i = 0; i < 50; i++) { | |
2758 | msleep(20); | |
2759 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2760 | break; | |
2761 | } | |
2762 | } | |
2763 | ||
ac718b69 | 2764 | out: |
ac718b69 | 2765 | |
2766 | return ret; | |
2767 | } | |
2768 | ||
d70b1137 | 2769 | static void rtl8152_up(struct r8152 *tp) |
2770 | { | |
2771 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2772 | return; | |
2773 | ||
2774 | r8152b_disable_aldps(tp); | |
2775 | r8152b_exit_oob(tp); | |
2776 | r8152b_enable_aldps(tp); | |
2777 | } | |
2778 | ||
ac718b69 | 2779 | static void rtl8152_down(struct r8152 *tp) |
2780 | { | |
6871438c | 2781 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2782 | rtl_drop_queued_tx(tp); | |
2783 | return; | |
2784 | } | |
2785 | ||
00a5e360 | 2786 | r8152_power_cut_en(tp, false); |
ac718b69 | 2787 | r8152b_disable_aldps(tp); |
2788 | r8152b_enter_oob(tp); | |
2789 | r8152b_enable_aldps(tp); | |
2790 | } | |
2791 | ||
d70b1137 | 2792 | static void rtl8153_up(struct r8152 *tp) |
2793 | { | |
2794 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2795 | return; | |
2796 | ||
2797 | r8153_disable_aldps(tp); | |
2798 | r8153_first_init(tp); | |
2799 | r8153_enable_aldps(tp); | |
2800 | } | |
2801 | ||
43779f8d | 2802 | static void rtl8153_down(struct r8152 *tp) |
2803 | { | |
6871438c | 2804 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2805 | rtl_drop_queued_tx(tp); | |
2806 | return; | |
2807 | } | |
2808 | ||
b9702723 | 2809 | r8153_u1u2en(tp, false); |
2810 | r8153_power_cut_en(tp, false); | |
43779f8d | 2811 | r8153_disable_aldps(tp); |
2812 | r8153_enter_oob(tp); | |
2813 | r8153_enable_aldps(tp); | |
2814 | } | |
2815 | ||
ac718b69 | 2816 | static void set_carrier(struct r8152 *tp) |
2817 | { | |
2818 | struct net_device *netdev = tp->netdev; | |
2819 | u8 speed; | |
2820 | ||
40a82917 | 2821 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2822 | speed = rtl8152_get_speed(tp); |
2823 | ||
2824 | if (speed & LINK_STATUS) { | |
2825 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2826 | tp->rtl_ops.enable(tp); |
ac718b69 | 2827 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2828 | netif_carrier_on(netdev); | |
2829 | } | |
2830 | } else { | |
2831 | if (tp->speed & LINK_STATUS) { | |
2832 | netif_carrier_off(netdev); | |
ebc2ec48 | 2833 | tasklet_disable(&tp->tl); |
c81229c9 | 2834 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2835 | tasklet_enable(&tp->tl); |
ac718b69 | 2836 | } |
2837 | } | |
2838 | tp->speed = speed; | |
2839 | } | |
2840 | ||
2841 | static void rtl_work_func_t(struct work_struct *work) | |
2842 | { | |
2843 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2844 | ||
9a4be1bd | 2845 | if (usb_autopm_get_interface(tp->intf) < 0) |
2846 | return; | |
2847 | ||
ac718b69 | 2848 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2849 | goto out1; | |
2850 | ||
2851 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2852 | goto out1; | |
2853 | ||
40a82917 | 2854 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2855 | set_carrier(tp); | |
ac718b69 | 2856 | |
2857 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2858 | _rtl8152_set_rx_mode(tp->netdev); | |
2859 | ||
0c3121fc | 2860 | if (test_bit(SCHEDULE_TASKLET, &tp->flags) && |
2861 | (tp->speed & LINK_STATUS)) { | |
2862 | clear_bit(SCHEDULE_TASKLET, &tp->flags); | |
2863 | tasklet_schedule(&tp->tl); | |
2864 | } | |
aa66a5f1 | 2865 | |
2866 | if (test_bit(PHY_RESET, &tp->flags)) | |
2867 | rtl_phy_reset(tp); | |
2868 | ||
ac718b69 | 2869 | out1: |
9a4be1bd | 2870 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2871 | } |
2872 | ||
2873 | static int rtl8152_open(struct net_device *netdev) | |
2874 | { | |
2875 | struct r8152 *tp = netdev_priv(netdev); | |
2876 | int res = 0; | |
2877 | ||
7e9da481 | 2878 | res = alloc_all_mem(tp); |
2879 | if (res) | |
2880 | goto out; | |
2881 | ||
9a4be1bd | 2882 | res = usb_autopm_get_interface(tp->intf); |
2883 | if (res < 0) { | |
2884 | free_all_mem(tp); | |
2885 | goto out; | |
2886 | } | |
2887 | ||
2888 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2889 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2890 | clear_bit(WORK_ENABLE, &tp->flags); | |
2891 | usb_kill_urb(tp->intr_urb); | |
2892 | cancel_delayed_work_sync(&tp->schedule); | |
2893 | if (tp->speed & LINK_STATUS) | |
2894 | tp->rtl_ops.disable(tp); | |
2895 | } | |
2896 | ||
7e9da481 | 2897 | tp->rtl_ops.up(tp); |
2898 | ||
3d55f44f | 2899 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2900 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2901 | DUPLEX_FULL); | |
2902 | tp->speed = 0; | |
2903 | netif_carrier_off(netdev); | |
2904 | netif_start_queue(netdev); | |
2905 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2906 | |
40a82917 | 2907 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2908 | if (res) { | |
2909 | if (res == -ENODEV) | |
2910 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2911 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2912 | res); | |
7e9da481 | 2913 | free_all_mem(tp); |
ac718b69 | 2914 | } |
2915 | ||
9a4be1bd | 2916 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2917 | |
7e9da481 | 2918 | out: |
ac718b69 | 2919 | return res; |
2920 | } | |
2921 | ||
2922 | static int rtl8152_close(struct net_device *netdev) | |
2923 | { | |
2924 | struct r8152 *tp = netdev_priv(netdev); | |
2925 | int res = 0; | |
2926 | ||
2927 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2928 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2929 | cancel_delayed_work_sync(&tp->schedule); |
2930 | netif_stop_queue(netdev); | |
9a4be1bd | 2931 | |
2932 | res = usb_autopm_get_interface(tp->intf); | |
2933 | if (res < 0) { | |
2934 | rtl_drop_queued_tx(tp); | |
2935 | } else { | |
b209af99 | 2936 | /* The autosuspend may have been enabled and wouldn't |
9a4be1bd | 2937 | * be disable when autoresume occurs, because the |
2938 | * netif_running() would be false. | |
2939 | */ | |
2940 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2941 | rtl_runtime_suspend_enable(tp, false); | |
2942 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2943 | } | |
2944 | ||
2945 | tasklet_disable(&tp->tl); | |
2946 | tp->rtl_ops.down(tp); | |
2947 | tasklet_enable(&tp->tl); | |
2948 | usb_autopm_put_interface(tp->intf); | |
2949 | } | |
ac718b69 | 2950 | |
7e9da481 | 2951 | free_all_mem(tp); |
2952 | ||
ac718b69 | 2953 | return res; |
2954 | } | |
2955 | ||
d24f6134 | 2956 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
2957 | { | |
2958 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
2959 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
2960 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
2961 | } | |
2962 | ||
2963 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
2964 | { | |
2965 | u16 data; | |
2966 | ||
2967 | r8152_mmd_indirect(tp, dev, reg); | |
2968 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
2969 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2970 | ||
2971 | return data; | |
2972 | } | |
2973 | ||
2974 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
ac718b69 | 2975 | { |
d24f6134 | 2976 | r8152_mmd_indirect(tp, dev, reg); |
2977 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
2978 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2979 | } | |
2980 | ||
2981 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
2982 | { | |
2983 | u16 config1, config2, config3; | |
45f4a19f | 2984 | u32 ocp_data; |
ac718b69 | 2985 | |
2986 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 2987 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; |
2988 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
2989 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
2990 | ||
2991 | if (enable) { | |
2992 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2993 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
2994 | config1 |= sd_rise_time(1); | |
2995 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
2996 | config3 |= fast_snr(42); | |
2997 | } else { | |
2998 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2999 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
3000 | RX_QUIET_EN); | |
3001 | config1 |= sd_rise_time(7); | |
3002 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
3003 | config3 |= fast_snr(511); | |
3004 | } | |
3005 | ||
ac718b69 | 3006 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3007 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); |
3008 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
3009 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
ac718b69 | 3010 | } |
3011 | ||
d24f6134 | 3012 | static void r8152b_enable_eee(struct r8152 *tp) |
3013 | { | |
3014 | r8152_eee_en(tp, true); | |
3015 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
3016 | } | |
3017 | ||
3018 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
43779f8d | 3019 | { |
3020 | u32 ocp_data; | |
d24f6134 | 3021 | u16 config; |
43779f8d | 3022 | |
3023 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3024 | config = ocp_reg_read(tp, OCP_EEE_CFG); |
3025 | ||
3026 | if (enable) { | |
3027 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3028 | config |= EEE10_EN; | |
3029 | } else { | |
3030 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3031 | config &= ~EEE10_EN; | |
3032 | } | |
3033 | ||
43779f8d | 3034 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3035 | ocp_reg_write(tp, OCP_EEE_CFG, config); |
3036 | } | |
3037 | ||
3038 | static void r8153_enable_eee(struct r8152 *tp) | |
3039 | { | |
3040 | r8153_eee_en(tp, true); | |
3041 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
43779f8d | 3042 | } |
3043 | ||
ac718b69 | 3044 | static void r8152b_enable_fc(struct r8152 *tp) |
3045 | { | |
3046 | u16 anar; | |
3047 | ||
3048 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
3049 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3050 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3051 | } | |
3052 | ||
4f1d4d54 | 3053 | static void rtl_tally_reset(struct r8152 *tp) |
3054 | { | |
3055 | u32 ocp_data; | |
3056 | ||
3057 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3058 | ocp_data |= TALLY_RESET; | |
3059 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3060 | } | |
3061 | ||
ac718b69 | 3062 | static void r8152b_init(struct r8152 *tp) |
3063 | { | |
ebc2ec48 | 3064 | u32 ocp_data; |
ac718b69 | 3065 | |
6871438c | 3066 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3067 | return; | |
3068 | ||
d70b1137 | 3069 | r8152b_disable_aldps(tp); |
3070 | ||
ac718b69 | 3071 | if (tp->version == RTL_VER_01) { |
3072 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3073 | ocp_data &= ~LED_MODE_MASK; | |
3074 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3075 | } | |
3076 | ||
00a5e360 | 3077 | r8152_power_cut_en(tp, false); |
ac718b69 | 3078 | |
ac718b69 | 3079 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3080 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3081 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3082 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3083 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3084 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3085 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3086 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3087 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3088 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3089 | ||
3090 | r8152b_enable_eee(tp); | |
3091 | r8152b_enable_aldps(tp); | |
3092 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3093 | rtl_tally_reset(tp); |
ac718b69 | 3094 | |
ebc2ec48 | 3095 | /* enable rx aggregation */ |
ac718b69 | 3096 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 3097 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 3098 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3099 | } | |
3100 | ||
43779f8d | 3101 | static void r8153_init(struct r8152 *tp) |
3102 | { | |
3103 | u32 ocp_data; | |
3104 | int i; | |
3105 | ||
6871438c | 3106 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3107 | return; | |
3108 | ||
d70b1137 | 3109 | r8153_disable_aldps(tp); |
b9702723 | 3110 | r8153_u1u2en(tp, false); |
43779f8d | 3111 | |
3112 | for (i = 0; i < 500; i++) { | |
3113 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3114 | AUTOLOAD_DONE) | |
3115 | break; | |
3116 | msleep(20); | |
3117 | } | |
3118 | ||
3119 | for (i = 0; i < 500; i++) { | |
3120 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3121 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3122 | break; | |
3123 | msleep(20); | |
3124 | } | |
3125 | ||
b9702723 | 3126 | r8153_u2p3en(tp, false); |
43779f8d | 3127 | |
3128 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
3129 | ocp_data &= ~TIMER11_EN; | |
3130 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3131 | ||
43779f8d | 3132 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3133 | ocp_data &= ~LED_MODE_MASK; | |
3134 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3135 | ||
3136 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
3137 | ocp_data &= ~LPM_TIMER_MASK; | |
3138 | if (tp->udev->speed == USB_SPEED_SUPER) | |
3139 | ocp_data |= LPM_TIMER_500US; | |
3140 | else | |
3141 | ocp_data |= LPM_TIMER_500MS; | |
3142 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
3143 | ||
3144 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3145 | ocp_data &= ~SEN_VAL_MASK; | |
3146 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3147 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3148 | ||
b9702723 | 3149 | r8153_power_cut_en(tp, false); |
3150 | r8153_u1u2en(tp, true); | |
43779f8d | 3151 | |
43779f8d | 3152 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3153 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3154 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3155 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3156 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3157 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3158 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3159 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3160 | EEE_SPDWN_EN); | |
3161 | ||
3162 | r8153_enable_eee(tp); | |
3163 | r8153_enable_aldps(tp); | |
3164 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3165 | rtl_tally_reset(tp); |
43779f8d | 3166 | } |
3167 | ||
ac718b69 | 3168 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3169 | { | |
3170 | struct r8152 *tp = usb_get_intfdata(intf); | |
3171 | ||
9a4be1bd | 3172 | if (PMSG_IS_AUTO(message)) |
3173 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3174 | else | |
3175 | netif_device_detach(tp->netdev); | |
ac718b69 | 3176 | |
3177 | if (netif_running(tp->netdev)) { | |
3178 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 3179 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3180 | cancel_delayed_work_sync(&tp->schedule); |
445f7f4d | 3181 | tasklet_disable(&tp->tl); |
9a4be1bd | 3182 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
445f7f4d | 3183 | rtl_stop_rx(tp); |
9a4be1bd | 3184 | rtl_runtime_suspend_enable(tp, true); |
3185 | } else { | |
9a4be1bd | 3186 | tp->rtl_ops.down(tp); |
9a4be1bd | 3187 | } |
445f7f4d | 3188 | tasklet_enable(&tp->tl); |
ac718b69 | 3189 | } |
3190 | ||
ac718b69 | 3191 | return 0; |
3192 | } | |
3193 | ||
3194 | static int rtl8152_resume(struct usb_interface *intf) | |
3195 | { | |
3196 | struct r8152 *tp = usb_get_intfdata(intf); | |
3197 | ||
9a4be1bd | 3198 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3199 | tp->rtl_ops.init(tp); | |
3200 | netif_device_attach(tp->netdev); | |
3201 | } | |
3202 | ||
ac718b69 | 3203 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3204 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3205 | rtl_runtime_suspend_enable(tp, false); | |
3206 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
445f7f4d | 3207 | set_bit(WORK_ENABLE, &tp->flags); |
9a4be1bd | 3208 | if (tp->speed & LINK_STATUS) |
445f7f4d | 3209 | rtl_start_rx(tp); |
9a4be1bd | 3210 | } else { |
3211 | tp->rtl_ops.up(tp); | |
3212 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3213 | tp->mii.supports_gmii ? |
3214 | SPEED_1000 : SPEED_100, | |
3215 | DUPLEX_FULL); | |
445f7f4d | 3216 | tp->speed = 0; |
3217 | netif_carrier_off(tp->netdev); | |
3218 | set_bit(WORK_ENABLE, &tp->flags); | |
9a4be1bd | 3219 | } |
40a82917 | 3220 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 3221 | } |
3222 | ||
3223 | return 0; | |
3224 | } | |
3225 | ||
21ff2e89 | 3226 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3227 | { | |
3228 | struct r8152 *tp = netdev_priv(dev); | |
3229 | ||
9a4be1bd | 3230 | if (usb_autopm_get_interface(tp->intf) < 0) |
3231 | return; | |
3232 | ||
21ff2e89 | 3233 | wol->supported = WAKE_ANY; |
3234 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 3235 | |
3236 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 3237 | } |
3238 | ||
3239 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3240 | { | |
3241 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3242 | int ret; |
3243 | ||
3244 | ret = usb_autopm_get_interface(tp->intf); | |
3245 | if (ret < 0) | |
3246 | goto out_set_wol; | |
21ff2e89 | 3247 | |
3248 | __rtl_set_wol(tp, wol->wolopts); | |
3249 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3250 | ||
9a4be1bd | 3251 | usb_autopm_put_interface(tp->intf); |
3252 | ||
3253 | out_set_wol: | |
3254 | return ret; | |
21ff2e89 | 3255 | } |
3256 | ||
a5ec27c1 | 3257 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3258 | { | |
3259 | struct r8152 *tp = netdev_priv(dev); | |
3260 | ||
3261 | return tp->msg_enable; | |
3262 | } | |
3263 | ||
3264 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3265 | { | |
3266 | struct r8152 *tp = netdev_priv(dev); | |
3267 | ||
3268 | tp->msg_enable = value; | |
3269 | } | |
3270 | ||
ac718b69 | 3271 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3272 | struct ethtool_drvinfo *info) | |
3273 | { | |
3274 | struct r8152 *tp = netdev_priv(netdev); | |
3275 | ||
b0b46c77 | 3276 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3277 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3278 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3279 | } | |
3280 | ||
3281 | static | |
3282 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3283 | { | |
3284 | struct r8152 *tp = netdev_priv(netdev); | |
3285 | ||
3286 | if (!tp->mii.mdio_read) | |
3287 | return -EOPNOTSUPP; | |
3288 | ||
3289 | return mii_ethtool_gset(&tp->mii, cmd); | |
3290 | } | |
3291 | ||
3292 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3293 | { | |
3294 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3295 | int ret; |
3296 | ||
3297 | ret = usb_autopm_get_interface(tp->intf); | |
3298 | if (ret < 0) | |
3299 | goto out; | |
ac718b69 | 3300 | |
9a4be1bd | 3301 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3302 | ||
3303 | usb_autopm_put_interface(tp->intf); | |
3304 | ||
3305 | out: | |
3306 | return ret; | |
ac718b69 | 3307 | } |
3308 | ||
4f1d4d54 | 3309 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3310 | "tx_packets", | |
3311 | "rx_packets", | |
3312 | "tx_errors", | |
3313 | "rx_errors", | |
3314 | "rx_missed", | |
3315 | "align_errors", | |
3316 | "tx_single_collisions", | |
3317 | "tx_multi_collisions", | |
3318 | "rx_unicast", | |
3319 | "rx_broadcast", | |
3320 | "rx_multicast", | |
3321 | "tx_aborted", | |
3322 | "tx_underrun", | |
3323 | }; | |
3324 | ||
3325 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3326 | { | |
3327 | switch (sset) { | |
3328 | case ETH_SS_STATS: | |
3329 | return ARRAY_SIZE(rtl8152_gstrings); | |
3330 | default: | |
3331 | return -EOPNOTSUPP; | |
3332 | } | |
3333 | } | |
3334 | ||
3335 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3336 | struct ethtool_stats *stats, u64 *data) | |
3337 | { | |
3338 | struct r8152 *tp = netdev_priv(dev); | |
3339 | struct tally_counter tally; | |
3340 | ||
0b030244 | 3341 | if (usb_autopm_get_interface(tp->intf) < 0) |
3342 | return; | |
3343 | ||
4f1d4d54 | 3344 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3345 | ||
0b030244 | 3346 | usb_autopm_put_interface(tp->intf); |
3347 | ||
4f1d4d54 | 3348 | data[0] = le64_to_cpu(tally.tx_packets); |
3349 | data[1] = le64_to_cpu(tally.rx_packets); | |
3350 | data[2] = le64_to_cpu(tally.tx_errors); | |
3351 | data[3] = le32_to_cpu(tally.rx_errors); | |
3352 | data[4] = le16_to_cpu(tally.rx_missed); | |
3353 | data[5] = le16_to_cpu(tally.align_errors); | |
3354 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3355 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3356 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3357 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3358 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3359 | data[11] = le16_to_cpu(tally.tx_aborted); | |
3360 | data[12] = le16_to_cpu(tally.tx_underun); | |
3361 | } | |
3362 | ||
3363 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3364 | { | |
3365 | switch (stringset) { | |
3366 | case ETH_SS_STATS: | |
3367 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3368 | break; | |
3369 | } | |
3370 | } | |
3371 | ||
df35d283 | 3372 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
3373 | { | |
3374 | u32 ocp_data, lp, adv, supported = 0; | |
3375 | u16 val; | |
3376 | ||
3377 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
3378 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3379 | ||
3380 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
3381 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3382 | ||
3383 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
3384 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3385 | ||
3386 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3387 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3388 | ||
3389 | eee->eee_enabled = !!ocp_data; | |
3390 | eee->eee_active = !!(supported & adv & lp); | |
3391 | eee->supported = supported; | |
3392 | eee->advertised = adv; | |
3393 | eee->lp_advertised = lp; | |
3394 | ||
3395 | return 0; | |
3396 | } | |
3397 | ||
3398 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3399 | { | |
3400 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3401 | ||
3402 | r8152_eee_en(tp, eee->eee_enabled); | |
3403 | ||
3404 | if (!eee->eee_enabled) | |
3405 | val = 0; | |
3406 | ||
3407 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3408 | ||
3409 | return 0; | |
3410 | } | |
3411 | ||
3412 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3413 | { | |
3414 | u32 ocp_data, lp, adv, supported = 0; | |
3415 | u16 val; | |
3416 | ||
3417 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
3418 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3419 | ||
3420 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
3421 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3422 | ||
3423 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
3424 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3425 | ||
3426 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3427 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3428 | ||
3429 | eee->eee_enabled = !!ocp_data; | |
3430 | eee->eee_active = !!(supported & adv & lp); | |
3431 | eee->supported = supported; | |
3432 | eee->advertised = adv; | |
3433 | eee->lp_advertised = lp; | |
3434 | ||
3435 | return 0; | |
3436 | } | |
3437 | ||
3438 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3439 | { | |
3440 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3441 | ||
3442 | r8153_eee_en(tp, eee->eee_enabled); | |
3443 | ||
3444 | if (!eee->eee_enabled) | |
3445 | val = 0; | |
3446 | ||
3447 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
3448 | ||
3449 | return 0; | |
3450 | } | |
3451 | ||
3452 | static int | |
3453 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
3454 | { | |
3455 | struct r8152 *tp = netdev_priv(net); | |
3456 | int ret; | |
3457 | ||
3458 | ret = usb_autopm_get_interface(tp->intf); | |
3459 | if (ret < 0) | |
3460 | goto out; | |
3461 | ||
3462 | ret = tp->rtl_ops.eee_get(tp, edata); | |
3463 | ||
3464 | usb_autopm_put_interface(tp->intf); | |
3465 | ||
3466 | out: | |
3467 | return ret; | |
3468 | } | |
3469 | ||
3470 | static int | |
3471 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
3472 | { | |
3473 | struct r8152 *tp = netdev_priv(net); | |
3474 | int ret; | |
3475 | ||
3476 | ret = usb_autopm_get_interface(tp->intf); | |
3477 | if (ret < 0) | |
3478 | goto out; | |
3479 | ||
3480 | ret = tp->rtl_ops.eee_set(tp, edata); | |
9d31a7b9 | 3481 | if (!ret) |
3482 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 3483 | |
3484 | usb_autopm_put_interface(tp->intf); | |
3485 | ||
3486 | out: | |
3487 | return ret; | |
3488 | } | |
3489 | ||
ac718b69 | 3490 | static struct ethtool_ops ops = { |
3491 | .get_drvinfo = rtl8152_get_drvinfo, | |
3492 | .get_settings = rtl8152_get_settings, | |
3493 | .set_settings = rtl8152_set_settings, | |
3494 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 3495 | .get_msglevel = rtl8152_get_msglevel, |
3496 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3497 | .get_wol = rtl8152_get_wol, |
3498 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3499 | .get_strings = rtl8152_get_strings, |
3500 | .get_sset_count = rtl8152_get_sset_count, | |
3501 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
df35d283 | 3502 | .get_eee = rtl_ethtool_get_eee, |
3503 | .set_eee = rtl_ethtool_set_eee, | |
ac718b69 | 3504 | }; |
3505 | ||
3506 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3507 | { | |
3508 | struct r8152 *tp = netdev_priv(netdev); | |
3509 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3510 | int res; |
3511 | ||
6871438c | 3512 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3513 | return -ENODEV; | |
3514 | ||
9a4be1bd | 3515 | res = usb_autopm_get_interface(tp->intf); |
3516 | if (res < 0) | |
3517 | goto out; | |
ac718b69 | 3518 | |
3519 | switch (cmd) { | |
3520 | case SIOCGMIIPHY: | |
3521 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3522 | break; | |
3523 | ||
3524 | case SIOCGMIIREG: | |
3525 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
3526 | break; | |
3527 | ||
3528 | case SIOCSMIIREG: | |
3529 | if (!capable(CAP_NET_ADMIN)) { | |
3530 | res = -EPERM; | |
3531 | break; | |
3532 | } | |
3533 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
3534 | break; | |
3535 | ||
3536 | default: | |
3537 | res = -EOPNOTSUPP; | |
3538 | } | |
3539 | ||
9a4be1bd | 3540 | usb_autopm_put_interface(tp->intf); |
3541 | ||
3542 | out: | |
ac718b69 | 3543 | return res; |
3544 | } | |
3545 | ||
69b4b7a4 | 3546 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3547 | { | |
3548 | struct r8152 *tp = netdev_priv(dev); | |
3549 | ||
3550 | switch (tp->version) { | |
3551 | case RTL_VER_01: | |
3552 | case RTL_VER_02: | |
3553 | return eth_change_mtu(dev, new_mtu); | |
3554 | default: | |
3555 | break; | |
3556 | } | |
3557 | ||
3558 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3559 | return -EINVAL; | |
3560 | ||
3561 | dev->mtu = new_mtu; | |
3562 | ||
3563 | return 0; | |
3564 | } | |
3565 | ||
ac718b69 | 3566 | static const struct net_device_ops rtl8152_netdev_ops = { |
3567 | .ndo_open = rtl8152_open, | |
3568 | .ndo_stop = rtl8152_close, | |
3569 | .ndo_do_ioctl = rtl8152_ioctl, | |
3570 | .ndo_start_xmit = rtl8152_start_xmit, | |
3571 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 3572 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 3573 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
3574 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3575 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3576 | .ndo_validate_addr = eth_validate_addr, |
3577 | }; | |
3578 | ||
3579 | static void r8152b_get_version(struct r8152 *tp) | |
3580 | { | |
3581 | u32 ocp_data; | |
3582 | u16 version; | |
3583 | ||
3584 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3585 | version = (u16)(ocp_data & VERSION_MASK); | |
3586 | ||
3587 | switch (version) { | |
3588 | case 0x4c00: | |
3589 | tp->version = RTL_VER_01; | |
3590 | break; | |
3591 | case 0x4c10: | |
3592 | tp->version = RTL_VER_02; | |
3593 | break; | |
43779f8d | 3594 | case 0x5c00: |
3595 | tp->version = RTL_VER_03; | |
3596 | tp->mii.supports_gmii = 1; | |
3597 | break; | |
3598 | case 0x5c10: | |
3599 | tp->version = RTL_VER_04; | |
3600 | tp->mii.supports_gmii = 1; | |
3601 | break; | |
3602 | case 0x5c20: | |
3603 | tp->version = RTL_VER_05; | |
3604 | tp->mii.supports_gmii = 1; | |
3605 | break; | |
ac718b69 | 3606 | default: |
3607 | netif_info(tp, probe, tp->netdev, | |
3608 | "Unknown version 0x%04x\n", version); | |
3609 | break; | |
3610 | } | |
3611 | } | |
3612 | ||
e3fe0b1a | 3613 | static void rtl8152_unload(struct r8152 *tp) |
3614 | { | |
6871438c | 3615 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3616 | return; | |
3617 | ||
00a5e360 | 3618 | if (tp->version != RTL_VER_01) |
3619 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3620 | } |
3621 | ||
43779f8d | 3622 | static void rtl8153_unload(struct r8152 *tp) |
3623 | { | |
6871438c | 3624 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3625 | return; | |
3626 | ||
49be1723 | 3627 | r8153_power_cut_en(tp, false); |
43779f8d | 3628 | } |
3629 | ||
31ca1dec | 3630 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3631 | { |
3632 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3633 | int ret = -ENODEV; |
c81229c9 | 3634 | |
3635 | switch (id->idVendor) { | |
3636 | case VENDOR_ID_REALTEK: | |
3637 | switch (id->idProduct) { | |
3638 | case PRODUCT_ID_RTL8152: | |
3639 | ops->init = r8152b_init; | |
3640 | ops->enable = rtl8152_enable; | |
3641 | ops->disable = rtl8152_disable; | |
d70b1137 | 3642 | ops->up = rtl8152_up; |
c81229c9 | 3643 | ops->down = rtl8152_down; |
3644 | ops->unload = rtl8152_unload; | |
df35d283 | 3645 | ops->eee_get = r8152_get_eee; |
3646 | ops->eee_set = r8152_set_eee; | |
31ca1dec | 3647 | ret = 0; |
c81229c9 | 3648 | break; |
43779f8d | 3649 | case PRODUCT_ID_RTL8153: |
3650 | ops->init = r8153_init; | |
3651 | ops->enable = rtl8153_enable; | |
d70b1137 | 3652 | ops->disable = rtl8153_disable; |
3653 | ops->up = rtl8153_up; | |
43779f8d | 3654 | ops->down = rtl8153_down; |
3655 | ops->unload = rtl8153_unload; | |
df35d283 | 3656 | ops->eee_get = r8153_get_eee; |
3657 | ops->eee_set = r8153_set_eee; | |
31ca1dec | 3658 | ret = 0; |
43779f8d | 3659 | break; |
3660 | default: | |
43779f8d | 3661 | break; |
3662 | } | |
3663 | break; | |
3664 | ||
3665 | case VENDOR_ID_SAMSUNG: | |
3666 | switch (id->idProduct) { | |
3667 | case PRODUCT_ID_SAMSUNG: | |
3668 | ops->init = r8153_init; | |
3669 | ops->enable = rtl8153_enable; | |
d70b1137 | 3670 | ops->disable = rtl8153_disable; |
3671 | ops->up = rtl8153_up; | |
43779f8d | 3672 | ops->down = rtl8153_down; |
3673 | ops->unload = rtl8153_unload; | |
df35d283 | 3674 | ops->eee_get = r8153_get_eee; |
3675 | ops->eee_set = r8153_set_eee; | |
31ca1dec | 3676 | ret = 0; |
43779f8d | 3677 | break; |
c81229c9 | 3678 | default: |
c81229c9 | 3679 | break; |
3680 | } | |
3681 | break; | |
3682 | ||
3683 | default: | |
c81229c9 | 3684 | break; |
3685 | } | |
3686 | ||
31ca1dec | 3687 | if (ret) |
3688 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3689 | ||
c81229c9 | 3690 | return ret; |
3691 | } | |
3692 | ||
ac718b69 | 3693 | static int rtl8152_probe(struct usb_interface *intf, |
3694 | const struct usb_device_id *id) | |
3695 | { | |
3696 | struct usb_device *udev = interface_to_usbdev(intf); | |
3697 | struct r8152 *tp; | |
3698 | struct net_device *netdev; | |
ebc2ec48 | 3699 | int ret; |
ac718b69 | 3700 | |
10c32717 | 3701 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
3702 | usb_driver_set_configuration(udev, 1); | |
3703 | return -ENODEV; | |
3704 | } | |
3705 | ||
3706 | usb_reset_device(udev); | |
ac718b69 | 3707 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3708 | if (!netdev) { | |
4a8deae2 | 3709 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3710 | return -ENOMEM; |
3711 | } | |
3712 | ||
ebc2ec48 | 3713 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3714 | tp = netdev_priv(netdev); |
3715 | tp->msg_enable = 0x7FFF; | |
3716 | ||
e3ad412a | 3717 | tp->udev = udev; |
3718 | tp->netdev = netdev; | |
3719 | tp->intf = intf; | |
3720 | ||
31ca1dec | 3721 | ret = rtl_ops_init(tp, id); |
3722 | if (ret) | |
3723 | goto out; | |
c81229c9 | 3724 | |
ebc2ec48 | 3725 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3726 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3727 | ||
ac718b69 | 3728 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3729 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3730 | |
60c89071 | 3731 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3732 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 3733 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
3734 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 3735 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3736 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 3737 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
3738 | NETIF_F_HW_VLAN_CTAG_RX | | |
3739 | NETIF_F_HW_VLAN_CTAG_TX; | |
3740 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
3741 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
3742 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 3743 | |
7ad24ea4 | 3744 | netdev->ethtool_ops = &ops; |
60c89071 | 3745 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 3746 | |
3747 | tp->mii.dev = netdev; | |
3748 | tp->mii.mdio_read = read_mii_word; | |
3749 | tp->mii.mdio_write = write_mii_word; | |
3750 | tp->mii.phy_id_mask = 0x3f; | |
3751 | tp->mii.reg_num_mask = 0x1f; | |
3752 | tp->mii.phy_id = R8152_PHY_ID; | |
3753 | tp->mii.supports_gmii = 0; | |
3754 | ||
9a4be1bd | 3755 | intf->needs_remote_wakeup = 1; |
3756 | ||
ac718b69 | 3757 | r8152b_get_version(tp); |
c81229c9 | 3758 | tp->rtl_ops.init(tp); |
ac718b69 | 3759 | set_ethernet_addr(tp); |
3760 | ||
ac718b69 | 3761 | usb_set_intfdata(intf, tp); |
ac718b69 | 3762 | |
ebc2ec48 | 3763 | ret = register_netdev(netdev); |
3764 | if (ret != 0) { | |
4a8deae2 | 3765 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3766 | goto out1; |
ac718b69 | 3767 | } |
3768 | ||
21ff2e89 | 3769 | tp->saved_wolopts = __rtl_get_wol(tp); |
3770 | if (tp->saved_wolopts) | |
3771 | device_set_wakeup_enable(&udev->dev, true); | |
3772 | else | |
3773 | device_set_wakeup_enable(&udev->dev, false); | |
3774 | ||
4a8deae2 | 3775 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3776 | |
3777 | return 0; | |
3778 | ||
ac718b69 | 3779 | out1: |
ebc2ec48 | 3780 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3781 | out: |
3782 | free_netdev(netdev); | |
ebc2ec48 | 3783 | return ret; |
ac718b69 | 3784 | } |
3785 | ||
ac718b69 | 3786 | static void rtl8152_disconnect(struct usb_interface *intf) |
3787 | { | |
3788 | struct r8152 *tp = usb_get_intfdata(intf); | |
3789 | ||
3790 | usb_set_intfdata(intf, NULL); | |
3791 | if (tp) { | |
f561de33 | 3792 | struct usb_device *udev = tp->udev; |
3793 | ||
3794 | if (udev->state == USB_STATE_NOTATTACHED) | |
3795 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3796 | ||
ac718b69 | 3797 | tasklet_kill(&tp->tl); |
3798 | unregister_netdev(tp->netdev); | |
c81229c9 | 3799 | tp->rtl_ops.unload(tp); |
ac718b69 | 3800 | free_netdev(tp->netdev); |
3801 | } | |
3802 | } | |
3803 | ||
3804 | /* table of devices that work with this driver */ | |
3805 | static struct usb_device_id rtl8152_table[] = { | |
10c32717 | 3806 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3807 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3808 | {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3809 | {} |
3810 | }; | |
3811 | ||
3812 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3813 | ||
3814 | static struct usb_driver rtl8152_driver = { | |
3815 | .name = MODULENAME, | |
ebc2ec48 | 3816 | .id_table = rtl8152_table, |
ac718b69 | 3817 | .probe = rtl8152_probe, |
3818 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3819 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3820 | .resume = rtl8152_resume, |
3821 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3822 | .supports_autosuspend = 1, |
a634782f | 3823 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3824 | }; |
3825 | ||
b4236daa | 3826 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3827 | |
3828 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3829 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3830 | MODULE_LICENSE("GPL"); |