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[thirdparty/kernel/linux.git] / drivers / net / usb / r8152.c
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ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
ac718b69 27
28/* Version Information */
b5403273 29#define DRIVER_VERSION "v1.07.0 (2014/10/09)"
ac718b69 30#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 31#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 32#define MODULENAME "r8152"
33
34#define R8152_PHY_ID 32
35
36#define PLA_IDR 0xc000
37#define PLA_RCR 0xc010
38#define PLA_RMS 0xc016
39#define PLA_RXFIFO_CTRL0 0xc0a0
40#define PLA_RXFIFO_CTRL1 0xc0a4
41#define PLA_RXFIFO_CTRL2 0xc0a8
42#define PLA_FMC 0xc0b4
43#define PLA_CFG_WOL 0xc0b6
43779f8d 44#define PLA_TEREDO_CFG 0xc0bc
ac718b69 45#define PLA_MAR 0xcd00
43779f8d 46#define PLA_BACKUP 0xd000
ac718b69 47#define PAL_BDC_CR 0xd1a0
43779f8d 48#define PLA_TEREDO_TIMER 0xd2cc
49#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 50#define PLA_LEDSEL 0xdd90
51#define PLA_LED_FEATURE 0xdd92
52#define PLA_PHYAR 0xde00
43779f8d 53#define PLA_BOOT_CTRL 0xe004
ac718b69 54#define PLA_GPHY_INTR_IMR 0xe022
55#define PLA_EEE_CR 0xe040
56#define PLA_EEEP_CR 0xe080
57#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 58#define PLA_MAC_PWR_CTRL2 0xe0ca
59#define PLA_MAC_PWR_CTRL3 0xe0cc
60#define PLA_MAC_PWR_CTRL4 0xe0ce
61#define PLA_WDT6_CTRL 0xe428
ac718b69 62#define PLA_TCR0 0xe610
63#define PLA_TCR1 0xe612
69b4b7a4 64#define PLA_MTPS 0xe615
ac718b69 65#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 66#define PLA_RSTTALLY 0xe800
ac718b69 67#define PLA_CR 0xe813
68#define PLA_CRWECR 0xe81c
21ff2e89 69#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 71#define PLA_CONFIG5 0xe822
72#define PLA_PHY_PWR 0xe84c
73#define PLA_OOB_CTRL 0xe84f
74#define PLA_CPCR 0xe854
75#define PLA_MISC_0 0xe858
76#define PLA_MISC_1 0xe85a
77#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 78#define PLA_TALLYCNT 0xe890
ac718b69 79#define PLA_SFF_STS_7 0xe8de
80#define PLA_PHYSTATUS 0xe908
81#define PLA_BP_BA 0xfc26
82#define PLA_BP_0 0xfc28
83#define PLA_BP_1 0xfc2a
84#define PLA_BP_2 0xfc2c
85#define PLA_BP_3 0xfc2e
86#define PLA_BP_4 0xfc30
87#define PLA_BP_5 0xfc32
88#define PLA_BP_6 0xfc34
89#define PLA_BP_7 0xfc36
43779f8d 90#define PLA_BP_EN 0xfc38
ac718b69 91
43779f8d 92#define USB_U2P3_CTRL 0xb460
ac718b69 93#define USB_DEV_STAT 0xb808
94#define USB_USB_CTRL 0xd406
95#define USB_PHY_CTRL 0xd408
96#define USB_TX_AGG 0xd40a
97#define USB_RX_BUF_TH 0xd40c
98#define USB_USB_TIMER 0xd428
43779f8d 99#define USB_RX_EARLY_AGG 0xd42c
ac718b69 100#define USB_PM_CTRL_STATUS 0xd432
101#define USB_TX_DMA 0xd434
43779f8d 102#define USB_TOLERANCE 0xd490
103#define USB_LPM_CTRL 0xd41a
ac718b69 104#define USB_UPS_CTRL 0xd800
43779f8d 105#define USB_MISC_0 0xd81a
106#define USB_POWER_CUT 0xd80a
107#define USB_AFE_CTRL2 0xd824
108#define USB_WDT11_CTRL 0xe43c
ac718b69 109#define USB_BP_BA 0xfc26
110#define USB_BP_0 0xfc28
111#define USB_BP_1 0xfc2a
112#define USB_BP_2 0xfc2c
113#define USB_BP_3 0xfc2e
114#define USB_BP_4 0xfc30
115#define USB_BP_5 0xfc32
116#define USB_BP_6 0xfc34
117#define USB_BP_7 0xfc36
43779f8d 118#define USB_BP_EN 0xfc38
ac718b69 119
120/* OCP Registers */
121#define OCP_ALDPS_CONFIG 0x2010
122#define OCP_EEE_CONFIG1 0x2080
123#define OCP_EEE_CONFIG2 0x2092
124#define OCP_EEE_CONFIG3 0x2094
ac244d3e 125#define OCP_BASE_MII 0xa400
ac718b69 126#define OCP_EEE_AR 0xa41a
127#define OCP_EEE_DATA 0xa41c
43779f8d 128#define OCP_PHY_STATUS 0xa420
129#define OCP_POWER_CFG 0xa430
130#define OCP_EEE_CFG 0xa432
131#define OCP_SRAM_ADDR 0xa436
132#define OCP_SRAM_DATA 0xa438
133#define OCP_DOWN_SPEED 0xa442
df35d283 134#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 135#define OCP_EEE_ADV 0xa5d0
df35d283 136#define OCP_EEE_LPABLE 0xa5d2
43779f8d 137#define OCP_ADC_CFG 0xbc06
138
139/* SRAM Register */
140#define SRAM_LPF_CFG 0x8012
141#define SRAM_10M_AMP1 0x8080
142#define SRAM_10M_AMP2 0x8082
143#define SRAM_IMPEDANCE 0x8084
ac718b69 144
145/* PLA_RCR */
146#define RCR_AAP 0x00000001
147#define RCR_APM 0x00000002
148#define RCR_AM 0x00000004
149#define RCR_AB 0x00000008
150#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152/* PLA_RXFIFO_CTRL0 */
153#define RXFIFO_THR1_NORMAL 0x00080002
154#define RXFIFO_THR1_OOB 0x01800003
155
156/* PLA_RXFIFO_CTRL1 */
157#define RXFIFO_THR2_FULL 0x00000060
158#define RXFIFO_THR2_HIGH 0x00000038
159#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 160#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 161
162/* PLA_RXFIFO_CTRL2 */
163#define RXFIFO_THR3_FULL 0x00000078
164#define RXFIFO_THR3_HIGH 0x00000048
165#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 166#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 167
168/* PLA_TXFIFO_CTRL */
169#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 170#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 171
172/* PLA_FMC */
173#define FMC_FCR_MCU_EN 0x0001
174
175/* PLA_EEEP_CR */
176#define EEEP_CR_EEEP_TX 0x0002
177
43779f8d 178/* PLA_WDT6_CTRL */
179#define WDT6_SET_MODE 0x0010
180
ac718b69 181/* PLA_TCR0 */
182#define TCR0_TX_EMPTY 0x0800
183#define TCR0_AUTO_FIFO 0x0080
184
185/* PLA_TCR1 */
186#define VERSION_MASK 0x7cf0
187
69b4b7a4 188/* PLA_MTPS */
189#define MTPS_JUMBO (12 * 1024 / 64)
190#define MTPS_DEFAULT (6 * 1024 / 64)
191
4f1d4d54 192/* PLA_RSTTALLY */
193#define TALLY_RESET 0x0001
194
ac718b69 195/* PLA_CR */
196#define CR_RST 0x10
197#define CR_RE 0x08
198#define CR_TE 0x04
199
200/* PLA_CRWECR */
201#define CRWECR_NORAML 0x00
202#define CRWECR_CONFIG 0xc0
203
204/* PLA_OOB_CTRL */
205#define NOW_IS_OOB 0x80
206#define TXFIFO_EMPTY 0x20
207#define RXFIFO_EMPTY 0x10
208#define LINK_LIST_READY 0x02
209#define DIS_MCU_CLROOB 0x01
210#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212/* PLA_MISC_1 */
213#define RXDY_GATED_EN 0x0008
214
215/* PLA_SFF_STS_7 */
216#define RE_INIT_LL 0x8000
217#define MCU_BORW_EN 0x4000
218
219/* PLA_CPCR */
220#define CPCR_RX_VLAN 0x0040
221
222/* PLA_CFG_WOL */
223#define MAGIC_EN 0x0001
224
43779f8d 225/* PLA_TEREDO_CFG */
226#define TEREDO_SEL 0x8000
227#define TEREDO_WAKE_MASK 0x7f00
228#define TEREDO_RS_EVENT_MASK 0x00fe
229#define OOB_TEREDO_EN 0x0001
230
ac718b69 231/* PAL_BDC_CR */
232#define ALDPS_PROXY_MODE 0x0001
233
21ff2e89 234/* PLA_CONFIG34 */
235#define LINK_ON_WAKE_EN 0x0010
236#define LINK_OFF_WAKE_EN 0x0008
237
ac718b69 238/* PLA_CONFIG5 */
21ff2e89 239#define BWF_EN 0x0040
240#define MWF_EN 0x0020
241#define UWF_EN 0x0010
ac718b69 242#define LAN_WAKE_EN 0x0002
243
244/* PLA_LED_FEATURE */
245#define LED_MODE_MASK 0x0700
246
247/* PLA_PHY_PWR */
248#define TX_10M_IDLE_EN 0x0080
249#define PFM_PWM_SWITCH 0x0040
250
251/* PLA_MAC_PWR_CTRL */
252#define D3_CLK_GATED_EN 0x00004000
253#define MCU_CLK_RATIO 0x07010f07
254#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 255#define ALDPS_SPDWN_RATIO 0x0f87
256
257/* PLA_MAC_PWR_CTRL2 */
258#define EEE_SPDWN_RATIO 0x8007
259
260/* PLA_MAC_PWR_CTRL3 */
261#define PKT_AVAIL_SPDWN_EN 0x0100
262#define SUSPEND_SPDWN_EN 0x0004
263#define U1U2_SPDWN_EN 0x0002
264#define L1_SPDWN_EN 0x0001
265
266/* PLA_MAC_PWR_CTRL4 */
267#define PWRSAVE_SPDWN_EN 0x1000
268#define RXDV_SPDWN_EN 0x0800
269#define TX10MIDLE_EN 0x0100
270#define TP100_SPDWN_EN 0x0020
271#define TP500_SPDWN_EN 0x0010
272#define TP1000_SPDWN_EN 0x0008
273#define EEE_SPDWN_EN 0x0001
ac718b69 274
275/* PLA_GPHY_INTR_IMR */
276#define GPHY_STS_MSK 0x0001
277#define SPEED_DOWN_MSK 0x0002
278#define SPDWN_RXDV_MSK 0x0004
279#define SPDWN_LINKCHG_MSK 0x0008
280
281/* PLA_PHYAR */
282#define PHYAR_FLAG 0x80000000
283
284/* PLA_EEE_CR */
285#define EEE_RX_EN 0x0001
286#define EEE_TX_EN 0x0002
287
43779f8d 288/* PLA_BOOT_CTRL */
289#define AUTOLOAD_DONE 0x0002
290
ac718b69 291/* USB_DEV_STAT */
292#define STAT_SPEED_MASK 0x0006
293#define STAT_SPEED_HIGH 0x0000
a3cc465d 294#define STAT_SPEED_FULL 0x0002
ac718b69 295
296/* USB_TX_AGG */
297#define TX_AGG_MAX_THRESHOLD 0x03
298
299/* USB_RX_BUF_TH */
43779f8d 300#define RX_THR_SUPPER 0x0c350180
8e1f51bd 301#define RX_THR_HIGH 0x7a120180
43779f8d 302#define RX_THR_SLOW 0xffff0180
ac718b69 303
304/* USB_TX_DMA */
305#define TEST_MODE_DISABLE 0x00000001
306#define TX_SIZE_ADJUST1 0x00000100
307
308/* USB_UPS_CTRL */
309#define POWER_CUT 0x0100
310
311/* USB_PM_CTRL_STATUS */
8e1f51bd 312#define RESUME_INDICATE 0x0001
ac718b69 313
314/* USB_USB_CTRL */
315#define RX_AGG_DISABLE 0x0010
316
43779f8d 317/* USB_U2P3_CTRL */
318#define U2P3_ENABLE 0x0001
319
320/* USB_POWER_CUT */
321#define PWR_EN 0x0001
322#define PHASE2_EN 0x0008
323
324/* USB_MISC_0 */
325#define PCUT_STATUS 0x0001
326
327/* USB_RX_EARLY_AGG */
328#define EARLY_AGG_SUPPER 0x0e832981
329#define EARLY_AGG_HIGH 0x0e837a12
330#define EARLY_AGG_SLOW 0x0e83ffff
331
332/* USB_WDT11_CTRL */
333#define TIMER11_EN 0x0001
334
335/* USB_LPM_CTRL */
336#define LPM_TIMER_MASK 0x0c
337#define LPM_TIMER_500MS 0x04 /* 500 ms */
338#define LPM_TIMER_500US 0x0c /* 500 us */
339
340/* USB_AFE_CTRL2 */
341#define SEN_VAL_MASK 0xf800
342#define SEN_VAL_NORMAL 0xa000
343#define SEL_RXIDLE 0x0100
344
ac718b69 345/* OCP_ALDPS_CONFIG */
346#define ENPWRSAVE 0x8000
347#define ENPDNPS 0x0200
348#define LINKENA 0x0100
349#define DIS_SDSAVE 0x0010
350
43779f8d 351/* OCP_PHY_STATUS */
352#define PHY_STAT_MASK 0x0007
353#define PHY_STAT_LAN_ON 3
354#define PHY_STAT_PWRDN 5
355
356/* OCP_POWER_CFG */
357#define EEE_CLKDIV_EN 0x8000
358#define EN_ALDPS 0x0004
359#define EN_10M_PLLOFF 0x0001
360
ac718b69 361/* OCP_EEE_CONFIG1 */
362#define RG_TXLPI_MSK_HFDUP 0x8000
363#define RG_MATCLR_EN 0x4000
364#define EEE_10_CAP 0x2000
365#define EEE_NWAY_EN 0x1000
366#define TX_QUIET_EN 0x0200
367#define RX_QUIET_EN 0x0100
d24f6134 368#define sd_rise_time_mask 0x0070
4c4a6b1b 369#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 370#define RG_RXLPI_MSK_HFDUP 0x0008
371#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373/* OCP_EEE_CONFIG2 */
374#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375#define RG_DACQUIET_EN 0x0400
376#define RG_LDVQUIET_EN 0x0200
377#define RG_CKRSEL 0x0020
378#define RG_EEEPRG_EN 0x0010
379
380/* OCP_EEE_CONFIG3 */
d24f6134 381#define fast_snr_mask 0xff80
4c4a6b1b 382#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 383#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384#define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386/* OCP_EEE_AR */
387/* bit[15:14] function */
388#define FUN_ADDR 0x0000
389#define FUN_DATA 0x4000
390/* bit[4:0] device addr */
ac718b69 391
43779f8d 392/* OCP_EEE_CFG */
393#define CTAP_SHORT_EN 0x0040
394#define EEE10_EN 0x0010
395
396/* OCP_DOWN_SPEED */
397#define EN_10M_BGOFF 0x0080
398
43779f8d 399/* OCP_ADC_CFG */
400#define CKADSEL_L 0x0100
401#define ADC_EN 0x0080
402#define EN_EMI_L 0x0040
403
404/* SRAM_LPF_CFG */
405#define LPF_AUTO_TUNE 0x8000
406
407/* SRAM_10M_AMP1 */
408#define GDAC_IB_UPALL 0x0008
409
410/* SRAM_10M_AMP2 */
411#define AMP_DN 0x0200
412
413/* SRAM_IMPEDANCE */
414#define RX_DRIVING_MASK 0x6000
415
ac718b69 416enum rtl_register_content {
43779f8d 417 _1000bps = 0x10,
ac718b69 418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422};
423
1764bcd9 424#define RTL8152_MAX_TX 4
ebc2ec48 425#define RTL8152_MAX_RX 10
40a82917 426#define INTBUFSIZE 2
8e1f51bd 427#define CRC_SIZE 4
428#define TX_ALIGN 4
429#define RX_ALIGN 8
40a82917 430
431#define INTR_LINK 0x0004
ebc2ec48 432
ac718b69 433#define RTL8152_REQT_READ 0xc0
434#define RTL8152_REQT_WRITE 0x40
435#define RTL8152_REQ_GET_REGS 0x05
436#define RTL8152_REQ_SET_REGS 0x05
437
438#define BYTE_EN_DWORD 0xff
439#define BYTE_EN_WORD 0x33
440#define BYTE_EN_BYTE 0x11
441#define BYTE_EN_SIX_BYTES 0x3f
442#define BYTE_EN_START_MASK 0x0f
443#define BYTE_EN_END_MASK 0xf0
444
69b4b7a4 445#define RTL8153_MAX_PACKET 9216 /* 9K */
446#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 447#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 448#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 449#define RTL8152_TX_TIMEOUT (5 * HZ)
ac718b69 450
451/* rtl8152 flags */
452enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
ac718b69 454 RTL8152_SET_RX_MODE,
40a82917 455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
9a4be1bd 457 SELECTIVE_SUSPEND,
aa66a5f1 458 PHY_RESET,
0c3121fc 459 SCHEDULE_TASKLET,
ac718b69 460};
461
462/* Define these values to match your device */
463#define VENDOR_ID_REALTEK 0x0bda
43779f8d 464#define VENDOR_ID_SAMSUNG 0x04e8
ac718b69 465
466#define MCU_TYPE_PLA 0x0100
467#define MCU_TYPE_USB 0x0000
468
c7de7dec 469#define REALTEK_USB_DEVICE(vend, prod) \
470 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
471
4f1d4d54 472struct tally_counter {
473 __le64 tx_packets;
474 __le64 rx_packets;
475 __le64 tx_errors;
476 __le32 rx_errors;
477 __le16 rx_missed;
478 __le16 align_errors;
479 __le32 tx_one_collision;
480 __le32 tx_multi_collision;
481 __le64 rx_unicast;
482 __le64 rx_broadcast;
483 __le32 rx_multicast;
484 __le16 tx_aborted;
f37119c5 485 __le16 tx_underrun;
4f1d4d54 486};
487
ac718b69 488struct rx_desc {
500b6d7e 489 __le32 opts1;
ac718b69 490#define RX_LEN_MASK 0x7fff
565cab0a 491
500b6d7e 492 __le32 opts2;
565cab0a 493#define RD_UDP_CS (1 << 23)
494#define RD_TCP_CS (1 << 22)
6128d1bb 495#define RD_IPV6_CS (1 << 20)
565cab0a 496#define RD_IPV4_CS (1 << 19)
497
500b6d7e 498 __le32 opts3;
565cab0a 499#define IPF (1 << 23) /* IP checksum fail */
500#define UDPF (1 << 22) /* UDP checksum fail */
501#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 502#define RX_VLAN_TAG (1 << 16)
565cab0a 503
500b6d7e 504 __le32 opts4;
505 __le32 opts5;
506 __le32 opts6;
ac718b69 507};
508
509struct tx_desc {
500b6d7e 510 __le32 opts1;
ac718b69 511#define TX_FS (1 << 31) /* First segment of a packet */
512#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 513#define GTSENDV4 (1 << 28)
6128d1bb 514#define GTSENDV6 (1 << 27)
60c89071 515#define GTTCPHO_SHIFT 18
6128d1bb 516#define GTTCPHO_MAX 0x7fU
60c89071 517#define TX_LEN_MAX 0x3ffffU
5bd23881 518
500b6d7e 519 __le32 opts2;
5bd23881 520#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
521#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
522#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
523#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 524#define MSS_SHIFT 17
525#define MSS_MAX 0x7ffU
526#define TCPHO_SHIFT 17
6128d1bb 527#define TCPHO_MAX 0x7ffU
c5554298 528#define TX_VLAN_TAG (1 << 16)
ac718b69 529};
530
dff4e8ad 531struct r8152;
532
ebc2ec48 533struct rx_agg {
534 struct list_head list;
535 struct urb *urb;
dff4e8ad 536 struct r8152 *context;
ebc2ec48 537 void *buffer;
538 void *head;
539};
540
541struct tx_agg {
542 struct list_head list;
543 struct urb *urb;
dff4e8ad 544 struct r8152 *context;
ebc2ec48 545 void *buffer;
546 void *head;
547 u32 skb_num;
548 u32 skb_len;
549};
550
ac718b69 551struct r8152 {
552 unsigned long flags;
553 struct usb_device *udev;
554 struct tasklet_struct tl;
40a82917 555 struct usb_interface *intf;
ac718b69 556 struct net_device *netdev;
40a82917 557 struct urb *intr_urb;
ebc2ec48 558 struct tx_agg tx_info[RTL8152_MAX_TX];
559 struct rx_agg rx_info[RTL8152_MAX_RX];
560 struct list_head rx_done, tx_free;
561 struct sk_buff_head tx_queue;
562 spinlock_t rx_lock, tx_lock;
ac718b69 563 struct delayed_work schedule;
564 struct mii_if_info mii;
b5403273 565 struct mutex control; /* use for hw setting */
c81229c9 566
567 struct rtl_ops {
568 void (*init)(struct r8152 *);
569 int (*enable)(struct r8152 *);
570 void (*disable)(struct r8152 *);
7e9da481 571 void (*up)(struct r8152 *);
c81229c9 572 void (*down)(struct r8152 *);
573 void (*unload)(struct r8152 *);
df35d283 574 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
575 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 576 } rtl_ops;
577
40a82917 578 int intr_interval;
21ff2e89 579 u32 saved_wolopts;
ac718b69 580 u32 msg_enable;
dd1b119c 581 u32 tx_qlen;
ac718b69 582 u16 ocp_base;
40a82917 583 u8 *intr_buff;
ac718b69 584 u8 version;
585 u8 speed;
586};
587
588enum rtl_version {
589 RTL_VER_UNKNOWN = 0,
590 RTL_VER_01,
43779f8d 591 RTL_VER_02,
592 RTL_VER_03,
593 RTL_VER_04,
594 RTL_VER_05,
595 RTL_VER_MAX
ac718b69 596};
597
60c89071 598enum tx_csum_stat {
599 TX_CSUM_SUCCESS = 0,
600 TX_CSUM_TSO,
601 TX_CSUM_NONE
602};
603
ac718b69 604/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
605 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
606 */
607static const int multicast_filter_limit = 32;
52aec126 608static unsigned int agg_buf_sz = 16384;
ac718b69 609
52aec126 610#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 611 VLAN_ETH_HLEN - VLAN_HLEN)
612
ac718b69 613static
614int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
615{
31787f53 616 int ret;
617 void *tmp;
618
619 tmp = kmalloc(size, GFP_KERNEL);
620 if (!tmp)
621 return -ENOMEM;
622
623 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 624 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
625 value, index, tmp, size, 500);
31787f53 626
627 memcpy(data, tmp, size);
628 kfree(tmp);
629
630 return ret;
ac718b69 631}
632
633static
634int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
635{
31787f53 636 int ret;
637 void *tmp;
638
c4438f03 639 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 640 if (!tmp)
641 return -ENOMEM;
642
31787f53 643 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 644 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
645 value, index, tmp, size, 500);
31787f53 646
647 kfree(tmp);
db8515ef 648
31787f53 649 return ret;
ac718b69 650}
651
652static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 653 void *data, u16 type)
ac718b69 654{
45f4a19f 655 u16 limit = 64;
656 int ret = 0;
ac718b69 657
658 if (test_bit(RTL8152_UNPLUG, &tp->flags))
659 return -ENODEV;
660
661 /* both size and indix must be 4 bytes align */
662 if ((size & 3) || !size || (index & 3) || !data)
663 return -EPERM;
664
665 if ((u32)index + (u32)size > 0xffff)
666 return -EPERM;
667
668 while (size) {
669 if (size > limit) {
670 ret = get_registers(tp, index, type, limit, data);
671 if (ret < 0)
672 break;
673
674 index += limit;
675 data += limit;
676 size -= limit;
677 } else {
678 ret = get_registers(tp, index, type, size, data);
679 if (ret < 0)
680 break;
681
682 index += size;
683 data += size;
684 size = 0;
685 break;
686 }
687 }
688
67610496 689 if (ret == -ENODEV)
690 set_bit(RTL8152_UNPLUG, &tp->flags);
691
ac718b69 692 return ret;
693}
694
695static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 696 u16 size, void *data, u16 type)
ac718b69 697{
45f4a19f 698 int ret;
699 u16 byteen_start, byteen_end, byen;
700 u16 limit = 512;
ac718b69 701
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
703 return -ENODEV;
704
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
707 return -EPERM;
708
709 if ((u32)index + (u32)size > 0xffff)
710 return -EPERM;
711
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
714
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
717 if (ret < 0)
718 goto error1;
719
720 index += 4;
721 data += 4;
722 size -= 4;
723
724 if (size) {
725 size -= 4;
726
727 while (size) {
728 if (size > limit) {
729 ret = set_registers(tp, index,
b209af99 730 type | BYTE_EN_DWORD,
731 limit, data);
ac718b69 732 if (ret < 0)
733 goto error1;
734
735 index += limit;
736 data += limit;
737 size -= limit;
738 } else {
739 ret = set_registers(tp, index,
b209af99 740 type | BYTE_EN_DWORD,
741 size, data);
ac718b69 742 if (ret < 0)
743 goto error1;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
754 if (ret < 0)
755 goto error1;
756 }
757
758error1:
67610496 759 if (ret == -ENODEV)
760 set_bit(RTL8152_UNPLUG, &tp->flags);
761
ac718b69 762 return ret;
763}
764
765static inline
766int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
767{
768 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
769}
770
771static inline
772int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
773{
774 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
775}
776
777static inline
778int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
779{
780 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
781}
782
783static inline
784int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
785{
786 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
787}
788
789static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
790{
c8826de8 791 __le32 data;
ac718b69 792
c8826de8 793 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 794
795 return __le32_to_cpu(data);
796}
797
798static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
799{
c8826de8 800 __le32 tmp = __cpu_to_le32(data);
801
802 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 803}
804
805static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
806{
807 u32 data;
c8826de8 808 __le32 tmp;
ac718b69 809 u8 shift = index & 2;
810
811 index &= ~3;
812
c8826de8 813 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 814
c8826de8 815 data = __le32_to_cpu(tmp);
ac718b69 816 data >>= (shift * 8);
817 data &= 0xffff;
818
819 return (u16)data;
820}
821
822static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
823{
c8826de8 824 u32 mask = 0xffff;
825 __le32 tmp;
ac718b69 826 u16 byen = BYTE_EN_WORD;
827 u8 shift = index & 2;
828
829 data &= mask;
830
831 if (index & 2) {
832 byen <<= shift;
833 mask <<= (shift * 8);
834 data <<= (shift * 8);
835 index &= ~3;
836 }
837
c8826de8 838 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 839
c8826de8 840 data |= __le32_to_cpu(tmp) & ~mask;
841 tmp = __cpu_to_le32(data);
ac718b69 842
c8826de8 843 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 844}
845
846static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
847{
848 u32 data;
c8826de8 849 __le32 tmp;
ac718b69 850 u8 shift = index & 3;
851
852 index &= ~3;
853
c8826de8 854 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 855
c8826de8 856 data = __le32_to_cpu(tmp);
ac718b69 857 data >>= (shift * 8);
858 data &= 0xff;
859
860 return (u8)data;
861}
862
863static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
864{
c8826de8 865 u32 mask = 0xff;
866 __le32 tmp;
ac718b69 867 u16 byen = BYTE_EN_BYTE;
868 u8 shift = index & 3;
869
870 data &= mask;
871
872 if (index & 3) {
873 byen <<= shift;
874 mask <<= (shift * 8);
875 data <<= (shift * 8);
876 index &= ~3;
877 }
878
c8826de8 879 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 880
c8826de8 881 data |= __le32_to_cpu(tmp) & ~mask;
882 tmp = __cpu_to_le32(data);
ac718b69 883
c8826de8 884 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 885}
886
ac244d3e 887static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 888{
889 u16 ocp_base, ocp_index;
890
891 ocp_base = addr & 0xf000;
892 if (ocp_base != tp->ocp_base) {
893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
894 tp->ocp_base = ocp_base;
895 }
896
897 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 898 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 899}
900
ac244d3e 901static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 902{
ac244d3e 903 u16 ocp_base, ocp_index;
ac718b69 904
ac244d3e 905 ocp_base = addr & 0xf000;
906 if (ocp_base != tp->ocp_base) {
907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
908 tp->ocp_base = ocp_base;
ac718b69 909 }
ac244d3e 910
911 ocp_index = (addr & 0x0fff) | 0xb000;
912 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 913}
914
ac244d3e 915static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 916{
ac244d3e 917 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
918}
ac718b69 919
ac244d3e 920static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
921{
922 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 923}
924
43779f8d 925static void sram_write(struct r8152 *tp, u16 addr, u16 data)
926{
927 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
928 ocp_reg_write(tp, OCP_SRAM_DATA, data);
929}
930
931static u16 sram_read(struct r8152 *tp, u16 addr)
932{
933 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
934 return ocp_reg_read(tp, OCP_SRAM_DATA);
935}
936
ac718b69 937static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
938{
939 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 940 int ret;
ac718b69 941
6871438c 942 if (test_bit(RTL8152_UNPLUG, &tp->flags))
943 return -ENODEV;
944
ac718b69 945 if (phy_id != R8152_PHY_ID)
946 return -EINVAL;
947
9a4be1bd 948 ret = r8152_mdio_read(tp, reg);
949
9a4be1bd 950 return ret;
ac718b69 951}
952
953static
954void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
955{
956 struct r8152 *tp = netdev_priv(netdev);
957
6871438c 958 if (test_bit(RTL8152_UNPLUG, &tp->flags))
959 return;
960
ac718b69 961 if (phy_id != R8152_PHY_ID)
962 return;
963
964 r8152_mdio_write(tp, reg, val);
965}
966
b209af99 967static int
968r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 969
8ba789ab 970static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
971{
972 struct r8152 *tp = netdev_priv(netdev);
973 struct sockaddr *addr = p;
ea6a7112 974 int ret = -EADDRNOTAVAIL;
8ba789ab 975
976 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 977 goto out1;
978
979 ret = usb_autopm_get_interface(tp->intf);
980 if (ret < 0)
981 goto out1;
8ba789ab 982
b5403273 983 mutex_lock(&tp->control);
984
8ba789ab 985 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
986
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
988 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
990
b5403273 991 mutex_unlock(&tp->control);
992
ea6a7112 993 usb_autopm_put_interface(tp->intf);
994out1:
995 return ret;
8ba789ab 996}
997
179bb6d7 998static int set_ethernet_addr(struct r8152 *tp)
ac718b69 999{
1000 struct net_device *dev = tp->netdev;
179bb6d7 1001 struct sockaddr sa;
8a91c824 1002 int ret;
ac718b69 1003
8a91c824 1004 if (tp->version == RTL_VER_01)
179bb6d7 1005 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1006 else
179bb6d7 1007 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1008
1009 if (ret < 0) {
179bb6d7 1010 netif_err(tp, probe, dev, "Get ether addr fail\n");
1011 } else if (!is_valid_ether_addr(sa.sa_data)) {
1012 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1013 sa.sa_data);
1014 eth_hw_addr_random(dev);
1015 ether_addr_copy(sa.sa_data, dev->dev_addr);
1016 ret = rtl8152_set_mac_address(dev, &sa);
1017 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1018 sa.sa_data);
8a91c824 1019 } else {
179bb6d7 1020 if (tp->version == RTL_VER_01)
1021 ether_addr_copy(dev->dev_addr, sa.sa_data);
1022 else
1023 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1024 }
179bb6d7 1025
1026 return ret;
ac718b69 1027}
1028
ac718b69 1029static void read_bulk_callback(struct urb *urb)
1030{
ac718b69 1031 struct net_device *netdev;
ac718b69 1032 int status = urb->status;
ebc2ec48 1033 struct rx_agg *agg;
1034 struct r8152 *tp;
ac718b69 1035 int result;
ac718b69 1036
ebc2ec48 1037 agg = urb->context;
1038 if (!agg)
1039 return;
1040
1041 tp = agg->context;
ac718b69 1042 if (!tp)
1043 return;
ebc2ec48 1044
ac718b69 1045 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1046 return;
ebc2ec48 1047
1048 if (!test_bit(WORK_ENABLE, &tp->flags))
1049 return;
1050
ac718b69 1051 netdev = tp->netdev;
7559fb2f 1052
1053 /* When link down, the driver would cancel all bulks. */
1054 /* This avoid the re-submitting bulk */
ebc2ec48 1055 if (!netif_carrier_ok(netdev))
ac718b69 1056 return;
1057
9a4be1bd 1058 usb_mark_last_busy(tp->udev);
1059
ac718b69 1060 switch (status) {
1061 case 0:
ebc2ec48 1062 if (urb->actual_length < ETH_ZLEN)
1063 break;
1064
2685d410 1065 spin_lock(&tp->rx_lock);
ebc2ec48 1066 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1067 spin_unlock(&tp->rx_lock);
ebc2ec48 1068 tasklet_schedule(&tp->tl);
1069 return;
ac718b69 1070 case -ESHUTDOWN:
1071 set_bit(RTL8152_UNPLUG, &tp->flags);
1072 netif_device_detach(tp->netdev);
ebc2ec48 1073 return;
ac718b69 1074 case -ENOENT:
1075 return; /* the urb is in unlink state */
1076 case -ETIME:
4a8deae2
HW
1077 if (net_ratelimit())
1078 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1079 break;
ac718b69 1080 default:
4a8deae2
HW
1081 if (net_ratelimit())
1082 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1083 break;
ac718b69 1084 }
1085
ebc2ec48 1086 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1087 if (result == -ENODEV) {
67610496 1088 set_bit(RTL8152_UNPLUG, &tp->flags);
ac718b69 1089 netif_device_detach(tp->netdev);
1090 } else if (result) {
2685d410 1091 spin_lock(&tp->rx_lock);
ebc2ec48 1092 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1093 spin_unlock(&tp->rx_lock);
ebc2ec48 1094 tasklet_schedule(&tp->tl);
ac718b69 1095 }
ac718b69 1096}
1097
ebc2ec48 1098static void write_bulk_callback(struct urb *urb)
ac718b69 1099{
ebc2ec48 1100 struct net_device_stats *stats;
d104eafa 1101 struct net_device *netdev;
ebc2ec48 1102 struct tx_agg *agg;
ac718b69 1103 struct r8152 *tp;
ebc2ec48 1104 int status = urb->status;
ac718b69 1105
ebc2ec48 1106 agg = urb->context;
1107 if (!agg)
ac718b69 1108 return;
1109
ebc2ec48 1110 tp = agg->context;
1111 if (!tp)
1112 return;
1113
d104eafa 1114 netdev = tp->netdev;
05e0f1aa 1115 stats = &netdev->stats;
ebc2ec48 1116 if (status) {
4a8deae2 1117 if (net_ratelimit())
d104eafa 1118 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1119 stats->tx_errors += agg->skb_num;
ac718b69 1120 } else {
ebc2ec48 1121 stats->tx_packets += agg->skb_num;
1122 stats->tx_bytes += agg->skb_len;
ac718b69 1123 }
1124
2685d410 1125 spin_lock(&tp->tx_lock);
ebc2ec48 1126 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1127 spin_unlock(&tp->tx_lock);
ebc2ec48 1128
9a4be1bd 1129 usb_autopm_put_interface_async(tp->intf);
1130
d104eafa 1131 if (!netif_carrier_ok(netdev))
ebc2ec48 1132 return;
1133
1134 if (!test_bit(WORK_ENABLE, &tp->flags))
1135 return;
1136
1137 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1138 return;
1139
1140 if (!skb_queue_empty(&tp->tx_queue))
0c3121fc 1141 tasklet_schedule(&tp->tl);
ac718b69 1142}
1143
40a82917 1144static void intr_callback(struct urb *urb)
1145{
1146 struct r8152 *tp;
500b6d7e 1147 __le16 *d;
40a82917 1148 int status = urb->status;
1149 int res;
1150
1151 tp = urb->context;
1152 if (!tp)
1153 return;
1154
1155 if (!test_bit(WORK_ENABLE, &tp->flags))
1156 return;
1157
1158 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1159 return;
1160
1161 switch (status) {
1162 case 0: /* success */
1163 break;
1164 case -ECONNRESET: /* unlink */
1165 case -ESHUTDOWN:
1166 netif_device_detach(tp->netdev);
1167 case -ENOENT:
d59c876d 1168 case -EPROTO:
1169 netif_info(tp, intr, tp->netdev,
1170 "Stop submitting intr, status %d\n", status);
40a82917 1171 return;
1172 case -EOVERFLOW:
1173 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1174 goto resubmit;
1175 /* -EPIPE: should clear the halt */
1176 default:
1177 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1178 goto resubmit;
1179 }
1180
1181 d = urb->transfer_buffer;
1182 if (INTR_LINK & __le16_to_cpu(d[0])) {
1183 if (!(tp->speed & LINK_STATUS)) {
1184 set_bit(RTL8152_LINK_CHG, &tp->flags);
1185 schedule_delayed_work(&tp->schedule, 0);
1186 }
1187 } else {
1188 if (tp->speed & LINK_STATUS) {
1189 set_bit(RTL8152_LINK_CHG, &tp->flags);
1190 schedule_delayed_work(&tp->schedule, 0);
1191 }
1192 }
1193
1194resubmit:
1195 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1196 if (res == -ENODEV) {
1197 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1198 netif_device_detach(tp->netdev);
67610496 1199 } else if (res) {
40a82917 1200 netif_err(tp, intr, tp->netdev,
4a8deae2 1201 "can't resubmit intr, status %d\n", res);
67610496 1202 }
40a82917 1203}
1204
ebc2ec48 1205static inline void *rx_agg_align(void *data)
1206{
8e1f51bd 1207 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1208}
1209
1210static inline void *tx_agg_align(void *data)
1211{
8e1f51bd 1212 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1213}
1214
1215static void free_all_mem(struct r8152 *tp)
1216{
1217 int i;
1218
1219 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1220 usb_free_urb(tp->rx_info[i].urb);
1221 tp->rx_info[i].urb = NULL;
ebc2ec48 1222
9629e3c0 1223 kfree(tp->rx_info[i].buffer);
1224 tp->rx_info[i].buffer = NULL;
1225 tp->rx_info[i].head = NULL;
ebc2ec48 1226 }
1227
1228 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1229 usb_free_urb(tp->tx_info[i].urb);
1230 tp->tx_info[i].urb = NULL;
ebc2ec48 1231
9629e3c0 1232 kfree(tp->tx_info[i].buffer);
1233 tp->tx_info[i].buffer = NULL;
1234 tp->tx_info[i].head = NULL;
ebc2ec48 1235 }
40a82917 1236
9629e3c0 1237 usb_free_urb(tp->intr_urb);
1238 tp->intr_urb = NULL;
40a82917 1239
9629e3c0 1240 kfree(tp->intr_buff);
1241 tp->intr_buff = NULL;
ebc2ec48 1242}
1243
1244static int alloc_all_mem(struct r8152 *tp)
1245{
1246 struct net_device *netdev = tp->netdev;
40a82917 1247 struct usb_interface *intf = tp->intf;
1248 struct usb_host_interface *alt = intf->cur_altsetting;
1249 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1250 struct urb *urb;
1251 int node, i;
1252 u8 *buf;
1253
1254 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1255
1256 spin_lock_init(&tp->rx_lock);
1257 spin_lock_init(&tp->tx_lock);
ebc2ec48 1258 INIT_LIST_HEAD(&tp->tx_free);
1259 skb_queue_head_init(&tp->tx_queue);
1260
1261 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1262 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1263 if (!buf)
1264 goto err1;
1265
1266 if (buf != rx_agg_align(buf)) {
1267 kfree(buf);
52aec126 1268 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1269 node);
ebc2ec48 1270 if (!buf)
1271 goto err1;
1272 }
1273
1274 urb = usb_alloc_urb(0, GFP_KERNEL);
1275 if (!urb) {
1276 kfree(buf);
1277 goto err1;
1278 }
1279
1280 INIT_LIST_HEAD(&tp->rx_info[i].list);
1281 tp->rx_info[i].context = tp;
1282 tp->rx_info[i].urb = urb;
1283 tp->rx_info[i].buffer = buf;
1284 tp->rx_info[i].head = rx_agg_align(buf);
1285 }
1286
1287 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1288 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1289 if (!buf)
1290 goto err1;
1291
1292 if (buf != tx_agg_align(buf)) {
1293 kfree(buf);
52aec126 1294 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1295 node);
ebc2ec48 1296 if (!buf)
1297 goto err1;
1298 }
1299
1300 urb = usb_alloc_urb(0, GFP_KERNEL);
1301 if (!urb) {
1302 kfree(buf);
1303 goto err1;
1304 }
1305
1306 INIT_LIST_HEAD(&tp->tx_info[i].list);
1307 tp->tx_info[i].context = tp;
1308 tp->tx_info[i].urb = urb;
1309 tp->tx_info[i].buffer = buf;
1310 tp->tx_info[i].head = tx_agg_align(buf);
1311
1312 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1313 }
1314
40a82917 1315 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1316 if (!tp->intr_urb)
1317 goto err1;
1318
1319 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1320 if (!tp->intr_buff)
1321 goto err1;
1322
1323 tp->intr_interval = (int)ep_intr->desc.bInterval;
1324 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1325 tp->intr_buff, INTBUFSIZE, intr_callback,
1326 tp, tp->intr_interval);
40a82917 1327
ebc2ec48 1328 return 0;
1329
1330err1:
1331 free_all_mem(tp);
1332 return -ENOMEM;
1333}
1334
0de98f6c 1335static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1336{
1337 struct tx_agg *agg = NULL;
1338 unsigned long flags;
1339
21949ab7 1340 if (list_empty(&tp->tx_free))
1341 return NULL;
1342
0de98f6c 1343 spin_lock_irqsave(&tp->tx_lock, flags);
1344 if (!list_empty(&tp->tx_free)) {
1345 struct list_head *cursor;
1346
1347 cursor = tp->tx_free.next;
1348 list_del_init(cursor);
1349 agg = list_entry(cursor, struct tx_agg, list);
1350 }
1351 spin_unlock_irqrestore(&tp->tx_lock, flags);
1352
1353 return agg;
1354}
1355
60c89071 1356static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1357{
60c89071 1358 __be16 protocol;
5bd23881 1359
60c89071 1360 if (skb->protocol == htons(ETH_P_8021Q))
1361 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1362 else
1363 protocol = skb->protocol;
5bd23881 1364
60c89071 1365 return protocol;
1366}
5bd23881 1367
b209af99 1368/* r8152_csum_workaround()
6128d1bb 1369 * The hw limites the value the transport offset. When the offset is out of the
1370 * range, calculate the checksum by sw.
1371 */
1372static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1373 struct sk_buff_head *list)
1374{
1375 if (skb_shinfo(skb)->gso_size) {
1376 netdev_features_t features = tp->netdev->features;
1377 struct sk_buff_head seg_list;
1378 struct sk_buff *segs, *nskb;
1379
a91d45f1 1380 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1381 segs = skb_gso_segment(skb, features);
1382 if (IS_ERR(segs) || !segs)
1383 goto drop;
1384
1385 __skb_queue_head_init(&seg_list);
1386
1387 do {
1388 nskb = segs;
1389 segs = segs->next;
1390 nskb->next = NULL;
1391 __skb_queue_tail(&seg_list, nskb);
1392 } while (segs);
1393
1394 skb_queue_splice(&seg_list, list);
1395 dev_kfree_skb(skb);
1396 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1397 if (skb_checksum_help(skb) < 0)
1398 goto drop;
1399
1400 __skb_queue_head(list, skb);
1401 } else {
1402 struct net_device_stats *stats;
1403
1404drop:
1405 stats = &tp->netdev->stats;
1406 stats->tx_dropped++;
1407 dev_kfree_skb(skb);
1408 }
1409}
1410
b209af99 1411/* msdn_giant_send_check()
6128d1bb 1412 * According to the document of microsoft, the TCP Pseudo Header excludes the
1413 * packet length for IPv6 TCP large packets.
1414 */
1415static int msdn_giant_send_check(struct sk_buff *skb)
1416{
1417 const struct ipv6hdr *ipv6h;
1418 struct tcphdr *th;
fcb308d5 1419 int ret;
1420
1421 ret = skb_cow_head(skb, 0);
1422 if (ret)
1423 return ret;
6128d1bb 1424
1425 ipv6h = ipv6_hdr(skb);
1426 th = tcp_hdr(skb);
1427
1428 th->check = 0;
1429 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1430
fcb308d5 1431 return ret;
6128d1bb 1432}
1433
c5554298 1434static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1435{
1436 if (vlan_tx_tag_present(skb)) {
1437 u32 opts2;
1438
1439 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1440 desc->opts2 |= cpu_to_le32(opts2);
1441 }
1442}
1443
1444static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1445{
1446 u32 opts2 = le32_to_cpu(desc->opts2);
1447
1448 if (opts2 & RX_VLAN_TAG)
1449 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1450 swab16(opts2 & 0xffff));
1451}
1452
60c89071 1453static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1454 struct sk_buff *skb, u32 len, u32 transport_offset)
1455{
1456 u32 mss = skb_shinfo(skb)->gso_size;
1457 u32 opts1, opts2 = 0;
1458 int ret = TX_CSUM_SUCCESS;
1459
1460 WARN_ON_ONCE(len > TX_LEN_MAX);
1461
1462 opts1 = len | TX_FS | TX_LS;
1463
1464 if (mss) {
6128d1bb 1465 if (transport_offset > GTTCPHO_MAX) {
1466 netif_warn(tp, tx_err, tp->netdev,
1467 "Invalid transport offset 0x%x for TSO\n",
1468 transport_offset);
1469 ret = TX_CSUM_TSO;
1470 goto unavailable;
1471 }
1472
60c89071 1473 switch (get_protocol(skb)) {
1474 case htons(ETH_P_IP):
1475 opts1 |= GTSENDV4;
1476 break;
1477
6128d1bb 1478 case htons(ETH_P_IPV6):
fcb308d5 1479 if (msdn_giant_send_check(skb)) {
1480 ret = TX_CSUM_TSO;
1481 goto unavailable;
1482 }
6128d1bb 1483 opts1 |= GTSENDV6;
6128d1bb 1484 break;
1485
60c89071 1486 default:
1487 WARN_ON_ONCE(1);
1488 break;
1489 }
1490
1491 opts1 |= transport_offset << GTTCPHO_SHIFT;
1492 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1493 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1494 u8 ip_protocol;
5bd23881 1495
6128d1bb 1496 if (transport_offset > TCPHO_MAX) {
1497 netif_warn(tp, tx_err, tp->netdev,
1498 "Invalid transport offset 0x%x\n",
1499 transport_offset);
1500 ret = TX_CSUM_NONE;
1501 goto unavailable;
1502 }
1503
60c89071 1504 switch (get_protocol(skb)) {
5bd23881 1505 case htons(ETH_P_IP):
1506 opts2 |= IPV4_CS;
1507 ip_protocol = ip_hdr(skb)->protocol;
1508 break;
1509
1510 case htons(ETH_P_IPV6):
1511 opts2 |= IPV6_CS;
1512 ip_protocol = ipv6_hdr(skb)->nexthdr;
1513 break;
1514
1515 default:
1516 ip_protocol = IPPROTO_RAW;
1517 break;
1518 }
1519
60c89071 1520 if (ip_protocol == IPPROTO_TCP)
5bd23881 1521 opts2 |= TCP_CS;
60c89071 1522 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1523 opts2 |= UDP_CS;
60c89071 1524 else
5bd23881 1525 WARN_ON_ONCE(1);
5bd23881 1526
60c89071 1527 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1528 }
60c89071 1529
1530 desc->opts2 = cpu_to_le32(opts2);
1531 desc->opts1 = cpu_to_le32(opts1);
1532
6128d1bb 1533unavailable:
60c89071 1534 return ret;
5bd23881 1535}
1536
b1379d9a 1537static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1538{
d84130a1 1539 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1540 int remain, ret;
b1379d9a 1541 u8 *tx_data;
1542
d84130a1 1543 __skb_queue_head_init(&skb_head);
0c3121fc 1544 spin_lock(&tx_queue->lock);
d84130a1 1545 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1546 spin_unlock(&tx_queue->lock);
d84130a1 1547
b1379d9a 1548 tx_data = agg->head;
b209af99 1549 agg->skb_num = 0;
1550 agg->skb_len = 0;
52aec126 1551 remain = agg_buf_sz;
b1379d9a 1552
7937f9e5 1553 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1554 struct tx_desc *tx_desc;
1555 struct sk_buff *skb;
1556 unsigned int len;
60c89071 1557 u32 offset;
b1379d9a 1558
d84130a1 1559 skb = __skb_dequeue(&skb_head);
b1379d9a 1560 if (!skb)
1561 break;
1562
60c89071 1563 len = skb->len + sizeof(*tx_desc);
1564
1565 if (len > remain) {
d84130a1 1566 __skb_queue_head(&skb_head, skb);
b1379d9a 1567 break;
1568 }
1569
7937f9e5 1570 tx_data = tx_agg_align(tx_data);
b1379d9a 1571 tx_desc = (struct tx_desc *)tx_data;
60c89071 1572
1573 offset = (u32)skb_transport_offset(skb);
1574
6128d1bb 1575 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1576 r8152_csum_workaround(tp, skb, &skb_head);
1577 continue;
1578 }
60c89071 1579
c5554298 1580 rtl_tx_vlan_tag(tx_desc, skb);
1581
b1379d9a 1582 tx_data += sizeof(*tx_desc);
1583
60c89071 1584 len = skb->len;
1585 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1586 struct net_device_stats *stats = &tp->netdev->stats;
1587
1588 stats->tx_dropped++;
1589 dev_kfree_skb_any(skb);
1590 tx_data -= sizeof(*tx_desc);
1591 continue;
1592 }
1593
1594 tx_data += len;
b1379d9a 1595 agg->skb_len += len;
60c89071 1596 agg->skb_num++;
1597
b1379d9a 1598 dev_kfree_skb_any(skb);
1599
52aec126 1600 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1601 }
1602
d84130a1 1603 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1604 spin_lock(&tx_queue->lock);
d84130a1 1605 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1606 spin_unlock(&tx_queue->lock);
d84130a1 1607 }
1608
0c3121fc 1609 netif_tx_lock(tp->netdev);
dd1b119c 1610
1611 if (netif_queue_stopped(tp->netdev) &&
1612 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1613 netif_wake_queue(tp->netdev);
1614
0c3121fc 1615 netif_tx_unlock(tp->netdev);
9a4be1bd 1616
0c3121fc 1617 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1618 if (ret < 0)
1619 goto out_tx_fill;
dd1b119c 1620
b1379d9a 1621 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1622 agg->head, (int)(tx_data - (u8 *)agg->head),
1623 (usb_complete_t)write_bulk_callback, agg);
1624
0c3121fc 1625 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1626 if (ret < 0)
0c3121fc 1627 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1628
1629out_tx_fill:
1630 return ret;
b1379d9a 1631}
1632
565cab0a 1633static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1634{
1635 u8 checksum = CHECKSUM_NONE;
1636 u32 opts2, opts3;
1637
1638 if (tp->version == RTL_VER_01)
1639 goto return_result;
1640
1641 opts2 = le32_to_cpu(rx_desc->opts2);
1642 opts3 = le32_to_cpu(rx_desc->opts3);
1643
1644 if (opts2 & RD_IPV4_CS) {
1645 if (opts3 & IPF)
1646 checksum = CHECKSUM_NONE;
1647 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1648 checksum = CHECKSUM_NONE;
1649 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1650 checksum = CHECKSUM_NONE;
1651 else
1652 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1653 } else if (RD_IPV6_CS) {
1654 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1655 checksum = CHECKSUM_UNNECESSARY;
1656 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1657 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1658 }
1659
1660return_result:
1661 return checksum;
1662}
1663
ebc2ec48 1664static void rx_bottom(struct r8152 *tp)
1665{
a5a4f468 1666 unsigned long flags;
d84130a1 1667 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1668
d84130a1 1669 if (list_empty(&tp->rx_done))
1670 return;
1671
1672 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1673 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1674 list_splice_init(&tp->rx_done, &rx_queue);
1675 spin_unlock_irqrestore(&tp->rx_lock, flags);
1676
1677 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1678 struct rx_desc *rx_desc;
1679 struct rx_agg *agg;
43a4478d 1680 int len_used = 0;
1681 struct urb *urb;
1682 u8 *rx_data;
1683 int ret;
1684
ebc2ec48 1685 list_del_init(cursor);
ebc2ec48 1686
1687 agg = list_entry(cursor, struct rx_agg, list);
1688 urb = agg->urb;
0de98f6c 1689 if (urb->actual_length < ETH_ZLEN)
1690 goto submit;
ebc2ec48 1691
ebc2ec48 1692 rx_desc = agg->head;
1693 rx_data = agg->head;
7937f9e5 1694 len_used += sizeof(struct rx_desc);
ebc2ec48 1695
7937f9e5 1696 while (urb->actual_length > len_used) {
43a4478d 1697 struct net_device *netdev = tp->netdev;
05e0f1aa 1698 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1699 unsigned int pkt_len;
43a4478d 1700 struct sk_buff *skb;
1701
7937f9e5 1702 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1703 if (pkt_len < ETH_ZLEN)
1704 break;
1705
7937f9e5 1706 len_used += pkt_len;
1707 if (urb->actual_length < len_used)
1708 break;
1709
8e1f51bd 1710 pkt_len -= CRC_SIZE;
ebc2ec48 1711 rx_data += sizeof(struct rx_desc);
1712
1713 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1714 if (!skb) {
1715 stats->rx_dropped++;
5e2f7485 1716 goto find_next_rx;
ebc2ec48 1717 }
565cab0a 1718
1719 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1720 memcpy(skb->data, rx_data, pkt_len);
1721 skb_put(skb, pkt_len);
1722 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1723 rtl_rx_vlan_tag(rx_desc, skb);
9d9aafa1 1724 netif_receive_skb(skb);
ebc2ec48 1725 stats->rx_packets++;
1726 stats->rx_bytes += pkt_len;
1727
5e2f7485 1728find_next_rx:
8e1f51bd 1729 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1730 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1731 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1732 len_used += sizeof(struct rx_desc);
ebc2ec48 1733 }
1734
0de98f6c 1735submit:
ebc2ec48 1736 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1737 if (ret && ret != -ENODEV) {
d84130a1 1738 spin_lock_irqsave(&tp->rx_lock, flags);
1739 list_add_tail(&agg->list, &tp->rx_done);
1740 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1741 tasklet_schedule(&tp->tl);
1742 }
1743 }
ebc2ec48 1744}
1745
1746static void tx_bottom(struct r8152 *tp)
1747{
ebc2ec48 1748 int res;
1749
b1379d9a 1750 do {
1751 struct tx_agg *agg;
ebc2ec48 1752
b1379d9a 1753 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1754 break;
1755
b1379d9a 1756 agg = r8152_get_tx_agg(tp);
1757 if (!agg)
ebc2ec48 1758 break;
ebc2ec48 1759
b1379d9a 1760 res = r8152_tx_agg_fill(tp, agg);
1761 if (res) {
05e0f1aa 1762 struct net_device *netdev = tp->netdev;
ebc2ec48 1763
b1379d9a 1764 if (res == -ENODEV) {
67610496 1765 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1766 netif_device_detach(netdev);
1767 } else {
05e0f1aa 1768 struct net_device_stats *stats = &netdev->stats;
1769 unsigned long flags;
1770
b1379d9a 1771 netif_warn(tp, tx_err, netdev,
1772 "failed tx_urb %d\n", res);
1773 stats->tx_dropped += agg->skb_num;
db8515ef 1774
b1379d9a 1775 spin_lock_irqsave(&tp->tx_lock, flags);
1776 list_add_tail(&agg->list, &tp->tx_free);
1777 spin_unlock_irqrestore(&tp->tx_lock, flags);
1778 }
ebc2ec48 1779 }
b1379d9a 1780 } while (res == 0);
ebc2ec48 1781}
1782
1783static void bottom_half(unsigned long data)
ac718b69 1784{
1785 struct r8152 *tp;
ac718b69 1786
ebc2ec48 1787 tp = (struct r8152 *)data;
1788
1789 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1790 return;
1791
1792 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1793 return;
ebc2ec48 1794
7559fb2f 1795 /* When link down, the driver would cancel all bulks. */
1796 /* This avoid the re-submitting bulk */
ebc2ec48 1797 if (!netif_carrier_ok(tp->netdev))
ac718b69 1798 return;
ebc2ec48 1799
9451a11c 1800 clear_bit(SCHEDULE_TASKLET, &tp->flags);
1801
ebc2ec48 1802 rx_bottom(tp);
0c3121fc 1803 tx_bottom(tp);
ebc2ec48 1804}
1805
1806static
1807int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1808{
1809 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1810 agg->head, agg_buf_sz,
b209af99 1811 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1812
1813 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1814}
1815
00a5e360 1816static void rtl_drop_queued_tx(struct r8152 *tp)
1817{
1818 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1819 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1820 struct sk_buff *skb;
1821
d84130a1 1822 if (skb_queue_empty(tx_queue))
1823 return;
1824
1825 __skb_queue_head_init(&skb_head);
2685d410 1826 spin_lock_bh(&tx_queue->lock);
d84130a1 1827 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1828 spin_unlock_bh(&tx_queue->lock);
d84130a1 1829
1830 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1831 dev_kfree_skb(skb);
1832 stats->tx_dropped++;
1833 }
1834}
1835
ac718b69 1836static void rtl8152_tx_timeout(struct net_device *netdev)
1837{
1838 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1839 int i;
1840
4a8deae2 1841 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1842 for (i = 0; i < RTL8152_MAX_TX; i++)
1843 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1844}
1845
1846static void rtl8152_set_rx_mode(struct net_device *netdev)
1847{
1848 struct r8152 *tp = netdev_priv(netdev);
1849
40a82917 1850 if (tp->speed & LINK_STATUS) {
ac718b69 1851 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1852 schedule_delayed_work(&tp->schedule, 0);
1853 }
ac718b69 1854}
1855
1856static void _rtl8152_set_rx_mode(struct net_device *netdev)
1857{
1858 struct r8152 *tp = netdev_priv(netdev);
31787f53 1859 u32 mc_filter[2]; /* Multicast hash filter */
1860 __le32 tmp[2];
ac718b69 1861 u32 ocp_data;
1862
ac718b69 1863 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1864 netif_stop_queue(netdev);
1865 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1866 ocp_data &= ~RCR_ACPT_ALL;
1867 ocp_data |= RCR_AB | RCR_APM;
1868
1869 if (netdev->flags & IFF_PROMISC) {
1870 /* Unconditionally log net taps. */
1871 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1872 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1873 mc_filter[1] = 0xffffffff;
1874 mc_filter[0] = 0xffffffff;
ac718b69 1875 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1876 (netdev->flags & IFF_ALLMULTI)) {
1877 /* Too many to filter perfectly -- accept all multicasts. */
1878 ocp_data |= RCR_AM;
b209af99 1879 mc_filter[1] = 0xffffffff;
1880 mc_filter[0] = 0xffffffff;
ac718b69 1881 } else {
1882 struct netdev_hw_addr *ha;
1883
b209af99 1884 mc_filter[1] = 0;
1885 mc_filter[0] = 0;
ac718b69 1886 netdev_for_each_mc_addr(ha, netdev) {
1887 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1888
ac718b69 1889 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1890 ocp_data |= RCR_AM;
1891 }
1892 }
1893
31787f53 1894 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1895 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1896
31787f53 1897 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1898 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1899 netif_wake_queue(netdev);
ac718b69 1900}
1901
1902static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1903 struct net_device *netdev)
ac718b69 1904{
1905 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1906
ebc2ec48 1907 skb_tx_timestamp(skb);
ac718b69 1908
61598788 1909 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1910
0c3121fc 1911 if (!list_empty(&tp->tx_free)) {
1912 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1913 set_bit(SCHEDULE_TASKLET, &tp->flags);
1914 schedule_delayed_work(&tp->schedule, 0);
1915 } else {
1916 usb_mark_last_busy(tp->udev);
1917 tasklet_schedule(&tp->tl);
1918 }
b209af99 1919 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1920 netif_stop_queue(netdev);
b209af99 1921 }
dd1b119c 1922
ac718b69 1923 return NETDEV_TX_OK;
1924}
1925
1926static void r8152b_reset_packet_filter(struct r8152 *tp)
1927{
1928 u32 ocp_data;
1929
1930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1931 ocp_data &= ~FMC_FCR_MCU_EN;
1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1933 ocp_data |= FMC_FCR_MCU_EN;
1934 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1935}
1936
1937static void rtl8152_nic_reset(struct r8152 *tp)
1938{
1939 int i;
1940
1941 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1942
1943 for (i = 0; i < 1000; i++) {
1944 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1945 break;
b209af99 1946 usleep_range(100, 400);
ac718b69 1947 }
1948}
1949
dd1b119c 1950static void set_tx_qlen(struct r8152 *tp)
1951{
1952 struct net_device *netdev = tp->netdev;
1953
52aec126 1954 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1955 sizeof(struct tx_desc));
dd1b119c 1956}
1957
ac718b69 1958static inline u8 rtl8152_get_speed(struct r8152 *tp)
1959{
1960 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1961}
1962
507605a8 1963static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1964{
ebc2ec48 1965 u32 ocp_data;
ac718b69 1966 u8 speed;
1967
1968 speed = rtl8152_get_speed(tp);
ebc2ec48 1969 if (speed & _10bps) {
ac718b69 1970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1971 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1973 } else {
1974 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1975 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1976 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1977 }
507605a8 1978}
1979
00a5e360 1980static void rxdy_gated_en(struct r8152 *tp, bool enable)
1981{
1982 u32 ocp_data;
1983
1984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1985 if (enable)
1986 ocp_data |= RXDY_GATED_EN;
1987 else
1988 ocp_data &= ~RXDY_GATED_EN;
1989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1990}
1991
445f7f4d 1992static int rtl_start_rx(struct r8152 *tp)
1993{
1994 int i, ret = 0;
1995
1996 INIT_LIST_HEAD(&tp->rx_done);
1997 for (i = 0; i < RTL8152_MAX_RX; i++) {
1998 INIT_LIST_HEAD(&tp->rx_info[i].list);
1999 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2000 if (ret)
2001 break;
2002 }
2003
2004 return ret;
2005}
2006
2007static int rtl_stop_rx(struct r8152 *tp)
2008{
2009 int i;
2010
2011 for (i = 0; i < RTL8152_MAX_RX; i++)
2012 usb_kill_urb(tp->rx_info[i].urb);
2013
2014 return 0;
2015}
2016
507605a8 2017static int rtl_enable(struct r8152 *tp)
2018{
2019 u32 ocp_data;
ac718b69 2020
2021 r8152b_reset_packet_filter(tp);
2022
2023 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2024 ocp_data |= CR_RE | CR_TE;
2025 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2026
00a5e360 2027 rxdy_gated_en(tp, false);
ac718b69 2028
445f7f4d 2029 return rtl_start_rx(tp);
ac718b69 2030}
2031
507605a8 2032static int rtl8152_enable(struct r8152 *tp)
2033{
6871438c 2034 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2035 return -ENODEV;
2036
507605a8 2037 set_tx_qlen(tp);
2038 rtl_set_eee_plus(tp);
2039
2040 return rtl_enable(tp);
2041}
2042
43779f8d 2043static void r8153_set_rx_agg(struct r8152 *tp)
2044{
2045 u8 speed;
2046
2047 speed = rtl8152_get_speed(tp);
2048 if (speed & _1000bps) {
2049 if (tp->udev->speed == USB_SPEED_SUPER) {
2050 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2051 RX_THR_SUPPER);
2052 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2053 EARLY_AGG_SUPPER);
2054 } else {
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2056 RX_THR_HIGH);
2057 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2058 EARLY_AGG_HIGH);
2059 }
2060 } else {
2061 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2062 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2063 EARLY_AGG_SLOW);
2064 }
2065}
2066
2067static int rtl8153_enable(struct r8152 *tp)
2068{
6871438c 2069 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2070 return -ENODEV;
2071
43779f8d 2072 set_tx_qlen(tp);
2073 rtl_set_eee_plus(tp);
2074 r8153_set_rx_agg(tp);
2075
2076 return rtl_enable(tp);
2077}
2078
d70b1137 2079static void rtl_disable(struct r8152 *tp)
ac718b69 2080{
ebc2ec48 2081 u32 ocp_data;
2082 int i;
ac718b69 2083
6871438c 2084 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2085 rtl_drop_queued_tx(tp);
2086 return;
2087 }
2088
ac718b69 2089 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2090 ocp_data &= ~RCR_ACPT_ALL;
2091 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2092
00a5e360 2093 rtl_drop_queued_tx(tp);
ebc2ec48 2094
2095 for (i = 0; i < RTL8152_MAX_TX; i++)
2096 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2097
00a5e360 2098 rxdy_gated_en(tp, true);
ac718b69 2099
2100 for (i = 0; i < 1000; i++) {
2101 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2102 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2103 break;
8ddfa077 2104 usleep_range(1000, 2000);
ac718b69 2105 }
2106
2107 for (i = 0; i < 1000; i++) {
2108 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2109 break;
8ddfa077 2110 usleep_range(1000, 2000);
ac718b69 2111 }
2112
445f7f4d 2113 rtl_stop_rx(tp);
ac718b69 2114
2115 rtl8152_nic_reset(tp);
2116}
2117
00a5e360 2118static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2119{
2120 u32 ocp_data;
2121
2122 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2123 if (enable)
2124 ocp_data |= POWER_CUT;
2125 else
2126 ocp_data &= ~POWER_CUT;
2127 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2128
2129 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2130 ocp_data &= ~RESUME_INDICATE;
2131 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2132}
2133
c5554298 2134static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2135{
2136 u32 ocp_data;
2137
2138 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2139 if (enable)
2140 ocp_data |= CPCR_RX_VLAN;
2141 else
2142 ocp_data &= ~CPCR_RX_VLAN;
2143 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2144}
2145
2146static int rtl8152_set_features(struct net_device *dev,
2147 netdev_features_t features)
2148{
2149 netdev_features_t changed = features ^ dev->features;
2150 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2151 int ret;
2152
2153 ret = usb_autopm_get_interface(tp->intf);
2154 if (ret < 0)
2155 goto out;
c5554298 2156
b5403273 2157 mutex_lock(&tp->control);
2158
c5554298 2159 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2160 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2161 rtl_rx_vlan_en(tp, true);
2162 else
2163 rtl_rx_vlan_en(tp, false);
2164 }
2165
b5403273 2166 mutex_unlock(&tp->control);
2167
405f8a0e 2168 usb_autopm_put_interface(tp->intf);
2169
2170out:
2171 return ret;
c5554298 2172}
2173
21ff2e89 2174#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2175
2176static u32 __rtl_get_wol(struct r8152 *tp)
2177{
2178 u32 ocp_data;
2179 u32 wolopts = 0;
2180
2181 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2182 if (!(ocp_data & LAN_WAKE_EN))
2183 return 0;
2184
2185 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2186 if (ocp_data & LINK_ON_WAKE_EN)
2187 wolopts |= WAKE_PHY;
2188
2189 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2190 if (ocp_data & UWF_EN)
2191 wolopts |= WAKE_UCAST;
2192 if (ocp_data & BWF_EN)
2193 wolopts |= WAKE_BCAST;
2194 if (ocp_data & MWF_EN)
2195 wolopts |= WAKE_MCAST;
2196
2197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2198 if (ocp_data & MAGIC_EN)
2199 wolopts |= WAKE_MAGIC;
2200
2201 return wolopts;
2202}
2203
2204static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2205{
2206 u32 ocp_data;
2207
2208 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2209
2210 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2211 ocp_data &= ~LINK_ON_WAKE_EN;
2212 if (wolopts & WAKE_PHY)
2213 ocp_data |= LINK_ON_WAKE_EN;
2214 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2215
2216 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2217 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2218 if (wolopts & WAKE_UCAST)
2219 ocp_data |= UWF_EN;
2220 if (wolopts & WAKE_BCAST)
2221 ocp_data |= BWF_EN;
2222 if (wolopts & WAKE_MCAST)
2223 ocp_data |= MWF_EN;
2224 if (wolopts & WAKE_ANY)
2225 ocp_data |= LAN_WAKE_EN;
2226 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2227
2228 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2229
2230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2231 ocp_data &= ~MAGIC_EN;
2232 if (wolopts & WAKE_MAGIC)
2233 ocp_data |= MAGIC_EN;
2234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2235
2236 if (wolopts & WAKE_ANY)
2237 device_set_wakeup_enable(&tp->udev->dev, true);
2238 else
2239 device_set_wakeup_enable(&tp->udev->dev, false);
2240}
2241
9a4be1bd 2242static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2243{
2244 if (enable) {
2245 u32 ocp_data;
2246
2247 __rtl_set_wol(tp, WAKE_ANY);
2248
2249 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2250
2251 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2252 ocp_data |= LINK_OFF_WAKE_EN;
2253 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2254
2255 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2256 } else {
2257 __rtl_set_wol(tp, tp->saved_wolopts);
2258 }
2259}
2260
aa66a5f1 2261static void rtl_phy_reset(struct r8152 *tp)
2262{
2263 u16 data;
2264 int i;
2265
2266 clear_bit(PHY_RESET, &tp->flags);
2267
2268 data = r8152_mdio_read(tp, MII_BMCR);
2269
2270 /* don't reset again before the previous one complete */
2271 if (data & BMCR_RESET)
2272 return;
2273
2274 data |= BMCR_RESET;
2275 r8152_mdio_write(tp, MII_BMCR, data);
2276
2277 for (i = 0; i < 50; i++) {
2278 msleep(20);
2279 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2280 break;
2281 }
2282}
2283
4349968a 2284static void r8153_teredo_off(struct r8152 *tp)
2285{
2286 u32 ocp_data;
2287
2288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2289 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2291
2292 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2294 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2295}
2296
2297static void r8152b_disable_aldps(struct r8152 *tp)
2298{
2299 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2300 msleep(20);
2301}
2302
2303static inline void r8152b_enable_aldps(struct r8152 *tp)
2304{
2305 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2306 LINKENA | DIS_SDSAVE);
2307}
2308
d70b1137 2309static void rtl8152_disable(struct r8152 *tp)
2310{
2311 r8152b_disable_aldps(tp);
2312 rtl_disable(tp);
2313 r8152b_enable_aldps(tp);
2314}
2315
4349968a 2316static void r8152b_hw_phy_cfg(struct r8152 *tp)
2317{
f0cbe0ac 2318 u16 data;
2319
2320 data = r8152_mdio_read(tp, MII_BMCR);
2321 if (data & BMCR_PDOWN) {
2322 data &= ~BMCR_PDOWN;
2323 r8152_mdio_write(tp, MII_BMCR, data);
2324 }
2325
aa66a5f1 2326 set_bit(PHY_RESET, &tp->flags);
4349968a 2327}
2328
ac718b69 2329static void r8152b_exit_oob(struct r8152 *tp)
2330{
db8515ef 2331 u32 ocp_data;
2332 int i;
ac718b69 2333
2334 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2335 ocp_data &= ~RCR_ACPT_ALL;
2336 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2337
00a5e360 2338 rxdy_gated_en(tp, true);
da9bd117 2339 r8153_teredo_off(tp);
7e9da481 2340 r8152b_hw_phy_cfg(tp);
ac718b69 2341
2342 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2343 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2344
2345 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2346 ocp_data &= ~NOW_IS_OOB;
2347 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2348
2349 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2350 ocp_data &= ~MCU_BORW_EN;
2351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2352
2353 for (i = 0; i < 1000; i++) {
2354 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2355 if (ocp_data & LINK_LIST_READY)
2356 break;
8ddfa077 2357 usleep_range(1000, 2000);
ac718b69 2358 }
2359
2360 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2361 ocp_data |= RE_INIT_LL;
2362 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2363
2364 for (i = 0; i < 1000; i++) {
2365 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2366 if (ocp_data & LINK_LIST_READY)
2367 break;
8ddfa077 2368 usleep_range(1000, 2000);
ac718b69 2369 }
2370
2371 rtl8152_nic_reset(tp);
2372
2373 /* rx share fifo credit full threshold */
2374 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2375
a3cc465d 2376 if (tp->udev->speed == USB_SPEED_FULL ||
2377 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2378 /* rx share fifo credit near full threshold */
2379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2380 RXFIFO_THR2_FULL);
2381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2382 RXFIFO_THR3_FULL);
2383 } else {
2384 /* rx share fifo credit near full threshold */
2385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2386 RXFIFO_THR2_HIGH);
2387 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2388 RXFIFO_THR3_HIGH);
2389 }
2390
2391 /* TX share fifo free credit full threshold */
2392 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2393
2394 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2395 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2396 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2397 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2398
c5554298 2399 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2400
2401 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2402
2403 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2404 ocp_data |= TCR0_AUTO_FIFO;
2405 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2406}
2407
2408static void r8152b_enter_oob(struct r8152 *tp)
2409{
45f4a19f 2410 u32 ocp_data;
2411 int i;
ac718b69 2412
2413 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2414 ocp_data &= ~NOW_IS_OOB;
2415 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2416
2417 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2418 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2419 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2420
d70b1137 2421 rtl_disable(tp);
ac718b69 2422
2423 for (i = 0; i < 1000; i++) {
2424 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2425 if (ocp_data & LINK_LIST_READY)
2426 break;
8ddfa077 2427 usleep_range(1000, 2000);
ac718b69 2428 }
2429
2430 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2431 ocp_data |= RE_INIT_LL;
2432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2433
2434 for (i = 0; i < 1000; i++) {
2435 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2436 if (ocp_data & LINK_LIST_READY)
2437 break;
8ddfa077 2438 usleep_range(1000, 2000);
ac718b69 2439 }
2440
2441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2442
c5554298 2443 rtl_rx_vlan_en(tp, true);
ac718b69 2444
2445 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2446 ocp_data |= ALDPS_PROXY_MODE;
2447 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2448
2449 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2450 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2451 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2452
00a5e360 2453 rxdy_gated_en(tp, false);
ac718b69 2454
2455 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2456 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2457 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2458}
2459
43779f8d 2460static void r8153_hw_phy_cfg(struct r8152 *tp)
2461{
2462 u32 ocp_data;
2463 u16 data;
2464
2465 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2466 data = r8152_mdio_read(tp, MII_BMCR);
2467 if (data & BMCR_PDOWN) {
2468 data &= ~BMCR_PDOWN;
2469 r8152_mdio_write(tp, MII_BMCR, data);
2470 }
43779f8d 2471
2472 if (tp->version == RTL_VER_03) {
2473 data = ocp_reg_read(tp, OCP_EEE_CFG);
2474 data &= ~CTAP_SHORT_EN;
2475 ocp_reg_write(tp, OCP_EEE_CFG, data);
2476 }
2477
2478 data = ocp_reg_read(tp, OCP_POWER_CFG);
2479 data |= EEE_CLKDIV_EN;
2480 ocp_reg_write(tp, OCP_POWER_CFG, data);
2481
2482 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2483 data |= EN_10M_BGOFF;
2484 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2485 data = ocp_reg_read(tp, OCP_POWER_CFG);
2486 data |= EN_10M_PLLOFF;
2487 ocp_reg_write(tp, OCP_POWER_CFG, data);
2488 data = sram_read(tp, SRAM_IMPEDANCE);
2489 data &= ~RX_DRIVING_MASK;
2490 sram_write(tp, SRAM_IMPEDANCE, data);
2491
2492 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2493 ocp_data |= PFM_PWM_SWITCH;
2494 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2495
2496 data = sram_read(tp, SRAM_LPF_CFG);
2497 data |= LPF_AUTO_TUNE;
2498 sram_write(tp, SRAM_LPF_CFG, data);
2499
2500 data = sram_read(tp, SRAM_10M_AMP1);
2501 data |= GDAC_IB_UPALL;
2502 sram_write(tp, SRAM_10M_AMP1, data);
2503 data = sram_read(tp, SRAM_10M_AMP2);
2504 data |= AMP_DN;
2505 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2506
2507 set_bit(PHY_RESET, &tp->flags);
43779f8d 2508}
2509
b9702723 2510static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2511{
2512 u8 u1u2[8];
2513
2514 if (enable)
2515 memset(u1u2, 0xff, sizeof(u1u2));
2516 else
2517 memset(u1u2, 0x00, sizeof(u1u2));
2518
2519 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2520}
2521
b9702723 2522static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2523{
2524 u32 ocp_data;
2525
2526 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2527 if (enable)
2528 ocp_data |= U2P3_ENABLE;
2529 else
2530 ocp_data &= ~U2P3_ENABLE;
2531 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2532}
2533
b9702723 2534static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2535{
2536 u32 ocp_data;
2537
2538 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2539 if (enable)
2540 ocp_data |= PWR_EN | PHASE2_EN;
2541 else
2542 ocp_data &= ~(PWR_EN | PHASE2_EN);
2543 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2544
2545 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2546 ocp_data &= ~PCUT_STATUS;
2547 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2548}
2549
43779f8d 2550static void r8153_first_init(struct r8152 *tp)
2551{
2552 u32 ocp_data;
2553 int i;
2554
00a5e360 2555 rxdy_gated_en(tp, true);
43779f8d 2556 r8153_teredo_off(tp);
2557
2558 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2559 ocp_data &= ~RCR_ACPT_ALL;
2560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2561
2562 r8153_hw_phy_cfg(tp);
2563
2564 rtl8152_nic_reset(tp);
2565
2566 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2567 ocp_data &= ~NOW_IS_OOB;
2568 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2569
2570 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2571 ocp_data &= ~MCU_BORW_EN;
2572 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2573
2574 for (i = 0; i < 1000; i++) {
2575 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2576 if (ocp_data & LINK_LIST_READY)
2577 break;
8ddfa077 2578 usleep_range(1000, 2000);
43779f8d 2579 }
2580
2581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2582 ocp_data |= RE_INIT_LL;
2583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2584
2585 for (i = 0; i < 1000; i++) {
2586 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2587 if (ocp_data & LINK_LIST_READY)
2588 break;
8ddfa077 2589 usleep_range(1000, 2000);
43779f8d 2590 }
2591
c5554298 2592 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2593
69b4b7a4 2594 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2595 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2596
2597 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2598 ocp_data |= TCR0_AUTO_FIFO;
2599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2600
2601 rtl8152_nic_reset(tp);
2602
2603 /* rx share fifo credit full threshold */
2604 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2606 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2607 /* TX share fifo free credit full threshold */
2608 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2609
9629e3c0 2610 /* rx aggregation */
43779f8d 2611 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2612 ocp_data &= ~RX_AGG_DISABLE;
2613 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2614}
2615
2616static void r8153_enter_oob(struct r8152 *tp)
2617{
2618 u32 ocp_data;
2619 int i;
2620
2621 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2622 ocp_data &= ~NOW_IS_OOB;
2623 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2624
d70b1137 2625 rtl_disable(tp);
43779f8d 2626
2627 for (i = 0; i < 1000; i++) {
2628 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2629 if (ocp_data & LINK_LIST_READY)
2630 break;
8ddfa077 2631 usleep_range(1000, 2000);
43779f8d 2632 }
2633
2634 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2635 ocp_data |= RE_INIT_LL;
2636 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2637
2638 for (i = 0; i < 1000; i++) {
2639 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2640 if (ocp_data & LINK_LIST_READY)
2641 break;
8ddfa077 2642 usleep_range(1000, 2000);
43779f8d 2643 }
2644
69b4b7a4 2645 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2646
43779f8d 2647 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2648 ocp_data &= ~TEREDO_WAKE_MASK;
2649 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2650
c5554298 2651 rtl_rx_vlan_en(tp, true);
43779f8d 2652
2653 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2654 ocp_data |= ALDPS_PROXY_MODE;
2655 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2656
2657 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2658 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2659 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2660
00a5e360 2661 rxdy_gated_en(tp, false);
43779f8d 2662
2663 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2664 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2665 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2666}
2667
2668static void r8153_disable_aldps(struct r8152 *tp)
2669{
2670 u16 data;
2671
2672 data = ocp_reg_read(tp, OCP_POWER_CFG);
2673 data &= ~EN_ALDPS;
2674 ocp_reg_write(tp, OCP_POWER_CFG, data);
2675 msleep(20);
2676}
2677
2678static void r8153_enable_aldps(struct r8152 *tp)
2679{
2680 u16 data;
2681
2682 data = ocp_reg_read(tp, OCP_POWER_CFG);
2683 data |= EN_ALDPS;
2684 ocp_reg_write(tp, OCP_POWER_CFG, data);
2685}
2686
d70b1137 2687static void rtl8153_disable(struct r8152 *tp)
2688{
2689 r8153_disable_aldps(tp);
2690 rtl_disable(tp);
2691 r8153_enable_aldps(tp);
2692}
2693
ac718b69 2694static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2695{
43779f8d 2696 u16 bmcr, anar, gbcr;
ac718b69 2697 int ret = 0;
2698
2699 cancel_delayed_work_sync(&tp->schedule);
2700 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2701 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2702 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2703 if (tp->mii.supports_gmii) {
2704 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2705 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2706 } else {
2707 gbcr = 0;
2708 }
ac718b69 2709
2710 if (autoneg == AUTONEG_DISABLE) {
2711 if (speed == SPEED_10) {
2712 bmcr = 0;
2713 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2714 } else if (speed == SPEED_100) {
2715 bmcr = BMCR_SPEED100;
2716 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2717 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2718 bmcr = BMCR_SPEED1000;
2719 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2720 } else {
2721 ret = -EINVAL;
2722 goto out;
2723 }
2724
2725 if (duplex == DUPLEX_FULL)
2726 bmcr |= BMCR_FULLDPLX;
2727 } else {
2728 if (speed == SPEED_10) {
2729 if (duplex == DUPLEX_FULL)
2730 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2731 else
2732 anar |= ADVERTISE_10HALF;
2733 } else if (speed == SPEED_100) {
2734 if (duplex == DUPLEX_FULL) {
2735 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2736 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2737 } else {
2738 anar |= ADVERTISE_10HALF;
2739 anar |= ADVERTISE_100HALF;
2740 }
43779f8d 2741 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2742 if (duplex == DUPLEX_FULL) {
2743 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2744 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2745 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2746 } else {
2747 anar |= ADVERTISE_10HALF;
2748 anar |= ADVERTISE_100HALF;
2749 gbcr |= ADVERTISE_1000HALF;
2750 }
ac718b69 2751 } else {
2752 ret = -EINVAL;
2753 goto out;
2754 }
2755
2756 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2757 }
2758
aa66a5f1 2759 if (test_bit(PHY_RESET, &tp->flags))
2760 bmcr |= BMCR_RESET;
2761
43779f8d 2762 if (tp->mii.supports_gmii)
2763 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2764
ac718b69 2765 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2766 r8152_mdio_write(tp, MII_BMCR, bmcr);
2767
aa66a5f1 2768 if (test_bit(PHY_RESET, &tp->flags)) {
2769 int i;
2770
2771 clear_bit(PHY_RESET, &tp->flags);
2772 for (i = 0; i < 50; i++) {
2773 msleep(20);
2774 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2775 break;
2776 }
2777 }
2778
ac718b69 2779out:
ac718b69 2780
2781 return ret;
2782}
2783
d70b1137 2784static void rtl8152_up(struct r8152 *tp)
2785{
2786 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2787 return;
2788
2789 r8152b_disable_aldps(tp);
2790 r8152b_exit_oob(tp);
2791 r8152b_enable_aldps(tp);
2792}
2793
ac718b69 2794static void rtl8152_down(struct r8152 *tp)
2795{
6871438c 2796 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2797 rtl_drop_queued_tx(tp);
2798 return;
2799 }
2800
00a5e360 2801 r8152_power_cut_en(tp, false);
ac718b69 2802 r8152b_disable_aldps(tp);
2803 r8152b_enter_oob(tp);
2804 r8152b_enable_aldps(tp);
2805}
2806
d70b1137 2807static void rtl8153_up(struct r8152 *tp)
2808{
2809 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2810 return;
2811
2812 r8153_disable_aldps(tp);
2813 r8153_first_init(tp);
2814 r8153_enable_aldps(tp);
2815}
2816
43779f8d 2817static void rtl8153_down(struct r8152 *tp)
2818{
6871438c 2819 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2820 rtl_drop_queued_tx(tp);
2821 return;
2822 }
2823
b9702723 2824 r8153_u1u2en(tp, false);
2825 r8153_power_cut_en(tp, false);
43779f8d 2826 r8153_disable_aldps(tp);
2827 r8153_enter_oob(tp);
2828 r8153_enable_aldps(tp);
2829}
2830
ac718b69 2831static void set_carrier(struct r8152 *tp)
2832{
2833 struct net_device *netdev = tp->netdev;
2834 u8 speed;
2835
40a82917 2836 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2837 speed = rtl8152_get_speed(tp);
2838
2839 if (speed & LINK_STATUS) {
2840 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2841 tp->rtl_ops.enable(tp);
ac718b69 2842 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2843 netif_carrier_on(netdev);
2844 }
2845 } else {
2846 if (tp->speed & LINK_STATUS) {
2847 netif_carrier_off(netdev);
ebc2ec48 2848 tasklet_disable(&tp->tl);
c81229c9 2849 tp->rtl_ops.disable(tp);
ebc2ec48 2850 tasklet_enable(&tp->tl);
ac718b69 2851 }
2852 }
2853 tp->speed = speed;
2854}
2855
2856static void rtl_work_func_t(struct work_struct *work)
2857{
2858 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2859
a1f83fee 2860 /* If the device is unplugged or !netif_running(), the workqueue
2861 * doesn't need to wake the device, and could return directly.
2862 */
2863 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2864 return;
2865
9a4be1bd 2866 if (usb_autopm_get_interface(tp->intf) < 0)
2867 return;
2868
ac718b69 2869 if (!test_bit(WORK_ENABLE, &tp->flags))
2870 goto out1;
2871
b5403273 2872 if (!mutex_trylock(&tp->control)) {
2873 schedule_delayed_work(&tp->schedule, 0);
2874 goto out1;
2875 }
2876
40a82917 2877 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2878 set_carrier(tp);
ac718b69 2879
2880 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2881 _rtl8152_set_rx_mode(tp->netdev);
2882
0c3121fc 2883 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2884 (tp->speed & LINK_STATUS)) {
2885 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2886 tasklet_schedule(&tp->tl);
2887 }
aa66a5f1 2888
2889 if (test_bit(PHY_RESET, &tp->flags))
2890 rtl_phy_reset(tp);
2891
b5403273 2892 mutex_unlock(&tp->control);
2893
ac718b69 2894out1:
9a4be1bd 2895 usb_autopm_put_interface(tp->intf);
ac718b69 2896}
2897
2898static int rtl8152_open(struct net_device *netdev)
2899{
2900 struct r8152 *tp = netdev_priv(netdev);
2901 int res = 0;
2902
7e9da481 2903 res = alloc_all_mem(tp);
2904 if (res)
2905 goto out;
2906
f4c7476b 2907 /* set speed to 0 to avoid autoresume try to submit rx */
2908 tp->speed = 0;
2909
9a4be1bd 2910 res = usb_autopm_get_interface(tp->intf);
2911 if (res < 0) {
2912 free_all_mem(tp);
2913 goto out;
2914 }
2915
b5403273 2916 mutex_lock(&tp->control);
2917
9a4be1bd 2918 /* The WORK_ENABLE may be set when autoresume occurs */
2919 if (test_bit(WORK_ENABLE, &tp->flags)) {
2920 clear_bit(WORK_ENABLE, &tp->flags);
2921 usb_kill_urb(tp->intr_urb);
2922 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 2923
2924 /* disable the tx/rx, if the workqueue has enabled them. */
9a4be1bd 2925 if (tp->speed & LINK_STATUS)
2926 tp->rtl_ops.disable(tp);
2927 }
2928
7e9da481 2929 tp->rtl_ops.up(tp);
2930
3d55f44f 2931 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2932 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2933 DUPLEX_FULL);
2934 tp->speed = 0;
2935 netif_carrier_off(netdev);
2936 netif_start_queue(netdev);
2937 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 2938
40a82917 2939 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2940 if (res) {
2941 if (res == -ENODEV)
2942 netif_device_detach(tp->netdev);
4a8deae2
HW
2943 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2944 res);
7e9da481 2945 free_all_mem(tp);
93ffbeab 2946 } else {
2947 tasklet_enable(&tp->tl);
ac718b69 2948 }
2949
b5403273 2950 mutex_unlock(&tp->control);
2951
9a4be1bd 2952 usb_autopm_put_interface(tp->intf);
ac718b69 2953
7e9da481 2954out:
ac718b69 2955 return res;
2956}
2957
2958static int rtl8152_close(struct net_device *netdev)
2959{
2960 struct r8152 *tp = netdev_priv(netdev);
2961 int res = 0;
2962
93ffbeab 2963 tasklet_disable(&tp->tl);
ac718b69 2964 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2965 usb_kill_urb(tp->intr_urb);
ac718b69 2966 cancel_delayed_work_sync(&tp->schedule);
2967 netif_stop_queue(netdev);
9a4be1bd 2968
2969 res = usb_autopm_get_interface(tp->intf);
2970 if (res < 0) {
2971 rtl_drop_queued_tx(tp);
2972 } else {
b5403273 2973 mutex_lock(&tp->control);
2974
b209af99 2975 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 2976 * be disable when autoresume occurs, because the
2977 * netif_running() would be false.
2978 */
923e1ee3 2979 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 2980
9a4be1bd 2981 tp->rtl_ops.down(tp);
b5403273 2982
2983 mutex_unlock(&tp->control);
2984
9a4be1bd 2985 usb_autopm_put_interface(tp->intf);
2986 }
ac718b69 2987
7e9da481 2988 free_all_mem(tp);
2989
ac718b69 2990 return res;
2991}
2992
d24f6134 2993static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2994{
2995 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2996 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2997 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2998}
2999
3000static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3001{
3002 u16 data;
3003
3004 r8152_mmd_indirect(tp, dev, reg);
3005 data = ocp_reg_read(tp, OCP_EEE_DATA);
3006 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3007
3008 return data;
3009}
3010
3011static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3012{
d24f6134 3013 r8152_mmd_indirect(tp, dev, reg);
3014 ocp_reg_write(tp, OCP_EEE_DATA, data);
3015 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3016}
3017
3018static void r8152_eee_en(struct r8152 *tp, bool enable)
3019{
3020 u16 config1, config2, config3;
45f4a19f 3021 u32 ocp_data;
ac718b69 3022
3023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3024 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3025 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3026 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3027
3028 if (enable) {
3029 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3030 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3031 config1 |= sd_rise_time(1);
3032 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3033 config3 |= fast_snr(42);
3034 } else {
3035 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3036 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3037 RX_QUIET_EN);
3038 config1 |= sd_rise_time(7);
3039 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3040 config3 |= fast_snr(511);
3041 }
3042
ac718b69 3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3044 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3045 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3046 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3047}
3048
d24f6134 3049static void r8152b_enable_eee(struct r8152 *tp)
3050{
3051 r8152_eee_en(tp, true);
3052 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3053}
3054
3055static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3056{
3057 u32 ocp_data;
d24f6134 3058 u16 config;
43779f8d 3059
3060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3061 config = ocp_reg_read(tp, OCP_EEE_CFG);
3062
3063 if (enable) {
3064 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3065 config |= EEE10_EN;
3066 } else {
3067 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3068 config &= ~EEE10_EN;
3069 }
3070
43779f8d 3071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3072 ocp_reg_write(tp, OCP_EEE_CFG, config);
3073}
3074
3075static void r8153_enable_eee(struct r8152 *tp)
3076{
3077 r8153_eee_en(tp, true);
3078 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3079}
3080
ac718b69 3081static void r8152b_enable_fc(struct r8152 *tp)
3082{
3083 u16 anar;
3084
3085 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3086 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3087 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3088}
3089
4f1d4d54 3090static void rtl_tally_reset(struct r8152 *tp)
3091{
3092 u32 ocp_data;
3093
3094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3095 ocp_data |= TALLY_RESET;
3096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3097}
3098
ac718b69 3099static void r8152b_init(struct r8152 *tp)
3100{
ebc2ec48 3101 u32 ocp_data;
ac718b69 3102
6871438c 3103 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3104 return;
3105
d70b1137 3106 r8152b_disable_aldps(tp);
3107
ac718b69 3108 if (tp->version == RTL_VER_01) {
3109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3110 ocp_data &= ~LED_MODE_MASK;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3112 }
3113
00a5e360 3114 r8152_power_cut_en(tp, false);
ac718b69 3115
ac718b69 3116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3117 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3119 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3120 ocp_data &= ~MCU_CLK_RATIO_MASK;
3121 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3122 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3123 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3124 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3126
3127 r8152b_enable_eee(tp);
3128 r8152b_enable_aldps(tp);
3129 r8152b_enable_fc(tp);
4f1d4d54 3130 rtl_tally_reset(tp);
ac718b69 3131
ebc2ec48 3132 /* enable rx aggregation */
ac718b69 3133 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3134 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3135 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3136}
3137
43779f8d 3138static void r8153_init(struct r8152 *tp)
3139{
3140 u32 ocp_data;
3141 int i;
3142
6871438c 3143 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3144 return;
3145
d70b1137 3146 r8153_disable_aldps(tp);
b9702723 3147 r8153_u1u2en(tp, false);
43779f8d 3148
3149 for (i = 0; i < 500; i++) {
3150 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3151 AUTOLOAD_DONE)
3152 break;
3153 msleep(20);
3154 }
3155
3156 for (i = 0; i < 500; i++) {
3157 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3158 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3159 break;
3160 msleep(20);
3161 }
3162
b9702723 3163 r8153_u2p3en(tp, false);
43779f8d 3164
3165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3166 ocp_data &= ~TIMER11_EN;
3167 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3168
43779f8d 3169 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3170 ocp_data &= ~LED_MODE_MASK;
3171 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3172
3173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3174 ocp_data &= ~LPM_TIMER_MASK;
3175 if (tp->udev->speed == USB_SPEED_SUPER)
3176 ocp_data |= LPM_TIMER_500US;
3177 else
3178 ocp_data |= LPM_TIMER_500MS;
3179 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3180
3181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3182 ocp_data &= ~SEN_VAL_MASK;
3183 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3184 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3185
b9702723 3186 r8153_power_cut_en(tp, false);
3187 r8153_u1u2en(tp, true);
43779f8d 3188
43779f8d 3189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3192 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3193 U1U2_SPDWN_EN | L1_SPDWN_EN);
3194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3195 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3196 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3197 EEE_SPDWN_EN);
3198
3199 r8153_enable_eee(tp);
3200 r8153_enable_aldps(tp);
3201 r8152b_enable_fc(tp);
4f1d4d54 3202 rtl_tally_reset(tp);
43779f8d 3203}
3204
ac718b69 3205static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3206{
3207 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3208 struct net_device *netdev = tp->netdev;
3209 int ret = 0;
ac718b69 3210
b5403273 3211 mutex_lock(&tp->control);
3212
6cc69f2a 3213 if (PMSG_IS_AUTO(message)) {
3214 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3215 ret = -EBUSY;
3216 goto out1;
3217 }
3218
9a4be1bd 3219 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3220 } else {
3221 netif_device_detach(netdev);
3222 }
ac718b69 3223
e3bd1a81 3224 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3225 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3226 usb_kill_urb(tp->intr_urb);
445f7f4d 3227 tasklet_disable(&tp->tl);
9a4be1bd 3228 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3229 rtl_stop_rx(tp);
9a4be1bd 3230 rtl_runtime_suspend_enable(tp, true);
3231 } else {
6cc69f2a 3232 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3233 tp->rtl_ops.down(tp);
9a4be1bd 3234 }
445f7f4d 3235 tasklet_enable(&tp->tl);
ac718b69 3236 }
6cc69f2a 3237out1:
b5403273 3238 mutex_unlock(&tp->control);
3239
6cc69f2a 3240 return ret;
ac718b69 3241}
3242
3243static int rtl8152_resume(struct usb_interface *intf)
3244{
3245 struct r8152 *tp = usb_get_intfdata(intf);
3246
b5403273 3247 mutex_lock(&tp->control);
3248
9a4be1bd 3249 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3250 tp->rtl_ops.init(tp);
3251 netif_device_attach(tp->netdev);
3252 }
3253
ac718b69 3254 if (netif_running(tp->netdev)) {
9a4be1bd 3255 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3256 rtl_runtime_suspend_enable(tp, false);
3257 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3258 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3259 if (tp->speed & LINK_STATUS)
445f7f4d 3260 rtl_start_rx(tp);
9a4be1bd 3261 } else {
3262 tp->rtl_ops.up(tp);
3263 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3264 tp->mii.supports_gmii ?
3265 SPEED_1000 : SPEED_100,
3266 DUPLEX_FULL);
445f7f4d 3267 tp->speed = 0;
3268 netif_carrier_off(tp->netdev);
3269 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3270 }
40a82917 3271 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3272 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3273 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3274 }
3275
b5403273 3276 mutex_unlock(&tp->control);
3277
ac718b69 3278 return 0;
3279}
3280
21ff2e89 3281static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3282{
3283 struct r8152 *tp = netdev_priv(dev);
3284
9a4be1bd 3285 if (usb_autopm_get_interface(tp->intf) < 0)
3286 return;
3287
b5403273 3288 mutex_lock(&tp->control);
3289
21ff2e89 3290 wol->supported = WAKE_ANY;
3291 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3292
b5403273 3293 mutex_unlock(&tp->control);
3294
9a4be1bd 3295 usb_autopm_put_interface(tp->intf);
21ff2e89 3296}
3297
3298static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3299{
3300 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3301 int ret;
3302
3303 ret = usb_autopm_get_interface(tp->intf);
3304 if (ret < 0)
3305 goto out_set_wol;
21ff2e89 3306
b5403273 3307 mutex_lock(&tp->control);
3308
21ff2e89 3309 __rtl_set_wol(tp, wol->wolopts);
3310 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3311
b5403273 3312 mutex_unlock(&tp->control);
3313
9a4be1bd 3314 usb_autopm_put_interface(tp->intf);
3315
3316out_set_wol:
3317 return ret;
21ff2e89 3318}
3319
a5ec27c1 3320static u32 rtl8152_get_msglevel(struct net_device *dev)
3321{
3322 struct r8152 *tp = netdev_priv(dev);
3323
3324 return tp->msg_enable;
3325}
3326
3327static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3328{
3329 struct r8152 *tp = netdev_priv(dev);
3330
3331 tp->msg_enable = value;
3332}
3333
ac718b69 3334static void rtl8152_get_drvinfo(struct net_device *netdev,
3335 struct ethtool_drvinfo *info)
3336{
3337 struct r8152 *tp = netdev_priv(netdev);
3338
b0b46c77 3339 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3340 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3341 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3342}
3343
3344static
3345int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3346{
3347 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3348 int ret;
ac718b69 3349
3350 if (!tp->mii.mdio_read)
3351 return -EOPNOTSUPP;
3352
8d4a4d72 3353 ret = usb_autopm_get_interface(tp->intf);
3354 if (ret < 0)
3355 goto out;
3356
b5403273 3357 mutex_lock(&tp->control);
3358
8d4a4d72 3359 ret = mii_ethtool_gset(&tp->mii, cmd);
3360
b5403273 3361 mutex_unlock(&tp->control);
3362
8d4a4d72 3363 usb_autopm_put_interface(tp->intf);
3364
3365out:
3366 return ret;
ac718b69 3367}
3368
3369static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3370{
3371 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3372 int ret;
3373
3374 ret = usb_autopm_get_interface(tp->intf);
3375 if (ret < 0)
3376 goto out;
ac718b69 3377
b5403273 3378 mutex_lock(&tp->control);
3379
9a4be1bd 3380 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3381
b5403273 3382 mutex_unlock(&tp->control);
3383
9a4be1bd 3384 usb_autopm_put_interface(tp->intf);
3385
3386out:
3387 return ret;
ac718b69 3388}
3389
4f1d4d54 3390static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3391 "tx_packets",
3392 "rx_packets",
3393 "tx_errors",
3394 "rx_errors",
3395 "rx_missed",
3396 "align_errors",
3397 "tx_single_collisions",
3398 "tx_multi_collisions",
3399 "rx_unicast",
3400 "rx_broadcast",
3401 "rx_multicast",
3402 "tx_aborted",
3403 "tx_underrun",
3404};
3405
3406static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3407{
3408 switch (sset) {
3409 case ETH_SS_STATS:
3410 return ARRAY_SIZE(rtl8152_gstrings);
3411 default:
3412 return -EOPNOTSUPP;
3413 }
3414}
3415
3416static void rtl8152_get_ethtool_stats(struct net_device *dev,
3417 struct ethtool_stats *stats, u64 *data)
3418{
3419 struct r8152 *tp = netdev_priv(dev);
3420 struct tally_counter tally;
3421
0b030244 3422 if (usb_autopm_get_interface(tp->intf) < 0)
3423 return;
3424
4f1d4d54 3425 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3426
0b030244 3427 usb_autopm_put_interface(tp->intf);
3428
4f1d4d54 3429 data[0] = le64_to_cpu(tally.tx_packets);
3430 data[1] = le64_to_cpu(tally.rx_packets);
3431 data[2] = le64_to_cpu(tally.tx_errors);
3432 data[3] = le32_to_cpu(tally.rx_errors);
3433 data[4] = le16_to_cpu(tally.rx_missed);
3434 data[5] = le16_to_cpu(tally.align_errors);
3435 data[6] = le32_to_cpu(tally.tx_one_collision);
3436 data[7] = le32_to_cpu(tally.tx_multi_collision);
3437 data[8] = le64_to_cpu(tally.rx_unicast);
3438 data[9] = le64_to_cpu(tally.rx_broadcast);
3439 data[10] = le32_to_cpu(tally.rx_multicast);
3440 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3441 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3442}
3443
3444static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3445{
3446 switch (stringset) {
3447 case ETH_SS_STATS:
3448 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3449 break;
3450 }
3451}
3452
df35d283 3453static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3454{
3455 u32 ocp_data, lp, adv, supported = 0;
3456 u16 val;
3457
3458 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3459 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3460
3461 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3462 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3463
3464 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3465 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3466
3467 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3468 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3469
3470 eee->eee_enabled = !!ocp_data;
3471 eee->eee_active = !!(supported & adv & lp);
3472 eee->supported = supported;
3473 eee->advertised = adv;
3474 eee->lp_advertised = lp;
3475
3476 return 0;
3477}
3478
3479static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3480{
3481 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3482
3483 r8152_eee_en(tp, eee->eee_enabled);
3484
3485 if (!eee->eee_enabled)
3486 val = 0;
3487
3488 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3489
3490 return 0;
3491}
3492
3493static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3494{
3495 u32 ocp_data, lp, adv, supported = 0;
3496 u16 val;
3497
3498 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3499 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3500
3501 val = ocp_reg_read(tp, OCP_EEE_ADV);
3502 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3503
3504 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3505 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3506
3507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3508 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3509
3510 eee->eee_enabled = !!ocp_data;
3511 eee->eee_active = !!(supported & adv & lp);
3512 eee->supported = supported;
3513 eee->advertised = adv;
3514 eee->lp_advertised = lp;
3515
3516 return 0;
3517}
3518
3519static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3520{
3521 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3522
3523 r8153_eee_en(tp, eee->eee_enabled);
3524
3525 if (!eee->eee_enabled)
3526 val = 0;
3527
3528 ocp_reg_write(tp, OCP_EEE_ADV, val);
3529
3530 return 0;
3531}
3532
3533static int
3534rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3535{
3536 struct r8152 *tp = netdev_priv(net);
3537 int ret;
3538
3539 ret = usb_autopm_get_interface(tp->intf);
3540 if (ret < 0)
3541 goto out;
3542
b5403273 3543 mutex_lock(&tp->control);
3544
df35d283 3545 ret = tp->rtl_ops.eee_get(tp, edata);
3546
b5403273 3547 mutex_unlock(&tp->control);
3548
df35d283 3549 usb_autopm_put_interface(tp->intf);
3550
3551out:
3552 return ret;
3553}
3554
3555static int
3556rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3557{
3558 struct r8152 *tp = netdev_priv(net);
3559 int ret;
3560
3561 ret = usb_autopm_get_interface(tp->intf);
3562 if (ret < 0)
3563 goto out;
3564
b5403273 3565 mutex_lock(&tp->control);
3566
df35d283 3567 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3568 if (!ret)
3569 ret = mii_nway_restart(&tp->mii);
df35d283 3570
b5403273 3571 mutex_unlock(&tp->control);
3572
df35d283 3573 usb_autopm_put_interface(tp->intf);
3574
3575out:
3576 return ret;
3577}
3578
8884f507 3579static int rtl8152_nway_reset(struct net_device *dev)
3580{
3581 struct r8152 *tp = netdev_priv(dev);
3582 int ret;
3583
3584 ret = usb_autopm_get_interface(tp->intf);
3585 if (ret < 0)
3586 goto out;
3587
3588 mutex_lock(&tp->control);
3589
3590 ret = mii_nway_restart(&tp->mii);
3591
3592 mutex_unlock(&tp->control);
3593
3594 usb_autopm_put_interface(tp->intf);
3595
3596out:
3597 return ret;
3598}
3599
ac718b69 3600static struct ethtool_ops ops = {
3601 .get_drvinfo = rtl8152_get_drvinfo,
3602 .get_settings = rtl8152_get_settings,
3603 .set_settings = rtl8152_set_settings,
3604 .get_link = ethtool_op_get_link,
8884f507 3605 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3606 .get_msglevel = rtl8152_get_msglevel,
3607 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3608 .get_wol = rtl8152_get_wol,
3609 .set_wol = rtl8152_set_wol,
4f1d4d54 3610 .get_strings = rtl8152_get_strings,
3611 .get_sset_count = rtl8152_get_sset_count,
3612 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3613 .get_eee = rtl_ethtool_get_eee,
3614 .set_eee = rtl_ethtool_set_eee,
ac718b69 3615};
3616
3617static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3618{
3619 struct r8152 *tp = netdev_priv(netdev);
3620 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3621 int res;
3622
6871438c 3623 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3624 return -ENODEV;
3625
9a4be1bd 3626 res = usb_autopm_get_interface(tp->intf);
3627 if (res < 0)
3628 goto out;
ac718b69 3629
3630 switch (cmd) {
3631 case SIOCGMIIPHY:
3632 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3633 break;
3634
3635 case SIOCGMIIREG:
b5403273 3636 mutex_lock(&tp->control);
ac718b69 3637 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3638 mutex_unlock(&tp->control);
ac718b69 3639 break;
3640
3641 case SIOCSMIIREG:
3642 if (!capable(CAP_NET_ADMIN)) {
3643 res = -EPERM;
3644 break;
3645 }
b5403273 3646 mutex_lock(&tp->control);
ac718b69 3647 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3648 mutex_unlock(&tp->control);
ac718b69 3649 break;
3650
3651 default:
3652 res = -EOPNOTSUPP;
3653 }
3654
9a4be1bd 3655 usb_autopm_put_interface(tp->intf);
3656
3657out:
ac718b69 3658 return res;
3659}
3660
69b4b7a4 3661static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3662{
3663 struct r8152 *tp = netdev_priv(dev);
3664
3665 switch (tp->version) {
3666 case RTL_VER_01:
3667 case RTL_VER_02:
3668 return eth_change_mtu(dev, new_mtu);
3669 default:
3670 break;
3671 }
3672
3673 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3674 return -EINVAL;
3675
3676 dev->mtu = new_mtu;
3677
3678 return 0;
3679}
3680
ac718b69 3681static const struct net_device_ops rtl8152_netdev_ops = {
3682 .ndo_open = rtl8152_open,
3683 .ndo_stop = rtl8152_close,
3684 .ndo_do_ioctl = rtl8152_ioctl,
3685 .ndo_start_xmit = rtl8152_start_xmit,
3686 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3687 .ndo_set_features = rtl8152_set_features,
ac718b69 3688 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3689 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3690 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3691 .ndo_validate_addr = eth_validate_addr,
3692};
3693
3694static void r8152b_get_version(struct r8152 *tp)
3695{
3696 u32 ocp_data;
3697 u16 version;
3698
3699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3700 version = (u16)(ocp_data & VERSION_MASK);
3701
3702 switch (version) {
3703 case 0x4c00:
3704 tp->version = RTL_VER_01;
3705 break;
3706 case 0x4c10:
3707 tp->version = RTL_VER_02;
3708 break;
43779f8d 3709 case 0x5c00:
3710 tp->version = RTL_VER_03;
3711 tp->mii.supports_gmii = 1;
3712 break;
3713 case 0x5c10:
3714 tp->version = RTL_VER_04;
3715 tp->mii.supports_gmii = 1;
3716 break;
3717 case 0x5c20:
3718 tp->version = RTL_VER_05;
3719 tp->mii.supports_gmii = 1;
3720 break;
ac718b69 3721 default:
3722 netif_info(tp, probe, tp->netdev,
3723 "Unknown version 0x%04x\n", version);
3724 break;
3725 }
3726}
3727
e3fe0b1a 3728static void rtl8152_unload(struct r8152 *tp)
3729{
6871438c 3730 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3731 return;
3732
00a5e360 3733 if (tp->version != RTL_VER_01)
3734 r8152_power_cut_en(tp, true);
e3fe0b1a 3735}
3736
43779f8d 3737static void rtl8153_unload(struct r8152 *tp)
3738{
6871438c 3739 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3740 return;
3741
49be1723 3742 r8153_power_cut_en(tp, false);
43779f8d 3743}
3744
55b65475 3745static int rtl_ops_init(struct r8152 *tp)
c81229c9 3746{
3747 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 3748 int ret = 0;
3749
3750 switch (tp->version) {
3751 case RTL_VER_01:
3752 case RTL_VER_02:
3753 ops->init = r8152b_init;
3754 ops->enable = rtl8152_enable;
3755 ops->disable = rtl8152_disable;
3756 ops->up = rtl8152_up;
3757 ops->down = rtl8152_down;
3758 ops->unload = rtl8152_unload;
3759 ops->eee_get = r8152_get_eee;
3760 ops->eee_set = r8152_set_eee;
43779f8d 3761 break;
3762
55b65475 3763 case RTL_VER_03:
3764 case RTL_VER_04:
3765 case RTL_VER_05:
3766 ops->init = r8153_init;
3767 ops->enable = rtl8153_enable;
3768 ops->disable = rtl8153_disable;
3769 ops->up = rtl8153_up;
3770 ops->down = rtl8153_down;
3771 ops->unload = rtl8153_unload;
3772 ops->eee_get = r8153_get_eee;
3773 ops->eee_set = r8153_set_eee;
c81229c9 3774 break;
3775
3776 default:
55b65475 3777 ret = -ENODEV;
3778 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 3779 break;
3780 }
3781
3782 return ret;
3783}
3784
ac718b69 3785static int rtl8152_probe(struct usb_interface *intf,
3786 const struct usb_device_id *id)
3787{
3788 struct usb_device *udev = interface_to_usbdev(intf);
3789 struct r8152 *tp;
3790 struct net_device *netdev;
ebc2ec48 3791 int ret;
ac718b69 3792
10c32717 3793 if (udev->actconfig->desc.bConfigurationValue != 1) {
3794 usb_driver_set_configuration(udev, 1);
3795 return -ENODEV;
3796 }
3797
3798 usb_reset_device(udev);
ac718b69 3799 netdev = alloc_etherdev(sizeof(struct r8152));
3800 if (!netdev) {
4a8deae2 3801 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3802 return -ENOMEM;
3803 }
3804
ebc2ec48 3805 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3806 tp = netdev_priv(netdev);
3807 tp->msg_enable = 0x7FFF;
3808
e3ad412a 3809 tp->udev = udev;
3810 tp->netdev = netdev;
3811 tp->intf = intf;
3812
82cf94cb 3813 r8152b_get_version(tp);
55b65475 3814 ret = rtl_ops_init(tp);
31ca1dec 3815 if (ret)
3816 goto out;
c81229c9 3817
ebc2ec48 3818 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
b5403273 3819 mutex_init(&tp->control);
ac718b69 3820 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3821
ac718b69 3822 netdev->netdev_ops = &rtl8152_netdev_ops;
3823 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3824
60c89071 3825 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3826 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3827 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3828 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3829 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3830 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3831 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3832 NETIF_F_HW_VLAN_CTAG_RX |
3833 NETIF_F_HW_VLAN_CTAG_TX;
3834 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3835 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3836 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3837
7ad24ea4 3838 netdev->ethtool_ops = &ops;
60c89071 3839 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3840
3841 tp->mii.dev = netdev;
3842 tp->mii.mdio_read = read_mii_word;
3843 tp->mii.mdio_write = write_mii_word;
3844 tp->mii.phy_id_mask = 0x3f;
3845 tp->mii.reg_num_mask = 0x1f;
3846 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 3847
9a4be1bd 3848 intf->needs_remote_wakeup = 1;
3849
c81229c9 3850 tp->rtl_ops.init(tp);
ac718b69 3851 set_ethernet_addr(tp);
3852
ac718b69 3853 usb_set_intfdata(intf, tp);
ac718b69 3854
ebc2ec48 3855 ret = register_netdev(netdev);
3856 if (ret != 0) {
4a8deae2 3857 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3858 goto out1;
ac718b69 3859 }
3860
21ff2e89 3861 tp->saved_wolopts = __rtl_get_wol(tp);
3862 if (tp->saved_wolopts)
3863 device_set_wakeup_enable(&udev->dev, true);
3864 else
3865 device_set_wakeup_enable(&udev->dev, false);
3866
93ffbeab 3867 tasklet_disable(&tp->tl);
3868
4a8deae2 3869 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3870
3871 return 0;
3872
ac718b69 3873out1:
ebc2ec48 3874 usb_set_intfdata(intf, NULL);
93ffbeab 3875 tasklet_kill(&tp->tl);
ac718b69 3876out:
3877 free_netdev(netdev);
ebc2ec48 3878 return ret;
ac718b69 3879}
3880
ac718b69 3881static void rtl8152_disconnect(struct usb_interface *intf)
3882{
3883 struct r8152 *tp = usb_get_intfdata(intf);
3884
3885 usb_set_intfdata(intf, NULL);
3886 if (tp) {
f561de33 3887 struct usb_device *udev = tp->udev;
3888
3889 if (udev->state == USB_STATE_NOTATTACHED)
3890 set_bit(RTL8152_UNPLUG, &tp->flags);
3891
ac718b69 3892 tasklet_kill(&tp->tl);
3893 unregister_netdev(tp->netdev);
c81229c9 3894 tp->rtl_ops.unload(tp);
ac718b69 3895 free_netdev(tp->netdev);
3896 }
3897}
3898
3899/* table of devices that work with this driver */
3900static struct usb_device_id rtl8152_table[] = {
662412d1 3901 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3902 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3903 {USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
ac718b69 3904 {}
3905};
3906
3907MODULE_DEVICE_TABLE(usb, rtl8152_table);
3908
3909static struct usb_driver rtl8152_driver = {
3910 .name = MODULENAME,
ebc2ec48 3911 .id_table = rtl8152_table,
ac718b69 3912 .probe = rtl8152_probe,
3913 .disconnect = rtl8152_disconnect,
ac718b69 3914 .suspend = rtl8152_suspend,
ebc2ec48 3915 .resume = rtl8152_resume,
3916 .reset_resume = rtl8152_resume,
9a4be1bd 3917 .supports_autosuspend = 1,
a634782f 3918 .disable_hub_initiated_lpm = 1,
ac718b69 3919};
3920
b4236daa 3921module_usb_driver(rtl8152_driver);
ac718b69 3922
3923MODULE_AUTHOR(DRIVER_AUTHOR);
3924MODULE_DESCRIPTION(DRIVER_DESC);
3925MODULE_LICENSE("GPL");