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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
ac718b69 | 2 | /* |
c7de7dec | 3 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 4 | */ |
5 | ||
ac718b69 | 6 | #include <linux/signal.h> |
7 | #include <linux/slab.h> | |
8 | #include <linux/module.h> | |
ac718b69 | 9 | #include <linux/netdevice.h> |
10 | #include <linux/etherdevice.h> | |
11 | #include <linux/mii.h> | |
12 | #include <linux/ethtool.h> | |
17206c11 | 13 | #include <linux/phy.h> |
ac718b69 | 14 | #include <linux/usb.h> |
15 | #include <linux/crc32.h> | |
16 | #include <linux/if_vlan.h> | |
17 | #include <linux/uaccess.h> | |
ebc2ec48 | 18 | #include <linux/list.h> |
5bd23881 | 19 | #include <linux/ip.h> |
20 | #include <linux/ipv6.h> | |
6128d1bb | 21 | #include <net/ip6_checksum.h> |
4c4a6b1b | 22 | #include <uapi/linux/mdio.h> |
23 | #include <linux/mdio.h> | |
d9a28c5b | 24 | #include <linux/usb/cdc.h> |
5ee3c60c | 25 | #include <linux/suspend.h> |
252df8b8 | 26 | #include <linux/atomic.h> |
34ee32c9 | 27 | #include <linux/acpi.h> |
9370f2d0 HW |
28 | #include <linux/firmware.h> |
29 | #include <crypto/hash.h> | |
c1aedf01 | 30 | #include <linux/usb/r8152.h> |
d457a0e3 | 31 | #include <net/gso.h> |
ac718b69 | 32 | |
d0942473 | 33 | /* Information for net-next */ |
c2198943 | 34 | #define NETNEXT_VERSION "12" |
d0942473 | 35 | |
36 | /* Information for net */ | |
cdf0b86b | 37 | #define NET_VERSION "13" |
d0942473 | 38 | |
39 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 40 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 41 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 42 | #define MODULENAME "r8152" |
43 | ||
44 | #define R8152_PHY_ID 32 | |
45 | ||
46 | #define PLA_IDR 0xc000 | |
47 | #define PLA_RCR 0xc010 | |
195aae32 | 48 | #define PLA_RCR1 0xc012 |
ac718b69 | 49 | #define PLA_RMS 0xc016 |
50 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
195aae32 | 51 | #define PLA_RXFIFO_FULL 0xc0a2 |
ac718b69 | 52 | #define PLA_RXFIFO_CTRL1 0xc0a4 |
195aae32 | 53 | #define PLA_RX_FIFO_FULL 0xc0a6 |
ac718b69 | 54 | #define PLA_RXFIFO_CTRL2 0xc0a8 |
195aae32 | 55 | #define PLA_RX_FIFO_EMPTY 0xc0aa |
65bab84c | 56 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 57 | #define PLA_FMC 0xc0b4 |
58 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 59 | #define PLA_TEREDO_CFG 0xc0bc |
65b82d69 | 60 | #define PLA_TEREDO_WAKE_BASE 0xc0c4 |
ac718b69 | 61 | #define PLA_MAR 0xcd00 |
43779f8d | 62 | #define PLA_BACKUP 0xd000 |
59c0b47a | 63 | #define PLA_BDC_CR 0xd1a0 |
43779f8d | 64 | #define PLA_TEREDO_TIMER 0xd2cc |
65 | #define PLA_REALWOW_TIMER 0xd2e8 | |
9370f2d0 | 66 | #define PLA_UPHY_TIMER 0xd388 |
13e04fbf HW |
67 | #define PLA_SUSPEND_FLAG 0xd38a |
68 | #define PLA_INDICATE_FALG 0xd38c | |
9370f2d0 HW |
69 | #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ |
70 | #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ | |
13e04fbf | 71 | #define PLA_EXTRA_STATUS 0xd398 |
195aae32 HW |
72 | #define PLA_GPHY_CTRL 0xd3ae |
73 | #define PLA_POL_GPIO_CTRL 0xdc6a | |
65b82d69 | 74 | #define PLA_EFUSE_DATA 0xdd00 |
75 | #define PLA_EFUSE_CMD 0xdd02 | |
ac718b69 | 76 | #define PLA_LEDSEL 0xdd90 |
77 | #define PLA_LED_FEATURE 0xdd92 | |
78 | #define PLA_PHYAR 0xde00 | |
43779f8d | 79 | #define PLA_BOOT_CTRL 0xe004 |
19813162 | 80 | #define PLA_LWAKE_CTRL_REG 0xe007 |
ac718b69 | 81 | #define PLA_GPHY_INTR_IMR 0xe022 |
82 | #define PLA_EEE_CR 0xe040 | |
195aae32 HW |
83 | #define PLA_EEE_TXTWSYS 0xe04c |
84 | #define PLA_EEE_TXTWSYS_2P5G 0xe058 | |
ac718b69 | 85 | #define PLA_EEEP_CR 0xe080 |
86 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 87 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
88 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
89 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
90 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 91 | #define PLA_TCR0 0xe610 |
92 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 93 | #define PLA_MTPS 0xe615 |
ac718b69 | 94 | #define PLA_TXFIFO_CTRL 0xe618 |
195aae32 | 95 | #define PLA_TXFIFO_FULL 0xe61a |
4f1d4d54 | 96 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 97 | #define PLA_CR 0xe813 |
98 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 99 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
100 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 101 | #define PLA_CONFIG5 0xe822 |
102 | #define PLA_PHY_PWR 0xe84c | |
103 | #define PLA_OOB_CTRL 0xe84f | |
104 | #define PLA_CPCR 0xe854 | |
105 | #define PLA_MISC_0 0xe858 | |
106 | #define PLA_MISC_1 0xe85a | |
107 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 108 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 109 | #define PLA_SFF_STS_7 0xe8de |
110 | #define PLA_PHYSTATUS 0xe908 | |
19813162 | 111 | #define PLA_CONFIG6 0xe90a /* CONFIG6 */ |
195aae32 | 112 | #define PLA_USB_CFG 0xe952 |
ac718b69 | 113 | #define PLA_BP_BA 0xfc26 |
114 | #define PLA_BP_0 0xfc28 | |
115 | #define PLA_BP_1 0xfc2a | |
116 | #define PLA_BP_2 0xfc2c | |
117 | #define PLA_BP_3 0xfc2e | |
118 | #define PLA_BP_4 0xfc30 | |
119 | #define PLA_BP_5 0xfc32 | |
120 | #define PLA_BP_6 0xfc34 | |
121 | #define PLA_BP_7 0xfc36 | |
43779f8d | 122 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 123 | |
65bab84c | 124 | #define USB_USB2PHY 0xb41e |
aa475d93 | 125 | #define USB_SSPHYLINK1 0xb426 |
65bab84c | 126 | #define USB_SSPHYLINK2 0xb428 |
195aae32 | 127 | #define USB_L1_CTRL 0xb45e |
43779f8d | 128 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 129 | #define USB_CSR_DUMMY1 0xb464 |
130 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 131 | #define USB_DEV_STAT 0xb808 |
65bab84c | 132 | #define USB_CONNECT_TIMER 0xcbf8 |
65b82d69 | 133 | #define USB_MSC_TIMER 0xcbfc |
65bab84c | 134 | #define USB_BURST_SIZE 0xcfc0 |
9370f2d0 HW |
135 | #define USB_FW_FIX_EN0 0xcfca |
136 | #define USB_FW_FIX_EN1 0xcfcc | |
65b82d69 | 137 | #define USB_LPM_CONFIG 0xcfd8 |
195aae32 | 138 | #define USB_ECM_OPTION 0xcfee |
9370f2d0 | 139 | #define USB_CSTMR 0xcfef /* RTL8153A */ |
195aae32 HW |
140 | #define USB_MISC_2 0xcfff |
141 | #define USB_ECM_OP 0xd26b | |
142 | #define USB_GPHY_CTRL 0xd284 | |
143 | #define USB_SPEED_OPTION 0xd32a | |
9370f2d0 HW |
144 | #define USB_FW_CTRL 0xd334 /* RTL8153B */ |
145 | #define USB_FC_TIMER 0xd340 | |
ac718b69 | 146 | #define USB_USB_CTRL 0xd406 |
147 | #define USB_PHY_CTRL 0xd408 | |
148 | #define USB_TX_AGG 0xd40a | |
149 | #define USB_RX_BUF_TH 0xd40c | |
150 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 151 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
152 | #define USB_RX_EARLY_SIZE 0xd42e | |
65b82d69 | 153 | #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ |
154 | #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ | |
ac718b69 | 155 | #define USB_TX_DMA 0xd434 |
65b82d69 | 156 | #define USB_UPT_RXDMA_OWN 0xd437 |
195aae32 | 157 | #define USB_UPHY3_MDCMDIO 0xd480 |
43779f8d | 158 | #define USB_TOLERANCE 0xd490 |
159 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 160 | #define USB_BMU_RESET 0xd4b0 |
195aae32 | 161 | #define USB_BMU_CONFIG 0xd4b4 |
65b82d69 | 162 | #define USB_U1U2_TIMER 0xd4da |
9370f2d0 | 163 | #define USB_FW_TASK 0xd4e8 /* RTL8153B */ |
195aae32 | 164 | #define USB_RX_AGGR_NUM 0xd4ee |
ac718b69 | 165 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 166 | #define USB_POWER_CUT 0xd80a |
65b82d69 | 167 | #define USB_MISC_0 0xd81a |
9c27369f | 168 | #define USB_MISC_1 0xd81f |
43779f8d | 169 | #define USB_AFE_CTRL2 0xd824 |
195aae32 | 170 | #define USB_UPHY_XTAL 0xd826 |
65b82d69 | 171 | #define USB_UPS_CFG 0xd842 |
172 | #define USB_UPS_FLAGS 0xd848 | |
9370f2d0 | 173 | #define USB_WDT1_CTRL 0xe404 |
43779f8d | 174 | #define USB_WDT11_CTRL 0xe43c |
9370f2d0 HW |
175 | #define USB_BP_BA PLA_BP_BA |
176 | #define USB_BP_0 PLA_BP_0 | |
177 | #define USB_BP_1 PLA_BP_1 | |
178 | #define USB_BP_2 PLA_BP_2 | |
179 | #define USB_BP_3 PLA_BP_3 | |
180 | #define USB_BP_4 PLA_BP_4 | |
181 | #define USB_BP_5 PLA_BP_5 | |
182 | #define USB_BP_6 PLA_BP_6 | |
183 | #define USB_BP_7 PLA_BP_7 | |
184 | #define USB_BP_EN PLA_BP_EN /* RTL8153A */ | |
185 | #define USB_BP_8 0xfc38 /* RTL8153B */ | |
65b82d69 | 186 | #define USB_BP_9 0xfc3a |
187 | #define USB_BP_10 0xfc3c | |
188 | #define USB_BP_11 0xfc3e | |
189 | #define USB_BP_12 0xfc40 | |
190 | #define USB_BP_13 0xfc42 | |
191 | #define USB_BP_14 0xfc44 | |
192 | #define USB_BP_15 0xfc46 | |
193 | #define USB_BP2_EN 0xfc48 | |
ac718b69 | 194 | |
195 | /* OCP Registers */ | |
196 | #define OCP_ALDPS_CONFIG 0x2010 | |
197 | #define OCP_EEE_CONFIG1 0x2080 | |
198 | #define OCP_EEE_CONFIG2 0x2092 | |
199 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 200 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 201 | #define OCP_EEE_AR 0xa41a |
202 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 203 | #define OCP_PHY_STATUS 0xa420 |
61b0ad6f | 204 | #define OCP_INTR_EN 0xa424 |
65b82d69 | 205 | #define OCP_NCTL_CFG 0xa42c |
43779f8d | 206 | #define OCP_POWER_CFG 0xa430 |
207 | #define OCP_EEE_CFG 0xa432 | |
208 | #define OCP_SRAM_ADDR 0xa436 | |
209 | #define OCP_SRAM_DATA 0xa438 | |
210 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 211 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 212 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 213 | #define OCP_EEE_LPABLE 0xa5d2 |
195aae32 HW |
214 | #define OCP_10GBT_CTRL 0xa5d4 |
215 | #define OCP_10GBT_STAT 0xa5d6 | |
216 | #define OCP_EEE_ADV2 0xa6d4 | |
2dd49e0f | 217 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
65b82d69 | 218 | #define OCP_PHY_PATCH_STAT 0xb800 |
219 | #define OCP_PHY_PATCH_CMD 0xb820 | |
af14288f | 220 | #define OCP_PHY_LOCK 0xb82e |
65b82d69 | 221 | #define OCP_ADC_IOFFSET 0xbcfc |
43779f8d | 222 | #define OCP_ADC_CFG 0xbc06 |
65b82d69 | 223 | #define OCP_SYSCLK_CFG 0xc416 |
43779f8d | 224 | |
225 | /* SRAM Register */ | |
65b82d69 | 226 | #define SRAM_GREEN_CFG 0x8011 |
43779f8d | 227 | #define SRAM_LPF_CFG 0x8012 |
195aae32 | 228 | #define SRAM_GPHY_FW_VER 0x801e |
43779f8d | 229 | #define SRAM_10M_AMP1 0x8080 |
230 | #define SRAM_10M_AMP2 0x8082 | |
231 | #define SRAM_IMPEDANCE 0x8084 | |
af14288f | 232 | #define SRAM_PHY_LOCK 0xb82e |
ac718b69 | 233 | |
234 | /* PLA_RCR */ | |
235 | #define RCR_AAP 0x00000001 | |
236 | #define RCR_APM 0x00000002 | |
237 | #define RCR_AM 0x00000004 | |
238 | #define RCR_AB 0x00000008 | |
239 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
195aae32 HW |
240 | #define SLOT_EN BIT(11) |
241 | ||
242 | /* PLA_RCR1 */ | |
243 | #define OUTER_VLAN BIT(7) | |
244 | #define INNER_VLAN BIT(6) | |
ac718b69 | 245 | |
246 | /* PLA_RXFIFO_CTRL0 */ | |
247 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
248 | #define RXFIFO_THR1_OOB 0x01800003 | |
249 | ||
195aae32 HW |
250 | /* PLA_RXFIFO_FULL */ |
251 | #define RXFIFO_FULL_MASK 0xfff | |
252 | ||
ac718b69 | 253 | /* PLA_RXFIFO_CTRL1 */ |
254 | #define RXFIFO_THR2_FULL 0x00000060 | |
255 | #define RXFIFO_THR2_HIGH 0x00000038 | |
256 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 257 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 258 | |
259 | /* PLA_RXFIFO_CTRL2 */ | |
260 | #define RXFIFO_THR3_FULL 0x00000078 | |
261 | #define RXFIFO_THR3_HIGH 0x00000048 | |
262 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 263 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 264 | |
265 | /* PLA_TXFIFO_CTRL */ | |
266 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 267 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 268 | |
65bab84c | 269 | /* PLA_DMY_REG0 */ |
270 | #define ECM_ALDPS 0x0002 | |
271 | ||
ac718b69 | 272 | /* PLA_FMC */ |
273 | #define FMC_FCR_MCU_EN 0x0001 | |
274 | ||
275 | /* PLA_EEEP_CR */ | |
276 | #define EEEP_CR_EEEP_TX 0x0002 | |
277 | ||
43779f8d | 278 | /* PLA_WDT6_CTRL */ |
279 | #define WDT6_SET_MODE 0x0010 | |
280 | ||
ac718b69 | 281 | /* PLA_TCR0 */ |
282 | #define TCR0_TX_EMPTY 0x0800 | |
283 | #define TCR0_AUTO_FIFO 0x0080 | |
284 | ||
285 | /* PLA_TCR1 */ | |
286 | #define VERSION_MASK 0x7cf0 | |
5133bcc7 HW |
287 | #define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) |
288 | #define IFG_144NS BIT(9) | |
289 | #define IFG_96NS (BIT(9) | BIT(8)) | |
ac718b69 | 290 | |
69b4b7a4 | 291 | /* PLA_MTPS */ |
292 | #define MTPS_JUMBO (12 * 1024 / 64) | |
293 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
294 | ||
4f1d4d54 | 295 | /* PLA_RSTTALLY */ |
296 | #define TALLY_RESET 0x0001 | |
297 | ||
ac718b69 | 298 | /* PLA_CR */ |
299 | #define CR_RST 0x10 | |
300 | #define CR_RE 0x08 | |
301 | #define CR_TE 0x04 | |
302 | ||
303 | /* PLA_CRWECR */ | |
304 | #define CRWECR_NORAML 0x00 | |
305 | #define CRWECR_CONFIG 0xc0 | |
306 | ||
307 | /* PLA_OOB_CTRL */ | |
308 | #define NOW_IS_OOB 0x80 | |
309 | #define TXFIFO_EMPTY 0x20 | |
310 | #define RXFIFO_EMPTY 0x10 | |
311 | #define LINK_LIST_READY 0x02 | |
312 | #define DIS_MCU_CLROOB 0x01 | |
313 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
314 | ||
315 | /* PLA_MISC_1 */ | |
316 | #define RXDY_GATED_EN 0x0008 | |
317 | ||
318 | /* PLA_SFF_STS_7 */ | |
319 | #define RE_INIT_LL 0x8000 | |
320 | #define MCU_BORW_EN 0x4000 | |
321 | ||
322 | /* PLA_CPCR */ | |
195aae32 | 323 | #define FLOW_CTRL_EN BIT(0) |
ac718b69 | 324 | #define CPCR_RX_VLAN 0x0040 |
325 | ||
326 | /* PLA_CFG_WOL */ | |
327 | #define MAGIC_EN 0x0001 | |
328 | ||
43779f8d | 329 | /* PLA_TEREDO_CFG */ |
330 | #define TEREDO_SEL 0x8000 | |
331 | #define TEREDO_WAKE_MASK 0x7f00 | |
332 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
333 | #define OOB_TEREDO_EN 0x0001 | |
334 | ||
59c0b47a | 335 | /* PLA_BDC_CR */ |
ac718b69 | 336 | #define ALDPS_PROXY_MODE 0x0001 |
337 | ||
65b82d69 | 338 | /* PLA_EFUSE_CMD */ |
339 | #define EFUSE_READ_CMD BIT(15) | |
340 | #define EFUSE_DATA_BIT16 BIT(7) | |
341 | ||
21ff2e89 | 342 | /* PLA_CONFIG34 */ |
343 | #define LINK_ON_WAKE_EN 0x0010 | |
344 | #define LINK_OFF_WAKE_EN 0x0008 | |
345 | ||
19813162 HW |
346 | /* PLA_CONFIG6 */ |
347 | #define LANWAKE_CLR_EN BIT(0) | |
348 | ||
195aae32 HW |
349 | /* PLA_USB_CFG */ |
350 | #define EN_XG_LIP BIT(1) | |
351 | #define EN_G_LIP BIT(2) | |
352 | ||
ac718b69 | 353 | /* PLA_CONFIG5 */ |
21ff2e89 | 354 | #define BWF_EN 0x0040 |
355 | #define MWF_EN 0x0020 | |
356 | #define UWF_EN 0x0010 | |
ac718b69 | 357 | #define LAN_WAKE_EN 0x0002 |
358 | ||
359 | /* PLA_LED_FEATURE */ | |
360 | #define LED_MODE_MASK 0x0700 | |
361 | ||
362 | /* PLA_PHY_PWR */ | |
363 | #define TX_10M_IDLE_EN 0x0080 | |
364 | #define PFM_PWM_SWITCH 0x0040 | |
d7f1b596 | 365 | #define TEST_IO_OFF BIT(4) |
ac718b69 | 366 | |
367 | /* PLA_MAC_PWR_CTRL */ | |
368 | #define D3_CLK_GATED_EN 0x00004000 | |
369 | #define MCU_CLK_RATIO 0x07010f07 | |
370 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 371 | #define ALDPS_SPDWN_RATIO 0x0f87 |
372 | ||
373 | /* PLA_MAC_PWR_CTRL2 */ | |
374 | #define EEE_SPDWN_RATIO 0x8007 | |
65b82d69 | 375 | #define MAC_CLK_SPDWN_EN BIT(15) |
195aae32 | 376 | #define EEE_SPDWN_RATIO_MASK 0xff |
43779f8d | 377 | |
378 | /* PLA_MAC_PWR_CTRL3 */ | |
08997b5e | 379 | #define PLA_MCU_SPDWN_EN BIT(14) |
43779f8d | 380 | #define PKT_AVAIL_SPDWN_EN 0x0100 |
381 | #define SUSPEND_SPDWN_EN 0x0004 | |
382 | #define U1U2_SPDWN_EN 0x0002 | |
383 | #define L1_SPDWN_EN 0x0001 | |
384 | ||
385 | /* PLA_MAC_PWR_CTRL4 */ | |
386 | #define PWRSAVE_SPDWN_EN 0x1000 | |
387 | #define RXDV_SPDWN_EN 0x0800 | |
388 | #define TX10MIDLE_EN 0x0100 | |
195aae32 | 389 | #define IDLE_SPDWN_EN BIT(6) |
43779f8d | 390 | #define TP100_SPDWN_EN 0x0020 |
391 | #define TP500_SPDWN_EN 0x0010 | |
392 | #define TP1000_SPDWN_EN 0x0008 | |
393 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 394 | |
395 | /* PLA_GPHY_INTR_IMR */ | |
396 | #define GPHY_STS_MSK 0x0001 | |
397 | #define SPEED_DOWN_MSK 0x0002 | |
398 | #define SPDWN_RXDV_MSK 0x0004 | |
399 | #define SPDWN_LINKCHG_MSK 0x0008 | |
400 | ||
401 | /* PLA_PHYAR */ | |
402 | #define PHYAR_FLAG 0x80000000 | |
403 | ||
404 | /* PLA_EEE_CR */ | |
405 | #define EEE_RX_EN 0x0001 | |
406 | #define EEE_TX_EN 0x0002 | |
407 | ||
43779f8d | 408 | /* PLA_BOOT_CTRL */ |
409 | #define AUTOLOAD_DONE 0x0002 | |
410 | ||
19813162 HW |
411 | /* PLA_LWAKE_CTRL_REG */ |
412 | #define LANWAKE_PIN BIT(7) | |
413 | ||
13e04fbf HW |
414 | /* PLA_SUSPEND_FLAG */ |
415 | #define LINK_CHG_EVENT BIT(0) | |
416 | ||
417 | /* PLA_INDICATE_FALG */ | |
418 | #define UPCOMING_RUNTIME_D3 BIT(0) | |
419 | ||
9370f2d0 HW |
420 | /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ |
421 | #define DEBUG_OE BIT(0) | |
422 | #define DEBUG_LTSSM 0x0082 | |
423 | ||
13e04fbf | 424 | /* PLA_EXTRA_STATUS */ |
a3914272 | 425 | #define CUR_LINK_OK BIT(15) |
9370f2d0 | 426 | #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ |
13e04fbf | 427 | #define LINK_CHANGE_FLAG BIT(8) |
a3914272 | 428 | #define POLL_LINK_CHG BIT(0) |
13e04fbf | 429 | |
195aae32 HW |
430 | /* PLA_GPHY_CTRL */ |
431 | #define GPHY_FLASH BIT(1) | |
432 | ||
433 | /* PLA_POL_GPIO_CTRL */ | |
434 | #define DACK_DET_EN BIT(15) | |
435 | #define POL_GPHY_PATCH BIT(4) | |
436 | ||
65bab84c | 437 | /* USB_USB2PHY */ |
438 | #define USB2PHY_SUSPEND 0x0001 | |
439 | #define USB2PHY_L1 0x0002 | |
440 | ||
aa475d93 HW |
441 | /* USB_SSPHYLINK1 */ |
442 | #define DELAY_PHY_PWR_CHG BIT(1) | |
443 | ||
65bab84c | 444 | /* USB_SSPHYLINK2 */ |
445 | #define pwd_dn_scale_mask 0x3ffe | |
446 | #define pwd_dn_scale(x) ((x) << 1) | |
447 | ||
448 | /* USB_CSR_DUMMY1 */ | |
449 | #define DYNAMIC_BURST 0x0001 | |
450 | ||
451 | /* USB_CSR_DUMMY2 */ | |
452 | #define EP4_FULL_FC 0x0001 | |
453 | ||
ac718b69 | 454 | /* USB_DEV_STAT */ |
455 | #define STAT_SPEED_MASK 0x0006 | |
456 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 457 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 458 | |
9370f2d0 HW |
459 | /* USB_FW_FIX_EN0 */ |
460 | #define FW_FIX_SUSPEND BIT(14) | |
461 | ||
462 | /* USB_FW_FIX_EN1 */ | |
463 | #define FW_IP_RESET_EN BIT(9) | |
464 | ||
65b82d69 | 465 | /* USB_LPM_CONFIG */ |
466 | #define LPM_U1U2_EN BIT(0) | |
467 | ||
ac718b69 | 468 | /* USB_TX_AGG */ |
469 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
470 | ||
471 | /* USB_RX_BUF_TH */ | |
43779f8d | 472 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 473 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 474 | #define RX_THR_SLOW 0xffff0180 |
65b82d69 | 475 | #define RX_THR_B 0x00010001 |
ac718b69 | 476 | |
477 | /* USB_TX_DMA */ | |
478 | #define TEST_MODE_DISABLE 0x00000001 | |
479 | #define TX_SIZE_ADJUST1 0x00000100 | |
480 | ||
93fe9b18 | 481 | /* USB_BMU_RESET */ |
482 | #define BMU_RESET_EP_IN 0x01 | |
483 | #define BMU_RESET_EP_OUT 0x02 | |
484 | ||
195aae32 HW |
485 | /* USB_BMU_CONFIG */ |
486 | #define ACT_ODMA BIT(1) | |
487 | ||
65b82d69 | 488 | /* USB_UPT_RXDMA_OWN */ |
489 | #define OWN_UPDATE BIT(0) | |
490 | #define OWN_CLEAR BIT(1) | |
491 | ||
9370f2d0 HW |
492 | /* USB_FW_TASK */ |
493 | #define FC_PATCH_TASK BIT(1) | |
494 | ||
195aae32 HW |
495 | /* USB_RX_AGGR_NUM */ |
496 | #define RX_AGGR_NUM_MASK 0x1ff | |
497 | ||
ac718b69 | 498 | /* USB_UPS_CTRL */ |
499 | #define POWER_CUT 0x0100 | |
500 | ||
501 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 502 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 503 | |
195aae32 HW |
504 | /* USB_ECM_OPTION */ |
505 | #define BYPASS_MAC_RESET BIT(5) | |
506 | ||
9370f2d0 HW |
507 | /* USB_CSTMR */ |
508 | #define FORCE_SUPER BIT(0) | |
509 | ||
195aae32 HW |
510 | /* USB_MISC_2 */ |
511 | #define UPS_FORCE_PWR_DOWN BIT(0) | |
512 | ||
513 | /* USB_ECM_OP */ | |
514 | #define EN_ALL_SPEED BIT(0) | |
515 | ||
516 | /* USB_GPHY_CTRL */ | |
517 | #define GPHY_PATCH_DONE BIT(2) | |
518 | #define BYPASS_FLASH BIT(5) | |
519 | #define BACKUP_RESTRORE BIT(6) | |
520 | ||
521 | /* USB_SPEED_OPTION */ | |
522 | #define RG_PWRDN_EN BIT(8) | |
523 | #define ALL_SPEED_OFF BIT(9) | |
524 | ||
9370f2d0 HW |
525 | /* USB_FW_CTRL */ |
526 | #define FLOW_CTRL_PATCH_OPT BIT(1) | |
195aae32 HW |
527 | #define AUTO_SPEEDUP BIT(3) |
528 | #define FLOW_CTRL_PATCH_2 BIT(8) | |
9370f2d0 HW |
529 | |
530 | /* USB_FC_TIMER */ | |
531 | #define CTRL_TIMER_EN BIT(15) | |
532 | ||
ac718b69 | 533 | /* USB_USB_CTRL */ |
195aae32 | 534 | #define CDC_ECM_EN BIT(3) |
ac718b69 | 535 | #define RX_AGG_DISABLE 0x0010 |
e90fba8d | 536 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 537 | |
43779f8d | 538 | /* USB_U2P3_CTRL */ |
539 | #define U2P3_ENABLE 0x0001 | |
195aae32 | 540 | #define RX_DETECT8 BIT(3) |
43779f8d | 541 | |
542 | /* USB_POWER_CUT */ | |
543 | #define PWR_EN 0x0001 | |
544 | #define PHASE2_EN 0x0008 | |
65b82d69 | 545 | #define UPS_EN BIT(4) |
546 | #define USP_PREWAKE BIT(5) | |
43779f8d | 547 | |
548 | /* USB_MISC_0 */ | |
549 | #define PCUT_STATUS 0x0001 | |
550 | ||
464ec10a | 551 | /* USB_RX_EARLY_TIMEOUT */ |
552 | #define COALESCE_SUPER 85000U | |
553 | #define COALESCE_HIGH 250000U | |
554 | #define COALESCE_SLOW 524280U | |
43779f8d | 555 | |
9370f2d0 HW |
556 | /* USB_WDT1_CTRL */ |
557 | #define WTD1_EN BIT(0) | |
558 | ||
43779f8d | 559 | /* USB_WDT11_CTRL */ |
560 | #define TIMER11_EN 0x0001 | |
561 | ||
562 | /* USB_LPM_CTRL */ | |
65bab84c | 563 | /* bit 4 ~ 5: fifo empty boundary */ |
564 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
565 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 566 | #define LPM_TIMER_MASK 0x0c |
567 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
568 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 569 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 570 | |
571 | /* USB_AFE_CTRL2 */ | |
572 | #define SEN_VAL_MASK 0xf800 | |
573 | #define SEN_VAL_NORMAL 0xa000 | |
574 | #define SEL_RXIDLE 0x0100 | |
575 | ||
195aae32 HW |
576 | /* USB_UPHY_XTAL */ |
577 | #define OOBS_POLLING BIT(8) | |
578 | ||
65b82d69 | 579 | /* USB_UPS_CFG */ |
580 | #define SAW_CNT_1MS_MASK 0x0fff | |
195aae32 | 581 | #define MID_REVERSE BIT(5) /* RTL8156A */ |
65b82d69 | 582 | |
583 | /* USB_UPS_FLAGS */ | |
584 | #define UPS_FLAGS_R_TUNE BIT(0) | |
585 | #define UPS_FLAGS_EN_10M_CKDIV BIT(1) | |
586 | #define UPS_FLAGS_250M_CKDIV BIT(2) | |
587 | #define UPS_FLAGS_EN_ALDPS BIT(3) | |
588 | #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) | |
195aae32 | 589 | #define UPS_FLAGS_SPEED_MASK (0xf << 16) |
65b82d69 | 590 | #define ups_flags_speed(x) ((x) << 16) |
591 | #define UPS_FLAGS_EN_EEE BIT(20) | |
592 | #define UPS_FLAGS_EN_500M_EEE BIT(21) | |
593 | #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) | |
0e5b36bc | 594 | #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) |
65b82d69 | 595 | #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) |
596 | #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) | |
597 | #define UPS_FLAGS_EN_GREEN BIT(26) | |
598 | #define UPS_FLAGS_EN_FLOW_CTR BIT(27) | |
599 | ||
600 | enum spd_duplex { | |
0e5b36bc | 601 | NWAY_10M_HALF, |
65b82d69 | 602 | NWAY_10M_FULL, |
603 | NWAY_100M_HALF, | |
604 | NWAY_100M_FULL, | |
605 | NWAY_1000M_FULL, | |
606 | FORCE_10M_HALF, | |
607 | FORCE_10M_FULL, | |
608 | FORCE_100M_HALF, | |
609 | FORCE_100M_FULL, | |
195aae32 HW |
610 | FORCE_1000M_FULL, |
611 | NWAY_2500M_FULL, | |
65b82d69 | 612 | }; |
613 | ||
ac718b69 | 614 | /* OCP_ALDPS_CONFIG */ |
615 | #define ENPWRSAVE 0x8000 | |
616 | #define ENPDNPS 0x0200 | |
617 | #define LINKENA 0x0100 | |
618 | #define DIS_SDSAVE 0x0010 | |
619 | ||
43779f8d | 620 | /* OCP_PHY_STATUS */ |
621 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 622 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 623 | #define PHY_STAT_LAN_ON 3 |
624 | #define PHY_STAT_PWRDN 5 | |
625 | ||
61b0ad6f HW |
626 | /* OCP_INTR_EN */ |
627 | #define INTR_SPEED_FORCE BIT(3) | |
628 | ||
65b82d69 | 629 | /* OCP_NCTL_CFG */ |
630 | #define PGA_RETURN_EN BIT(1) | |
631 | ||
43779f8d | 632 | /* OCP_POWER_CFG */ |
633 | #define EEE_CLKDIV_EN 0x8000 | |
634 | #define EN_ALDPS 0x0004 | |
635 | #define EN_10M_PLLOFF 0x0001 | |
636 | ||
ac718b69 | 637 | /* OCP_EEE_CONFIG1 */ |
638 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
639 | #define RG_MATCLR_EN 0x4000 | |
640 | #define EEE_10_CAP 0x2000 | |
641 | #define EEE_NWAY_EN 0x1000 | |
642 | #define TX_QUIET_EN 0x0200 | |
643 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 644 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 645 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 646 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
647 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
648 | ||
649 | /* OCP_EEE_CONFIG2 */ | |
650 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
651 | #define RG_DACQUIET_EN 0x0400 | |
652 | #define RG_LDVQUIET_EN 0x0200 | |
653 | #define RG_CKRSEL 0x0020 | |
654 | #define RG_EEEPRG_EN 0x0010 | |
655 | ||
656 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 657 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 658 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 659 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
660 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
661 | ||
662 | /* OCP_EEE_AR */ | |
663 | /* bit[15:14] function */ | |
664 | #define FUN_ADDR 0x0000 | |
665 | #define FUN_DATA 0x4000 | |
666 | /* bit[4:0] device addr */ | |
ac718b69 | 667 | |
43779f8d | 668 | /* OCP_EEE_CFG */ |
669 | #define CTAP_SHORT_EN 0x0040 | |
670 | #define EEE10_EN 0x0010 | |
671 | ||
672 | /* OCP_DOWN_SPEED */ | |
65b82d69 | 673 | #define EN_EEE_CMODE BIT(14) |
674 | #define EN_EEE_1000 BIT(13) | |
675 | #define EN_EEE_100 BIT(12) | |
676 | #define EN_10M_CLKDIV BIT(11) | |
43779f8d | 677 | #define EN_10M_BGOFF 0x0080 |
678 | ||
195aae32 HW |
679 | /* OCP_10GBT_CTRL */ |
680 | #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ | |
681 | ||
2dd49e0f | 682 | /* OCP_PHY_STATE */ |
683 | #define TXDIS_STATE 0x01 | |
684 | #define ABD_STATE 0x02 | |
685 | ||
65b82d69 | 686 | /* OCP_PHY_PATCH_STAT */ |
687 | #define PATCH_READY BIT(6) | |
688 | ||
689 | /* OCP_PHY_PATCH_CMD */ | |
690 | #define PATCH_REQUEST BIT(4) | |
691 | ||
af14288f HW |
692 | /* OCP_PHY_LOCK */ |
693 | #define PATCH_LOCK BIT(0) | |
694 | ||
43779f8d | 695 | /* OCP_ADC_CFG */ |
696 | #define CKADSEL_L 0x0100 | |
697 | #define ADC_EN 0x0080 | |
698 | #define EN_EMI_L 0x0040 | |
699 | ||
65b82d69 | 700 | /* OCP_SYSCLK_CFG */ |
195aae32 HW |
701 | #define sysclk_div_expo(x) (min(x, 5) << 8) |
702 | #define clk_div_expo(x) (min(x, 5) << 4) | |
65b82d69 | 703 | |
704 | /* SRAM_GREEN_CFG */ | |
705 | #define GREEN_ETH_EN BIT(15) | |
706 | #define R_TUNE_EN BIT(11) | |
707 | ||
43779f8d | 708 | /* SRAM_LPF_CFG */ |
709 | #define LPF_AUTO_TUNE 0x8000 | |
710 | ||
711 | /* SRAM_10M_AMP1 */ | |
712 | #define GDAC_IB_UPALL 0x0008 | |
713 | ||
714 | /* SRAM_10M_AMP2 */ | |
715 | #define AMP_DN 0x0200 | |
716 | ||
717 | /* SRAM_IMPEDANCE */ | |
718 | #define RX_DRIVING_MASK 0x6000 | |
719 | ||
af14288f HW |
720 | /* SRAM_PHY_LOCK */ |
721 | #define PHY_PATCH_LOCK 0x0001 | |
722 | ||
34ee32c9 ML |
723 | /* MAC PASSTHRU */ |
724 | #define AD_MASK 0xfee0 | |
9c27369f | 725 | #define BND_MASK 0x0004 |
8e29d23e | 726 | #define BD_MASK 0x0001 |
34ee32c9 ML |
727 | #define EFUSE 0xcfdb |
728 | #define PASS_THRU_MASK 0x1 | |
729 | ||
9370f2d0 HW |
730 | #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ |
731 | ||
ac718b69 | 732 | enum rtl_register_content { |
195aae32 HW |
733 | _2500bps = BIT(10), |
734 | _1250bps = BIT(9), | |
735 | _500bps = BIT(8), | |
736 | _tx_flow = BIT(6), | |
737 | _rx_flow = BIT(5), | |
43779f8d | 738 | _1000bps = 0x10, |
ac718b69 | 739 | _100bps = 0x08, |
740 | _10bps = 0x04, | |
741 | LINK_STATUS = 0x02, | |
742 | FULL_DUP = 0x01, | |
743 | }; | |
744 | ||
195aae32 HW |
745 | #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) |
746 | #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) | |
747 | ||
1764bcd9 | 748 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 749 | #define RTL8152_MAX_RX 10 |
40a82917 | 750 | #define INTBUFSIZE 2 |
8e1f51bd | 751 | #define TX_ALIGN 4 |
752 | #define RX_ALIGN 8 | |
40a82917 | 753 | |
e4a5017a | 754 | #define RTL8152_RX_MAX_PENDING 4096 |
47922fcd HW |
755 | #define RTL8152_RXFG_HEADSZ 256 |
756 | ||
40a82917 | 757 | #define INTR_LINK 0x0004 |
ebc2ec48 | 758 | |
b65c0c9b | 759 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) |
69b4b7a4 | 760 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 761 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
67ce1a80 HW |
762 | #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) |
763 | #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) | |
764 | #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) | |
ac718b69 | 765 | |
766 | /* rtl8152 flags */ | |
767 | enum rtl8152_flags { | |
715f67f3 | 768 | RTL8152_INACCESSIBLE = 0, |
ac718b69 | 769 | RTL8152_SET_RX_MODE, |
40a82917 | 770 | WORK_ENABLE, |
771 | RTL8152_LINK_CHG, | |
9a4be1bd | 772 | SELECTIVE_SUSPEND, |
aa66a5f1 | 773 | PHY_RESET, |
d2187f8e | 774 | SCHEDULE_TASKLET, |
65b82d69 | 775 | GREEN_ETHERNET, |
baf33d7a | 776 | RX_EPROTO, |
d9962b0d DA |
777 | IN_PRE_RESET, |
778 | PROBED_WITH_NO_ERRORS, | |
779 | PROBE_SHOULD_RETRY, | |
ac718b69 | 780 | }; |
781 | ||
e26c2584 | 782 | #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e |
76d7df94 | 783 | #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054 |
b4b771fd | 784 | #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082 |
f01cdcf8 | 785 | #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c |
b4b771fd | 786 | #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387 |
f01cdcf8 | 787 | #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062 |
b4b771fd | 788 | |
4f1d4d54 | 789 | struct tally_counter { |
790 | __le64 tx_packets; | |
791 | __le64 rx_packets; | |
792 | __le64 tx_errors; | |
793 | __le32 rx_errors; | |
794 | __le16 rx_missed; | |
795 | __le16 align_errors; | |
796 | __le32 tx_one_collision; | |
797 | __le32 tx_multi_collision; | |
798 | __le64 rx_unicast; | |
799 | __le64 rx_broadcast; | |
800 | __le32 rx_multicast; | |
801 | __le16 tx_aborted; | |
f37119c5 | 802 | __le16 tx_underrun; |
4f1d4d54 | 803 | }; |
804 | ||
ac718b69 | 805 | struct rx_desc { |
500b6d7e | 806 | __le32 opts1; |
ac718b69 | 807 | #define RX_LEN_MASK 0x7fff |
565cab0a | 808 | |
500b6d7e | 809 | __le32 opts2; |
f5aaaa6d | 810 | #define RD_UDP_CS BIT(23) |
811 | #define RD_TCP_CS BIT(22) | |
812 | #define RD_IPV6_CS BIT(20) | |
813 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 814 | |
500b6d7e | 815 | __le32 opts3; |
f5aaaa6d | 816 | #define IPF BIT(23) /* IP checksum fail */ |
817 | #define UDPF BIT(22) /* UDP checksum fail */ | |
818 | #define TCPF BIT(21) /* TCP checksum fail */ | |
819 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 820 | |
500b6d7e | 821 | __le32 opts4; |
822 | __le32 opts5; | |
823 | __le32 opts6; | |
ac718b69 | 824 | }; |
825 | ||
826 | struct tx_desc { | |
500b6d7e | 827 | __le32 opts1; |
f5aaaa6d | 828 | #define TX_FS BIT(31) /* First segment of a packet */ |
829 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
830 | #define GTSENDV4 BIT(28) | |
831 | #define GTSENDV6 BIT(27) | |
60c89071 | 832 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 833 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 834 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 835 | |
500b6d7e | 836 | __le32 opts2; |
f5aaaa6d | 837 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
838 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
839 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
840 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 841 | #define MSS_SHIFT 17 |
842 | #define MSS_MAX 0x7ffU | |
843 | #define TCPHO_SHIFT 17 | |
6128d1bb | 844 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 845 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 846 | }; |
847 | ||
dff4e8ad | 848 | struct r8152; |
849 | ||
ebc2ec48 | 850 | struct rx_agg { |
252df8b8 | 851 | struct list_head list, info_list; |
ebc2ec48 | 852 | struct urb *urb; |
dff4e8ad | 853 | struct r8152 *context; |
d55d7089 | 854 | struct page *page; |
ebc2ec48 | 855 | void *buffer; |
ebc2ec48 | 856 | }; |
857 | ||
858 | struct tx_agg { | |
859 | struct list_head list; | |
860 | struct urb *urb; | |
dff4e8ad | 861 | struct r8152 *context; |
ebc2ec48 | 862 | void *buffer; |
863 | void *head; | |
864 | u32 skb_num; | |
865 | u32 skb_len; | |
866 | }; | |
867 | ||
ac718b69 | 868 | struct r8152 { |
869 | unsigned long flags; | |
870 | struct usb_device *udev; | |
d823ab68 | 871 | struct napi_struct napi; |
40a82917 | 872 | struct usb_interface *intf; |
ac718b69 | 873 | struct net_device *netdev; |
40a82917 | 874 | struct urb *intr_urb; |
ebc2ec48 | 875 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
47922fcd | 876 | struct list_head rx_info, rx_used; |
ebc2ec48 | 877 | struct list_head rx_done, tx_free; |
d823ab68 | 878 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 879 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 880 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 881 | struct mii_if_info mii; |
b5403273 | 882 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 883 | #ifdef CONFIG_PM_SLEEP |
884 | struct notifier_block pm_notifier; | |
885 | #endif | |
d2187f8e | 886 | struct tasklet_struct tx_tl; |
c81229c9 | 887 | |
888 | struct rtl_ops { | |
151ea094 PM |
889 | void (*init)(struct r8152 *tp); |
890 | int (*enable)(struct r8152 *tp); | |
891 | void (*disable)(struct r8152 *tp); | |
892 | void (*up)(struct r8152 *tp); | |
893 | void (*down)(struct r8152 *tp); | |
894 | void (*unload)(struct r8152 *tp); | |
d80a5233 HK |
895 | int (*eee_get)(struct r8152 *tp, struct ethtool_keee *eee); |
896 | int (*eee_set)(struct r8152 *tp, struct ethtool_keee *eee); | |
151ea094 PM |
897 | bool (*in_nway)(struct r8152 *tp); |
898 | void (*hw_phy_cfg)(struct r8152 *tp); | |
2609af19 | 899 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
67ce1a80 | 900 | void (*change_mtu)(struct r8152 *tp); |
c81229c9 | 901 | } rtl_ops; |
902 | ||
0e5b36bc | 903 | struct ups_info { |
195aae32 | 904 | u32 r_tune:1; |
0e5b36bc HW |
905 | u32 _10m_ckdiv:1; |
906 | u32 _250m_ckdiv:1; | |
907 | u32 aldps:1; | |
908 | u32 lite_mode:2; | |
909 | u32 speed_duplex:4; | |
910 | u32 eee:1; | |
911 | u32 eee_lite:1; | |
912 | u32 eee_ckdiv:1; | |
913 | u32 eee_plloff_100:1; | |
914 | u32 eee_plloff_giga:1; | |
915 | u32 eee_cmod_lv:1; | |
916 | u32 green:1; | |
917 | u32 flow_control:1; | |
918 | u32 ctap_short_off:1; | |
919 | } ups_info; | |
920 | ||
9370f2d0 HW |
921 | #define RTL_VER_SIZE 32 |
922 | ||
923 | struct rtl_fw { | |
924 | const char *fw_name; | |
925 | const struct firmware *fw; | |
926 | ||
927 | char version[RTL_VER_SIZE]; | |
928 | int (*pre_fw)(struct r8152 *tp); | |
929 | int (*post_fw)(struct r8152 *tp); | |
930 | ||
931 | bool retry; | |
932 | } rtl_fw; | |
933 | ||
252df8b8 HW |
934 | atomic_t rx_count; |
935 | ||
f4a93be6 | 936 | bool eee_en; |
40a82917 | 937 | int intr_interval; |
21ff2e89 | 938 | u32 saved_wolopts; |
ac718b69 | 939 | u32 msg_enable; |
dd1b119c | 940 | u32 tx_qlen; |
464ec10a | 941 | u32 coalesce; |
771efeda | 942 | u32 advertising; |
ec5791c2 | 943 | u32 rx_buf_sz; |
e4a5017a HW |
944 | u32 rx_copybreak; |
945 | u32 rx_pending; | |
195aae32 | 946 | u32 fc_pause_on, fc_pause_off; |
e4a5017a | 947 | |
b67fda9a HW |
948 | unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; |
949 | ||
195aae32 | 950 | u32 support_2500full:1; |
9c68011b HW |
951 | u32 lenovo_macpassthru:1; |
952 | u32 dell_tb_rx_agg_bug:1; | |
ac718b69 | 953 | u16 ocp_base; |
aa7e26b6 | 954 | u16 speed; |
f4a93be6 | 955 | u16 eee_adv; |
40a82917 | 956 | u8 *intr_buff; |
ac718b69 | 957 | u8 version; |
aa7e26b6 | 958 | u8 duplex; |
959 | u8 autoneg; | |
d9962b0d DA |
960 | |
961 | unsigned int reg_access_reset_count; | |
ac718b69 | 962 | }; |
963 | ||
9370f2d0 HW |
964 | /** |
965 | * struct fw_block - block type and total length | |
966 | * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA, | |
967 | * RTL_FW_USB and so on. | |
968 | * @length: total length of the current block. | |
969 | */ | |
970 | struct fw_block { | |
971 | __le32 type; | |
972 | __le32 length; | |
973 | } __packed; | |
974 | ||
975 | /** | |
976 | * struct fw_header - header of the firmware file | |
977 | * @checksum: checksum of sha256 which is calculated from the whole file | |
978 | * except the checksum field of the file. That is, calculate sha256 | |
979 | * from the version field to the end of the file. | |
980 | * @version: version of this firmware. | |
981 | * @blocks: the first firmware block of the file | |
982 | */ | |
983 | struct fw_header { | |
984 | u8 checksum[32]; | |
985 | char version[RTL_VER_SIZE]; | |
ee3bc9c2 | 986 | struct fw_block blocks[]; |
9370f2d0 HW |
987 | } __packed; |
988 | ||
a8a7be17 HW |
989 | enum rtl8152_fw_flags { |
990 | FW_FLAGS_USB = 0, | |
991 | FW_FLAGS_PLA, | |
992 | FW_FLAGS_START, | |
993 | FW_FLAGS_STOP, | |
994 | FW_FLAGS_NC, | |
4a51b0e8 HW |
995 | FW_FLAGS_NC1, |
996 | FW_FLAGS_NC2, | |
997 | FW_FLAGS_UC2, | |
998 | FW_FLAGS_UC, | |
999 | FW_FLAGS_SPEED_UP, | |
1000 | FW_FLAGS_VER, | |
a8a7be17 HW |
1001 | }; |
1002 | ||
4a51b0e8 HW |
1003 | enum rtl8152_fw_fixup_cmd { |
1004 | FW_FIXUP_AND = 0, | |
1005 | FW_FIXUP_OR, | |
1006 | FW_FIXUP_NOT, | |
1007 | FW_FIXUP_XOR, | |
1008 | }; | |
1009 | ||
1010 | struct fw_phy_set { | |
1011 | __le16 addr; | |
1012 | __le16 data; | |
1013 | } __packed; | |
1014 | ||
1015 | struct fw_phy_speed_up { | |
1016 | struct fw_block blk_hdr; | |
1017 | __le16 fw_offset; | |
1018 | __le16 version; | |
1019 | __le16 fw_reg; | |
1020 | __le16 reserved; | |
1021 | char info[]; | |
1022 | } __packed; | |
1023 | ||
1024 | struct fw_phy_ver { | |
1025 | struct fw_block blk_hdr; | |
1026 | struct fw_phy_set ver; | |
1027 | __le32 reserved; | |
1028 | } __packed; | |
1029 | ||
1030 | struct fw_phy_fixup { | |
1031 | struct fw_block blk_hdr; | |
1032 | struct fw_phy_set setting; | |
1033 | __le16 bit_cmd; | |
1034 | __le16 reserved; | |
1035 | } __packed; | |
1036 | ||
1037 | struct fw_phy_union { | |
1038 | struct fw_block blk_hdr; | |
1039 | __le16 fw_offset; | |
1040 | __le16 fw_reg; | |
1041 | struct fw_phy_set pre_set[2]; | |
1042 | struct fw_phy_set bp[8]; | |
1043 | struct fw_phy_set bp_en; | |
1044 | u8 pre_num; | |
1045 | u8 bp_num; | |
1046 | char info[]; | |
1047 | } __packed; | |
1048 | ||
9370f2d0 | 1049 | /** |
a66edaaf | 1050 | * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. |
9370f2d0 | 1051 | * The layout of the firmware block is: |
a66edaaf | 1052 | * <struct fw_mac> + <info> + <firmware data>. |
34e653ef | 1053 | * @blk_hdr: firmware descriptor (type, length) |
9370f2d0 | 1054 | * @fw_offset: offset of the firmware binary data. The start address of |
a66edaaf | 1055 | * the data would be the address of struct fw_mac + @fw_offset. |
9370f2d0 HW |
1056 | * @fw_reg: the register to load the firmware. Depends on chip. |
1057 | * @bp_ba_addr: the register to write break point base address. Depends on | |
1058 | * chip. | |
1059 | * @bp_ba_value: break point base address. Depends on chip. | |
1060 | * @bp_en_addr: the register to write break point enabled mask. Depends | |
1061 | * on chip. | |
1062 | * @bp_en_value: break point enabled mask. Depends on the firmware. | |
1063 | * @bp_start: the start register of break points. Depends on chip. | |
1064 | * @bp_num: the break point number which needs to be set for this firmware. | |
1065 | * Depends on the firmware. | |
1066 | * @bp: break points. Depends on firmware. | |
34e653ef | 1067 | * @reserved: reserved space (unused) |
9370f2d0 HW |
1068 | * @fw_ver_reg: the register to store the fw version. |
1069 | * @fw_ver_data: the firmware version of the current type. | |
1070 | * @info: additional information for debugging, and is followed by the | |
1071 | * binary data of firmware. | |
1072 | */ | |
a66edaaf | 1073 | struct fw_mac { |
9370f2d0 HW |
1074 | struct fw_block blk_hdr; |
1075 | __le16 fw_offset; | |
1076 | __le16 fw_reg; | |
1077 | __le16 bp_ba_addr; | |
1078 | __le16 bp_ba_value; | |
1079 | __le16 bp_en_addr; | |
1080 | __le16 bp_en_value; | |
1081 | __le16 bp_start; | |
1082 | __le16 bp_num; | |
1083 | __le16 bp[16]; /* any value determined by firmware */ | |
1084 | __le32 reserved; | |
1085 | __le16 fw_ver_reg; | |
1086 | u8 fw_ver_data; | |
ee3bc9c2 | 1087 | char info[]; |
9370f2d0 HW |
1088 | } __packed; |
1089 | ||
af14288f HW |
1090 | /** |
1091 | * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. | |
1092 | * This is used to set patch key when loading the firmware of PHY. | |
34e653ef | 1093 | * @blk_hdr: firmware descriptor (type, length) |
af14288f HW |
1094 | * @key_reg: the register to write the patch key. |
1095 | * @key_data: patch key. | |
34e653ef | 1096 | * @reserved: reserved space (unused) |
af14288f HW |
1097 | */ |
1098 | struct fw_phy_patch_key { | |
1099 | struct fw_block blk_hdr; | |
1100 | __le16 key_reg; | |
1101 | __le16 key_data; | |
1102 | __le32 reserved; | |
1103 | } __packed; | |
1104 | ||
1105 | /** | |
1106 | * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. | |
1107 | * The layout of the firmware block is: | |
1108 | * <struct fw_phy_nc> + <info> + <firmware data>. | |
34e653ef | 1109 | * @blk_hdr: firmware descriptor (type, length) |
af14288f HW |
1110 | * @fw_offset: offset of the firmware binary data. The start address of |
1111 | * the data would be the address of struct fw_phy_nc + @fw_offset. | |
1112 | * @fw_reg: the register to load the firmware. Depends on chip. | |
1113 | * @ba_reg: the register to write the base address. Depends on chip. | |
1114 | * @ba_data: base address. Depends on chip. | |
1115 | * @patch_en_addr: the register of enabling patch mode. Depends on chip. | |
1116 | * @patch_en_value: patch mode enabled mask. Depends on the firmware. | |
1117 | * @mode_reg: the regitster of switching the mode. | |
9f07814d LJ |
1118 | * @mode_pre: the mode needing to be set before loading the firmware. |
1119 | * @mode_post: the mode to be set when finishing to load the firmware. | |
34e653ef | 1120 | * @reserved: reserved space (unused) |
af14288f HW |
1121 | * @bp_start: the start register of break points. Depends on chip. |
1122 | * @bp_num: the break point number which needs to be set for this firmware. | |
1123 | * Depends on the firmware. | |
1124 | * @bp: break points. Depends on firmware. | |
1125 | * @info: additional information for debugging, and is followed by the | |
1126 | * binary data of firmware. | |
1127 | */ | |
1128 | struct fw_phy_nc { | |
1129 | struct fw_block blk_hdr; | |
1130 | __le16 fw_offset; | |
1131 | __le16 fw_reg; | |
1132 | __le16 ba_reg; | |
1133 | __le16 ba_data; | |
1134 | __le16 patch_en_addr; | |
1135 | __le16 patch_en_value; | |
1136 | __le16 mode_reg; | |
1137 | __le16 mode_pre; | |
1138 | __le16 mode_post; | |
1139 | __le16 reserved; | |
1140 | __le16 bp_start; | |
1141 | __le16 bp_num; | |
1142 | __le16 bp[4]; | |
ee3bc9c2 | 1143 | char info[]; |
af14288f HW |
1144 | } __packed; |
1145 | ||
9370f2d0 HW |
1146 | enum rtl_fw_type { |
1147 | RTL_FW_END = 0, | |
1148 | RTL_FW_PLA, | |
1149 | RTL_FW_USB, | |
af14288f HW |
1150 | RTL_FW_PHY_START, |
1151 | RTL_FW_PHY_STOP, | |
1152 | RTL_FW_PHY_NC, | |
4a51b0e8 HW |
1153 | RTL_FW_PHY_FIXUP, |
1154 | RTL_FW_PHY_UNION_NC, | |
1155 | RTL_FW_PHY_UNION_NC1, | |
1156 | RTL_FW_PHY_UNION_NC2, | |
1157 | RTL_FW_PHY_UNION_UC2, | |
1158 | RTL_FW_PHY_UNION_UC, | |
1159 | RTL_FW_PHY_UNION_MISC, | |
1160 | RTL_FW_PHY_SPEED_UP, | |
1161 | RTL_FW_PHY_VER, | |
9370f2d0 HW |
1162 | }; |
1163 | ||
ac718b69 | 1164 | enum rtl_version { |
1165 | RTL_VER_UNKNOWN = 0, | |
1166 | RTL_VER_01, | |
43779f8d | 1167 | RTL_VER_02, |
1168 | RTL_VER_03, | |
1169 | RTL_VER_04, | |
1170 | RTL_VER_05, | |
fb02eb4a | 1171 | RTL_VER_06, |
c27b32c2 | 1172 | RTL_VER_07, |
65b82d69 | 1173 | RTL_VER_08, |
1174 | RTL_VER_09, | |
195aae32 HW |
1175 | |
1176 | RTL_TEST_01, | |
1177 | RTL_VER_10, | |
1178 | RTL_VER_11, | |
1179 | RTL_VER_12, | |
1180 | RTL_VER_13, | |
1181 | RTL_VER_14, | |
1182 | RTL_VER_15, | |
1183 | ||
43779f8d | 1184 | RTL_VER_MAX |
ac718b69 | 1185 | }; |
1186 | ||
60c89071 | 1187 | enum tx_csum_stat { |
1188 | TX_CSUM_SUCCESS = 0, | |
1189 | TX_CSUM_TSO, | |
1190 | TX_CSUM_NONE | |
1191 | }; | |
1192 | ||
771efeda HW |
1193 | #define RTL_ADVERTISED_10_HALF BIT(0) |
1194 | #define RTL_ADVERTISED_10_FULL BIT(1) | |
1195 | #define RTL_ADVERTISED_100_HALF BIT(2) | |
1196 | #define RTL_ADVERTISED_100_FULL BIT(3) | |
1197 | #define RTL_ADVERTISED_1000_HALF BIT(4) | |
1198 | #define RTL_ADVERTISED_1000_FULL BIT(5) | |
195aae32 | 1199 | #define RTL_ADVERTISED_2500_FULL BIT(6) |
771efeda | 1200 | |
ac718b69 | 1201 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
1202 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
1203 | */ | |
1204 | static const int multicast_filter_limit = 32; | |
52aec126 | 1205 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 1206 | |
67ce1a80 | 1207 | #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) |
60c89071 | 1208 | |
d9962b0d DA |
1209 | /* If register access fails then we block access and issue a reset. If this |
1210 | * happens too many times in a row without a successful access then we stop | |
1211 | * trying to reset and just leave access blocked. | |
1212 | */ | |
1213 | #define REGISTER_ACCESS_MAX_RESETS 3 | |
1214 | ||
1215 | static void rtl_set_inaccessible(struct r8152 *tp) | |
1216 | { | |
1217 | set_bit(RTL8152_INACCESSIBLE, &tp->flags); | |
1218 | smp_mb__after_atomic(); | |
1219 | } | |
1220 | ||
1221 | static void rtl_set_accessible(struct r8152 *tp) | |
1222 | { | |
1223 | clear_bit(RTL8152_INACCESSIBLE, &tp->flags); | |
1224 | smp_mb__after_atomic(); | |
1225 | } | |
1226 | ||
1227 | static | |
1228 | int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request, | |
1229 | __u8 requesttype, __u16 value, __u16 index, void *data, | |
1230 | __u16 size, const char *msg_tag) | |
1231 | { | |
1232 | struct usb_device *udev = tp->udev; | |
1233 | int ret; | |
1234 | ||
1235 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) | |
1236 | return -ENODEV; | |
1237 | ||
1238 | ret = usb_control_msg(udev, pipe, request, requesttype, | |
1239 | value, index, data, size, | |
1240 | USB_CTRL_GET_TIMEOUT); | |
1241 | ||
1242 | /* No need to issue a reset to report an error if the USB device got | |
1243 | * unplugged; just return immediately. | |
1244 | */ | |
1245 | if (ret == -ENODEV) | |
1246 | return ret; | |
1247 | ||
1248 | /* If the write was successful then we're done */ | |
1249 | if (ret >= 0) { | |
1250 | tp->reg_access_reset_count = 0; | |
1251 | return ret; | |
1252 | } | |
1253 | ||
1254 | dev_err(&udev->dev, | |
1255 | "Failed to %s %d bytes at %#06x/%#06x (%d)\n", | |
1256 | msg_tag, size, value, index, ret); | |
1257 | ||
1258 | /* Block all future register access until we reset. Much of the code | |
1259 | * in the driver doesn't check for errors. Notably, many parts of the | |
1260 | * driver do a read/modify/write of a register value without | |
1261 | * confirming that the read succeeded. Writing back modified garbage | |
1262 | * like this can fully wedge the adapter, requiring a power cycle. | |
1263 | */ | |
1264 | rtl_set_inaccessible(tp); | |
1265 | ||
1266 | /* If probe hasn't yet finished, then we'll request a retry of the | |
1267 | * whole probe routine if we get any control transfer errors. We | |
1268 | * never have to clear this bit since we free/reallocate the whole "tp" | |
1269 | * structure if we retry probe. | |
1270 | */ | |
1271 | if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) { | |
1272 | set_bit(PROBE_SHOULD_RETRY, &tp->flags); | |
1273 | return ret; | |
1274 | } | |
1275 | ||
1276 | /* Failing to access registers in pre-reset is not surprising since we | |
1277 | * wouldn't be resetting if things were behaving normally. The register | |
1278 | * access we do in pre-reset isn't truly mandatory--we're just reusing | |
1279 | * the disable() function and trying to be nice by powering the | |
1280 | * adapter down before resetting it. Thus, if we're in pre-reset, | |
1281 | * we'll return right away and not try to queue up yet another reset. | |
1282 | * We know the post-reset is already coming. | |
1283 | */ | |
1284 | if (test_bit(IN_PRE_RESET, &tp->flags)) | |
1285 | return ret; | |
1286 | ||
1287 | if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) { | |
1288 | usb_queue_reset_device(tp->intf); | |
1289 | tp->reg_access_reset_count++; | |
1290 | } else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) { | |
1291 | dev_err(&udev->dev, | |
1292 | "Tried to reset %d times; giving up.\n", | |
1293 | REGISTER_ACCESS_MAX_RESETS); | |
1294 | } | |
1295 | ||
1296 | return ret; | |
1297 | } | |
1298 | ||
ac718b69 | 1299 | static |
1300 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
1301 | { | |
31787f53 | 1302 | int ret; |
1303 | void *tmp; | |
1304 | ||
1305 | tmp = kmalloc(size, GFP_KERNEL); | |
1306 | if (!tmp) | |
1307 | return -ENOMEM; | |
1308 | ||
d9962b0d DA |
1309 | ret = r8152_control_msg(tp, tp->pipe_ctrl_in, |
1310 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
1311 | value, index, tmp, size, "read"); | |
1312 | ||
f53a7ad1 PM |
1313 | if (ret < 0) |
1314 | memset(data, 0xff, size); | |
1315 | else | |
1316 | memcpy(data, tmp, size); | |
31787f53 | 1317 | |
31787f53 | 1318 | kfree(tmp); |
1319 | ||
1320 | return ret; | |
ac718b69 | 1321 | } |
1322 | ||
1323 | static | |
1324 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
1325 | { | |
31787f53 | 1326 | int ret; |
1327 | void *tmp; | |
1328 | ||
c4438f03 | 1329 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 1330 | if (!tmp) |
1331 | return -ENOMEM; | |
1332 | ||
d9962b0d DA |
1333 | ret = r8152_control_msg(tp, tp->pipe_ctrl_out, |
1334 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, | |
1335 | value, index, tmp, size, "write"); | |
31787f53 | 1336 | |
1337 | kfree(tmp); | |
db8515ef | 1338 | |
31787f53 | 1339 | return ret; |
ac718b69 | 1340 | } |
1341 | ||
ffa9fec3 HW |
1342 | static void rtl_set_unplug(struct r8152 *tp) |
1343 | { | |
d9962b0d DA |
1344 | if (tp->udev->state == USB_STATE_NOTATTACHED) |
1345 | rtl_set_inaccessible(tp); | |
ffa9fec3 HW |
1346 | } |
1347 | ||
ac718b69 | 1348 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, |
b209af99 | 1349 | void *data, u16 type) |
ac718b69 | 1350 | { |
45f4a19f | 1351 | u16 limit = 64; |
1352 | int ret = 0; | |
ac718b69 | 1353 | |
715f67f3 | 1354 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
ac718b69 | 1355 | return -ENODEV; |
1356 | ||
1357 | /* both size and indix must be 4 bytes align */ | |
1358 | if ((size & 3) || !size || (index & 3) || !data) | |
1359 | return -EPERM; | |
1360 | ||
1361 | if ((u32)index + (u32)size > 0xffff) | |
1362 | return -EPERM; | |
1363 | ||
1364 | while (size) { | |
1365 | if (size > limit) { | |
1366 | ret = get_registers(tp, index, type, limit, data); | |
1367 | if (ret < 0) | |
1368 | break; | |
1369 | ||
1370 | index += limit; | |
1371 | data += limit; | |
1372 | size -= limit; | |
1373 | } else { | |
1374 | ret = get_registers(tp, index, type, size, data); | |
1375 | if (ret < 0) | |
1376 | break; | |
1377 | ||
1378 | index += size; | |
1379 | data += size; | |
1380 | size = 0; | |
1381 | break; | |
1382 | } | |
1383 | } | |
1384 | ||
67610496 | 1385 | if (ret == -ENODEV) |
ffa9fec3 | 1386 | rtl_set_unplug(tp); |
67610496 | 1387 | |
ac718b69 | 1388 | return ret; |
1389 | } | |
1390 | ||
1391 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 1392 | u16 size, void *data, u16 type) |
ac718b69 | 1393 | { |
45f4a19f | 1394 | int ret; |
1395 | u16 byteen_start, byteen_end, byen; | |
1396 | u16 limit = 512; | |
ac718b69 | 1397 | |
715f67f3 | 1398 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
ac718b69 | 1399 | return -ENODEV; |
1400 | ||
1401 | /* both size and indix must be 4 bytes align */ | |
1402 | if ((size & 3) || !size || (index & 3) || !data) | |
1403 | return -EPERM; | |
1404 | ||
1405 | if ((u32)index + (u32)size > 0xffff) | |
1406 | return -EPERM; | |
1407 | ||
1408 | byteen_start = byteen & BYTE_EN_START_MASK; | |
1409 | byteen_end = byteen & BYTE_EN_END_MASK; | |
1410 | ||
1411 | byen = byteen_start | (byteen_start << 4); | |
ac718b69 | 1412 | |
57df0fb9 HW |
1413 | /* Split the first DWORD if the byte_en is not 0xff */ |
1414 | if (byen != BYTE_EN_DWORD) { | |
1415 | ret = set_registers(tp, index, type | byen, 4, data); | |
1416 | if (ret < 0) | |
1417 | goto error1; | |
ac718b69 | 1418 | |
57df0fb9 HW |
1419 | index += 4; |
1420 | data += 4; | |
ac718b69 | 1421 | size -= 4; |
57df0fb9 HW |
1422 | } |
1423 | ||
1424 | if (size) { | |
1425 | byen = byteen_end | (byteen_end >> 4); | |
1426 | ||
1427 | /* Split the last DWORD if the byte_en is not 0xff */ | |
1428 | if (byen != BYTE_EN_DWORD) | |
1429 | size -= 4; | |
ac718b69 | 1430 | |
1431 | while (size) { | |
1432 | if (size > limit) { | |
1433 | ret = set_registers(tp, index, | |
b209af99 | 1434 | type | BYTE_EN_DWORD, |
1435 | limit, data); | |
ac718b69 | 1436 | if (ret < 0) |
1437 | goto error1; | |
1438 | ||
1439 | index += limit; | |
1440 | data += limit; | |
1441 | size -= limit; | |
1442 | } else { | |
1443 | ret = set_registers(tp, index, | |
b209af99 | 1444 | type | BYTE_EN_DWORD, |
1445 | size, data); | |
ac718b69 | 1446 | if (ret < 0) |
1447 | goto error1; | |
1448 | ||
1449 | index += size; | |
1450 | data += size; | |
1451 | size = 0; | |
1452 | break; | |
1453 | } | |
1454 | } | |
1455 | ||
57df0fb9 HW |
1456 | /* Set the last DWORD */ |
1457 | if (byen != BYTE_EN_DWORD) | |
1458 | ret = set_registers(tp, index, type | byen, 4, data); | |
ac718b69 | 1459 | } |
1460 | ||
1461 | error1: | |
67610496 | 1462 | if (ret == -ENODEV) |
ffa9fec3 | 1463 | rtl_set_unplug(tp); |
67610496 | 1464 | |
ac718b69 | 1465 | return ret; |
1466 | } | |
1467 | ||
1468 | static inline | |
1469 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
1470 | { | |
1471 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
1472 | } | |
1473 | ||
1474 | static inline | |
1475 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
1476 | { | |
1477 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
1478 | } | |
1479 | ||
ac718b69 | 1480 | static inline |
1481 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
1482 | { | |
1483 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
1484 | } | |
1485 | ||
1486 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
1487 | { | |
c8826de8 | 1488 | __le32 data; |
ac718b69 | 1489 | |
c8826de8 | 1490 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 1491 | |
1492 | return __le32_to_cpu(data); | |
1493 | } | |
1494 | ||
1495 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1496 | { | |
c8826de8 | 1497 | __le32 tmp = __cpu_to_le32(data); |
1498 | ||
1499 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 1500 | } |
1501 | ||
1502 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
1503 | { | |
1504 | u32 data; | |
c8826de8 | 1505 | __le32 tmp; |
d8fbd274 | 1506 | u16 byen = BYTE_EN_WORD; |
ac718b69 | 1507 | u8 shift = index & 2; |
1508 | ||
1509 | index &= ~3; | |
d8fbd274 | 1510 | byen <<= shift; |
ac718b69 | 1511 | |
d8fbd274 | 1512 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); |
ac718b69 | 1513 | |
c8826de8 | 1514 | data = __le32_to_cpu(tmp); |
ac718b69 | 1515 | data >>= (shift * 8); |
1516 | data &= 0xffff; | |
1517 | ||
1518 | return (u16)data; | |
1519 | } | |
1520 | ||
1521 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1522 | { | |
c8826de8 | 1523 | u32 mask = 0xffff; |
1524 | __le32 tmp; | |
ac718b69 | 1525 | u16 byen = BYTE_EN_WORD; |
1526 | u8 shift = index & 2; | |
1527 | ||
1528 | data &= mask; | |
1529 | ||
1530 | if (index & 2) { | |
1531 | byen <<= shift; | |
1532 | mask <<= (shift * 8); | |
1533 | data <<= (shift * 8); | |
1534 | index &= ~3; | |
1535 | } | |
1536 | ||
c8826de8 | 1537 | tmp = __cpu_to_le32(data); |
ac718b69 | 1538 | |
c8826de8 | 1539 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1540 | } |
1541 | ||
1542 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
1543 | { | |
1544 | u32 data; | |
c8826de8 | 1545 | __le32 tmp; |
ac718b69 | 1546 | u8 shift = index & 3; |
1547 | ||
1548 | index &= ~3; | |
1549 | ||
c8826de8 | 1550 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 1551 | |
c8826de8 | 1552 | data = __le32_to_cpu(tmp); |
ac718b69 | 1553 | data >>= (shift * 8); |
1554 | data &= 0xff; | |
1555 | ||
1556 | return (u8)data; | |
1557 | } | |
1558 | ||
1559 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1560 | { | |
c8826de8 | 1561 | u32 mask = 0xff; |
1562 | __le32 tmp; | |
ac718b69 | 1563 | u16 byen = BYTE_EN_BYTE; |
1564 | u8 shift = index & 3; | |
1565 | ||
1566 | data &= mask; | |
1567 | ||
1568 | if (index & 3) { | |
1569 | byen <<= shift; | |
1570 | mask <<= (shift * 8); | |
1571 | data <<= (shift * 8); | |
1572 | index &= ~3; | |
1573 | } | |
1574 | ||
c8826de8 | 1575 | tmp = __cpu_to_le32(data); |
ac718b69 | 1576 | |
c8826de8 | 1577 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1578 | } |
1579 | ||
ac244d3e | 1580 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 1581 | { |
1582 | u16 ocp_base, ocp_index; | |
1583 | ||
1584 | ocp_base = addr & 0xf000; | |
1585 | if (ocp_base != tp->ocp_base) { | |
1586 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1587 | tp->ocp_base = ocp_base; | |
1588 | } | |
1589 | ||
1590 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 1591 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 1592 | } |
1593 | ||
ac244d3e | 1594 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 1595 | { |
ac244d3e | 1596 | u16 ocp_base, ocp_index; |
ac718b69 | 1597 | |
ac244d3e | 1598 | ocp_base = addr & 0xf000; |
1599 | if (ocp_base != tp->ocp_base) { | |
1600 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1601 | tp->ocp_base = ocp_base; | |
ac718b69 | 1602 | } |
ac244d3e | 1603 | |
1604 | ocp_index = (addr & 0x0fff) | 0xb000; | |
1605 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 1606 | } |
1607 | ||
ac244d3e | 1608 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 1609 | { |
ac244d3e | 1610 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
1611 | } | |
ac718b69 | 1612 | |
ac244d3e | 1613 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
1614 | { | |
1615 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 1616 | } |
1617 | ||
43779f8d | 1618 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
1619 | { | |
1620 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1621 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
1622 | } | |
1623 | ||
65b82d69 | 1624 | static u16 sram_read(struct r8152 *tp, u16 addr) |
1625 | { | |
1626 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1627 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
1628 | } | |
1629 | ||
ac718b69 | 1630 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
1631 | { | |
1632 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 1633 | int ret; |
ac718b69 | 1634 | |
715f67f3 | 1635 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 1636 | return -ENODEV; |
1637 | ||
ac718b69 | 1638 | if (phy_id != R8152_PHY_ID) |
1639 | return -EINVAL; | |
1640 | ||
9a4be1bd | 1641 | ret = r8152_mdio_read(tp, reg); |
1642 | ||
9a4be1bd | 1643 | return ret; |
ac718b69 | 1644 | } |
1645 | ||
1646 | static | |
1647 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1648 | { | |
1649 | struct r8152 *tp = netdev_priv(netdev); | |
1650 | ||
715f67f3 | 1651 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 1652 | return; |
1653 | ||
ac718b69 | 1654 | if (phy_id != R8152_PHY_ID) |
1655 | return; | |
1656 | ||
1657 | r8152_mdio_write(tp, reg, val); | |
1658 | } | |
1659 | ||
b209af99 | 1660 | static int |
1661 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1662 | |
80fd850b HW |
1663 | static int |
1664 | rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, | |
1665 | u32 advertising); | |
1666 | ||
776ac63a TI |
1667 | static int __rtl8152_set_mac_address(struct net_device *netdev, void *p, |
1668 | bool in_resume) | |
8ba789ab | 1669 | { |
1670 | struct r8152 *tp = netdev_priv(netdev); | |
1671 | struct sockaddr *addr = p; | |
ea6a7112 | 1672 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1673 | |
1674 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1675 | goto out1; |
1676 | ||
776ac63a TI |
1677 | if (!in_resume) { |
1678 | ret = usb_autopm_get_interface(tp->intf); | |
1679 | if (ret < 0) | |
1680 | goto out1; | |
1681 | } | |
8ba789ab | 1682 | |
b5403273 | 1683 | mutex_lock(&tp->control); |
1684 | ||
49ed8dde | 1685 | eth_hw_addr_set(netdev, addr->sa_data); |
8ba789ab | 1686 | |
1687 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1688 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1689 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1690 | ||
b5403273 | 1691 | mutex_unlock(&tp->control); |
1692 | ||
776ac63a TI |
1693 | if (!in_resume) |
1694 | usb_autopm_put_interface(tp->intf); | |
ea6a7112 | 1695 | out1: |
1696 | return ret; | |
8ba789ab | 1697 | } |
1698 | ||
776ac63a TI |
1699 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1700 | { | |
1701 | return __rtl8152_set_mac_address(netdev, p, false); | |
1702 | } | |
1703 | ||
9c27369f | 1704 | /* Devices containing proper chips can support a persistent |
34ee32c9 ML |
1705 | * host system provided MAC address. |
1706 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1707 | */ | |
1708 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1709 | { | |
1710 | acpi_status status; | |
1711 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1712 | union acpi_object *obj; | |
1713 | int ret = -EINVAL; | |
1714 | u32 ocp_data; | |
1715 | unsigned char buf[6]; | |
9647722b KHF |
1716 | char *mac_obj_name; |
1717 | acpi_object_type mac_obj_type; | |
1718 | int mac_strlen; | |
1719 | ||
9c68011b | 1720 | if (tp->lenovo_macpassthru) { |
9647722b KHF |
1721 | mac_obj_name = "\\MACA"; |
1722 | mac_obj_type = ACPI_TYPE_STRING; | |
1723 | mac_strlen = 0x16; | |
9c27369f | 1724 | } else { |
9647722b KHF |
1725 | /* test for -AD variant of RTL8153 */ |
1726 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1727 | if ((ocp_data & AD_MASK) == 0x1000) { | |
1728 | /* test for MAC address pass-through bit */ | |
1729 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1730 | if ((ocp_data & PASS_THRU_MASK) != 1) { | |
1731 | netif_dbg(tp, probe, tp->netdev, | |
1732 | "No efuse for RTL8153-AD MAC pass through\n"); | |
1733 | return -ENODEV; | |
1734 | } | |
1735 | } else { | |
1736 | /* test for RTL8153-BND and RTL8153-BD */ | |
1737 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); | |
1738 | if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { | |
1739 | netif_dbg(tp, probe, tp->netdev, | |
1740 | "Invalid variant for MAC pass through\n"); | |
1741 | return -ENODEV; | |
1742 | } | |
9c27369f | 1743 | } |
9647722b KHF |
1744 | |
1745 | mac_obj_name = "\\_SB.AMAC"; | |
1746 | mac_obj_type = ACPI_TYPE_BUFFER; | |
1747 | mac_strlen = 0x17; | |
9c27369f | 1748 | } |
34ee32c9 ML |
1749 | |
1750 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
9647722b | 1751 | status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); |
34ee32c9 ML |
1752 | obj = (union acpi_object *)buffer.pointer; |
1753 | if (!ACPI_SUCCESS(status)) | |
1754 | return -ENODEV; | |
9647722b | 1755 | if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { |
34ee32c9 | 1756 | netif_warn(tp, probe, tp->netdev, |
53700f0c | 1757 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1758 | obj->type, obj->string.length); |
1759 | goto amacout; | |
1760 | } | |
9647722b | 1761 | |
34ee32c9 ML |
1762 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || |
1763 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1764 | netif_warn(tp, probe, tp->netdev, | |
1765 | "Invalid header when reading pass-thru MAC addr\n"); | |
1766 | goto amacout; | |
1767 | } | |
1768 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1769 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1770 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1771 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1772 | ret, buf); | |
34ee32c9 ML |
1773 | ret = -EINVAL; |
1774 | goto amacout; | |
1775 | } | |
1776 | memcpy(sa->sa_data, buf, 6); | |
cb6cf082 | 1777 | tp->netdev->addr_assign_type = NET_ADDR_STOLEN; |
34ee32c9 ML |
1778 | netif_info(tp, probe, tp->netdev, |
1779 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1780 | ||
1781 | amacout: | |
1782 | kfree(obj); | |
1783 | return ret; | |
1784 | } | |
1785 | ||
25766271 | 1786 | static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) |
ac718b69 | 1787 | { |
1788 | struct net_device *dev = tp->netdev; | |
8a91c824 | 1789 | int ret; |
ac718b69 | 1790 | |
a6cbcb77 CW |
1791 | sa->sa_family = dev->type; |
1792 | ||
b9b40ee4 | 1793 | ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data); |
acb6d377 TR |
1794 | if (ret < 0) { |
1795 | if (tp->version == RTL_VER_01) { | |
1796 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); | |
1797 | } else { | |
1798 | /* if device doesn't support MAC pass through this will | |
1799 | * be expected to be non-zero | |
1800 | */ | |
1801 | ret = vendor_mac_passthru_addr_read(tp, sa); | |
1802 | if (ret < 0) | |
1803 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, | |
1804 | sa->sa_data); | |
1805 | } | |
34ee32c9 | 1806 | } |
8a91c824 | 1807 | |
1808 | if (ret < 0) { | |
179bb6d7 | 1809 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
25766271 | 1810 | } else if (!is_valid_ether_addr(sa->sa_data)) { |
179bb6d7 | 1811 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", |
25766271 | 1812 | sa->sa_data); |
179bb6d7 | 1813 | eth_hw_addr_random(dev); |
25766271 | 1814 | ether_addr_copy(sa->sa_data, dev->dev_addr); |
179bb6d7 | 1815 | netif_info(tp, probe, dev, "Random ether addr %pM\n", |
25766271 ML |
1816 | sa->sa_data); |
1817 | return 0; | |
ac718b69 | 1818 | } |
179bb6d7 | 1819 | |
1820 | return ret; | |
ac718b69 | 1821 | } |
1822 | ||
776ac63a | 1823 | static int set_ethernet_addr(struct r8152 *tp, bool in_resume) |
25766271 ML |
1824 | { |
1825 | struct net_device *dev = tp->netdev; | |
1826 | struct sockaddr sa; | |
1827 | int ret; | |
1828 | ||
1829 | ret = determine_ethernet_addr(tp, &sa); | |
1830 | if (ret < 0) | |
1831 | return ret; | |
1832 | ||
1833 | if (tp->version == RTL_VER_01) | |
af804e6d | 1834 | eth_hw_addr_set(dev, sa.sa_data); |
25766271 | 1835 | else |
776ac63a | 1836 | ret = __rtl8152_set_mac_address(dev, &sa, in_resume); |
25766271 ML |
1837 | |
1838 | return ret; | |
1839 | } | |
1840 | ||
ac718b69 | 1841 | static void read_bulk_callback(struct urb *urb) |
1842 | { | |
ac718b69 | 1843 | struct net_device *netdev; |
ac718b69 | 1844 | int status = urb->status; |
ebc2ec48 | 1845 | struct rx_agg *agg; |
1846 | struct r8152 *tp; | |
ed7aa30e | 1847 | unsigned long flags; |
ac718b69 | 1848 | |
ebc2ec48 | 1849 | agg = urb->context; |
1850 | if (!agg) | |
1851 | return; | |
1852 | ||
1853 | tp = agg->context; | |
ac718b69 | 1854 | if (!tp) |
1855 | return; | |
ebc2ec48 | 1856 | |
715f67f3 | 1857 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
ac718b69 | 1858 | return; |
ebc2ec48 | 1859 | |
1860 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1861 | return; | |
1862 | ||
ac718b69 | 1863 | netdev = tp->netdev; |
7559fb2f | 1864 | |
1865 | /* When link down, the driver would cancel all bulks. */ | |
1866 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1867 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1868 | return; |
1869 | ||
9a4be1bd | 1870 | usb_mark_last_busy(tp->udev); |
1871 | ||
ac718b69 | 1872 | switch (status) { |
1873 | case 0: | |
ebc2ec48 | 1874 | if (urb->actual_length < ETH_ZLEN) |
1875 | break; | |
1876 | ||
ed7aa30e | 1877 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1878 | list_add_tail(&agg->list, &tp->rx_done); |
ed7aa30e | 1879 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
d823ab68 | 1880 | napi_schedule(&tp->napi); |
ebc2ec48 | 1881 | return; |
ac718b69 | 1882 | case -ESHUTDOWN: |
ffa9fec3 | 1883 | rtl_set_unplug(tp); |
ac718b69 | 1884 | netif_device_detach(tp->netdev); |
ebc2ec48 | 1885 | return; |
baf33d7a HW |
1886 | case -EPROTO: |
1887 | urb->actual_length = 0; | |
1888 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1889 | list_add_tail(&agg->list, &tp->rx_done); | |
1890 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1891 | set_bit(RX_EPROTO, &tp->flags); | |
1892 | schedule_delayed_work(&tp->schedule, 1); | |
1893 | return; | |
ac718b69 | 1894 | case -ENOENT: |
1895 | return; /* the urb is in unlink state */ | |
1896 | case -ETIME: | |
4a8deae2 HW |
1897 | if (net_ratelimit()) |
1898 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1899 | break; |
ac718b69 | 1900 | default: |
4a8deae2 HW |
1901 | if (net_ratelimit()) |
1902 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1903 | break; |
ac718b69 | 1904 | } |
1905 | ||
a0fccd48 | 1906 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1907 | } |
1908 | ||
ebc2ec48 | 1909 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1910 | { |
ebc2ec48 | 1911 | struct net_device_stats *stats; |
d104eafa | 1912 | struct net_device *netdev; |
ebc2ec48 | 1913 | struct tx_agg *agg; |
ac718b69 | 1914 | struct r8152 *tp; |
ed7aa30e | 1915 | unsigned long flags; |
ebc2ec48 | 1916 | int status = urb->status; |
ac718b69 | 1917 | |
ebc2ec48 | 1918 | agg = urb->context; |
1919 | if (!agg) | |
ac718b69 | 1920 | return; |
1921 | ||
ebc2ec48 | 1922 | tp = agg->context; |
1923 | if (!tp) | |
1924 | return; | |
1925 | ||
d104eafa | 1926 | netdev = tp->netdev; |
05e0f1aa | 1927 | stats = &netdev->stats; |
ebc2ec48 | 1928 | if (status) { |
4a8deae2 | 1929 | if (net_ratelimit()) |
d104eafa | 1930 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1931 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1932 | } else { |
ebc2ec48 | 1933 | stats->tx_packets += agg->skb_num; |
1934 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1935 | } |
1936 | ||
ed7aa30e | 1937 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1938 | list_add_tail(&agg->list, &tp->tx_free); |
ed7aa30e | 1939 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1940 | |
9a4be1bd | 1941 | usb_autopm_put_interface_async(tp->intf); |
1942 | ||
d104eafa | 1943 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1944 | return; |
1945 | ||
1946 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1947 | return; | |
1948 | ||
715f67f3 | 1949 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
ebc2ec48 | 1950 | return; |
1951 | ||
1952 | if (!skb_queue_empty(&tp->tx_queue)) | |
d2187f8e | 1953 | tasklet_schedule(&tp->tx_tl); |
ac718b69 | 1954 | } |
1955 | ||
40a82917 | 1956 | static void intr_callback(struct urb *urb) |
1957 | { | |
1958 | struct r8152 *tp; | |
500b6d7e | 1959 | __le16 *d; |
40a82917 | 1960 | int status = urb->status; |
1961 | int res; | |
1962 | ||
1963 | tp = urb->context; | |
1964 | if (!tp) | |
1965 | return; | |
1966 | ||
1967 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1968 | return; | |
1969 | ||
715f67f3 | 1970 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
40a82917 | 1971 | return; |
1972 | ||
1973 | switch (status) { | |
1974 | case 0: /* success */ | |
1975 | break; | |
1976 | case -ECONNRESET: /* unlink */ | |
1977 | case -ESHUTDOWN: | |
1978 | netif_device_detach(tp->netdev); | |
df561f66 | 1979 | fallthrough; |
40a82917 | 1980 | case -ENOENT: |
d59c876d | 1981 | case -EPROTO: |
1982 | netif_info(tp, intr, tp->netdev, | |
1983 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1984 | return; |
1985 | case -EOVERFLOW: | |
93e2be34 AG |
1986 | if (net_ratelimit()) |
1987 | netif_info(tp, intr, tp->netdev, | |
1988 | "intr status -EOVERFLOW\n"); | |
40a82917 | 1989 | goto resubmit; |
1990 | /* -EPIPE: should clear the halt */ | |
1991 | default: | |
1992 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1993 | goto resubmit; | |
1994 | } | |
1995 | ||
1996 | d = urb->transfer_buffer; | |
1997 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1998 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1999 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
2000 | schedule_delayed_work(&tp->schedule, 0); | |
2001 | } | |
2002 | } else { | |
51d979fa | 2003 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 2004 | netif_stop_queue(tp->netdev); |
40a82917 | 2005 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
2006 | schedule_delayed_work(&tp->schedule, 0); | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | resubmit: | |
2011 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 2012 | if (res == -ENODEV) { |
ffa9fec3 | 2013 | rtl_set_unplug(tp); |
40a82917 | 2014 | netif_device_detach(tp->netdev); |
67610496 | 2015 | } else if (res) { |
40a82917 | 2016 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 2017 | "can't resubmit intr, status %d\n", res); |
67610496 | 2018 | } |
40a82917 | 2019 | } |
2020 | ||
ebc2ec48 | 2021 | static inline void *rx_agg_align(void *data) |
2022 | { | |
8e1f51bd | 2023 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 2024 | } |
2025 | ||
2026 | static inline void *tx_agg_align(void *data) | |
2027 | { | |
8e1f51bd | 2028 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 2029 | } |
2030 | ||
252df8b8 HW |
2031 | static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) |
2032 | { | |
2033 | list_del(&agg->info_list); | |
2034 | ||
2035 | usb_free_urb(agg->urb); | |
47922fcd | 2036 | put_page(agg->page); |
252df8b8 HW |
2037 | kfree(agg); |
2038 | ||
2039 | atomic_dec(&tp->rx_count); | |
2040 | } | |
2041 | ||
2042 | static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) | |
2043 | { | |
2044 | struct net_device *netdev = tp->netdev; | |
2045 | int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
d55d7089 | 2046 | unsigned int order = get_order(tp->rx_buf_sz); |
252df8b8 HW |
2047 | struct rx_agg *rx_agg; |
2048 | unsigned long flags; | |
252df8b8 HW |
2049 | |
2050 | rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); | |
2051 | if (!rx_agg) | |
2052 | return NULL; | |
2053 | ||
5cc33f13 | 2054 | rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order); |
d55d7089 | 2055 | if (!rx_agg->page) |
252df8b8 HW |
2056 | goto free_rx; |
2057 | ||
d55d7089 | 2058 | rx_agg->buffer = page_address(rx_agg->page); |
252df8b8 HW |
2059 | |
2060 | rx_agg->urb = usb_alloc_urb(0, mflags); | |
2061 | if (!rx_agg->urb) | |
2062 | goto free_buf; | |
2063 | ||
2064 | rx_agg->context = tp; | |
2065 | ||
2066 | INIT_LIST_HEAD(&rx_agg->list); | |
2067 | INIT_LIST_HEAD(&rx_agg->info_list); | |
2068 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2069 | list_add_tail(&rx_agg->info_list, &tp->rx_info); | |
2070 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2071 | ||
2072 | atomic_inc(&tp->rx_count); | |
2073 | ||
2074 | return rx_agg; | |
2075 | ||
2076 | free_buf: | |
d55d7089 | 2077 | __free_pages(rx_agg->page, order); |
252df8b8 HW |
2078 | free_rx: |
2079 | kfree(rx_agg); | |
2080 | return NULL; | |
2081 | } | |
2082 | ||
ebc2ec48 | 2083 | static void free_all_mem(struct r8152 *tp) |
2084 | { | |
252df8b8 HW |
2085 | struct rx_agg *agg, *agg_next; |
2086 | unsigned long flags; | |
ebc2ec48 | 2087 | int i; |
2088 | ||
252df8b8 | 2089 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 2090 | |
252df8b8 HW |
2091 | list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) |
2092 | free_rx_agg(tp, agg); | |
2093 | ||
2094 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2095 | ||
2096 | WARN_ON(atomic_read(&tp->rx_count)); | |
ebc2ec48 | 2097 | |
2098 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 2099 | usb_free_urb(tp->tx_info[i].urb); |
2100 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 2101 | |
9629e3c0 | 2102 | kfree(tp->tx_info[i].buffer); |
2103 | tp->tx_info[i].buffer = NULL; | |
2104 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 2105 | } |
40a82917 | 2106 | |
9629e3c0 | 2107 | usb_free_urb(tp->intr_urb); |
2108 | tp->intr_urb = NULL; | |
40a82917 | 2109 | |
9629e3c0 | 2110 | kfree(tp->intr_buff); |
2111 | tp->intr_buff = NULL; | |
ebc2ec48 | 2112 | } |
2113 | ||
2114 | static int alloc_all_mem(struct r8152 *tp) | |
2115 | { | |
2116 | struct net_device *netdev = tp->netdev; | |
40a82917 | 2117 | struct usb_interface *intf = tp->intf; |
2118 | struct usb_host_interface *alt = intf->cur_altsetting; | |
2119 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 2120 | int node, i; |
ebc2ec48 | 2121 | |
2122 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
2123 | ||
2124 | spin_lock_init(&tp->rx_lock); | |
2125 | spin_lock_init(&tp->tx_lock); | |
252df8b8 | 2126 | INIT_LIST_HEAD(&tp->rx_info); |
ebc2ec48 | 2127 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 2128 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 2129 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 2130 | skb_queue_head_init(&tp->rx_queue); |
252df8b8 | 2131 | atomic_set(&tp->rx_count, 0); |
ebc2ec48 | 2132 | |
2133 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
252df8b8 | 2134 | if (!alloc_rx_agg(tp, GFP_KERNEL)) |
ebc2ec48 | 2135 | goto err1; |
ebc2ec48 | 2136 | } |
2137 | ||
2138 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
252df8b8 HW |
2139 | struct urb *urb; |
2140 | u8 *buf; | |
2141 | ||
52aec126 | 2142 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 2143 | if (!buf) |
2144 | goto err1; | |
2145 | ||
2146 | if (buf != tx_agg_align(buf)) { | |
2147 | kfree(buf); | |
52aec126 | 2148 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 2149 | node); |
ebc2ec48 | 2150 | if (!buf) |
2151 | goto err1; | |
2152 | } | |
2153 | ||
2154 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
2155 | if (!urb) { | |
2156 | kfree(buf); | |
2157 | goto err1; | |
2158 | } | |
2159 | ||
2160 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
2161 | tp->tx_info[i].context = tp; | |
2162 | tp->tx_info[i].urb = urb; | |
2163 | tp->tx_info[i].buffer = buf; | |
2164 | tp->tx_info[i].head = tx_agg_align(buf); | |
2165 | ||
2166 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
2167 | } | |
2168 | ||
40a82917 | 2169 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
2170 | if (!tp->intr_urb) | |
2171 | goto err1; | |
2172 | ||
2173 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
2174 | if (!tp->intr_buff) | |
2175 | goto err1; | |
2176 | ||
2177 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
b67fda9a | 2178 | usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr, |
b209af99 | 2179 | tp->intr_buff, INTBUFSIZE, intr_callback, |
2180 | tp, tp->intr_interval); | |
40a82917 | 2181 | |
ebc2ec48 | 2182 | return 0; |
2183 | ||
2184 | err1: | |
2185 | free_all_mem(tp); | |
2186 | return -ENOMEM; | |
2187 | } | |
2188 | ||
0de98f6c | 2189 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
2190 | { | |
2191 | struct tx_agg *agg = NULL; | |
2192 | unsigned long flags; | |
2193 | ||
21949ab7 | 2194 | if (list_empty(&tp->tx_free)) |
2195 | return NULL; | |
2196 | ||
0de98f6c | 2197 | spin_lock_irqsave(&tp->tx_lock, flags); |
2198 | if (!list_empty(&tp->tx_free)) { | |
2199 | struct list_head *cursor; | |
2200 | ||
2201 | cursor = tp->tx_free.next; | |
2202 | list_del_init(cursor); | |
2203 | agg = list_entry(cursor, struct tx_agg, list); | |
2204 | } | |
2205 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
2206 | ||
2207 | return agg; | |
2208 | } | |
2209 | ||
b209af99 | 2210 | /* r8152_csum_workaround() |
c01ebd6c | 2211 | * The hw limits the value of the transport offset. When the offset is out of |
6128d1bb | 2212 | * range, calculate the checksum by sw. |
2213 | */ | |
2214 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
2215 | struct sk_buff_head *list) | |
2216 | { | |
2217 | if (skb_shinfo(skb)->gso_size) { | |
2218 | netdev_features_t features = tp->netdev->features; | |
1d7a7438 | 2219 | struct sk_buff *segs, *seg, *next; |
6128d1bb | 2220 | struct sk_buff_head seg_list; |
6128d1bb | 2221 | |
a91d45f1 | 2222 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 2223 | segs = skb_gso_segment(skb, features); |
2224 | if (IS_ERR(segs) || !segs) | |
2225 | goto drop; | |
2226 | ||
2227 | __skb_queue_head_init(&seg_list); | |
2228 | ||
1d7a7438 JD |
2229 | skb_list_walk_safe(segs, seg, next) { |
2230 | skb_mark_not_on_list(seg); | |
2231 | __skb_queue_tail(&seg_list, seg); | |
2232 | } | |
6128d1bb | 2233 | |
2234 | skb_queue_splice(&seg_list, list); | |
2235 | dev_kfree_skb(skb); | |
2236 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
2237 | if (skb_checksum_help(skb) < 0) | |
2238 | goto drop; | |
2239 | ||
2240 | __skb_queue_head(list, skb); | |
2241 | } else { | |
2242 | struct net_device_stats *stats; | |
2243 | ||
2244 | drop: | |
2245 | stats = &tp->netdev->stats; | |
2246 | stats->tx_dropped++; | |
2247 | dev_kfree_skb(skb); | |
2248 | } | |
2249 | } | |
2250 | ||
c5554298 | 2251 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
2252 | { | |
df8a39de | 2253 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 2254 | u32 opts2; |
2255 | ||
df8a39de | 2256 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 2257 | desc->opts2 |= cpu_to_le32(opts2); |
2258 | } | |
2259 | } | |
2260 | ||
2261 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
2262 | { | |
2263 | u32 opts2 = le32_to_cpu(desc->opts2); | |
2264 | ||
2265 | if (opts2 & RX_VLAN_TAG) | |
2266 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
2267 | swab16(opts2 & 0xffff)); | |
2268 | } | |
2269 | ||
60c89071 | 2270 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
057cc8c9 | 2271 | struct sk_buff *skb, u32 len) |
60c89071 | 2272 | { |
2273 | u32 mss = skb_shinfo(skb)->gso_size; | |
2274 | u32 opts1, opts2 = 0; | |
2275 | int ret = TX_CSUM_SUCCESS; | |
2276 | ||
2277 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
2278 | ||
2279 | opts1 = len | TX_FS | TX_LS; | |
2280 | ||
2281 | if (mss) { | |
057cc8c9 HW |
2282 | u32 transport_offset = (u32)skb_transport_offset(skb); |
2283 | ||
6128d1bb | 2284 | if (transport_offset > GTTCPHO_MAX) { |
2285 | netif_warn(tp, tx_err, tp->netdev, | |
2286 | "Invalid transport offset 0x%x for TSO\n", | |
2287 | transport_offset); | |
2288 | ret = TX_CSUM_TSO; | |
2289 | goto unavailable; | |
2290 | } | |
2291 | ||
6e74d174 | 2292 | switch (vlan_get_protocol(skb)) { |
60c89071 | 2293 | case htons(ETH_P_IP): |
2294 | opts1 |= GTSENDV4; | |
2295 | break; | |
2296 | ||
6128d1bb | 2297 | case htons(ETH_P_IPV6): |
2344120d | 2298 | if (skb_cow_head(skb, 0)) { |
fcb308d5 | 2299 | ret = TX_CSUM_TSO; |
2300 | goto unavailable; | |
2301 | } | |
2344120d | 2302 | tcp_v6_gso_csum_prep(skb); |
6128d1bb | 2303 | opts1 |= GTSENDV6; |
6128d1bb | 2304 | break; |
2305 | ||
60c89071 | 2306 | default: |
2307 | WARN_ON_ONCE(1); | |
2308 | break; | |
2309 | } | |
2310 | ||
2311 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
2312 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
2313 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
057cc8c9 | 2314 | u32 transport_offset = (u32)skb_transport_offset(skb); |
60c89071 | 2315 | u8 ip_protocol; |
5bd23881 | 2316 | |
6128d1bb | 2317 | if (transport_offset > TCPHO_MAX) { |
2318 | netif_warn(tp, tx_err, tp->netdev, | |
2319 | "Invalid transport offset 0x%x\n", | |
2320 | transport_offset); | |
2321 | ret = TX_CSUM_NONE; | |
2322 | goto unavailable; | |
2323 | } | |
2324 | ||
6e74d174 | 2325 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 2326 | case htons(ETH_P_IP): |
2327 | opts2 |= IPV4_CS; | |
2328 | ip_protocol = ip_hdr(skb)->protocol; | |
2329 | break; | |
2330 | ||
2331 | case htons(ETH_P_IPV6): | |
2332 | opts2 |= IPV6_CS; | |
2333 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
2334 | break; | |
2335 | ||
2336 | default: | |
2337 | ip_protocol = IPPROTO_RAW; | |
2338 | break; | |
2339 | } | |
2340 | ||
60c89071 | 2341 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 2342 | opts2 |= TCP_CS; |
60c89071 | 2343 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 2344 | opts2 |= UDP_CS; |
60c89071 | 2345 | else |
5bd23881 | 2346 | WARN_ON_ONCE(1); |
5bd23881 | 2347 | |
60c89071 | 2348 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 2349 | } |
60c89071 | 2350 | |
2351 | desc->opts2 = cpu_to_le32(opts2); | |
2352 | desc->opts1 = cpu_to_le32(opts1); | |
2353 | ||
6128d1bb | 2354 | unavailable: |
60c89071 | 2355 | return ret; |
5bd23881 | 2356 | } |
2357 | ||
b1379d9a | 2358 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
2359 | { | |
d84130a1 | 2360 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 2361 | int remain, ret; |
b1379d9a | 2362 | u8 *tx_data; |
2363 | ||
d84130a1 | 2364 | __skb_queue_head_init(&skb_head); |
0c3121fc | 2365 | spin_lock(&tx_queue->lock); |
d84130a1 | 2366 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 2367 | spin_unlock(&tx_queue->lock); |
d84130a1 | 2368 | |
b1379d9a | 2369 | tx_data = agg->head; |
b209af99 | 2370 | agg->skb_num = 0; |
2371 | agg->skb_len = 0; | |
52aec126 | 2372 | remain = agg_buf_sz; |
b1379d9a | 2373 | |
7937f9e5 | 2374 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 2375 | struct tx_desc *tx_desc; |
2376 | struct sk_buff *skb; | |
2377 | unsigned int len; | |
2378 | ||
d84130a1 | 2379 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 2380 | if (!skb) |
2381 | break; | |
2382 | ||
60c89071 | 2383 | len = skb->len + sizeof(*tx_desc); |
2384 | ||
2385 | if (len > remain) { | |
d84130a1 | 2386 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 2387 | break; |
2388 | } | |
2389 | ||
7937f9e5 | 2390 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 2391 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 2392 | |
057cc8c9 | 2393 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { |
6128d1bb | 2394 | r8152_csum_workaround(tp, skb, &skb_head); |
2395 | continue; | |
2396 | } | |
60c89071 | 2397 | |
c5554298 | 2398 | rtl_tx_vlan_tag(tx_desc, skb); |
2399 | ||
b1379d9a | 2400 | tx_data += sizeof(*tx_desc); |
2401 | ||
60c89071 | 2402 | len = skb->len; |
2403 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
2404 | struct net_device_stats *stats = &tp->netdev->stats; | |
2405 | ||
2406 | stats->tx_dropped++; | |
2407 | dev_kfree_skb_any(skb); | |
2408 | tx_data -= sizeof(*tx_desc); | |
2409 | continue; | |
2410 | } | |
2411 | ||
2412 | tx_data += len; | |
b1379d9a | 2413 | agg->skb_len += len; |
4c27bf3c | 2414 | agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; |
60c89071 | 2415 | |
b1379d9a | 2416 | dev_kfree_skb_any(skb); |
2417 | ||
52aec126 | 2418 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
0b165514 | 2419 | |
9c68011b | 2420 | if (tp->dell_tb_rx_agg_bug) |
0b165514 | 2421 | break; |
b1379d9a | 2422 | } |
2423 | ||
d84130a1 | 2424 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 2425 | spin_lock(&tx_queue->lock); |
d84130a1 | 2426 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 2427 | spin_unlock(&tx_queue->lock); |
d84130a1 | 2428 | } |
2429 | ||
0c3121fc | 2430 | netif_tx_lock(tp->netdev); |
dd1b119c | 2431 | |
2432 | if (netif_queue_stopped(tp->netdev) && | |
2433 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
2434 | netif_wake_queue(tp->netdev); | |
2435 | ||
0c3121fc | 2436 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 2437 | |
0c3121fc | 2438 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 2439 | if (ret < 0) |
2440 | goto out_tx_fill; | |
dd1b119c | 2441 | |
b67fda9a | 2442 | usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out, |
b1379d9a | 2443 | agg->head, (int)(tx_data - (u8 *)agg->head), |
2444 | (usb_complete_t)write_bulk_callback, agg); | |
2445 | ||
0c3121fc | 2446 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 2447 | if (ret < 0) |
0c3121fc | 2448 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 2449 | |
2450 | out_tx_fill: | |
2451 | return ret; | |
b1379d9a | 2452 | } |
2453 | ||
565cab0a | 2454 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
2455 | { | |
2456 | u8 checksum = CHECKSUM_NONE; | |
2457 | u32 opts2, opts3; | |
2458 | ||
19c0f40d | 2459 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 2460 | goto return_result; |
2461 | ||
2462 | opts2 = le32_to_cpu(rx_desc->opts2); | |
2463 | opts3 = le32_to_cpu(rx_desc->opts3); | |
2464 | ||
2465 | if (opts2 & RD_IPV4_CS) { | |
2466 | if (opts3 & IPF) | |
2467 | checksum = CHECKSUM_NONE; | |
ea6499e1 HW |
2468 | else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
2469 | checksum = CHECKSUM_UNNECESSARY; | |
2470 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
565cab0a | 2471 | checksum = CHECKSUM_UNNECESSARY; |
b9a321b4 | 2472 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 2473 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
2474 | checksum = CHECKSUM_UNNECESSARY; | |
2475 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
2476 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 2477 | } |
2478 | ||
2479 | return_result: | |
2480 | return checksum; | |
2481 | } | |
2482 | ||
47922fcd HW |
2483 | static inline bool rx_count_exceed(struct r8152 *tp) |
2484 | { | |
2485 | return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; | |
2486 | } | |
2487 | ||
2488 | static inline int agg_offset(struct rx_agg *agg, void *addr) | |
2489 | { | |
2490 | return (int)(addr - agg->buffer); | |
2491 | } | |
2492 | ||
2493 | static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) | |
2494 | { | |
2495 | struct rx_agg *agg, *agg_next, *agg_free = NULL; | |
2496 | unsigned long flags; | |
2497 | ||
2498 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2499 | ||
2500 | list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { | |
2501 | if (page_count(agg->page) == 1) { | |
2502 | if (!agg_free) { | |
2503 | list_del_init(&agg->list); | |
2504 | agg_free = agg; | |
2505 | continue; | |
2506 | } | |
2507 | if (rx_count_exceed(tp)) { | |
2508 | list_del_init(&agg->list); | |
2509 | free_rx_agg(tp, agg); | |
2510 | } | |
2511 | break; | |
2512 | } | |
2513 | } | |
2514 | ||
2515 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2516 | ||
e4a5017a | 2517 | if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) |
47922fcd HW |
2518 | agg_free = alloc_rx_agg(tp, mflags); |
2519 | ||
2520 | return agg_free; | |
2521 | } | |
2522 | ||
d823ab68 | 2523 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 2524 | { |
a5a4f468 | 2525 | unsigned long flags; |
d84130a1 | 2526 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 2527 | int ret = 0, work_done = 0; |
ce594e98 | 2528 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 2529 | |
2530 | if (!skb_queue_empty(&tp->rx_queue)) { | |
2531 | while (work_done < budget) { | |
2532 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
2533 | struct net_device *netdev = tp->netdev; | |
2534 | struct net_device_stats *stats = &netdev->stats; | |
2535 | unsigned int pkt_len; | |
2536 | ||
2537 | if (!skb) | |
2538 | break; | |
2539 | ||
2540 | pkt_len = skb->len; | |
ce594e98 | 2541 | napi_gro_receive(napi, skb); |
d823ab68 | 2542 | work_done++; |
2543 | stats->rx_packets++; | |
2544 | stats->rx_bytes += pkt_len; | |
2545 | } | |
2546 | } | |
ebc2ec48 | 2547 | |
2cf51f93 | 2548 | if (list_empty(&tp->rx_done) || work_done >= budget) |
d823ab68 | 2549 | goto out1; |
d84130a1 | 2550 | |
baf33d7a | 2551 | clear_bit(RX_EPROTO, &tp->flags); |
d84130a1 | 2552 | INIT_LIST_HEAD(&rx_queue); |
a5a4f468 | 2553 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 2554 | list_splice_init(&tp->rx_done, &rx_queue); |
2555 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2556 | ||
2557 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 2558 | struct rx_desc *rx_desc; |
47922fcd | 2559 | struct rx_agg *agg, *agg_free; |
43a4478d | 2560 | int len_used = 0; |
2561 | struct urb *urb; | |
2562 | u8 *rx_data; | |
43a4478d | 2563 | |
2cf51f93 HW |
2564 | /* A bulk transfer of USB may contain may packets, so the |
2565 | * total packets may more than the budget. Deal with all | |
2566 | * packets in current bulk transfer, and stop to handle the | |
2567 | * next bulk transfer until next schedule, if budget is | |
2568 | * exhausted. | |
2569 | */ | |
2570 | if (work_done >= budget) | |
2571 | break; | |
2572 | ||
ebc2ec48 | 2573 | list_del_init(cursor); |
ebc2ec48 | 2574 | |
2575 | agg = list_entry(cursor, struct rx_agg, list); | |
2576 | urb = agg->urb; | |
baf33d7a | 2577 | if (urb->status != 0 || urb->actual_length < ETH_ZLEN) |
0de98f6c | 2578 | goto submit; |
ebc2ec48 | 2579 | |
47922fcd HW |
2580 | agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); |
2581 | ||
d55d7089 HW |
2582 | rx_desc = agg->buffer; |
2583 | rx_data = agg->buffer; | |
7937f9e5 | 2584 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 2585 | |
7937f9e5 | 2586 | while (urb->actual_length > len_used) { |
43a4478d | 2587 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 2588 | struct net_device_stats *stats = &netdev->stats; |
788d30da | 2589 | unsigned int pkt_len, rx_frag_head_sz, len; |
43a4478d | 2590 | struct sk_buff *skb; |
788d30da | 2591 | bool use_frags; |
43a4478d | 2592 | |
2cf51f93 | 2593 | WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000); |
74544458 | 2594 | |
7937f9e5 | 2595 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 2596 | if (pkt_len < ETH_ZLEN) |
2597 | break; | |
2598 | ||
7937f9e5 | 2599 | len_used += pkt_len; |
2600 | if (urb->actual_length < len_used) | |
2601 | break; | |
2602 | ||
b65c0c9b | 2603 | pkt_len -= ETH_FCS_LEN; |
788d30da | 2604 | len = pkt_len; |
ebc2ec48 | 2605 | rx_data += sizeof(struct rx_desc); |
2606 | ||
788d30da HW |
2607 | if (!agg_free || tp->rx_copybreak > len) |
2608 | use_frags = false; | |
47922fcd | 2609 | else |
788d30da HW |
2610 | use_frags = true; |
2611 | ||
2612 | if (use_frags) { | |
2613 | /* If the budget is exhausted, the packet | |
2614 | * would be queued in the driver. That is, | |
2615 | * napi_gro_frags() wouldn't be called, so | |
2616 | * we couldn't use napi_get_frags(). | |
2617 | */ | |
2618 | if (work_done >= budget) { | |
2619 | rx_frag_head_sz = tp->rx_copybreak; | |
2620 | skb = napi_alloc_skb(napi, | |
2621 | rx_frag_head_sz); | |
2622 | } else { | |
2623 | rx_frag_head_sz = 0; | |
2624 | skb = napi_get_frags(napi); | |
2625 | } | |
2626 | } else { | |
2627 | rx_frag_head_sz = 0; | |
2628 | skb = napi_alloc_skb(napi, len); | |
2629 | } | |
47922fcd | 2630 | |
ebc2ec48 | 2631 | if (!skb) { |
2632 | stats->rx_dropped++; | |
5e2f7485 | 2633 | goto find_next_rx; |
ebc2ec48 | 2634 | } |
565cab0a | 2635 | |
2636 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
788d30da HW |
2637 | rtl_rx_vlan_tag(rx_desc, skb); |
2638 | ||
2639 | if (use_frags) { | |
2640 | if (rx_frag_head_sz) { | |
2641 | memcpy(skb->data, rx_data, | |
2642 | rx_frag_head_sz); | |
2643 | skb_put(skb, rx_frag_head_sz); | |
2644 | len -= rx_frag_head_sz; | |
2645 | rx_data += rx_frag_head_sz; | |
2646 | skb->protocol = eth_type_trans(skb, | |
2647 | netdev); | |
2648 | } | |
2649 | ||
47922fcd HW |
2650 | skb_add_rx_frag(skb, 0, agg->page, |
2651 | agg_offset(agg, rx_data), | |
788d30da | 2652 | len, SKB_DATA_ALIGN(len)); |
47922fcd | 2653 | get_page(agg->page); |
788d30da HW |
2654 | } else { |
2655 | memcpy(skb->data, rx_data, len); | |
2656 | skb_put(skb, len); | |
2657 | skb->protocol = eth_type_trans(skb, netdev); | |
47922fcd HW |
2658 | } |
2659 | ||
d823ab68 | 2660 | if (work_done < budget) { |
788d30da HW |
2661 | if (use_frags) |
2662 | napi_gro_frags(napi); | |
2663 | else | |
2664 | napi_gro_receive(napi, skb); | |
2665 | ||
d823ab68 | 2666 | work_done++; |
2667 | stats->rx_packets++; | |
788d30da | 2668 | stats->rx_bytes += pkt_len; |
d823ab68 | 2669 | } else { |
2670 | __skb_queue_tail(&tp->rx_queue, skb); | |
2671 | } | |
ebc2ec48 | 2672 | |
5e2f7485 | 2673 | find_next_rx: |
788d30da | 2674 | rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN); |
ebc2ec48 | 2675 | rx_desc = (struct rx_desc *)rx_data; |
47922fcd | 2676 | len_used = agg_offset(agg, rx_data); |
7937f9e5 | 2677 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 2678 | } |
2679 | ||
47922fcd HW |
2680 | WARN_ON(!agg_free && page_count(agg->page) > 1); |
2681 | ||
2682 | if (agg_free) { | |
2683 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2684 | if (page_count(agg->page) == 1) { | |
2685 | list_add(&agg_free->list, &tp->rx_used); | |
2686 | } else { | |
2687 | list_add_tail(&agg->list, &tp->rx_used); | |
2688 | agg = agg_free; | |
2689 | urb = agg->urb; | |
2690 | } | |
2691 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2692 | } | |
2693 | ||
0de98f6c | 2694 | submit: |
e1a2ca92 | 2695 | if (!ret) { |
2696 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
2697 | } else { | |
2698 | urb->actual_length = 0; | |
2699 | list_add_tail(&agg->list, next); | |
2700 | } | |
2701 | } | |
2702 | ||
2cf51f93 | 2703 | /* Splice the remained list back to rx_done for next schedule */ |
e1a2ca92 | 2704 | if (!list_empty(&rx_queue)) { |
2705 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2cf51f93 | 2706 | list_splice(&rx_queue, &tp->rx_done); |
e1a2ca92 | 2707 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 2708 | } |
d823ab68 | 2709 | |
2710 | out1: | |
2711 | return work_done; | |
ebc2ec48 | 2712 | } |
2713 | ||
2714 | static void tx_bottom(struct r8152 *tp) | |
2715 | { | |
ebc2ec48 | 2716 | int res; |
2717 | ||
b1379d9a | 2718 | do { |
c01ebd6c | 2719 | struct net_device *netdev = tp->netdev; |
b1379d9a | 2720 | struct tx_agg *agg; |
ebc2ec48 | 2721 | |
b1379d9a | 2722 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 2723 | break; |
2724 | ||
b1379d9a | 2725 | agg = r8152_get_tx_agg(tp); |
2726 | if (!agg) | |
ebc2ec48 | 2727 | break; |
ebc2ec48 | 2728 | |
b1379d9a | 2729 | res = r8152_tx_agg_fill(tp, agg); |
c01ebd6c PM |
2730 | if (!res) |
2731 | continue; | |
ebc2ec48 | 2732 | |
c01ebd6c PM |
2733 | if (res == -ENODEV) { |
2734 | rtl_set_unplug(tp); | |
2735 | netif_device_detach(netdev); | |
2736 | } else { | |
2737 | struct net_device_stats *stats = &netdev->stats; | |
2738 | unsigned long flags; | |
05e0f1aa | 2739 | |
c01ebd6c PM |
2740 | netif_warn(tp, tx_err, netdev, |
2741 | "failed tx_urb %d\n", res); | |
2742 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 2743 | |
c01ebd6c PM |
2744 | spin_lock_irqsave(&tp->tx_lock, flags); |
2745 | list_add_tail(&agg->list, &tp->tx_free); | |
2746 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
ebc2ec48 | 2747 | } |
b1379d9a | 2748 | } while (res == 0); |
ebc2ec48 | 2749 | } |
2750 | ||
f3163f1c | 2751 | static void bottom_half(struct tasklet_struct *t) |
ac718b69 | 2752 | { |
f3163f1c | 2753 | struct r8152 *tp = from_tasklet(tp, t, tx_tl); |
d2187f8e | 2754 | |
715f67f3 | 2755 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
ebc2ec48 | 2756 | return; |
2757 | ||
2758 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 2759 | return; |
ebc2ec48 | 2760 | |
7559fb2f | 2761 | /* When link down, the driver would cancel all bulks. */ |
2762 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 2763 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 2764 | return; |
ebc2ec48 | 2765 | |
d2187f8e | 2766 | clear_bit(SCHEDULE_TASKLET, &tp->flags); |
9451a11c | 2767 | |
0c3121fc | 2768 | tx_bottom(tp); |
ebc2ec48 | 2769 | } |
2770 | ||
d823ab68 | 2771 | static int r8152_poll(struct napi_struct *napi, int budget) |
2772 | { | |
2773 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
2774 | int work_done; | |
2775 | ||
a7b8d60b HW |
2776 | if (!budget) |
2777 | return 0; | |
2778 | ||
d823ab68 | 2779 | work_done = rx_bottom(tp, budget); |
d823ab68 | 2780 | |
2781 | if (work_done < budget) { | |
a3307f9b | 2782 | if (!napi_complete_done(napi, work_done)) |
2783 | goto out; | |
d823ab68 | 2784 | if (!list_empty(&tp->rx_done)) |
2785 | napi_schedule(napi); | |
2786 | } | |
2787 | ||
a3307f9b | 2788 | out: |
d823ab68 | 2789 | return work_done; |
2790 | } | |
2791 | ||
ebc2ec48 | 2792 | static |
2793 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
2794 | { | |
a0fccd48 | 2795 | int ret; |
2796 | ||
ef827a5b | 2797 | /* The rx would be stopped, so skip submitting */ |
715f67f3 | 2798 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || |
ef827a5b | 2799 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) |
2800 | return 0; | |
2801 | ||
b67fda9a | 2802 | usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in, |
d55d7089 | 2803 | agg->buffer, tp->rx_buf_sz, |
b209af99 | 2804 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 2805 | |
a0fccd48 | 2806 | ret = usb_submit_urb(agg->urb, mem_flags); |
2807 | if (ret == -ENODEV) { | |
ffa9fec3 | 2808 | rtl_set_unplug(tp); |
a0fccd48 | 2809 | netif_device_detach(tp->netdev); |
2810 | } else if (ret) { | |
2811 | struct urb *urb = agg->urb; | |
2812 | unsigned long flags; | |
2813 | ||
2814 | urb->actual_length = 0; | |
2815 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2816 | list_add_tail(&agg->list, &tp->rx_done); | |
2817 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 2818 | |
2819 | netif_err(tp, rx_err, tp->netdev, | |
2820 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
2821 | ||
2822 | napi_schedule(&tp->napi); | |
a0fccd48 | 2823 | } |
2824 | ||
2825 | return ret; | |
ac718b69 | 2826 | } |
2827 | ||
00a5e360 | 2828 | static void rtl_drop_queued_tx(struct r8152 *tp) |
2829 | { | |
2830 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 2831 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 2832 | struct sk_buff *skb; |
2833 | ||
d84130a1 | 2834 | if (skb_queue_empty(tx_queue)) |
2835 | return; | |
2836 | ||
2837 | __skb_queue_head_init(&skb_head); | |
2685d410 | 2838 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 2839 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 2840 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 2841 | |
2842 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 2843 | dev_kfree_skb(skb); |
2844 | stats->tx_dropped++; | |
2845 | } | |
2846 | } | |
2847 | ||
0290bd29 | 2848 | static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue) |
ac718b69 | 2849 | { |
2850 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2851 | |
4a8deae2 | 2852 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2853 | |
2854 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2855 | } |
2856 | ||
2857 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2858 | { | |
2859 | struct r8152 *tp = netdev_priv(netdev); | |
2860 | ||
51d979fa | 2861 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2862 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2863 | schedule_delayed_work(&tp->schedule, 0); |
2864 | } | |
ac718b69 | 2865 | } |
2866 | ||
2867 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2868 | { | |
2869 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2870 | u32 mc_filter[2]; /* Multicast hash filter */ |
2871 | __le32 tmp[2]; | |
ac718b69 | 2872 | u32 ocp_data; |
2873 | ||
ac718b69 | 2874 | netif_stop_queue(netdev); |
2875 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2876 | ocp_data &= ~RCR_ACPT_ALL; | |
2877 | ocp_data |= RCR_AB | RCR_APM; | |
2878 | ||
2879 | if (netdev->flags & IFF_PROMISC) { | |
2880 | /* Unconditionally log net taps. */ | |
2881 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2882 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2883 | mc_filter[1] = 0xffffffff; |
2884 | mc_filter[0] = 0xffffffff; | |
7305b78a SA |
2885 | } else if ((netdev->flags & IFF_MULTICAST && |
2886 | netdev_mc_count(netdev) > multicast_filter_limit) || | |
2887 | (netdev->flags & IFF_ALLMULTI)) { | |
ac718b69 | 2888 | /* Too many to filter perfectly -- accept all multicasts. */ |
2889 | ocp_data |= RCR_AM; | |
b209af99 | 2890 | mc_filter[1] = 0xffffffff; |
2891 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2892 | } else { |
b209af99 | 2893 | mc_filter[1] = 0; |
2894 | mc_filter[0] = 0; | |
b209af99 | 2895 | |
7305b78a SA |
2896 | if (netdev->flags & IFF_MULTICAST) { |
2897 | struct netdev_hw_addr *ha; | |
2898 | ||
2899 | netdev_for_each_mc_addr(ha, netdev) { | |
2900 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
2901 | ||
2902 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
2903 | ocp_data |= RCR_AM; | |
2904 | } | |
ac718b69 | 2905 | } |
2906 | } | |
2907 | ||
31787f53 | 2908 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2909 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2910 | |
31787f53 | 2911 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2912 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2913 | netif_wake_queue(netdev); | |
ac718b69 | 2914 | } |
2915 | ||
a5e31255 | 2916 | static netdev_features_t |
2917 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2918 | netdev_features_t features) | |
2919 | { | |
2920 | u32 mss = skb_shinfo(skb)->gso_size; | |
2921 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
a5e31255 | 2922 | |
057cc8c9 HW |
2923 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && |
2924 | skb_transport_offset(skb) > max_offset) | |
a188222b | 2925 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2926 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2927 | features &= ~NETIF_F_GSO_MASK; | |
2928 | ||
2929 | return features; | |
2930 | } | |
2931 | ||
ac718b69 | 2932 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2933 | struct net_device *netdev) |
ac718b69 | 2934 | { |
2935 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2936 | |
ebc2ec48 | 2937 | skb_tx_timestamp(skb); |
ac718b69 | 2938 | |
61598788 | 2939 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2940 | |
0c3121fc | 2941 | if (!list_empty(&tp->tx_free)) { |
2942 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d2187f8e | 2943 | set_bit(SCHEDULE_TASKLET, &tp->flags); |
0c3121fc | 2944 | schedule_delayed_work(&tp->schedule, 0); |
2945 | } else { | |
2946 | usb_mark_last_busy(tp->udev); | |
d2187f8e | 2947 | tasklet_schedule(&tp->tx_tl); |
0c3121fc | 2948 | } |
b209af99 | 2949 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2950 | netif_stop_queue(netdev); |
b209af99 | 2951 | } |
dd1b119c | 2952 | |
ac718b69 | 2953 | return NETDEV_TX_OK; |
2954 | } | |
2955 | ||
2956 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2957 | { | |
195aae32 | 2958 | u32 ocp_data; |
ac718b69 | 2959 | |
2960 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2961 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2962 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2963 | ocp_data |= FMC_FCR_MCU_EN; | |
2964 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2965 | } | |
2966 | ||
2967 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2968 | { | |
195aae32 HW |
2969 | u32 ocp_data; |
2970 | int i; | |
ac718b69 | 2971 | |
195aae32 HW |
2972 | switch (tp->version) { |
2973 | case RTL_TEST_01: | |
2974 | case RTL_VER_10: | |
2975 | case RTL_VER_11: | |
2976 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2977 | ocp_data &= ~CR_TE; | |
2978 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2979 | ||
2980 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2981 | ocp_data &= ~BMU_RESET_EP_IN; | |
2982 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2983 | ||
2984 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
2985 | ocp_data |= CDC_ECM_EN; | |
2986 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2987 | ||
2988 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2989 | ocp_data &= ~CR_RE; | |
2990 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2991 | ||
2992 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2993 | ocp_data |= BMU_RESET_EP_IN; | |
2994 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2995 | ||
2996 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
2997 | ocp_data &= ~CDC_ECM_EN; | |
2998 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2999 | break; | |
ac718b69 | 3000 | |
195aae32 HW |
3001 | default: |
3002 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
3003 | ||
3004 | for (i = 0; i < 1000; i++) { | |
32a574c7 DA |
3005 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
3006 | break; | |
195aae32 HW |
3007 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) |
3008 | break; | |
3009 | usleep_range(100, 400); | |
3010 | } | |
3011 | break; | |
ac718b69 | 3012 | } |
3013 | } | |
3014 | ||
dd1b119c | 3015 | static void set_tx_qlen(struct r8152 *tp) |
3016 | { | |
67ce1a80 | 3017 | tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); |
dd1b119c | 3018 | } |
3019 | ||
195aae32 | 3020 | static inline u16 rtl8152_get_speed(struct r8152 *tp) |
ac718b69 | 3021 | { |
195aae32 | 3022 | return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); |
ac718b69 | 3023 | } |
3024 | ||
40fa7568 | 3025 | static void rtl_eee_plus_en(struct r8152 *tp, bool enable) |
ac718b69 | 3026 | { |
ebc2ec48 | 3027 | u32 ocp_data; |
ac718b69 | 3028 | |
40fa7568 HW |
3029 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
3030 | if (enable) | |
ebc2ec48 | 3031 | ocp_data |= EEEP_CR_EEEP_TX; |
40fa7568 | 3032 | else |
ebc2ec48 | 3033 | ocp_data &= ~EEEP_CR_EEEP_TX; |
40fa7568 HW |
3034 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
3035 | } | |
3036 | ||
3037 | static void rtl_set_eee_plus(struct r8152 *tp) | |
3038 | { | |
3039 | if (rtl8152_get_speed(tp) & _10bps) | |
3040 | rtl_eee_plus_en(tp, true); | |
3041 | else | |
3042 | rtl_eee_plus_en(tp, false); | |
507605a8 | 3043 | } |
3044 | ||
00a5e360 | 3045 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
3046 | { | |
3047 | u32 ocp_data; | |
3048 | ||
3049 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
3050 | if (enable) | |
3051 | ocp_data |= RXDY_GATED_EN; | |
3052 | else | |
3053 | ocp_data &= ~RXDY_GATED_EN; | |
3054 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
3055 | } | |
3056 | ||
445f7f4d | 3057 | static int rtl_start_rx(struct r8152 *tp) |
3058 | { | |
252df8b8 HW |
3059 | struct rx_agg *agg, *agg_next; |
3060 | struct list_head tmp_list; | |
3061 | unsigned long flags; | |
47922fcd | 3062 | int ret = 0, i = 0; |
445f7f4d | 3063 | |
252df8b8 | 3064 | INIT_LIST_HEAD(&tmp_list); |
445f7f4d | 3065 | |
252df8b8 | 3066 | spin_lock_irqsave(&tp->rx_lock, flags); |
7bcf4f60 | 3067 | |
252df8b8 | 3068 | INIT_LIST_HEAD(&tp->rx_done); |
47922fcd | 3069 | INIT_LIST_HEAD(&tp->rx_used); |
7bcf4f60 | 3070 | |
252df8b8 | 3071 | list_splice_init(&tp->rx_info, &tmp_list); |
7bcf4f60 | 3072 | |
252df8b8 | 3073 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
7bcf4f60 | 3074 | |
252df8b8 HW |
3075 | list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { |
3076 | INIT_LIST_HEAD(&agg->list); | |
3077 | ||
47922fcd HW |
3078 | /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ |
3079 | if (++i > RTL8152_MAX_RX) { | |
3080 | spin_lock_irqsave(&tp->rx_lock, flags); | |
3081 | list_add_tail(&agg->list, &tp->rx_used); | |
3082 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
3083 | } else if (unlikely(ret < 0)) { | |
3084 | spin_lock_irqsave(&tp->rx_lock, flags); | |
252df8b8 | 3085 | list_add_tail(&agg->list, &tp->rx_done); |
47922fcd HW |
3086 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
3087 | } else { | |
252df8b8 | 3088 | ret = r8152_submit_rx(tp, agg, GFP_KERNEL); |
47922fcd | 3089 | } |
7bcf4f60 | 3090 | } |
3091 | ||
252df8b8 HW |
3092 | spin_lock_irqsave(&tp->rx_lock, flags); |
3093 | WARN_ON(!list_empty(&tp->rx_info)); | |
3094 | list_splice(&tmp_list, &tp->rx_info); | |
3095 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
3096 | ||
445f7f4d | 3097 | return ret; |
3098 | } | |
3099 | ||
3100 | static int rtl_stop_rx(struct r8152 *tp) | |
3101 | { | |
252df8b8 HW |
3102 | struct rx_agg *agg, *agg_next; |
3103 | struct list_head tmp_list; | |
3104 | unsigned long flags; | |
3105 | ||
3106 | INIT_LIST_HEAD(&tmp_list); | |
3107 | ||
3108 | /* The usb_kill_urb() couldn't be used in atomic. | |
3109 | * Therefore, move the list of rx_info to a tmp one. | |
3110 | * Then, list_for_each_entry_safe could be used without | |
3111 | * spin lock. | |
3112 | */ | |
3113 | ||
3114 | spin_lock_irqsave(&tp->rx_lock, flags); | |
3115 | list_splice_init(&tp->rx_info, &tmp_list); | |
3116 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
3117 | ||
47922fcd HW |
3118 | list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { |
3119 | /* At least RTL8152_MAX_RX rx_agg have the page_count being | |
3120 | * equal to 1, so the other ones could be freed safely. | |
3121 | */ | |
3122 | if (page_count(agg->page) > 1) | |
3123 | free_rx_agg(tp, agg); | |
3124 | else | |
3125 | usb_kill_urb(agg->urb); | |
3126 | } | |
445f7f4d | 3127 | |
252df8b8 HW |
3128 | /* Move back the list of temp to the rx_info */ |
3129 | spin_lock_irqsave(&tp->rx_lock, flags); | |
3130 | WARN_ON(!list_empty(&tp->rx_info)); | |
3131 | list_splice(&tmp_list, &tp->rx_info); | |
3132 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
445f7f4d | 3133 | |
d823ab68 | 3134 | while (!skb_queue_empty(&tp->rx_queue)) |
3135 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
3136 | ||
445f7f4d | 3137 | return 0; |
3138 | } | |
3139 | ||
5133bcc7 HW |
3140 | static void rtl_set_ifg(struct r8152 *tp, u16 speed) |
3141 | { | |
3142 | u32 ocp_data; | |
3143 | ||
3144 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3145 | ocp_data &= ~IFG_MASK; | |
3146 | if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { | |
3147 | ocp_data |= IFG_144NS; | |
3148 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); | |
3149 | ||
3150 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
3151 | ocp_data &= ~TX10MIDLE_EN; | |
3152 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
3153 | } else { | |
3154 | ocp_data |= IFG_96NS; | |
3155 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); | |
3156 | ||
3157 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
3158 | ocp_data |= TX10MIDLE_EN; | |
3159 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
3160 | } | |
3161 | } | |
3162 | ||
9fae5418 HW |
3163 | static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) |
3164 | { | |
3165 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, | |
3166 | OWN_UPDATE | OWN_CLEAR); | |
3167 | } | |
3168 | ||
507605a8 | 3169 | static int rtl_enable(struct r8152 *tp) |
3170 | { | |
3171 | u32 ocp_data; | |
ac718b69 | 3172 | |
3173 | r8152b_reset_packet_filter(tp); | |
3174 | ||
3175 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
3176 | ocp_data |= CR_RE | CR_TE; | |
3177 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
3178 | ||
9fae5418 | 3179 | switch (tp->version) { |
cce8334f HW |
3180 | case RTL_VER_01: |
3181 | case RTL_VER_02: | |
3182 | case RTL_VER_03: | |
3183 | case RTL_VER_04: | |
3184 | case RTL_VER_05: | |
3185 | case RTL_VER_06: | |
3186 | case RTL_VER_07: | |
9fae5418 HW |
3187 | break; |
3188 | default: | |
cce8334f | 3189 | r8153b_rx_agg_chg_indicate(tp); |
9fae5418 HW |
3190 | break; |
3191 | } | |
3192 | ||
00a5e360 | 3193 | rxdy_gated_en(tp, false); |
ac718b69 | 3194 | |
aa2e0926 | 3195 | return 0; |
ac718b69 | 3196 | } |
3197 | ||
507605a8 | 3198 | static int rtl8152_enable(struct r8152 *tp) |
3199 | { | |
715f67f3 | 3200 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 3201 | return -ENODEV; |
3202 | ||
507605a8 | 3203 | set_tx_qlen(tp); |
3204 | rtl_set_eee_plus(tp); | |
3205 | ||
3206 | return rtl_enable(tp); | |
3207 | } | |
3208 | ||
464ec10a | 3209 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 3210 | { |
464ec10a | 3211 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 3212 | |
65b82d69 | 3213 | switch (tp->version) { |
3214 | case RTL_VER_03: | |
3215 | case RTL_VER_04: | |
3216 | case RTL_VER_05: | |
3217 | case RTL_VER_06: | |
3218 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3219 | ocp_data); | |
3220 | break; | |
3221 | ||
3222 | case RTL_VER_08: | |
3223 | case RTL_VER_09: | |
195aae32 | 3224 | case RTL_VER_14: |
65b82d69 | 3225 | /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout |
3226 | * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. | |
3227 | */ | |
3228 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3229 | 128 / 8); | |
3230 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
3231 | ocp_data); | |
65b82d69 | 3232 | break; |
3233 | ||
195aae32 HW |
3234 | case RTL_VER_10: |
3235 | case RTL_VER_11: | |
3236 | case RTL_VER_12: | |
3237 | case RTL_VER_13: | |
3238 | case RTL_VER_15: | |
3239 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
3240 | 640 / 8); | |
3241 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
3242 | ocp_data); | |
195aae32 HW |
3243 | break; |
3244 | ||
65b82d69 | 3245 | default: |
3246 | break; | |
3247 | } | |
464ec10a | 3248 | } |
3249 | ||
3250 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
3251 | { | |
ec5791c2 | 3252 | u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); |
464ec10a | 3253 | |
65b82d69 | 3254 | switch (tp->version) { |
3255 | case RTL_VER_03: | |
3256 | case RTL_VER_04: | |
3257 | case RTL_VER_05: | |
3258 | case RTL_VER_06: | |
3259 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
3260 | ocp_data / 4); | |
3261 | break; | |
3262 | case RTL_VER_08: | |
3263 | case RTL_VER_09: | |
195aae32 HW |
3264 | case RTL_VER_14: |
3265 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
3266 | ocp_data / 8); | |
3267 | break; | |
3268 | case RTL_TEST_01: | |
3269 | case RTL_VER_10: | |
3270 | case RTL_VER_11: | |
3271 | case RTL_VER_12: | |
3272 | case RTL_VER_13: | |
3273 | case RTL_VER_15: | |
65b82d69 | 3274 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, |
3275 | ocp_data / 8); | |
65b82d69 | 3276 | break; |
3277 | default: | |
3278 | WARN_ON_ONCE(1); | |
3279 | break; | |
3280 | } | |
43779f8d | 3281 | } |
3282 | ||
3283 | static int rtl8153_enable(struct r8152 *tp) | |
3284 | { | |
195aae32 HW |
3285 | u32 ocp_data; |
3286 | ||
715f67f3 | 3287 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 3288 | return -ENODEV; |
3289 | ||
43779f8d | 3290 | set_tx_qlen(tp); |
3291 | rtl_set_eee_plus(tp); | |
464ec10a | 3292 | r8153_set_rx_early_timeout(tp); |
3293 | r8153_set_rx_early_size(tp); | |
43779f8d | 3294 | |
5133bcc7 HW |
3295 | rtl_set_ifg(tp, rtl8152_get_speed(tp)); |
3296 | ||
195aae32 HW |
3297 | switch (tp->version) { |
3298 | case RTL_VER_09: | |
3299 | case RTL_VER_14: | |
f99cd20e HW |
3300 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); |
3301 | ocp_data &= ~FC_PATCH_TASK; | |
3302 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
3303 | usleep_range(1000, 2000); | |
3304 | ocp_data |= FC_PATCH_TASK; | |
3305 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
195aae32 HW |
3306 | break; |
3307 | default: | |
3308 | break; | |
f99cd20e HW |
3309 | } |
3310 | ||
43779f8d | 3311 | return rtl_enable(tp); |
3312 | } | |
3313 | ||
d70b1137 | 3314 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 3315 | { |
ebc2ec48 | 3316 | u32 ocp_data; |
3317 | int i; | |
ac718b69 | 3318 | |
715f67f3 | 3319 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
6871438c | 3320 | rtl_drop_queued_tx(tp); |
3321 | return; | |
3322 | } | |
3323 | ||
ac718b69 | 3324 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
3325 | ocp_data &= ~RCR_ACPT_ALL; | |
3326 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3327 | ||
00a5e360 | 3328 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 3329 | |
3330 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
3331 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 3332 | |
00a5e360 | 3333 | rxdy_gated_en(tp, true); |
ac718b69 | 3334 | |
3335 | for (i = 0; i < 1000; i++) { | |
32a574c7 DA |
3336 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
3337 | break; | |
ac718b69 | 3338 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
3339 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
3340 | break; | |
8ddfa077 | 3341 | usleep_range(1000, 2000); |
ac718b69 | 3342 | } |
3343 | ||
3344 | for (i = 0; i < 1000; i++) { | |
32a574c7 DA |
3345 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
3346 | break; | |
ac718b69 | 3347 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) |
3348 | break; | |
8ddfa077 | 3349 | usleep_range(1000, 2000); |
ac718b69 | 3350 | } |
3351 | ||
445f7f4d | 3352 | rtl_stop_rx(tp); |
ac718b69 | 3353 | |
3354 | rtl8152_nic_reset(tp); | |
3355 | } | |
3356 | ||
00a5e360 | 3357 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
3358 | { | |
3359 | u32 ocp_data; | |
3360 | ||
3361 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
3362 | if (enable) | |
3363 | ocp_data |= POWER_CUT; | |
3364 | else | |
3365 | ocp_data &= ~POWER_CUT; | |
3366 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
3367 | ||
3368 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
3369 | ocp_data &= ~RESUME_INDICATE; | |
3370 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 3371 | } |
3372 | ||
c5554298 | 3373 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
3374 | { | |
3375 | u32 ocp_data; | |
3376 | ||
195aae32 HW |
3377 | switch (tp->version) { |
3378 | case RTL_VER_01: | |
3379 | case RTL_VER_02: | |
3380 | case RTL_VER_03: | |
3381 | case RTL_VER_04: | |
3382 | case RTL_VER_05: | |
3383 | case RTL_VER_06: | |
3384 | case RTL_VER_07: | |
3385 | case RTL_VER_08: | |
3386 | case RTL_VER_09: | |
3387 | case RTL_VER_14: | |
3388 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
3389 | if (enable) | |
3390 | ocp_data |= CPCR_RX_VLAN; | |
3391 | else | |
3392 | ocp_data &= ~CPCR_RX_VLAN; | |
3393 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
3394 | break; | |
3395 | ||
3396 | case RTL_TEST_01: | |
3397 | case RTL_VER_10: | |
3398 | case RTL_VER_11: | |
3399 | case RTL_VER_12: | |
3400 | case RTL_VER_13: | |
3401 | case RTL_VER_15: | |
3402 | default: | |
3403 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); | |
3404 | if (enable) | |
3405 | ocp_data |= OUTER_VLAN | INNER_VLAN; | |
3406 | else | |
3407 | ocp_data &= ~(OUTER_VLAN | INNER_VLAN); | |
3408 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); | |
3409 | break; | |
3410 | } | |
c5554298 | 3411 | } |
3412 | ||
3413 | static int rtl8152_set_features(struct net_device *dev, | |
3414 | netdev_features_t features) | |
3415 | { | |
3416 | netdev_features_t changed = features ^ dev->features; | |
3417 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 3418 | int ret; |
3419 | ||
3420 | ret = usb_autopm_get_interface(tp->intf); | |
3421 | if (ret < 0) | |
3422 | goto out; | |
c5554298 | 3423 | |
b5403273 | 3424 | mutex_lock(&tp->control); |
3425 | ||
c5554298 | 3426 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
3427 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
3428 | rtl_rx_vlan_en(tp, true); | |
3429 | else | |
3430 | rtl_rx_vlan_en(tp, false); | |
3431 | } | |
3432 | ||
b5403273 | 3433 | mutex_unlock(&tp->control); |
3434 | ||
405f8a0e | 3435 | usb_autopm_put_interface(tp->intf); |
3436 | ||
3437 | out: | |
3438 | return ret; | |
c5554298 | 3439 | } |
3440 | ||
21ff2e89 | 3441 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
3442 | ||
3443 | static u32 __rtl_get_wol(struct r8152 *tp) | |
3444 | { | |
3445 | u32 ocp_data; | |
3446 | u32 wolopts = 0; | |
3447 | ||
21ff2e89 | 3448 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
3449 | if (ocp_data & LINK_ON_WAKE_EN) | |
3450 | wolopts |= WAKE_PHY; | |
3451 | ||
3452 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
3453 | if (ocp_data & UWF_EN) | |
3454 | wolopts |= WAKE_UCAST; | |
3455 | if (ocp_data & BWF_EN) | |
3456 | wolopts |= WAKE_BCAST; | |
3457 | if (ocp_data & MWF_EN) | |
3458 | wolopts |= WAKE_MCAST; | |
3459 | ||
3460 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
3461 | if (ocp_data & MAGIC_EN) | |
3462 | wolopts |= WAKE_MAGIC; | |
3463 | ||
3464 | return wolopts; | |
3465 | } | |
3466 | ||
3467 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
3468 | { | |
3469 | u32 ocp_data; | |
3470 | ||
3471 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3472 | ||
3473 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3474 | ocp_data &= ~LINK_ON_WAKE_EN; | |
3475 | if (wolopts & WAKE_PHY) | |
3476 | ocp_data |= LINK_ON_WAKE_EN; | |
3477 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3478 | ||
3479 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 3480 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 3481 | if (wolopts & WAKE_UCAST) |
3482 | ocp_data |= UWF_EN; | |
3483 | if (wolopts & WAKE_BCAST) | |
3484 | ocp_data |= BWF_EN; | |
3485 | if (wolopts & WAKE_MCAST) | |
3486 | ocp_data |= MWF_EN; | |
21ff2e89 | 3487 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
3488 | ||
3489 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3490 | ||
3491 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
3492 | ocp_data &= ~MAGIC_EN; | |
3493 | if (wolopts & WAKE_MAGIC) | |
3494 | ocp_data |= MAGIC_EN; | |
3495 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
3496 | ||
3497 | if (wolopts & WAKE_ANY) | |
3498 | device_set_wakeup_enable(&tp->udev->dev, true); | |
3499 | else | |
3500 | device_set_wakeup_enable(&tp->udev->dev, false); | |
3501 | } | |
3502 | ||
195aae32 HW |
3503 | static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) |
3504 | { | |
3505 | u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3506 | ||
3507 | /* MAC clock speed down */ | |
3508 | if (enable) | |
3509 | ocp_data |= MAC_CLK_SPDWN_EN; | |
3510 | else | |
3511 | ocp_data &= ~MAC_CLK_SPDWN_EN; | |
3512 | ||
3513 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3514 | } | |
3515 | ||
3516 | static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) | |
3517 | { | |
3518 | u32 ocp_data; | |
3519 | ||
3520 | /* MAC clock speed down */ | |
3521 | if (enable) { | |
3522 | /* aldps_spdwn_ratio, tp10_spdwn_ratio */ | |
3523 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
3524 | 0x0403); | |
3525 | ||
3526 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3527 | ocp_data &= ~EEE_SPDWN_RATIO_MASK; | |
3528 | ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ | |
3529 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3530 | } else { | |
3531 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
3532 | ocp_data &= ~MAC_CLK_SPDWN_EN; | |
3533 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
3534 | } | |
3535 | } | |
3536 | ||
b214396f | 3537 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
3538 | { | |
3539 | u8 u1u2[8]; | |
3540 | ||
3541 | if (enable) | |
3542 | memset(u1u2, 0xff, sizeof(u1u2)); | |
3543 | else | |
3544 | memset(u1u2, 0x00, sizeof(u1u2)); | |
3545 | ||
3546 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
3547 | } | |
3548 | ||
65b82d69 | 3549 | static void r8153b_u1u2en(struct r8152 *tp, bool enable) |
3550 | { | |
3551 | u32 ocp_data; | |
3552 | ||
3553 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); | |
3554 | if (enable) | |
3555 | ocp_data |= LPM_U1U2_EN; | |
3556 | else | |
3557 | ocp_data &= ~LPM_U1U2_EN; | |
3558 | ||
3559 | ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); | |
3560 | } | |
3561 | ||
b214396f | 3562 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
3563 | { | |
3564 | u32 ocp_data; | |
3565 | ||
3566 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
3cb3234e | 3567 | if (enable) |
b214396f | 3568 | ocp_data |= U2P3_ENABLE; |
3569 | else | |
3570 | ocp_data &= ~U2P3_ENABLE; | |
3571 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
3572 | } | |
3573 | ||
0e5b36bc | 3574 | static void r8153b_ups_flags(struct r8152 *tp) |
65b82d69 | 3575 | { |
0e5b36bc HW |
3576 | u32 ups_flags = 0; |
3577 | ||
3578 | if (tp->ups_info.green) | |
3579 | ups_flags |= UPS_FLAGS_EN_GREEN; | |
3580 | ||
3581 | if (tp->ups_info.aldps) | |
3582 | ups_flags |= UPS_FLAGS_EN_ALDPS; | |
3583 | ||
3584 | if (tp->ups_info.eee) | |
3585 | ups_flags |= UPS_FLAGS_EN_EEE; | |
3586 | ||
3587 | if (tp->ups_info.flow_control) | |
3588 | ups_flags |= UPS_FLAGS_EN_FLOW_CTR; | |
3589 | ||
3590 | if (tp->ups_info.eee_ckdiv) | |
3591 | ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; | |
3592 | ||
3593 | if (tp->ups_info.eee_cmod_lv) | |
3594 | ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; | |
3595 | ||
195aae32 HW |
3596 | if (tp->ups_info.r_tune) |
3597 | ups_flags |= UPS_FLAGS_R_TUNE; | |
3598 | ||
0e5b36bc HW |
3599 | if (tp->ups_info._10m_ckdiv) |
3600 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV; | |
3601 | ||
3602 | if (tp->ups_info.eee_plloff_100) | |
3603 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; | |
65b82d69 | 3604 | |
0e5b36bc HW |
3605 | if (tp->ups_info.eee_plloff_giga) |
3606 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3607 | ||
3608 | if (tp->ups_info._250m_ckdiv) | |
3609 | ups_flags |= UPS_FLAGS_250M_CKDIV; | |
3610 | ||
3611 | if (tp->ups_info.ctap_short_off) | |
3612 | ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS; | |
3613 | ||
3614 | switch (tp->ups_info.speed_duplex) { | |
3615 | case NWAY_10M_HALF: | |
3616 | ups_flags |= ups_flags_speed(1); | |
3617 | break; | |
3618 | case NWAY_10M_FULL: | |
3619 | ups_flags |= ups_flags_speed(2); | |
3620 | break; | |
3621 | case NWAY_100M_HALF: | |
3622 | ups_flags |= ups_flags_speed(3); | |
3623 | break; | |
3624 | case NWAY_100M_FULL: | |
3625 | ups_flags |= ups_flags_speed(4); | |
3626 | break; | |
3627 | case NWAY_1000M_FULL: | |
3628 | ups_flags |= ups_flags_speed(5); | |
3629 | break; | |
3630 | case FORCE_10M_HALF: | |
3631 | ups_flags |= ups_flags_speed(6); | |
3632 | break; | |
3633 | case FORCE_10M_FULL: | |
3634 | ups_flags |= ups_flags_speed(7); | |
3635 | break; | |
3636 | case FORCE_100M_HALF: | |
3637 | ups_flags |= ups_flags_speed(8); | |
3638 | break; | |
3639 | case FORCE_100M_FULL: | |
3640 | ups_flags |= ups_flags_speed(9); | |
3641 | break; | |
3642 | default: | |
3643 | break; | |
3644 | } | |
3645 | ||
3646 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); | |
65b82d69 | 3647 | } |
3648 | ||
195aae32 HW |
3649 | static void r8156_ups_flags(struct r8152 *tp) |
3650 | { | |
3651 | u32 ups_flags = 0; | |
3652 | ||
3653 | if (tp->ups_info.green) | |
3654 | ups_flags |= UPS_FLAGS_EN_GREEN; | |
3655 | ||
3656 | if (tp->ups_info.aldps) | |
3657 | ups_flags |= UPS_FLAGS_EN_ALDPS; | |
3658 | ||
3659 | if (tp->ups_info.eee) | |
3660 | ups_flags |= UPS_FLAGS_EN_EEE; | |
3661 | ||
3662 | if (tp->ups_info.flow_control) | |
3663 | ups_flags |= UPS_FLAGS_EN_FLOW_CTR; | |
3664 | ||
3665 | if (tp->ups_info.eee_ckdiv) | |
3666 | ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; | |
3667 | ||
3668 | if (tp->ups_info._10m_ckdiv) | |
3669 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV; | |
3670 | ||
3671 | if (tp->ups_info.eee_plloff_100) | |
3672 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; | |
3673 | ||
3674 | if (tp->ups_info.eee_plloff_giga) | |
3675 | ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3676 | ||
3677 | if (tp->ups_info._250m_ckdiv) | |
3678 | ups_flags |= UPS_FLAGS_250M_CKDIV; | |
3679 | ||
3680 | switch (tp->ups_info.speed_duplex) { | |
3681 | case FORCE_10M_HALF: | |
3682 | ups_flags |= ups_flags_speed(0); | |
3683 | break; | |
3684 | case FORCE_10M_FULL: | |
3685 | ups_flags |= ups_flags_speed(1); | |
3686 | break; | |
3687 | case FORCE_100M_HALF: | |
3688 | ups_flags |= ups_flags_speed(2); | |
3689 | break; | |
3690 | case FORCE_100M_FULL: | |
3691 | ups_flags |= ups_flags_speed(3); | |
3692 | break; | |
3693 | case NWAY_10M_HALF: | |
3694 | ups_flags |= ups_flags_speed(4); | |
3695 | break; | |
3696 | case NWAY_10M_FULL: | |
3697 | ups_flags |= ups_flags_speed(5); | |
3698 | break; | |
3699 | case NWAY_100M_HALF: | |
3700 | ups_flags |= ups_flags_speed(6); | |
3701 | break; | |
3702 | case NWAY_100M_FULL: | |
3703 | ups_flags |= ups_flags_speed(7); | |
3704 | break; | |
3705 | case NWAY_1000M_FULL: | |
3706 | ups_flags |= ups_flags_speed(8); | |
3707 | break; | |
3708 | case NWAY_2500M_FULL: | |
3709 | ups_flags |= ups_flags_speed(9); | |
3710 | break; | |
3711 | default: | |
3712 | break; | |
3713 | } | |
3714 | ||
3715 | switch (tp->ups_info.lite_mode) { | |
3716 | case 1: | |
3717 | ups_flags |= 0 << 5; | |
3718 | break; | |
3719 | case 2: | |
3720 | ups_flags |= 2 << 5; | |
3721 | break; | |
3722 | case 0: | |
3723 | default: | |
3724 | ups_flags |= 1 << 5; | |
3725 | break; | |
3726 | } | |
3727 | ||
3728 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); | |
3729 | } | |
3730 | ||
40fa7568 | 3731 | static void rtl_green_en(struct r8152 *tp, bool enable) |
65b82d69 | 3732 | { |
3733 | u16 data; | |
3734 | ||
40fa7568 HW |
3735 | data = sram_read(tp, SRAM_GREEN_CFG); |
3736 | if (enable) | |
3737 | data |= GREEN_ETH_EN; | |
3738 | else | |
3739 | data &= ~GREEN_ETH_EN; | |
3740 | sram_write(tp, SRAM_GREEN_CFG, data); | |
3741 | ||
3742 | tp->ups_info.green = enable; | |
3743 | } | |
3744 | ||
3745 | static void r8153b_green_en(struct r8152 *tp, bool enable) | |
3746 | { | |
65b82d69 | 3747 | if (enable) { |
3748 | sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ | |
3749 | sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ | |
3750 | sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ | |
3751 | } else { | |
3752 | sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ | |
3753 | sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ | |
3754 | sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ | |
3755 | } | |
3756 | ||
40fa7568 | 3757 | rtl_green_en(tp, true); |
65b82d69 | 3758 | } |
3759 | ||
c564b871 | 3760 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
3761 | { | |
3762 | u16 data; | |
3763 | int i; | |
3764 | ||
3765 | for (i = 0; i < 500; i++) { | |
3766 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
3767 | data &= PHY_STAT_MASK; | |
3768 | if (desired) { | |
3769 | if (data == desired) | |
3770 | break; | |
3771 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
3772 | data == PHY_STAT_EXT_INIT) { | |
3773 | break; | |
3774 | } | |
3775 | ||
3776 | msleep(20); | |
715f67f3 | 3777 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
d64c7a08 | 3778 | break; |
c564b871 | 3779 | } |
3780 | ||
3781 | return data; | |
3782 | } | |
3783 | ||
65b82d69 | 3784 | static void r8153b_ups_en(struct r8152 *tp, bool enable) |
3785 | { | |
3786 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3787 | ||
3788 | if (enable) { | |
0e5b36bc HW |
3789 | r8153b_ups_flags(tp); |
3790 | ||
65b82d69 | 3791 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; |
3792 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3793 | ||
195aae32 HW |
3794 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); |
3795 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3796 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3797 | } else { | |
3798 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
3799 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3800 | ||
3801 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3802 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3803 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3804 | ||
3805 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { | |
3806 | int i; | |
3807 | ||
3808 | for (i = 0; i < 500; i++) { | |
715f67f3 | 3809 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
bc65cc42 | 3810 | return; |
195aae32 HW |
3811 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & |
3812 | AUTOLOAD_DONE) | |
3813 | break; | |
3814 | msleep(20); | |
3815 | } | |
3816 | ||
3817 | tp->rtl_ops.hw_phy_cfg(tp); | |
3818 | ||
3819 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, | |
3820 | tp->duplex, tp->advertising); | |
3821 | } | |
3822 | } | |
3823 | } | |
3824 | ||
3825 | static void r8153c_ups_en(struct r8152 *tp, bool enable) | |
3826 | { | |
3827 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3828 | ||
3829 | if (enable) { | |
3830 | r8153b_ups_flags(tp); | |
3831 | ||
3832 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
3833 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3834 | ||
3835 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3836 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3837 | ocp_data &= ~BIT(7); | |
3838 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
65b82d69 | 3839 | } else { |
65b82d69 | 3840 | ocp_data &= ~(UPS_EN | USP_PREWAKE); |
3841 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3842 | ||
195aae32 HW |
3843 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); |
3844 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3845 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
65b82d69 | 3846 | |
80fd850b HW |
3847 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { |
3848 | int i; | |
65b82d69 | 3849 | |
80fd850b | 3850 | for (i = 0; i < 500; i++) { |
715f67f3 | 3851 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
bc65cc42 | 3852 | return; |
80fd850b HW |
3853 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & |
3854 | AUTOLOAD_DONE) | |
3855 | break; | |
3856 | msleep(20); | |
3857 | } | |
65b82d69 | 3858 | |
80fd850b | 3859 | tp->rtl_ops.hw_phy_cfg(tp); |
65b82d69 | 3860 | |
80fd850b HW |
3861 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, |
3862 | tp->duplex, tp->advertising); | |
65b82d69 | 3863 | } |
195aae32 HW |
3864 | |
3865 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3866 | ||
3867 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3868 | ocp_data |= BIT(8); | |
3869 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3870 | ||
3871 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3872 | } | |
3873 | } | |
3874 | ||
3875 | static void r8156_ups_en(struct r8152 *tp, bool enable) | |
3876 | { | |
3877 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3878 | ||
3879 | if (enable) { | |
3880 | r8156_ups_flags(tp); | |
3881 | ||
3882 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
3883 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3884 | ||
3885 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3886 | ocp_data |= UPS_FORCE_PWR_DOWN; | |
3887 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3888 | ||
3889 | switch (tp->version) { | |
3890 | case RTL_VER_13: | |
3891 | case RTL_VER_15: | |
3892 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); | |
3893 | ocp_data &= ~OOBS_POLLING; | |
3894 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); | |
3895 | break; | |
3896 | default: | |
3897 | break; | |
3898 | } | |
3899 | } else { | |
3900 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
3901 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3902 | ||
3903 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
3904 | ocp_data &= ~UPS_FORCE_PWR_DOWN; | |
3905 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
3906 | ||
3907 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { | |
3908 | tp->rtl_ops.hw_phy_cfg(tp); | |
3909 | ||
3910 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, | |
3911 | tp->duplex, tp->advertising); | |
3912 | } | |
65b82d69 | 3913 | } |
3914 | } | |
3915 | ||
b214396f | 3916 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
3917 | { | |
3918 | u32 ocp_data; | |
3919 | ||
3920 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3921 | if (enable) | |
3922 | ocp_data |= PWR_EN | PHASE2_EN; | |
3923 | else | |
3924 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
3925 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3926 | ||
3927 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
3928 | ocp_data &= ~PCUT_STATUS; | |
3929 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
3930 | } | |
3931 | ||
65b82d69 | 3932 | static void r8153b_power_cut_en(struct r8152 *tp, bool enable) |
3933 | { | |
3934 | u32 ocp_data; | |
3935 | ||
3936 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
3937 | if (enable) | |
3938 | ocp_data |= PWR_EN | PHASE2_EN; | |
3939 | else | |
3940 | ocp_data &= ~PWR_EN; | |
3941 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
3942 | ||
3943 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
3944 | ocp_data &= ~PCUT_STATUS; | |
3945 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
3946 | } | |
3947 | ||
13e04fbf | 3948 | static void r8153_queue_wake(struct r8152 *tp, bool enable) |
65b82d69 | 3949 | { |
3950 | u32 ocp_data; | |
3951 | ||
13e04fbf | 3952 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); |
65b82d69 | 3953 | if (enable) |
13e04fbf | 3954 | ocp_data |= UPCOMING_RUNTIME_D3; |
65b82d69 | 3955 | else |
13e04fbf HW |
3956 | ocp_data &= ~UPCOMING_RUNTIME_D3; |
3957 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); | |
3958 | ||
3959 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); | |
3960 | ocp_data &= ~LINK_CHG_EVENT; | |
3961 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); | |
65b82d69 | 3962 | |
13e04fbf HW |
3963 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
3964 | ocp_data &= ~LINK_CHANGE_FLAG; | |
3965 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
65b82d69 | 3966 | } |
3967 | ||
7daed8dc | 3968 | static bool rtl_can_wakeup(struct r8152 *tp) |
3969 | { | |
3970 | struct usb_device *udev = tp->udev; | |
3971 | ||
3972 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
3973 | } | |
3974 | ||
9a4be1bd | 3975 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
3976 | { | |
3977 | if (enable) { | |
3978 | u32 ocp_data; | |
3979 | ||
3980 | __rtl_set_wol(tp, WAKE_ANY); | |
3981 | ||
3982 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3983 | ||
3984 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3985 | ocp_data |= LINK_OFF_WAKE_EN; | |
3986 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3987 | ||
3988 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
3989 | } else { | |
f95ae8a0 | 3990 | u32 ocp_data; |
3991 | ||
9a4be1bd | 3992 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 3993 | |
3994 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
3995 | ||
3996 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
3997 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
3998 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
3999 | ||
4000 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 4001 | } |
4002 | } | |
f95ae8a0 | 4003 | |
2609af19 | 4004 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
4005 | { | |
2609af19 | 4006 | if (enable) { |
4007 | r8153_u1u2en(tp, false); | |
4008 | r8153_u2p3en(tp, false); | |
02552754 | 4009 | rtl_runtime_suspend_enable(tp, true); |
2609af19 | 4010 | } else { |
02552754 | 4011 | rtl_runtime_suspend_enable(tp, false); |
3cb3234e | 4012 | |
4013 | switch (tp->version) { | |
4014 | case RTL_VER_03: | |
4015 | case RTL_VER_04: | |
4016 | break; | |
4017 | case RTL_VER_05: | |
4018 | case RTL_VER_06: | |
4019 | default: | |
4020 | r8153_u2p3en(tp, true); | |
4021 | break; | |
4022 | } | |
4023 | ||
b214396f | 4024 | r8153_u1u2en(tp, true); |
9a4be1bd | 4025 | } |
4026 | } | |
4027 | ||
65b82d69 | 4028 | static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) |
4029 | { | |
4030 | if (enable) { | |
13e04fbf | 4031 | r8153_queue_wake(tp, true); |
65b82d69 | 4032 | r8153b_u1u2en(tp, false); |
4033 | r8153_u2p3en(tp, false); | |
4034 | rtl_runtime_suspend_enable(tp, true); | |
4035 | r8153b_ups_en(tp, true); | |
4036 | } else { | |
4037 | r8153b_ups_en(tp, false); | |
13e04fbf | 4038 | r8153_queue_wake(tp, false); |
65b82d69 | 4039 | rtl_runtime_suspend_enable(tp, false); |
7a0ae61a | 4040 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 4041 | r8153b_u1u2en(tp, true); |
65b82d69 | 4042 | } |
4043 | } | |
4044 | ||
195aae32 | 4045 | static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) |
4349968a | 4046 | { |
195aae32 HW |
4047 | if (enable) { |
4048 | r8153_queue_wake(tp, true); | |
4049 | r8153b_u1u2en(tp, false); | |
4050 | r8153_u2p3en(tp, false); | |
4051 | rtl_runtime_suspend_enable(tp, true); | |
4052 | r8153c_ups_en(tp, true); | |
4053 | } else { | |
4054 | r8153c_ups_en(tp, false); | |
4055 | r8153_queue_wake(tp, false); | |
4056 | rtl_runtime_suspend_enable(tp, false); | |
4057 | r8153b_u1u2en(tp, true); | |
4058 | } | |
4059 | } | |
4349968a | 4060 | |
195aae32 HW |
4061 | static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) |
4062 | { | |
4063 | if (enable) { | |
4064 | r8153_queue_wake(tp, true); | |
4065 | r8153b_u1u2en(tp, false); | |
4066 | r8153_u2p3en(tp, false); | |
4067 | rtl_runtime_suspend_enable(tp, true); | |
4068 | } else { | |
4069 | r8153_queue_wake(tp, false); | |
4070 | rtl_runtime_suspend_enable(tp, false); | |
4071 | r8153_u2p3en(tp, true); | |
4072 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
4073 | r8153b_u1u2en(tp, true); | |
4074 | } | |
4075 | } | |
4076 | ||
4077 | static void r8153_teredo_off(struct r8152 *tp) | |
4078 | { | |
4079 | u32 ocp_data; | |
4080 | ||
4081 | switch (tp->version) { | |
4082 | case RTL_VER_01: | |
4083 | case RTL_VER_02: | |
4084 | case RTL_VER_03: | |
4085 | case RTL_VER_04: | |
4086 | case RTL_VER_05: | |
4087 | case RTL_VER_06: | |
4088 | case RTL_VER_07: | |
4089 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
4090 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | | |
4091 | OOB_TEREDO_EN); | |
4092 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
4093 | break; | |
65b82d69 | 4094 | |
4095 | case RTL_VER_08: | |
4096 | case RTL_VER_09: | |
195aae32 HW |
4097 | case RTL_TEST_01: |
4098 | case RTL_VER_10: | |
4099 | case RTL_VER_11: | |
4100 | case RTL_VER_12: | |
4101 | case RTL_VER_13: | |
4102 | case RTL_VER_14: | |
4103 | case RTL_VER_15: | |
4104 | default: | |
65b82d69 | 4105 | /* The bit 0 ~ 7 are relative with teredo settings. They are |
4106 | * W1C (write 1 to clear), so set all 1 to disable it. | |
4107 | */ | |
4108 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); | |
4109 | break; | |
65b82d69 | 4110 | } |
4349968a | 4111 | |
4112 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
4113 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
4114 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
4115 | } | |
4116 | ||
93fe9b18 | 4117 | static void rtl_reset_bmu(struct r8152 *tp) |
4118 | { | |
4119 | u32 ocp_data; | |
4120 | ||
4121 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
4122 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
4123 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
4124 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
4125 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
4126 | } | |
4127 | ||
9370f2d0 HW |
4128 | /* Clear the bp to stop the firmware before loading a new one */ |
4129 | static void rtl_clear_bp(struct r8152 *tp, u16 type) | |
4130 | { | |
e5c266a6 HW |
4131 | u16 bp[16] = {0}; |
4132 | u16 bp_num; | |
6633fb83 | 4133 | |
e5c266a6 | 4134 | switch (tp->version) { |
9370f2d0 HW |
4135 | case RTL_VER_08: |
4136 | case RTL_VER_09: | |
195aae32 HW |
4137 | case RTL_VER_10: |
4138 | case RTL_VER_11: | |
4139 | case RTL_VER_12: | |
4140 | case RTL_VER_13: | |
195aae32 | 4141 | case RTL_VER_15: |
9370f2d0 | 4142 | if (type == MCU_TYPE_USB) { |
a876a33d | 4143 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); |
e5c266a6 HW |
4144 | bp_num = 16; |
4145 | break; | |
9370f2d0 | 4146 | } |
e5c266a6 HW |
4147 | fallthrough; |
4148 | case RTL_VER_03: | |
4149 | case RTL_VER_04: | |
4150 | case RTL_VER_05: | |
4151 | case RTL_VER_06: | |
4152 | ocp_write_byte(tp, type, PLA_BP_EN, 0); | |
4153 | fallthrough; | |
4154 | case RTL_VER_01: | |
4155 | case RTL_VER_02: | |
4156 | case RTL_VER_07: | |
4157 | bp_num = 8; | |
4158 | break; | |
4159 | case RTL_VER_14: | |
4160 | default: | |
4161 | ocp_write_word(tp, type, USB_BP2_EN, 0); | |
4162 | bp_num = 16; | |
9370f2d0 HW |
4163 | break; |
4164 | } | |
4165 | ||
e5c266a6 | 4166 | generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type); |
9370f2d0 HW |
4167 | |
4168 | /* wait 3 ms to make sure the firmware is stopped */ | |
4169 | usleep_range(3000, 6000); | |
4170 | ocp_write_word(tp, type, PLA_BP_BA, 0); | |
4171 | } | |
4172 | ||
b24edca3 HW |
4173 | static inline void rtl_reset_ocp_base(struct r8152 *tp) |
4174 | { | |
4175 | tp->ocp_base = -1; | |
4176 | } | |
4177 | ||
a08c0d30 | 4178 | static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) |
470e3919 | 4179 | { |
a08c0d30 | 4180 | u16 data, check; |
470e3919 HW |
4181 | int i; |
4182 | ||
4183 | data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); | |
a08c0d30 | 4184 | if (request) { |
470e3919 | 4185 | data |= PATCH_REQUEST; |
a08c0d30 HW |
4186 | check = 0; |
4187 | } else { | |
470e3919 | 4188 | data &= ~PATCH_REQUEST; |
a08c0d30 HW |
4189 | check = PATCH_READY; |
4190 | } | |
470e3919 HW |
4191 | ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); |
4192 | ||
a08c0d30 HW |
4193 | for (i = 0; wait && i < 5000; i++) { |
4194 | u32 ocp_data; | |
4195 | ||
715f67f3 DA |
4196 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
4197 | return -ENODEV; | |
dc90ba37 | 4198 | |
470e3919 | 4199 | usleep_range(1000, 2000); |
a08c0d30 HW |
4200 | ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); |
4201 | if ((ocp_data & PATCH_READY) ^ check) | |
470e3919 HW |
4202 | break; |
4203 | } | |
4204 | ||
a08c0d30 HW |
4205 | if (request && wait && |
4206 | !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { | |
4207 | dev_err(&tp->intf->dev, "PHY patch request fail\n"); | |
4208 | rtl_phy_patch_request(tp, false, false); | |
470e3919 HW |
4209 | return -ETIME; |
4210 | } else { | |
4211 | return 0; | |
4212 | } | |
4213 | } | |
4214 | ||
a08c0d30 | 4215 | static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) |
af14288f | 4216 | { |
a08c0d30 HW |
4217 | if (patch_key && key_addr) { |
4218 | sram_write(tp, key_addr, patch_key); | |
4219 | sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); | |
4220 | } else if (key_addr) { | |
4221 | u16 data; | |
af14288f | 4222 | |
a08c0d30 | 4223 | sram_write(tp, 0x0000, 0x0000); |
af14288f | 4224 | |
a08c0d30 HW |
4225 | data = ocp_reg_read(tp, OCP_PHY_LOCK); |
4226 | data &= ~PATCH_LOCK; | |
4227 | ocp_reg_write(tp, OCP_PHY_LOCK, data); | |
4228 | ||
4229 | sram_write(tp, key_addr, 0x0000); | |
4230 | } else { | |
4231 | WARN_ON_ONCE(1); | |
4232 | } | |
af14288f HW |
4233 | } |
4234 | ||
a08c0d30 HW |
4235 | static int |
4236 | rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) | |
af14288f | 4237 | { |
a08c0d30 HW |
4238 | if (rtl_phy_patch_request(tp, true, wait)) |
4239 | return -ETIME; | |
af14288f | 4240 | |
a08c0d30 | 4241 | rtl_patch_key_set(tp, key_addr, patch_key); |
af14288f | 4242 | |
a08c0d30 HW |
4243 | return 0; |
4244 | } | |
af14288f | 4245 | |
a08c0d30 HW |
4246 | static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) |
4247 | { | |
4248 | rtl_patch_key_set(tp, key_addr, 0); | |
af14288f | 4249 | |
a08c0d30 | 4250 | rtl_phy_patch_request(tp, false, wait); |
af14288f | 4251 | |
af14288f HW |
4252 | return 0; |
4253 | } | |
4254 | ||
4a51b0e8 HW |
4255 | static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) |
4256 | { | |
4257 | u16 fw_offset; | |
4258 | u32 length; | |
4259 | bool rc = false; | |
4260 | ||
4261 | switch (tp->version) { | |
4262 | case RTL_VER_01: | |
4263 | case RTL_VER_02: | |
4264 | case RTL_VER_03: | |
4265 | case RTL_VER_04: | |
4266 | case RTL_VER_05: | |
4267 | case RTL_VER_06: | |
4268 | case RTL_VER_07: | |
4269 | case RTL_VER_08: | |
4270 | case RTL_VER_09: | |
4271 | case RTL_VER_10: | |
4272 | case RTL_VER_11: | |
4273 | case RTL_VER_12: | |
4274 | case RTL_VER_14: | |
4275 | goto out; | |
4276 | case RTL_VER_13: | |
4277 | case RTL_VER_15: | |
4278 | default: | |
4279 | break; | |
4280 | } | |
4281 | ||
4282 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4283 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4284 | if (fw_offset < sizeof(*phy) || length <= fw_offset) { | |
4285 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4286 | goto out; | |
4287 | } | |
4288 | ||
4289 | length -= fw_offset; | |
4290 | if (length & 3) { | |
4291 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4292 | goto out; | |
4293 | } | |
4294 | ||
4295 | if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { | |
4296 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); | |
4297 | goto out; | |
4298 | } | |
4299 | ||
4300 | rc = true; | |
4301 | out: | |
4302 | return rc; | |
4303 | } | |
4304 | ||
4305 | static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) | |
4306 | { | |
4307 | bool rc = false; | |
4308 | ||
4309 | switch (tp->version) { | |
4310 | case RTL_VER_10: | |
4311 | case RTL_VER_11: | |
4312 | case RTL_VER_12: | |
4313 | case RTL_VER_13: | |
4314 | case RTL_VER_15: | |
4315 | break; | |
4316 | default: | |
4317 | goto out; | |
4318 | } | |
4319 | ||
4320 | if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) { | |
4321 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4322 | goto out; | |
4323 | } | |
4324 | ||
4325 | if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) { | |
4326 | dev_err(&tp->intf->dev, "invalid phy ver addr\n"); | |
4327 | goto out; | |
4328 | } | |
4329 | ||
4330 | rc = true; | |
4331 | out: | |
4332 | return rc; | |
4333 | } | |
4334 | ||
4335 | static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) | |
4336 | { | |
4337 | bool rc = false; | |
4338 | ||
4339 | switch (tp->version) { | |
4340 | case RTL_VER_10: | |
4341 | case RTL_VER_11: | |
4342 | case RTL_VER_12: | |
4343 | case RTL_VER_13: | |
4344 | case RTL_VER_15: | |
4345 | break; | |
4346 | default: | |
4347 | goto out; | |
4348 | } | |
4349 | ||
4350 | if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) { | |
4351 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4352 | goto out; | |
4353 | } | |
4354 | ||
4355 | if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD || | |
4356 | __le16_to_cpu(fix->setting.data) != BIT(7)) { | |
4357 | dev_err(&tp->intf->dev, "invalid phy fixup\n"); | |
4358 | goto out; | |
4359 | } | |
4360 | ||
4361 | rc = true; | |
4362 | out: | |
4363 | return rc; | |
4364 | } | |
4365 | ||
4366 | static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) | |
4367 | { | |
4368 | u16 fw_offset; | |
4369 | u32 length; | |
4370 | bool rc = false; | |
4371 | ||
4372 | switch (tp->version) { | |
4373 | case RTL_VER_10: | |
4374 | case RTL_VER_11: | |
4375 | case RTL_VER_12: | |
4376 | case RTL_VER_13: | |
4377 | case RTL_VER_15: | |
4378 | break; | |
4379 | default: | |
4380 | goto out; | |
4381 | } | |
4382 | ||
4383 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4384 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4385 | if (fw_offset < sizeof(*phy) || length <= fw_offset) { | |
4386 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4387 | goto out; | |
4388 | } | |
4389 | ||
4390 | length -= fw_offset; | |
4391 | if (length & 1) { | |
4392 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4393 | goto out; | |
4394 | } | |
4395 | ||
4396 | if (phy->pre_num > 2) { | |
4397 | dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num); | |
4398 | goto out; | |
4399 | } | |
4400 | ||
4401 | if (phy->bp_num > 8) { | |
4402 | dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num); | |
4403 | goto out; | |
4404 | } | |
4405 | ||
4406 | rc = true; | |
4407 | out: | |
4408 | return rc; | |
4409 | } | |
4410 | ||
af14288f HW |
4411 | static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) |
4412 | { | |
4413 | u32 length; | |
4414 | u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start; | |
4415 | bool rc = false; | |
4416 | ||
4417 | switch (tp->version) { | |
4418 | case RTL_VER_04: | |
4419 | case RTL_VER_05: | |
4420 | case RTL_VER_06: | |
4421 | fw_reg = 0xa014; | |
4422 | ba_reg = 0xa012; | |
4423 | patch_en_addr = 0xa01a; | |
4424 | mode_reg = 0xb820; | |
4425 | bp_start = 0xa000; | |
4426 | break; | |
4427 | default: | |
4428 | goto out; | |
4429 | } | |
4430 | ||
4431 | fw_offset = __le16_to_cpu(phy->fw_offset); | |
4432 | if (fw_offset < sizeof(*phy)) { | |
4433 | dev_err(&tp->intf->dev, "fw_offset too small\n"); | |
4434 | goto out; | |
4435 | } | |
4436 | ||
4437 | length = __le32_to_cpu(phy->blk_hdr.length); | |
4438 | if (length < fw_offset) { | |
4439 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); | |
4440 | goto out; | |
4441 | } | |
4442 | ||
4443 | length -= __le16_to_cpu(phy->fw_offset); | |
4444 | if (!length || (length & 1)) { | |
4445 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4446 | goto out; | |
4447 | } | |
4448 | ||
4449 | if (__le16_to_cpu(phy->fw_reg) != fw_reg) { | |
4450 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); | |
4451 | goto out; | |
4452 | } | |
4453 | ||
4454 | if (__le16_to_cpu(phy->ba_reg) != ba_reg) { | |
4455 | dev_err(&tp->intf->dev, "invalid base address register\n"); | |
4456 | goto out; | |
4457 | } | |
4458 | ||
4459 | if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) { | |
4460 | dev_err(&tp->intf->dev, | |
4461 | "invalid patch mode enabled register\n"); | |
4462 | goto out; | |
4463 | } | |
4464 | ||
4465 | if (__le16_to_cpu(phy->mode_reg) != mode_reg) { | |
4466 | dev_err(&tp->intf->dev, | |
4467 | "invalid register to switch the mode\n"); | |
4468 | goto out; | |
4469 | } | |
4470 | ||
4471 | if (__le16_to_cpu(phy->bp_start) != bp_start) { | |
4472 | dev_err(&tp->intf->dev, | |
4473 | "invalid start register of break point\n"); | |
4474 | goto out; | |
4475 | } | |
4476 | ||
4477 | if (__le16_to_cpu(phy->bp_num) > 4) { | |
4478 | dev_err(&tp->intf->dev, "invalid break point number\n"); | |
4479 | goto out; | |
4480 | } | |
4481 | ||
4482 | rc = true; | |
4483 | out: | |
4484 | return rc; | |
4485 | } | |
4486 | ||
a66edaaf | 4487 | static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac) |
9370f2d0 | 4488 | { |
5a16a3d9 | 4489 | u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset; |
9370f2d0 HW |
4490 | bool rc = false; |
4491 | u32 length, type; | |
4492 | int i, max_bp; | |
4493 | ||
a66edaaf | 4494 | type = __le32_to_cpu(mac->blk_hdr.type); |
9370f2d0 HW |
4495 | if (type == RTL_FW_PLA) { |
4496 | switch (tp->version) { | |
4497 | case RTL_VER_01: | |
4498 | case RTL_VER_02: | |
4499 | case RTL_VER_07: | |
4500 | fw_reg = 0xf800; | |
4501 | bp_ba_addr = PLA_BP_BA; | |
4502 | bp_en_addr = 0; | |
4503 | bp_start = PLA_BP_0; | |
4504 | max_bp = 8; | |
4505 | break; | |
4506 | case RTL_VER_03: | |
4507 | case RTL_VER_04: | |
4508 | case RTL_VER_05: | |
4509 | case RTL_VER_06: | |
4510 | case RTL_VER_08: | |
4511 | case RTL_VER_09: | |
195aae32 HW |
4512 | case RTL_VER_11: |
4513 | case RTL_VER_12: | |
4514 | case RTL_VER_13: | |
195aae32 | 4515 | case RTL_VER_15: |
9370f2d0 HW |
4516 | fw_reg = 0xf800; |
4517 | bp_ba_addr = PLA_BP_BA; | |
4518 | bp_en_addr = PLA_BP_EN; | |
4519 | bp_start = PLA_BP_0; | |
4520 | max_bp = 8; | |
4521 | break; | |
6633fb83 HW |
4522 | case RTL_VER_14: |
4523 | fw_reg = 0xf800; | |
4524 | bp_ba_addr = PLA_BP_BA; | |
4525 | bp_en_addr = USB_BP2_EN; | |
4526 | bp_start = PLA_BP_0; | |
4527 | max_bp = 16; | |
4528 | break; | |
9370f2d0 HW |
4529 | default: |
4530 | goto out; | |
4531 | } | |
4532 | } else if (type == RTL_FW_USB) { | |
4533 | switch (tp->version) { | |
4534 | case RTL_VER_03: | |
4535 | case RTL_VER_04: | |
4536 | case RTL_VER_05: | |
4537 | case RTL_VER_06: | |
4538 | fw_reg = 0xf800; | |
4539 | bp_ba_addr = USB_BP_BA; | |
4540 | bp_en_addr = USB_BP_EN; | |
4541 | bp_start = USB_BP_0; | |
4542 | max_bp = 8; | |
4543 | break; | |
4544 | case RTL_VER_08: | |
4545 | case RTL_VER_09: | |
195aae32 HW |
4546 | case RTL_VER_11: |
4547 | case RTL_VER_12: | |
4548 | case RTL_VER_13: | |
4549 | case RTL_VER_14: | |
4550 | case RTL_VER_15: | |
9370f2d0 HW |
4551 | fw_reg = 0xe600; |
4552 | bp_ba_addr = USB_BP_BA; | |
4553 | bp_en_addr = USB_BP2_EN; | |
4554 | bp_start = USB_BP_0; | |
4555 | max_bp = 16; | |
4556 | break; | |
4557 | case RTL_VER_01: | |
4558 | case RTL_VER_02: | |
4559 | case RTL_VER_07: | |
4560 | default: | |
4561 | goto out; | |
4562 | } | |
4563 | } else { | |
4564 | goto out; | |
4565 | } | |
4566 | ||
5a16a3d9 HW |
4567 | fw_offset = __le16_to_cpu(mac->fw_offset); |
4568 | if (fw_offset < sizeof(*mac)) { | |
4569 | dev_err(&tp->intf->dev, "fw_offset too small\n"); | |
4570 | goto out; | |
4571 | } | |
4572 | ||
a66edaaf | 4573 | length = __le32_to_cpu(mac->blk_hdr.length); |
5a16a3d9 | 4574 | if (length < fw_offset) { |
9370f2d0 HW |
4575 | dev_err(&tp->intf->dev, "invalid fw_offset\n"); |
4576 | goto out; | |
4577 | } | |
4578 | ||
5a16a3d9 | 4579 | length -= fw_offset; |
9370f2d0 HW |
4580 | if (length < 4 || (length & 3)) { |
4581 | dev_err(&tp->intf->dev, "invalid block length\n"); | |
4582 | goto out; | |
4583 | } | |
4584 | ||
a66edaaf | 4585 | if (__le16_to_cpu(mac->fw_reg) != fw_reg) { |
9370f2d0 HW |
4586 | dev_err(&tp->intf->dev, "invalid register to load firmware\n"); |
4587 | goto out; | |
4588 | } | |
4589 | ||
a66edaaf | 4590 | if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) { |
9370f2d0 HW |
4591 | dev_err(&tp->intf->dev, "invalid base address register\n"); |
4592 | goto out; | |
4593 | } | |
4594 | ||
a66edaaf | 4595 | if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) { |
9370f2d0 HW |
4596 | dev_err(&tp->intf->dev, "invalid enabled mask register\n"); |
4597 | goto out; | |
4598 | } | |
4599 | ||
a66edaaf | 4600 | if (__le16_to_cpu(mac->bp_start) != bp_start) { |
9370f2d0 HW |
4601 | dev_err(&tp->intf->dev, |
4602 | "invalid start register of break point\n"); | |
4603 | goto out; | |
4604 | } | |
4605 | ||
a66edaaf | 4606 | if (__le16_to_cpu(mac->bp_num) > max_bp) { |
9370f2d0 HW |
4607 | dev_err(&tp->intf->dev, "invalid break point number\n"); |
4608 | goto out; | |
4609 | } | |
4610 | ||
a66edaaf HW |
4611 | for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) { |
4612 | if (mac->bp[i]) { | |
9370f2d0 HW |
4613 | dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i); |
4614 | goto out; | |
4615 | } | |
4616 | } | |
4617 | ||
4618 | rc = true; | |
4619 | out: | |
4620 | return rc; | |
4621 | } | |
4622 | ||
4623 | /* Verify the checksum for the firmware file. It is calculated from the version | |
4624 | * field to the end of the file. Compare the result with the checksum field to | |
4625 | * make sure the file is correct. | |
4626 | */ | |
4627 | static long rtl8152_fw_verify_checksum(struct r8152 *tp, | |
4628 | struct fw_header *fw_hdr, size_t size) | |
4629 | { | |
4630 | unsigned char checksum[sizeof(fw_hdr->checksum)]; | |
4631 | struct crypto_shash *alg; | |
4632 | struct shash_desc *sdesc; | |
4633 | size_t len; | |
4634 | long rc; | |
4635 | ||
4636 | alg = crypto_alloc_shash("sha256", 0, 0); | |
4637 | if (IS_ERR(alg)) { | |
4638 | rc = PTR_ERR(alg); | |
4639 | goto out; | |
4640 | } | |
4641 | ||
4642 | if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) { | |
4643 | rc = -EFAULT; | |
4644 | dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n", | |
4645 | crypto_shash_digestsize(alg)); | |
4646 | goto free_shash; | |
4647 | } | |
4648 | ||
4649 | len = sizeof(*sdesc) + crypto_shash_descsize(alg); | |
4650 | sdesc = kmalloc(len, GFP_KERNEL); | |
4651 | if (!sdesc) { | |
4652 | rc = -ENOMEM; | |
4653 | goto free_shash; | |
4654 | } | |
4655 | sdesc->tfm = alg; | |
4656 | ||
4657 | len = size - sizeof(fw_hdr->checksum); | |
4658 | rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum); | |
4659 | kfree(sdesc); | |
4660 | if (rc) | |
4661 | goto free_shash; | |
4662 | ||
4663 | if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) { | |
4664 | dev_err(&tp->intf->dev, "checksum fail\n"); | |
4665 | rc = -EFAULT; | |
4666 | } | |
4667 | ||
4668 | free_shash: | |
4669 | crypto_free_shash(alg); | |
4670 | out: | |
4671 | return rc; | |
4672 | } | |
4673 | ||
4674 | static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw) | |
4675 | { | |
4676 | const struct firmware *fw = rtl_fw->fw; | |
4677 | struct fw_header *fw_hdr = (struct fw_header *)fw->data; | |
a8a7be17 | 4678 | unsigned long fw_flags = 0; |
9370f2d0 HW |
4679 | long ret = -EFAULT; |
4680 | int i; | |
4681 | ||
4682 | if (fw->size < sizeof(*fw_hdr)) { | |
4683 | dev_err(&tp->intf->dev, "file too small\n"); | |
4684 | goto fail; | |
4685 | } | |
4686 | ||
4687 | ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size); | |
4688 | if (ret) | |
4689 | goto fail; | |
4690 | ||
4691 | ret = -EFAULT; | |
4692 | ||
4693 | for (i = sizeof(*fw_hdr); i < fw->size;) { | |
4694 | struct fw_block *block = (struct fw_block *)&fw->data[i]; | |
4695 | u32 type; | |
4696 | ||
4697 | if ((i + sizeof(*block)) > fw->size) | |
4698 | goto fail; | |
4699 | ||
4700 | type = __le32_to_cpu(block->type); | |
4701 | switch (type) { | |
4702 | case RTL_FW_END: | |
4703 | if (__le32_to_cpu(block->length) != sizeof(*block)) | |
4704 | goto fail; | |
af14288f | 4705 | goto fw_end; |
9370f2d0 | 4706 | case RTL_FW_PLA: |
a8a7be17 | 4707 | if (test_bit(FW_FLAGS_PLA, &fw_flags)) { |
9370f2d0 HW |
4708 | dev_err(&tp->intf->dev, |
4709 | "multiple PLA firmware encountered"); | |
4710 | goto fail; | |
4711 | } | |
4712 | ||
a8a7be17 | 4713 | if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { |
9370f2d0 | 4714 | dev_err(&tp->intf->dev, |
a66edaaf | 4715 | "check PLA firmware failed\n"); |
9370f2d0 HW |
4716 | goto fail; |
4717 | } | |
a8a7be17 | 4718 | __set_bit(FW_FLAGS_PLA, &fw_flags); |
9370f2d0 HW |
4719 | break; |
4720 | case RTL_FW_USB: | |
a8a7be17 | 4721 | if (test_bit(FW_FLAGS_USB, &fw_flags)) { |
9370f2d0 HW |
4722 | dev_err(&tp->intf->dev, |
4723 | "multiple USB firmware encountered"); | |
4724 | goto fail; | |
4725 | } | |
4726 | ||
a8a7be17 | 4727 | if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { |
9370f2d0 | 4728 | dev_err(&tp->intf->dev, |
a66edaaf | 4729 | "check USB firmware failed\n"); |
9370f2d0 HW |
4730 | goto fail; |
4731 | } | |
a8a7be17 | 4732 | __set_bit(FW_FLAGS_USB, &fw_flags); |
af14288f HW |
4733 | break; |
4734 | case RTL_FW_PHY_START: | |
a8a7be17 HW |
4735 | if (test_bit(FW_FLAGS_START, &fw_flags) || |
4736 | test_bit(FW_FLAGS_NC, &fw_flags) || | |
4a51b0e8 HW |
4737 | test_bit(FW_FLAGS_NC1, &fw_flags) || |
4738 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4739 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4740 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
a8a7be17 | 4741 | test_bit(FW_FLAGS_STOP, &fw_flags)) { |
af14288f HW |
4742 | dev_err(&tp->intf->dev, |
4743 | "check PHY_START fail\n"); | |
4744 | goto fail; | |
4745 | } | |
4746 | ||
a8a7be17 | 4747 | if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) { |
af14288f HW |
4748 | dev_err(&tp->intf->dev, |
4749 | "Invalid length for PHY_START\n"); | |
4750 | goto fail; | |
4751 | } | |
a8a7be17 | 4752 | __set_bit(FW_FLAGS_START, &fw_flags); |
af14288f HW |
4753 | break; |
4754 | case RTL_FW_PHY_STOP: | |
a8a7be17 HW |
4755 | if (test_bit(FW_FLAGS_STOP, &fw_flags) || |
4756 | !test_bit(FW_FLAGS_START, &fw_flags)) { | |
af14288f HW |
4757 | dev_err(&tp->intf->dev, |
4758 | "Check PHY_STOP fail\n"); | |
4759 | goto fail; | |
4760 | } | |
4761 | ||
4762 | if (__le32_to_cpu(block->length) != sizeof(*block)) { | |
4763 | dev_err(&tp->intf->dev, | |
4764 | "Invalid length for PHY_STOP\n"); | |
4765 | goto fail; | |
4766 | } | |
a8a7be17 | 4767 | __set_bit(FW_FLAGS_STOP, &fw_flags); |
af14288f HW |
4768 | break; |
4769 | case RTL_FW_PHY_NC: | |
a8a7be17 HW |
4770 | if (!test_bit(FW_FLAGS_START, &fw_flags) || |
4771 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
af14288f HW |
4772 | dev_err(&tp->intf->dev, |
4773 | "check PHY_NC fail\n"); | |
4774 | goto fail; | |
4775 | } | |
4776 | ||
a8a7be17 | 4777 | if (test_bit(FW_FLAGS_NC, &fw_flags)) { |
af14288f HW |
4778 | dev_err(&tp->intf->dev, |
4779 | "multiple PHY NC encountered\n"); | |
4780 | goto fail; | |
4781 | } | |
4782 | ||
a8a7be17 | 4783 | if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) { |
af14288f HW |
4784 | dev_err(&tp->intf->dev, |
4785 | "check PHY NC firmware failed\n"); | |
4786 | goto fail; | |
4787 | } | |
a8a7be17 | 4788 | __set_bit(FW_FLAGS_NC, &fw_flags); |
4a51b0e8 HW |
4789 | break; |
4790 | case RTL_FW_PHY_UNION_NC: | |
4791 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4792 | test_bit(FW_FLAGS_NC1, &fw_flags) || | |
4793 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4794 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4795 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4796 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4797 | dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n"); | |
4798 | goto fail; | |
4799 | } | |
4800 | ||
4801 | if (test_bit(FW_FLAGS_NC, &fw_flags)) { | |
4802 | dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n"); | |
4803 | goto fail; | |
4804 | } | |
4805 | ||
4806 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4807 | dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n"); | |
4808 | goto fail; | |
4809 | } | |
4810 | __set_bit(FW_FLAGS_NC, &fw_flags); | |
4811 | break; | |
4812 | case RTL_FW_PHY_UNION_NC1: | |
4813 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4814 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4815 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4816 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4817 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4818 | dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n"); | |
4819 | goto fail; | |
4820 | } | |
4821 | ||
4822 | if (test_bit(FW_FLAGS_NC1, &fw_flags)) { | |
4823 | dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n"); | |
4824 | goto fail; | |
4825 | } | |
4826 | ||
4827 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4828 | dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n"); | |
4829 | goto fail; | |
4830 | } | |
4831 | __set_bit(FW_FLAGS_NC1, &fw_flags); | |
4832 | break; | |
4833 | case RTL_FW_PHY_UNION_NC2: | |
4834 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4835 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4836 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4837 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4838 | dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n"); | |
4839 | goto fail; | |
4840 | } | |
4841 | ||
4842 | if (test_bit(FW_FLAGS_NC2, &fw_flags)) { | |
4843 | dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n"); | |
4844 | goto fail; | |
4845 | } | |
4846 | ||
4847 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4848 | dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n"); | |
4849 | goto fail; | |
4850 | } | |
4851 | __set_bit(FW_FLAGS_NC2, &fw_flags); | |
4852 | break; | |
4853 | case RTL_FW_PHY_UNION_UC2: | |
4854 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4855 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4856 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4857 | dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n"); | |
4858 | goto fail; | |
4859 | } | |
4860 | ||
4861 | if (test_bit(FW_FLAGS_UC2, &fw_flags)) { | |
4862 | dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n"); | |
4863 | goto fail; | |
4864 | } | |
4865 | ||
4866 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4867 | dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n"); | |
4868 | goto fail; | |
4869 | } | |
4870 | __set_bit(FW_FLAGS_UC2, &fw_flags); | |
4871 | break; | |
4872 | case RTL_FW_PHY_UNION_UC: | |
4873 | if (!test_bit(FW_FLAGS_START, &fw_flags) || | |
4874 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4875 | dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n"); | |
4876 | goto fail; | |
4877 | } | |
4878 | ||
4879 | if (test_bit(FW_FLAGS_UC, &fw_flags)) { | |
4880 | dev_err(&tp->intf->dev, "multiple PHY UC encountered\n"); | |
4881 | goto fail; | |
4882 | } | |
4883 | ||
4884 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4885 | dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n"); | |
4886 | goto fail; | |
4887 | } | |
4888 | __set_bit(FW_FLAGS_UC, &fw_flags); | |
4889 | break; | |
4890 | case RTL_FW_PHY_UNION_MISC: | |
4891 | if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { | |
4892 | dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n"); | |
4893 | goto fail; | |
4894 | } | |
4895 | break; | |
4896 | case RTL_FW_PHY_FIXUP: | |
4897 | if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) { | |
4898 | dev_err(&tp->intf->dev, "check PHY fixup failed\n"); | |
4899 | goto fail; | |
4900 | } | |
4901 | break; | |
4902 | case RTL_FW_PHY_SPEED_UP: | |
4903 | if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) { | |
4904 | dev_err(&tp->intf->dev, "multiple PHY firmware encountered"); | |
4905 | goto fail; | |
4906 | } | |
af14288f | 4907 | |
4a51b0e8 HW |
4908 | if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) { |
4909 | dev_err(&tp->intf->dev, "check PHY speed up failed\n"); | |
4910 | goto fail; | |
4911 | } | |
4912 | __set_bit(FW_FLAGS_SPEED_UP, &fw_flags); | |
4913 | break; | |
4914 | case RTL_FW_PHY_VER: | |
4915 | if (test_bit(FW_FLAGS_START, &fw_flags) || | |
4916 | test_bit(FW_FLAGS_NC, &fw_flags) || | |
4917 | test_bit(FW_FLAGS_NC1, &fw_flags) || | |
4918 | test_bit(FW_FLAGS_NC2, &fw_flags) || | |
4919 | test_bit(FW_FLAGS_UC2, &fw_flags) || | |
4920 | test_bit(FW_FLAGS_UC, &fw_flags) || | |
4921 | test_bit(FW_FLAGS_STOP, &fw_flags)) { | |
4922 | dev_err(&tp->intf->dev, "Invalid order to set PHY version\n"); | |
4923 | goto fail; | |
4924 | } | |
4925 | ||
4926 | if (test_bit(FW_FLAGS_VER, &fw_flags)) { | |
4927 | dev_err(&tp->intf->dev, "multiple PHY version encountered"); | |
4928 | goto fail; | |
4929 | } | |
4930 | ||
4931 | if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) { | |
4932 | dev_err(&tp->intf->dev, "check PHY version failed\n"); | |
4933 | goto fail; | |
4934 | } | |
4935 | __set_bit(FW_FLAGS_VER, &fw_flags); | |
9370f2d0 HW |
4936 | break; |
4937 | default: | |
4938 | dev_warn(&tp->intf->dev, "Unknown type %u is found\n", | |
4939 | type); | |
4940 | break; | |
4941 | } | |
4942 | ||
4943 | /* next block */ | |
4944 | i += ALIGN(__le32_to_cpu(block->length), 8); | |
4945 | } | |
4946 | ||
af14288f | 4947 | fw_end: |
a8a7be17 | 4948 | if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) { |
af14288f HW |
4949 | dev_err(&tp->intf->dev, "without PHY_STOP\n"); |
4950 | goto fail; | |
4951 | } | |
4952 | ||
9370f2d0 HW |
4953 | return 0; |
4954 | fail: | |
4955 | return ret; | |
4956 | } | |
4957 | ||
4a51b0e8 HW |
4958 | static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) |
4959 | { | |
4960 | u32 len; | |
4961 | u8 *data; | |
4962 | ||
b24edca3 HW |
4963 | rtl_reset_ocp_base(tp); |
4964 | ||
4a51b0e8 HW |
4965 | if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) { |
4966 | dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); | |
4967 | return; | |
4968 | } | |
4969 | ||
4970 | len = __le32_to_cpu(phy->blk_hdr.length); | |
4971 | len -= __le16_to_cpu(phy->fw_offset); | |
4972 | data = (u8 *)phy + __le16_to_cpu(phy->fw_offset); | |
4973 | ||
4974 | if (rtl_phy_patch_request(tp, true, wait)) | |
4975 | return; | |
4976 | ||
4977 | while (len) { | |
4978 | u32 ocp_data, size; | |
4979 | int i; | |
4980 | ||
4981 | if (len < 2048) | |
4982 | size = len; | |
4983 | else | |
4984 | size = 2048; | |
4985 | ||
4986 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); | |
4987 | ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; | |
4988 | ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); | |
4989 | ||
4990 | generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); | |
4991 | ||
4992 | data += size; | |
4993 | len -= size; | |
4994 | ||
4995 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); | |
4996 | ocp_data |= POL_GPHY_PATCH; | |
4997 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); | |
4998 | ||
4999 | for (i = 0; i < 1000; i++) { | |
5000 | if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) | |
5001 | break; | |
5002 | } | |
5003 | ||
5004 | if (i == 1000) { | |
5005 | dev_err(&tp->intf->dev, "ram code speedup mode timeout\n"); | |
f49c35b8 | 5006 | break; |
4a51b0e8 HW |
5007 | } |
5008 | } | |
5009 | ||
b24edca3 HW |
5010 | rtl_reset_ocp_base(tp); |
5011 | ||
4a51b0e8 HW |
5012 | rtl_phy_patch_request(tp, false, wait); |
5013 | ||
5014 | if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version)) | |
5015 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
5016 | else | |
5017 | dev_err(&tp->intf->dev, "ram code speedup mode fail\n"); | |
5018 | } | |
5019 | ||
5020 | static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) | |
5021 | { | |
5022 | u16 ver_addr, ver; | |
5023 | ||
5024 | ver_addr = __le16_to_cpu(phy_ver->ver.addr); | |
5025 | ver = __le16_to_cpu(phy_ver->ver.data); | |
5026 | ||
b24edca3 HW |
5027 | rtl_reset_ocp_base(tp); |
5028 | ||
4a51b0e8 HW |
5029 | if (sram_read(tp, ver_addr) >= ver) { |
5030 | dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); | |
5031 | return 0; | |
5032 | } | |
5033 | ||
5034 | sram_write(tp, ver_addr, ver); | |
5035 | ||
5036 | dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver); | |
5037 | ||
5038 | return ver; | |
5039 | } | |
5040 | ||
5041 | static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) | |
5042 | { | |
5043 | u16 addr, data; | |
5044 | ||
b24edca3 HW |
5045 | rtl_reset_ocp_base(tp); |
5046 | ||
4a51b0e8 HW |
5047 | addr = __le16_to_cpu(fix->setting.addr); |
5048 | data = ocp_reg_read(tp, addr); | |
5049 | ||
5050 | switch (__le16_to_cpu(fix->bit_cmd)) { | |
5051 | case FW_FIXUP_AND: | |
5052 | data &= __le16_to_cpu(fix->setting.data); | |
5053 | break; | |
5054 | case FW_FIXUP_OR: | |
5055 | data |= __le16_to_cpu(fix->setting.data); | |
5056 | break; | |
5057 | case FW_FIXUP_NOT: | |
5058 | data &= ~__le16_to_cpu(fix->setting.data); | |
5059 | break; | |
5060 | case FW_FIXUP_XOR: | |
5061 | data ^= __le16_to_cpu(fix->setting.data); | |
5062 | break; | |
5063 | default: | |
5064 | return; | |
5065 | } | |
5066 | ||
5067 | ocp_reg_write(tp, addr, data); | |
5068 | ||
5069 | dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data); | |
5070 | } | |
5071 | ||
5072 | static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) | |
5073 | { | |
5074 | __le16 *data; | |
5075 | u32 length; | |
5076 | int i, num; | |
5077 | ||
b24edca3 HW |
5078 | rtl_reset_ocp_base(tp); |
5079 | ||
4a51b0e8 HW |
5080 | num = phy->pre_num; |
5081 | for (i = 0; i < num; i++) | |
5082 | sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr), | |
5083 | __le16_to_cpu(phy->pre_set[i].data)); | |
5084 | ||
5085 | length = __le32_to_cpu(phy->blk_hdr.length); | |
5086 | length -= __le16_to_cpu(phy->fw_offset); | |
5087 | num = length / 2; | |
5088 | data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); | |
5089 | ||
5090 | ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); | |
5091 | for (i = 0; i < num; i++) | |
5092 | ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); | |
5093 | ||
5094 | num = phy->bp_num; | |
5095 | for (i = 0; i < num; i++) | |
5096 | sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data)); | |
5097 | ||
5098 | if (phy->bp_num && phy->bp_en.addr) | |
5099 | sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data)); | |
5100 | ||
5101 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
5102 | } | |
5103 | ||
af14288f HW |
5104 | static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) |
5105 | { | |
5106 | u16 mode_reg, bp_index; | |
5107 | u32 length, i, num; | |
5108 | __le16 *data; | |
5109 | ||
b24edca3 HW |
5110 | rtl_reset_ocp_base(tp); |
5111 | ||
af14288f HW |
5112 | mode_reg = __le16_to_cpu(phy->mode_reg); |
5113 | sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre)); | |
5114 | sram_write(tp, __le16_to_cpu(phy->ba_reg), | |
5115 | __le16_to_cpu(phy->ba_data)); | |
5116 | ||
5117 | length = __le32_to_cpu(phy->blk_hdr.length); | |
5118 | length -= __le16_to_cpu(phy->fw_offset); | |
5119 | num = length / 2; | |
5120 | data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); | |
5121 | ||
5122 | ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); | |
5123 | for (i = 0; i < num; i++) | |
5124 | ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); | |
5125 | ||
5126 | sram_write(tp, __le16_to_cpu(phy->patch_en_addr), | |
5127 | __le16_to_cpu(phy->patch_en_value)); | |
5128 | ||
5129 | bp_index = __le16_to_cpu(phy->bp_start); | |
5130 | num = __le16_to_cpu(phy->bp_num); | |
5131 | for (i = 0; i < num; i++) { | |
5132 | sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i])); | |
5133 | bp_index += 2; | |
5134 | } | |
5135 | ||
5136 | sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post)); | |
5137 | ||
5138 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); | |
5139 | } | |
5140 | ||
a66edaaf | 5141 | static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) |
9370f2d0 | 5142 | { |
e5c266a6 | 5143 | u16 bp_en_addr, type, fw_ver_reg; |
9370f2d0 HW |
5144 | u32 length; |
5145 | u8 *data; | |
9370f2d0 | 5146 | |
a66edaaf | 5147 | switch (__le32_to_cpu(mac->blk_hdr.type)) { |
9370f2d0 HW |
5148 | case RTL_FW_PLA: |
5149 | type = MCU_TYPE_PLA; | |
5150 | break; | |
5151 | case RTL_FW_USB: | |
5152 | type = MCU_TYPE_USB; | |
5153 | break; | |
5154 | default: | |
5155 | return; | |
5156 | } | |
5157 | ||
4a51b0e8 HW |
5158 | fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); |
5159 | if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) { | |
5160 | dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB"); | |
5161 | return; | |
5162 | } | |
5163 | ||
9370f2d0 HW |
5164 | rtl_clear_bp(tp, type); |
5165 | ||
5166 | /* Enable backup/restore of MACDBG. This is required after clearing PLA | |
5167 | * break points and before applying the PLA firmware. | |
5168 | */ | |
5169 | if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA && | |
5170 | !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) { | |
5171 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM); | |
5172 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM); | |
5173 | } | |
5174 | ||
a66edaaf HW |
5175 | length = __le32_to_cpu(mac->blk_hdr.length); |
5176 | length -= __le16_to_cpu(mac->fw_offset); | |
9370f2d0 | 5177 | |
a66edaaf HW |
5178 | data = (u8 *)mac; |
5179 | data += __le16_to_cpu(mac->fw_offset); | |
9370f2d0 | 5180 | |
8487b4af HW |
5181 | if (generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, |
5182 | data, type) < 0) { | |
5183 | dev_err(&tp->intf->dev, "Write %s fw fail\n", | |
5184 | type ? "PLA" : "USB"); | |
5185 | return; | |
5186 | } | |
9370f2d0 | 5187 | |
a66edaaf HW |
5188 | ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), |
5189 | __le16_to_cpu(mac->bp_ba_value)); | |
9370f2d0 | 5190 | |
8487b4af HW |
5191 | if (generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD, |
5192 | ALIGN(__le16_to_cpu(mac->bp_num) << 1, 4), | |
5193 | mac->bp, type) < 0) { | |
5194 | dev_err(&tp->intf->dev, "Write %s bp fail\n", | |
5195 | type ? "PLA" : "USB"); | |
5196 | return; | |
5197 | } | |
9370f2d0 | 5198 | |
a66edaaf | 5199 | bp_en_addr = __le16_to_cpu(mac->bp_en_addr); |
9370f2d0 HW |
5200 | if (bp_en_addr) |
5201 | ocp_write_word(tp, type, bp_en_addr, | |
a66edaaf | 5202 | __le16_to_cpu(mac->bp_en_value)); |
9370f2d0 | 5203 | |
9370f2d0 HW |
5204 | if (fw_ver_reg) |
5205 | ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, | |
a66edaaf | 5206 | mac->fw_ver_data); |
9370f2d0 | 5207 | |
a66edaaf | 5208 | dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); |
9370f2d0 HW |
5209 | } |
5210 | ||
a08c0d30 | 5211 | static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) |
9370f2d0 HW |
5212 | { |
5213 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
8e484ebb HW |
5214 | const struct firmware *fw; |
5215 | struct fw_header *fw_hdr; | |
af14288f HW |
5216 | struct fw_phy_patch_key *key; |
5217 | u16 key_addr = 0; | |
4a51b0e8 | 5218 | int i, patch_phy = 1; |
9370f2d0 HW |
5219 | |
5220 | if (IS_ERR_OR_NULL(rtl_fw->fw)) | |
5221 | return; | |
5222 | ||
8e484ebb HW |
5223 | fw = rtl_fw->fw; |
5224 | fw_hdr = (struct fw_header *)fw->data; | |
5225 | ||
9370f2d0 HW |
5226 | if (rtl_fw->pre_fw) |
5227 | rtl_fw->pre_fw(tp); | |
5228 | ||
5229 | for (i = offsetof(struct fw_header, blocks); i < fw->size;) { | |
5230 | struct fw_block *block = (struct fw_block *)&fw->data[i]; | |
5231 | ||
5232 | switch (__le32_to_cpu(block->type)) { | |
5233 | case RTL_FW_END: | |
5234 | goto post_fw; | |
5235 | case RTL_FW_PLA: | |
5236 | case RTL_FW_USB: | |
a66edaaf | 5237 | rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); |
9370f2d0 | 5238 | break; |
af14288f | 5239 | case RTL_FW_PHY_START: |
4a51b0e8 HW |
5240 | if (!patch_phy) |
5241 | break; | |
af14288f HW |
5242 | key = (struct fw_phy_patch_key *)block; |
5243 | key_addr = __le16_to_cpu(key->key_reg); | |
a08c0d30 | 5244 | rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); |
af14288f HW |
5245 | break; |
5246 | case RTL_FW_PHY_STOP: | |
4a51b0e8 HW |
5247 | if (!patch_phy) |
5248 | break; | |
af14288f | 5249 | WARN_ON(!key_addr); |
a08c0d30 | 5250 | rtl_post_ram_code(tp, key_addr, !power_cut); |
af14288f HW |
5251 | break; |
5252 | case RTL_FW_PHY_NC: | |
5253 | rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); | |
5254 | break; | |
4a51b0e8 HW |
5255 | case RTL_FW_PHY_VER: |
5256 | patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block); | |
5257 | break; | |
5258 | case RTL_FW_PHY_UNION_NC: | |
5259 | case RTL_FW_PHY_UNION_NC1: | |
5260 | case RTL_FW_PHY_UNION_NC2: | |
5261 | case RTL_FW_PHY_UNION_UC2: | |
5262 | case RTL_FW_PHY_UNION_UC: | |
5263 | case RTL_FW_PHY_UNION_MISC: | |
5264 | if (patch_phy) | |
5265 | rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block); | |
5266 | break; | |
5267 | case RTL_FW_PHY_FIXUP: | |
5268 | if (patch_phy) | |
5269 | rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block); | |
5270 | break; | |
5271 | case RTL_FW_PHY_SPEED_UP: | |
5272 | rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut); | |
5273 | break; | |
9370f2d0 HW |
5274 | default: |
5275 | break; | |
5276 | } | |
5277 | ||
5278 | i += ALIGN(__le32_to_cpu(block->length), 8); | |
5279 | } | |
5280 | ||
5281 | post_fw: | |
5282 | if (rtl_fw->post_fw) | |
5283 | rtl_fw->post_fw(tp); | |
5284 | ||
b24edca3 | 5285 | rtl_reset_ocp_base(tp); |
9370f2d0 | 5286 | strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE); |
092d2141 | 5287 | dev_dbg(&tp->intf->dev, "load %s successfully\n", rtl_fw->version); |
9370f2d0 HW |
5288 | } |
5289 | ||
5290 | static void rtl8152_release_firmware(struct r8152 *tp) | |
5291 | { | |
5292 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
5293 | ||
5294 | if (!IS_ERR_OR_NULL(rtl_fw->fw)) { | |
5295 | release_firmware(rtl_fw->fw); | |
5296 | rtl_fw->fw = NULL; | |
5297 | } | |
5298 | } | |
5299 | ||
5300 | static int rtl8152_request_firmware(struct r8152 *tp) | |
5301 | { | |
5302 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
5303 | long rc; | |
5304 | ||
5305 | if (rtl_fw->fw || !rtl_fw->fw_name) { | |
5306 | dev_info(&tp->intf->dev, "skip request firmware\n"); | |
5307 | rc = 0; | |
5308 | goto result; | |
5309 | } | |
5310 | ||
5311 | rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev); | |
5312 | if (rc < 0) | |
5313 | goto result; | |
5314 | ||
5315 | rc = rtl8152_check_firmware(tp, rtl_fw); | |
5316 | if (rc < 0) | |
5317 | release_firmware(rtl_fw->fw); | |
5318 | ||
5319 | result: | |
5320 | if (rc) { | |
5321 | rtl_fw->fw = ERR_PTR(rc); | |
5322 | ||
5323 | dev_warn(&tp->intf->dev, | |
5324 | "unable to load firmware patch %s (%ld)\n", | |
5325 | rtl_fw->fw_name, rc); | |
5326 | } | |
5327 | ||
5328 | return rc; | |
5329 | } | |
5330 | ||
cda9fb01 | 5331 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 5332 | { |
cda9fb01 | 5333 | if (enable) { |
5334 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
5335 | LINKENA | DIS_SDSAVE); | |
5336 | } else { | |
5337 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
5338 | DIS_SDSAVE); | |
5339 | msleep(20); | |
5340 | } | |
4349968a | 5341 | } |
5342 | ||
e6449539 | 5343 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
5344 | { | |
5345 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
5346 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
5347 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
5348 | } | |
5349 | ||
5350 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
5351 | { | |
5352 | u16 data; | |
5353 | ||
5354 | r8152_mmd_indirect(tp, dev, reg); | |
5355 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
5356 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
5357 | ||
5358 | return data; | |
5359 | } | |
5360 | ||
5361 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
5362 | { | |
5363 | r8152_mmd_indirect(tp, dev, reg); | |
5364 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
5365 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
5366 | } | |
5367 | ||
5368 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
5369 | { | |
5370 | u16 config1, config2, config3; | |
5371 | u32 ocp_data; | |
5372 | ||
5373 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
5374 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
5375 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
5376 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
5377 | ||
5378 | if (enable) { | |
5379 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
5380 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
5381 | config1 |= sd_rise_time(1); | |
5382 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
5383 | config3 |= fast_snr(42); | |
5384 | } else { | |
5385 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
5386 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
5387 | RX_QUIET_EN); | |
5388 | config1 |= sd_rise_time(7); | |
5389 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
5390 | config3 |= fast_snr(511); | |
5391 | } | |
5392 | ||
5393 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
5394 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
5395 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
5396 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
5397 | } | |
5398 | ||
e7bde56b | 5399 | static void r8153_eee_en(struct r8152 *tp, bool enable) |
e6449539 | 5400 | { |
e7bde56b HW |
5401 | u32 ocp_data; |
5402 | u16 config; | |
5403 | ||
5404 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
5405 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
5406 | ||
5407 | if (enable) { | |
5408 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
5409 | config |= EEE10_EN; | |
f4a93be6 | 5410 | } else { |
e7bde56b HW |
5411 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); |
5412 | config &= ~EEE10_EN; | |
5413 | } | |
5414 | ||
5415 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
5416 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
e7bde56b | 5417 | |
0e5b36bc | 5418 | tp->ups_info.eee = enable; |
e7bde56b HW |
5419 | } |
5420 | ||
195aae32 HW |
5421 | static void r8156_eee_en(struct r8152 *tp, bool enable) |
5422 | { | |
5423 | u16 config; | |
5424 | ||
5425 | r8153_eee_en(tp, enable); | |
5426 | ||
5427 | config = ocp_reg_read(tp, OCP_EEE_ADV2); | |
5428 | ||
5429 | if (enable) | |
5430 | config |= MDIO_EEE_2_5GT; | |
5431 | else | |
5432 | config &= ~MDIO_EEE_2_5GT; | |
5433 | ||
5434 | ocp_reg_write(tp, OCP_EEE_ADV2, config); | |
5435 | } | |
5436 | ||
e7bde56b HW |
5437 | static void rtl_eee_enable(struct r8152 *tp, bool enable) |
5438 | { | |
5439 | switch (tp->version) { | |
5440 | case RTL_VER_01: | |
5441 | case RTL_VER_02: | |
5442 | case RTL_VER_07: | |
5443 | if (enable) { | |
5444 | r8152_eee_en(tp, true); | |
5445 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, | |
5446 | tp->eee_adv); | |
5447 | } else { | |
5448 | r8152_eee_en(tp, false); | |
5449 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); | |
5450 | } | |
5451 | break; | |
5452 | case RTL_VER_03: | |
5453 | case RTL_VER_04: | |
5454 | case RTL_VER_05: | |
5455 | case RTL_VER_06: | |
e7bde56b HW |
5456 | case RTL_VER_08: |
5457 | case RTL_VER_09: | |
195aae32 | 5458 | case RTL_VER_14: |
e7bde56b | 5459 | if (enable) { |
0e5b36bc | 5460 | r8153_eee_en(tp, true); |
e7bde56b HW |
5461 | ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); |
5462 | } else { | |
0e5b36bc | 5463 | r8153_eee_en(tp, false); |
e7bde56b HW |
5464 | ocp_reg_write(tp, OCP_EEE_ADV, 0); |
5465 | } | |
5466 | break; | |
195aae32 HW |
5467 | case RTL_VER_10: |
5468 | case RTL_VER_11: | |
5469 | case RTL_VER_12: | |
5470 | case RTL_VER_13: | |
5471 | case RTL_VER_15: | |
5472 | if (enable) { | |
5473 | r8156_eee_en(tp, true); | |
5474 | ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); | |
5475 | } else { | |
5476 | r8156_eee_en(tp, false); | |
5477 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
5478 | } | |
5479 | break; | |
e7bde56b HW |
5480 | default: |
5481 | break; | |
f4a93be6 | 5482 | } |
e6449539 | 5483 | } |
5484 | ||
5485 | static void r8152b_enable_fc(struct r8152 *tp) | |
5486 | { | |
5487 | u16 anar; | |
5488 | ||
5489 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
5490 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
5491 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
0e5b36bc HW |
5492 | |
5493 | tp->ups_info.flow_control = true; | |
e6449539 | 5494 | } |
5495 | ||
d70b1137 | 5496 | static void rtl8152_disable(struct r8152 *tp) |
5497 | { | |
cda9fb01 | 5498 | r8152_aldps_en(tp, false); |
d70b1137 | 5499 | rtl_disable(tp); |
cda9fb01 | 5500 | r8152_aldps_en(tp, true); |
d70b1137 | 5501 | } |
5502 | ||
4349968a | 5503 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
5504 | { | |
a08c0d30 | 5505 | rtl8152_apply_firmware(tp, false); |
e7bde56b | 5506 | rtl_eee_enable(tp, tp->eee_en); |
ef39df8e | 5507 | r8152_aldps_en(tp, true); |
5508 | r8152b_enable_fc(tp); | |
f0cbe0ac | 5509 | |
aa66a5f1 | 5510 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 5511 | } |
5512 | ||
5f71c840 | 5513 | static void wait_oob_link_list_ready(struct r8152 *tp) |
ac718b69 | 5514 | { |
db8515ef | 5515 | u32 ocp_data; |
5516 | int i; | |
ac718b69 | 5517 | |
5f71c840 | 5518 | for (i = 0; i < 1000; i++) { |
32a574c7 DA |
5519 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
5520 | break; | |
5f71c840 PM |
5521 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
5522 | if (ocp_data & LINK_LIST_READY) | |
5523 | break; | |
5524 | usleep_range(1000, 2000); | |
5525 | } | |
5526 | } | |
5527 | ||
195aae32 HW |
5528 | static void r8156b_wait_loading_flash(struct r8152 *tp) |
5529 | { | |
5530 | if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) && | |
5531 | !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) { | |
5532 | int i; | |
5533 | ||
5534 | for (i = 0; i < 100; i++) { | |
8a67b47f DA |
5535 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
5536 | break; | |
195aae32 HW |
5537 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE) |
5538 | break; | |
5539 | usleep_range(1000, 2000); | |
5540 | } | |
5541 | } | |
5542 | } | |
5543 | ||
5f71c840 PM |
5544 | static void r8152b_exit_oob(struct r8152 *tp) |
5545 | { | |
5546 | u32 ocp_data; | |
5547 | ||
ac718b69 | 5548 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
5549 | ocp_data &= ~RCR_ACPT_ALL; | |
5550 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5551 | ||
00a5e360 | 5552 | rxdy_gated_en(tp, true); |
da9bd117 | 5553 | r8153_teredo_off(tp); |
ac718b69 | 5554 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
5555 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
5556 | ||
5557 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5558 | ocp_data &= ~NOW_IS_OOB; | |
5559 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5560 | ||
5561 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5562 | ocp_data &= ~MCU_BORW_EN; | |
5563 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5564 | ||
5f71c840 | 5565 | wait_oob_link_list_ready(tp); |
ac718b69 | 5566 | |
5567 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5568 | ocp_data |= RE_INIT_LL; | |
5569 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5570 | ||
5f71c840 | 5571 | wait_oob_link_list_ready(tp); |
ac718b69 | 5572 | |
5573 | rtl8152_nic_reset(tp); | |
5574 | ||
5575 | /* rx share fifo credit full threshold */ | |
5576 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
5577 | ||
a3cc465d | 5578 | if (tp->udev->speed == USB_SPEED_FULL || |
5579 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 5580 | /* rx share fifo credit near full threshold */ |
5581 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
5582 | RXFIFO_THR2_FULL); | |
5583 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
5584 | RXFIFO_THR3_FULL); | |
5585 | } else { | |
5586 | /* rx share fifo credit near full threshold */ | |
5587 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
5588 | RXFIFO_THR2_HIGH); | |
5589 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
5590 | RXFIFO_THR3_HIGH); | |
5591 | } | |
5592 | ||
5593 | /* TX share fifo free credit full threshold */ | |
195aae32 | 5594 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); |
ac718b69 | 5595 | |
5596 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 5597 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 5598 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
5599 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
5600 | ||
c5554298 | 5601 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 5602 | |
5603 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
5604 | ||
5605 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
5606 | ocp_data |= TCR0_AUTO_FIFO; | |
5607 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
5608 | } | |
5609 | ||
5610 | static void r8152b_enter_oob(struct r8152 *tp) | |
5611 | { | |
45f4a19f | 5612 | u32 ocp_data; |
ac718b69 | 5613 | |
5614 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5615 | ocp_data &= ~NOW_IS_OOB; | |
5616 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5617 | ||
5618 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
5619 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
5620 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
5621 | ||
d70b1137 | 5622 | rtl_disable(tp); |
ac718b69 | 5623 | |
5f71c840 | 5624 | wait_oob_link_list_ready(tp); |
ac718b69 | 5625 | |
5626 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
5627 | ocp_data |= RE_INIT_LL; | |
5628 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
5629 | ||
5f71c840 | 5630 | wait_oob_link_list_ready(tp); |
ac718b69 | 5631 | |
5632 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
5633 | ||
c5554298 | 5634 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 5635 | |
59c0b47a | 5636 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); |
ac718b69 | 5637 | ocp_data |= ALDPS_PROXY_MODE; |
59c0b47a | 5638 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); |
ac718b69 | 5639 | |
5640 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
5641 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
5642 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
5643 | ||
00a5e360 | 5644 | rxdy_gated_en(tp, false); |
ac718b69 | 5645 | |
5646 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
5647 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
5648 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
5649 | } | |
5650 | ||
9370f2d0 HW |
5651 | static int r8153_pre_firmware_1(struct r8152 *tp) |
5652 | { | |
5653 | int i; | |
5654 | ||
5655 | /* Wait till the WTD timer is ready. It would take at most 104 ms. */ | |
5656 | for (i = 0; i < 104; i++) { | |
5657 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL); | |
5658 | ||
8c53a7bd DA |
5659 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
5660 | return -ENODEV; | |
9370f2d0 HW |
5661 | if (!(ocp_data & WTD1_EN)) |
5662 | break; | |
5663 | usleep_range(1000, 2000); | |
5664 | } | |
5665 | ||
5666 | return 0; | |
5667 | } | |
5668 | ||
5669 | static int r8153_post_firmware_1(struct r8152 *tp) | |
5670 | { | |
5671 | /* set USB_BP_4 to support USB_SPEED_SUPER only */ | |
5672 | if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) | |
5673 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY); | |
5674 | ||
5675 | /* reset UPHY timer to 36 ms */ | |
5676 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); | |
5677 | ||
5678 | return 0; | |
5679 | } | |
5680 | ||
5681 | static int r8153_pre_firmware_2(struct r8152 *tp) | |
5682 | { | |
5683 | u32 ocp_data; | |
5684 | ||
5685 | r8153_pre_firmware_1(tp); | |
5686 | ||
5687 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); | |
5688 | ocp_data &= ~FW_FIX_SUSPEND; | |
5689 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); | |
5690 | ||
5691 | return 0; | |
5692 | } | |
5693 | ||
5694 | static int r8153_post_firmware_2(struct r8152 *tp) | |
5695 | { | |
5696 | u32 ocp_data; | |
5697 | ||
5698 | /* enable bp0 if support USB_SPEED_SUPER only */ | |
5699 | if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { | |
5700 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); | |
5701 | ocp_data |= BIT(0); | |
5702 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); | |
5703 | } | |
5704 | ||
5705 | /* reset UPHY timer to 36 ms */ | |
5706 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); | |
5707 | ||
5708 | /* enable U3P3 check, set the counter to 4 */ | |
5709 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); | |
5710 | ||
5711 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); | |
5712 | ocp_data |= FW_FIX_SUSPEND; | |
5713 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); | |
5714 | ||
5715 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
5716 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
5717 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
5718 | ||
5719 | return 0; | |
5720 | } | |
5721 | ||
5722 | static int r8153_post_firmware_3(struct r8152 *tp) | |
5723 | { | |
5724 | u32 ocp_data; | |
5725 | ||
5726 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
5727 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
5728 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
5729 | ||
5730 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5731 | ocp_data |= FW_IP_RESET_EN; | |
5732 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5733 | ||
5734 | return 0; | |
5735 | } | |
5736 | ||
5737 | static int r8153b_pre_firmware_1(struct r8152 *tp) | |
5738 | { | |
5739 | /* enable fc timer and set timer to 1 second. */ | |
5740 | ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, | |
5741 | CTRL_TIMER_EN | (1000 / 8)); | |
5742 | ||
5743 | return 0; | |
5744 | } | |
5745 | ||
5746 | static int r8153b_post_firmware_1(struct r8152 *tp) | |
5747 | { | |
5748 | u32 ocp_data; | |
5749 | ||
5750 | /* enable bp0 for RTL8153-BND */ | |
5751 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); | |
5752 | if (ocp_data & BND_MASK) { | |
5753 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); | |
5754 | ocp_data |= BIT(0); | |
5755 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); | |
5756 | } | |
5757 | ||
5758 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
5759 | ocp_data |= FLOW_CTRL_PATCH_OPT; | |
5760 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
5761 | ||
5762 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
5763 | ocp_data |= FC_PATCH_TASK; | |
5764 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
5765 | ||
5766 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5767 | ocp_data |= FW_IP_RESET_EN; | |
5768 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5769 | ||
5770 | return 0; | |
5771 | } | |
5772 | ||
195aae32 HW |
5773 | static int r8153c_post_firmware_1(struct r8152 *tp) |
5774 | { | |
5775 | u32 ocp_data; | |
5776 | ||
5777 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
5778 | ocp_data |= FLOW_CTRL_PATCH_2; | |
5779 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
5780 | ||
5781 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
5782 | ocp_data |= FC_PATCH_TASK; | |
5783 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
5784 | ||
5785 | return 0; | |
5786 | } | |
5787 | ||
4a51b0e8 HW |
5788 | static int r8156a_post_firmware_1(struct r8152 *tp) |
5789 | { | |
5790 | u32 ocp_data; | |
5791 | ||
5792 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); | |
5793 | ocp_data |= FW_IP_RESET_EN; | |
5794 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); | |
5795 | ||
5796 | /* Modify U3PHY parameter for compatibility issue */ | |
5797 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); | |
5798 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); | |
5799 | ||
5800 | return 0; | |
5801 | } | |
5802 | ||
e6449539 | 5803 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
5804 | { | |
5805 | u16 data; | |
5806 | ||
5807 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5808 | if (enable) { | |
5809 | data |= EN_ALDPS; | |
5810 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
5811 | } else { | |
4214cc55 | 5812 | int i; |
5813 | ||
e6449539 | 5814 | data &= ~EN_ALDPS; |
5815 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
4214cc55 | 5816 | for (i = 0; i < 20; i++) { |
79321a79 DA |
5817 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
5818 | return; | |
4214cc55 | 5819 | usleep_range(1000, 2000); |
5820 | if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) | |
5821 | break; | |
5822 | } | |
e6449539 | 5823 | } |
e6449539 | 5824 | |
0e5b36bc | 5825 | tp->ups_info.aldps = enable; |
65b82d69 | 5826 | } |
5827 | ||
43779f8d | 5828 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
5829 | { | |
5830 | u32 ocp_data; | |
5831 | u16 data; | |
5832 | ||
d768c61b | 5833 | /* disable ALDPS before updating the PHY parameters */ |
5834 | r8153_aldps_en(tp, false); | |
fb02eb4a | 5835 | |
d768c61b | 5836 | /* disable EEE before updating the PHY parameters */ |
e7bde56b | 5837 | rtl_eee_enable(tp, false); |
43779f8d | 5838 | |
a08c0d30 | 5839 | rtl8152_apply_firmware(tp, false); |
9370f2d0 | 5840 | |
43779f8d | 5841 | if (tp->version == RTL_VER_03) { |
5842 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
5843 | data &= ~CTAP_SHORT_EN; | |
5844 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
5845 | } | |
5846 | ||
5847 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5848 | data |= EEE_CLKDIV_EN; | |
5849 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
5850 | ||
5851 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
5852 | data |= EN_10M_BGOFF; | |
5853 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
5854 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
5855 | data |= EN_10M_PLLOFF; | |
5856 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 5857 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 5858 | |
5859 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
5860 | ocp_data |= PFM_PWM_SWITCH; | |
5861 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
5862 | ||
b4d99def | 5863 | /* Enable LPF corner auto tune */ |
5864 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 5865 | |
b4d99def | 5866 | /* Adjust 10M Amplitude */ |
5867 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
5868 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 5869 | |
e7bde56b HW |
5870 | if (tp->eee_en) |
5871 | rtl_eee_enable(tp, true); | |
af0287ec | 5872 | |
ef39df8e | 5873 | r8153_aldps_en(tp, true); |
5874 | r8152b_enable_fc(tp); | |
5875 | ||
3cb3234e | 5876 | switch (tp->version) { |
5877 | case RTL_VER_03: | |
5878 | case RTL_VER_04: | |
5879 | break; | |
5880 | case RTL_VER_05: | |
5881 | case RTL_VER_06: | |
5882 | default: | |
5883 | r8153_u2p3en(tp, true); | |
5884 | break; | |
5885 | } | |
5886 | ||
aa66a5f1 | 5887 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 5888 | } |
5889 | ||
65b82d69 | 5890 | static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) |
5891 | { | |
5892 | u32 ocp_data; | |
5893 | ||
5894 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); | |
5895 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); | |
5896 | ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ | |
5897 | ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); | |
5898 | ||
5899 | return ocp_data; | |
5900 | } | |
5901 | ||
5902 | static void r8153b_hw_phy_cfg(struct r8152 *tp) | |
5903 | { | |
0e5b36bc | 5904 | u32 ocp_data; |
65b82d69 | 5905 | u16 data; |
5906 | ||
80fd850b HW |
5907 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); |
5908 | if (ocp_data & PCUT_STATUS) { | |
5909 | ocp_data &= ~PCUT_STATUS; | |
5910 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
5911 | } | |
5912 | ||
65b82d69 | 5913 | /* disable ALDPS before updating the PHY parameters */ |
0e5b36bc | 5914 | r8153_aldps_en(tp, false); |
65b82d69 | 5915 | |
5916 | /* disable EEE before updating the PHY parameters */ | |
e7bde56b | 5917 | rtl_eee_enable(tp, false); |
65b82d69 | 5918 | |
80fd850b HW |
5919 | /* U1/U2/L1 idle timer. 500 us */ |
5920 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
5921 | ||
5922 | data = r8153_phy_status(tp, 0); | |
5923 | ||
5924 | switch (data) { | |
5925 | case PHY_STAT_PWRDN: | |
5926 | case PHY_STAT_EXT_INIT: | |
5927 | rtl8152_apply_firmware(tp, true); | |
5928 | ||
5929 | data = r8152_mdio_read(tp, MII_BMCR); | |
5930 | data &= ~BMCR_PDOWN; | |
5931 | r8152_mdio_write(tp, MII_BMCR, data); | |
5932 | break; | |
5933 | case PHY_STAT_LAN_ON: | |
5934 | default: | |
5935 | rtl8152_apply_firmware(tp, false); | |
5936 | break; | |
5937 | } | |
9370f2d0 | 5938 | |
65b82d69 | 5939 | r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); |
5940 | ||
5941 | data = sram_read(tp, SRAM_GREEN_CFG); | |
5942 | data |= R_TUNE_EN; | |
5943 | sram_write(tp, SRAM_GREEN_CFG, data); | |
5944 | data = ocp_reg_read(tp, OCP_NCTL_CFG); | |
5945 | data |= PGA_RETURN_EN; | |
5946 | ocp_reg_write(tp, OCP_NCTL_CFG, data); | |
5947 | ||
5948 | /* ADC Bias Calibration: | |
5949 | * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake | |
5950 | * bit (bit3) to rebuild the real 16-bit data. Write the data to the | |
5951 | * ADC ioffset. | |
5952 | */ | |
5953 | ocp_data = r8152_efuse_read(tp, 0x7d); | |
5954 | data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); | |
5955 | if (data != 0xffff) | |
5956 | ocp_reg_write(tp, OCP_ADC_IOFFSET, data); | |
5957 | ||
5958 | /* ups mode tx-link-pulse timing adjustment: | |
5959 | * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] | |
5960 | * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt | |
5961 | */ | |
5962 | ocp_data = ocp_reg_read(tp, 0xc426); | |
5963 | ocp_data &= 0x3fff; | |
5964 | if (ocp_data) { | |
5965 | u32 swr_cnt_1ms_ini; | |
5966 | ||
5967 | swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; | |
5968 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); | |
5969 | ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; | |
5970 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); | |
5971 | } | |
5972 | ||
5973 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
5974 | ocp_data |= PFM_PWM_SWITCH; | |
5975 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
5976 | ||
5977 | /* Advnace EEE */ | |
a08c0d30 | 5978 | if (!rtl_phy_patch_request(tp, true, true)) { |
65b82d69 | 5979 | data = ocp_reg_read(tp, OCP_POWER_CFG); |
5980 | data |= EEE_CLKDIV_EN; | |
5981 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
0e5b36bc | 5982 | tp->ups_info.eee_ckdiv = true; |
65b82d69 | 5983 | |
5984 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
5985 | data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; | |
5986 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
0e5b36bc HW |
5987 | tp->ups_info.eee_cmod_lv = true; |
5988 | tp->ups_info._10m_ckdiv = true; | |
5989 | tp->ups_info.eee_plloff_giga = true; | |
65b82d69 | 5990 | |
5991 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
5992 | ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); | |
0e5b36bc | 5993 | tp->ups_info._250m_ckdiv = true; |
65b82d69 | 5994 | |
a08c0d30 | 5995 | rtl_phy_patch_request(tp, false, true); |
65b82d69 | 5996 | } |
5997 | ||
e7bde56b HW |
5998 | if (tp->eee_en) |
5999 | rtl_eee_enable(tp, true); | |
65b82d69 | 6000 | |
0e5b36bc HW |
6001 | r8153_aldps_en(tp, true); |
6002 | r8152b_enable_fc(tp); | |
65b82d69 | 6003 | |
6004 | set_bit(PHY_RESET, &tp->flags); | |
6005 | } | |
6006 | ||
195aae32 HW |
6007 | static void r8153c_hw_phy_cfg(struct r8152 *tp) |
6008 | { | |
6009 | r8153b_hw_phy_cfg(tp); | |
6010 | ||
6011 | tp->ups_info.r_tune = true; | |
6012 | } | |
6013 | ||
67ce1a80 HW |
6014 | static void rtl8153_change_mtu(struct r8152 *tp) |
6015 | { | |
6016 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); | |
6017 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
6018 | } | |
6019 | ||
43779f8d | 6020 | static void r8153_first_init(struct r8152 *tp) |
6021 | { | |
6022 | u32 ocp_data; | |
43779f8d | 6023 | |
00a5e360 | 6024 | rxdy_gated_en(tp, true); |
43779f8d | 6025 | r8153_teredo_off(tp); |
6026 | ||
6027 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6028 | ocp_data &= ~RCR_ACPT_ALL; | |
6029 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6030 | ||
43779f8d | 6031 | rtl8152_nic_reset(tp); |
93fe9b18 | 6032 | rtl_reset_bmu(tp); |
43779f8d | 6033 | |
6034 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6035 | ocp_data &= ~NOW_IS_OOB; | |
6036 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6037 | ||
6038 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
6039 | ocp_data &= ~MCU_BORW_EN; | |
6040 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6041 | ||
5f71c840 | 6042 | wait_oob_link_list_ready(tp); |
43779f8d | 6043 | |
6044 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
6045 | ocp_data |= RE_INIT_LL; | |
6046 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6047 | ||
5f71c840 | 6048 | wait_oob_link_list_ready(tp); |
43779f8d | 6049 | |
c5554298 | 6050 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 6051 | |
67ce1a80 | 6052 | rtl8153_change_mtu(tp); |
43779f8d | 6053 | |
6054 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
6055 | ocp_data |= TCR0_AUTO_FIFO; | |
6056 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
6057 | ||
6058 | rtl8152_nic_reset(tp); | |
6059 | ||
6060 | /* rx share fifo credit full threshold */ | |
6061 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
6062 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
6063 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
6064 | /* TX share fifo free credit full threshold */ | |
6065 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
43779f8d | 6066 | } |
6067 | ||
6068 | static void r8153_enter_oob(struct r8152 *tp) | |
6069 | { | |
6070 | u32 ocp_data; | |
43779f8d | 6071 | |
6072 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6073 | ocp_data &= ~NOW_IS_OOB; | |
6074 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6075 | ||
b75d6120 HW |
6076 | /* RX FIFO settings for OOB */ |
6077 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
6078 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
6079 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
6080 | ||
d70b1137 | 6081 | rtl_disable(tp); |
93fe9b18 | 6082 | rtl_reset_bmu(tp); |
43779f8d | 6083 | |
5f71c840 | 6084 | wait_oob_link_list_ready(tp); |
43779f8d | 6085 | |
6086 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
6087 | ocp_data |= RE_INIT_LL; | |
6088 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6089 | ||
5f71c840 | 6090 | wait_oob_link_list_ready(tp); |
43779f8d | 6091 | |
cdf0b86b HW |
6092 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); |
6093 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); | |
43779f8d | 6094 | |
65b82d69 | 6095 | switch (tp->version) { |
6096 | case RTL_VER_03: | |
6097 | case RTL_VER_04: | |
6098 | case RTL_VER_05: | |
6099 | case RTL_VER_06: | |
6100 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
6101 | ocp_data &= ~TEREDO_WAKE_MASK; | |
6102 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
6103 | break; | |
6104 | ||
6105 | case RTL_VER_08: | |
6106 | case RTL_VER_09: | |
195aae32 | 6107 | case RTL_VER_14: |
65b82d69 | 6108 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup |
6109 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
6110 | * the events. Set them to all 1 to clear them. | |
6111 | */ | |
6112 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
6113 | break; | |
6114 | ||
6115 | default: | |
6116 | break; | |
6117 | } | |
43779f8d | 6118 | |
c5554298 | 6119 | rtl_rx_vlan_en(tp, true); |
43779f8d | 6120 | |
59c0b47a | 6121 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); |
43779f8d | 6122 | ocp_data |= ALDPS_PROXY_MODE; |
59c0b47a | 6123 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); |
43779f8d | 6124 | |
6125 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6126 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
6127 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6128 | ||
cdf0b86b HW |
6129 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6130 | ocp_data |= MCU_BORW_EN; | |
6131 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6132 | ||
00a5e360 | 6133 | rxdy_gated_en(tp, false); |
43779f8d | 6134 | |
6135 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6136 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
6137 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6138 | } | |
6139 | ||
d70b1137 | 6140 | static void rtl8153_disable(struct r8152 *tp) |
6141 | { | |
cda9fb01 | 6142 | r8153_aldps_en(tp, false); |
d70b1137 | 6143 | rtl_disable(tp); |
93fe9b18 | 6144 | rtl_reset_bmu(tp); |
cda9fb01 | 6145 | r8153_aldps_en(tp, true); |
d70b1137 | 6146 | } |
6147 | ||
8ceda6d5 HW |
6148 | static u32 fc_pause_on_auto(struct r8152 *tp) |
6149 | { | |
6150 | return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024); | |
6151 | } | |
6152 | ||
6153 | static u32 fc_pause_off_auto(struct r8152 *tp) | |
6154 | { | |
6155 | return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024); | |
6156 | } | |
6157 | ||
6158 | static void r8156_fc_parameter(struct r8152 *tp) | |
6159 | { | |
6160 | u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp); | |
6161 | u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp); | |
6162 | ||
6163 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16); | |
6164 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16); | |
6165 | } | |
6166 | ||
195aae32 HW |
6167 | static int rtl8156_enable(struct r8152 *tp) |
6168 | { | |
6169 | u32 ocp_data; | |
6170 | u16 speed; | |
6171 | ||
715f67f3 | 6172 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
6173 | return -ENODEV; |
6174 | ||
8ceda6d5 | 6175 | r8156_fc_parameter(tp); |
195aae32 HW |
6176 | set_tx_qlen(tp); |
6177 | rtl_set_eee_plus(tp); | |
6178 | r8153_set_rx_early_timeout(tp); | |
6179 | r8153_set_rx_early_size(tp); | |
6180 | ||
6181 | speed = rtl8152_get_speed(tp); | |
6182 | rtl_set_ifg(tp, speed); | |
6183 | ||
6184 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
6185 | if (speed & _2500bps) | |
6186 | ocp_data &= ~IDLE_SPDWN_EN; | |
6187 | else | |
6188 | ocp_data |= IDLE_SPDWN_EN; | |
6189 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
6190 | ||
6191 | if (speed & _1000bps) | |
6192 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); | |
6193 | else if (speed & _500bps) | |
6194 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); | |
6195 | ||
6196 | if (tp->udev->speed == USB_SPEED_HIGH) { | |
6197 | /* USB 0xb45e[3:0] l1_nyet_hird */ | |
6198 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); | |
6199 | ocp_data &= ~0xf; | |
6200 | if (is_flow_control(speed)) | |
6201 | ocp_data |= 0xf; | |
6202 | else | |
6203 | ocp_data |= 0x1; | |
6204 | ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); | |
6205 | } | |
6206 | ||
8ceda6d5 HW |
6207 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); |
6208 | ocp_data &= ~FC_PATCH_TASK; | |
6209 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6210 | usleep_range(1000, 2000); | |
6211 | ocp_data |= FC_PATCH_TASK; | |
6212 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6213 | ||
195aae32 HW |
6214 | return rtl_enable(tp); |
6215 | } | |
6216 | ||
8ceda6d5 HW |
6217 | static void rtl8156_disable(struct r8152 *tp) |
6218 | { | |
6219 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0); | |
6220 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0); | |
6221 | ||
6222 | rtl8153_disable(tp); | |
6223 | } | |
6224 | ||
195aae32 HW |
6225 | static int rtl8156b_enable(struct r8152 *tp) |
6226 | { | |
6227 | u32 ocp_data; | |
6228 | u16 speed; | |
6229 | ||
715f67f3 | 6230 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
6231 | return -ENODEV; |
6232 | ||
6233 | set_tx_qlen(tp); | |
6234 | rtl_set_eee_plus(tp); | |
6235 | ||
6236 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); | |
6237 | ocp_data &= ~RX_AGGR_NUM_MASK; | |
6238 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); | |
6239 | ||
6240 | r8153_set_rx_early_timeout(tp); | |
6241 | r8153_set_rx_early_size(tp); | |
6242 | ||
6243 | speed = rtl8152_get_speed(tp); | |
6244 | rtl_set_ifg(tp, speed); | |
6245 | ||
6246 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
6247 | if (speed & _2500bps) | |
6248 | ocp_data &= ~IDLE_SPDWN_EN; | |
6249 | else | |
6250 | ocp_data |= IDLE_SPDWN_EN; | |
6251 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
6252 | ||
6253 | if (tp->udev->speed == USB_SPEED_HIGH) { | |
6254 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); | |
6255 | ocp_data &= ~0xf; | |
6256 | if (is_flow_control(speed)) | |
6257 | ocp_data |= 0xf; | |
6258 | else | |
6259 | ocp_data |= 0x1; | |
6260 | ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); | |
6261 | } | |
6262 | ||
6263 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
6264 | ocp_data &= ~FC_PATCH_TASK; | |
6265 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6266 | usleep_range(1000, 2000); | |
6267 | ocp_data |= FC_PATCH_TASK; | |
6268 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
6269 | ||
6270 | return rtl_enable(tp); | |
6271 | } | |
6272 | ||
771efeda HW |
6273 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, |
6274 | u32 advertising) | |
ac718b69 | 6275 | { |
771efeda | 6276 | u16 bmcr; |
ac718b69 | 6277 | int ret = 0; |
6278 | ||
ac718b69 | 6279 | if (autoneg == AUTONEG_DISABLE) { |
771efeda HW |
6280 | if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL) |
6281 | return -EINVAL; | |
ac718b69 | 6282 | |
771efeda HW |
6283 | switch (speed) { |
6284 | case SPEED_10: | |
6285 | bmcr = BMCR_SPEED10; | |
65b82d69 | 6286 | if (duplex == DUPLEX_FULL) { |
771efeda | 6287 | bmcr |= BMCR_FULLDPLX; |
0e5b36bc | 6288 | tp->ups_info.speed_duplex = FORCE_10M_FULL; |
65b82d69 | 6289 | } else { |
0e5b36bc | 6290 | tp->ups_info.speed_duplex = FORCE_10M_HALF; |
65b82d69 | 6291 | } |
771efeda HW |
6292 | break; |
6293 | case SPEED_100: | |
6294 | bmcr = BMCR_SPEED100; | |
ac718b69 | 6295 | if (duplex == DUPLEX_FULL) { |
771efeda | 6296 | bmcr |= BMCR_FULLDPLX; |
0e5b36bc | 6297 | tp->ups_info.speed_duplex = FORCE_100M_FULL; |
ac718b69 | 6298 | } else { |
0e5b36bc | 6299 | tp->ups_info.speed_duplex = FORCE_100M_HALF; |
ac718b69 | 6300 | } |
771efeda HW |
6301 | break; |
6302 | case SPEED_1000: | |
6303 | if (tp->mii.supports_gmii) { | |
6304 | bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX; | |
0e5b36bc | 6305 | tp->ups_info.speed_duplex = NWAY_1000M_FULL; |
771efeda | 6306 | break; |
43779f8d | 6307 | } |
df561f66 | 6308 | fallthrough; |
771efeda | 6309 | default: |
ac718b69 | 6310 | ret = -EINVAL; |
6311 | goto out; | |
6312 | } | |
6313 | ||
771efeda HW |
6314 | if (duplex == DUPLEX_FULL) |
6315 | tp->mii.full_duplex = 1; | |
6316 | else | |
6317 | tp->mii.full_duplex = 0; | |
6318 | ||
6319 | tp->mii.force_media = 1; | |
6320 | } else { | |
195aae32 | 6321 | u16 orig, new1; |
771efeda HW |
6322 | u32 support; |
6323 | ||
6324 | support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | | |
6325 | RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; | |
6326 | ||
195aae32 | 6327 | if (tp->mii.supports_gmii) { |
771efeda HW |
6328 | support |= RTL_ADVERTISED_1000_FULL; |
6329 | ||
195aae32 HW |
6330 | if (tp->support_2500full) |
6331 | support |= RTL_ADVERTISED_2500_FULL; | |
6332 | } | |
6333 | ||
771efeda HW |
6334 | if (!(advertising & support)) |
6335 | return -EINVAL; | |
6336 | ||
195aae32 HW |
6337 | orig = r8152_mdio_read(tp, MII_ADVERTISE); |
6338 | new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
771efeda HW |
6339 | ADVERTISE_100HALF | ADVERTISE_100FULL); |
6340 | if (advertising & RTL_ADVERTISED_10_HALF) { | |
195aae32 | 6341 | new1 |= ADVERTISE_10HALF; |
0e5b36bc | 6342 | tp->ups_info.speed_duplex = NWAY_10M_HALF; |
771efeda HW |
6343 | } |
6344 | if (advertising & RTL_ADVERTISED_10_FULL) { | |
195aae32 | 6345 | new1 |= ADVERTISE_10FULL; |
0e5b36bc | 6346 | tp->ups_info.speed_duplex = NWAY_10M_FULL; |
771efeda HW |
6347 | } |
6348 | ||
6349 | if (advertising & RTL_ADVERTISED_100_HALF) { | |
195aae32 | 6350 | new1 |= ADVERTISE_100HALF; |
0e5b36bc | 6351 | tp->ups_info.speed_duplex = NWAY_100M_HALF; |
771efeda HW |
6352 | } |
6353 | if (advertising & RTL_ADVERTISED_100_FULL) { | |
195aae32 | 6354 | new1 |= ADVERTISE_100FULL; |
0e5b36bc | 6355 | tp->ups_info.speed_duplex = NWAY_100M_FULL; |
771efeda HW |
6356 | } |
6357 | ||
195aae32 HW |
6358 | if (orig != new1) { |
6359 | r8152_mdio_write(tp, MII_ADVERTISE, new1); | |
6360 | tp->mii.advertising = new1; | |
771efeda HW |
6361 | } |
6362 | ||
6363 | if (tp->mii.supports_gmii) { | |
195aae32 HW |
6364 | orig = r8152_mdio_read(tp, MII_CTRL1000); |
6365 | new1 = orig & ~(ADVERTISE_1000FULL | | |
771efeda HW |
6366 | ADVERTISE_1000HALF); |
6367 | ||
6368 | if (advertising & RTL_ADVERTISED_1000_FULL) { | |
195aae32 | 6369 | new1 |= ADVERTISE_1000FULL; |
0e5b36bc | 6370 | tp->ups_info.speed_duplex = NWAY_1000M_FULL; |
771efeda HW |
6371 | } |
6372 | ||
195aae32 HW |
6373 | if (orig != new1) |
6374 | r8152_mdio_write(tp, MII_CTRL1000, new1); | |
6375 | } | |
6376 | ||
6377 | if (tp->support_2500full) { | |
6378 | orig = ocp_reg_read(tp, OCP_10GBT_CTRL); | |
6379 | new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; | |
6380 | ||
6381 | if (advertising & RTL_ADVERTISED_2500_FULL) { | |
6382 | new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; | |
6383 | tp->ups_info.speed_duplex = NWAY_2500M_FULL; | |
6384 | } | |
6385 | ||
6386 | if (orig != new1) | |
6387 | ocp_reg_write(tp, OCP_10GBT_CTRL, new1); | |
771efeda HW |
6388 | } |
6389 | ||
ac718b69 | 6390 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
771efeda HW |
6391 | |
6392 | tp->mii.force_media = 0; | |
ac718b69 | 6393 | } |
6394 | ||
fae56178 | 6395 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 6396 | bmcr |= BMCR_RESET; |
6397 | ||
ac718b69 | 6398 | r8152_mdio_write(tp, MII_BMCR, bmcr); |
6399 | ||
fae56178 | 6400 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 6401 | int i; |
6402 | ||
aa66a5f1 | 6403 | for (i = 0; i < 50; i++) { |
6404 | msleep(20); | |
6405 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
6406 | break; | |
6407 | } | |
6408 | } | |
6409 | ||
ac718b69 | 6410 | out: |
ac718b69 | 6411 | return ret; |
6412 | } | |
6413 | ||
d70b1137 | 6414 | static void rtl8152_up(struct r8152 *tp) |
6415 | { | |
715f67f3 | 6416 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
d70b1137 | 6417 | return; |
6418 | ||
cda9fb01 | 6419 | r8152_aldps_en(tp, false); |
d70b1137 | 6420 | r8152b_exit_oob(tp); |
cda9fb01 | 6421 | r8152_aldps_en(tp, true); |
d70b1137 | 6422 | } |
6423 | ||
ac718b69 | 6424 | static void rtl8152_down(struct r8152 *tp) |
6425 | { | |
715f67f3 | 6426 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
6871438c | 6427 | rtl_drop_queued_tx(tp); |
6428 | return; | |
6429 | } | |
6430 | ||
00a5e360 | 6431 | r8152_power_cut_en(tp, false); |
cda9fb01 | 6432 | r8152_aldps_en(tp, false); |
ac718b69 | 6433 | r8152b_enter_oob(tp); |
cda9fb01 | 6434 | r8152_aldps_en(tp, true); |
ac718b69 | 6435 | } |
6436 | ||
d70b1137 | 6437 | static void rtl8153_up(struct r8152 *tp) |
6438 | { | |
19813162 HW |
6439 | u32 ocp_data; |
6440 | ||
715f67f3 | 6441 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
d70b1137 | 6442 | return; |
6443 | ||
b214396f | 6444 | r8153_u1u2en(tp, false); |
3cb3234e | 6445 | r8153_u2p3en(tp, false); |
cda9fb01 | 6446 | r8153_aldps_en(tp, false); |
d70b1137 | 6447 | r8153_first_init(tp); |
19813162 HW |
6448 | |
6449 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); | |
6450 | ocp_data |= LANWAKE_CLR_EN; | |
6451 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
6452 | ||
6453 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); | |
6454 | ocp_data &= ~LANWAKE_PIN; | |
6455 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); | |
6456 | ||
aa475d93 HW |
6457 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); |
6458 | ocp_data &= ~DELAY_PHY_PWR_CHG; | |
6459 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); | |
6460 | ||
cda9fb01 | 6461 | r8153_aldps_en(tp, true); |
3cb3234e | 6462 | |
6463 | switch (tp->version) { | |
6464 | case RTL_VER_03: | |
6465 | case RTL_VER_04: | |
6466 | break; | |
6467 | case RTL_VER_05: | |
6468 | case RTL_VER_06: | |
6469 | default: | |
6470 | r8153_u2p3en(tp, true); | |
6471 | break; | |
6472 | } | |
6473 | ||
b214396f | 6474 | r8153_u1u2en(tp, true); |
d70b1137 | 6475 | } |
6476 | ||
43779f8d | 6477 | static void rtl8153_down(struct r8152 *tp) |
6478 | { | |
19813162 HW |
6479 | u32 ocp_data; |
6480 | ||
715f67f3 | 6481 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
6871438c | 6482 | rtl_drop_queued_tx(tp); |
6483 | return; | |
6484 | } | |
6485 | ||
19813162 HW |
6486 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); |
6487 | ocp_data &= ~LANWAKE_CLR_EN; | |
6488 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
6489 | ||
b9702723 | 6490 | r8153_u1u2en(tp, false); |
b214396f | 6491 | r8153_u2p3en(tp, false); |
b9702723 | 6492 | r8153_power_cut_en(tp, false); |
cda9fb01 | 6493 | r8153_aldps_en(tp, false); |
43779f8d | 6494 | r8153_enter_oob(tp); |
cda9fb01 | 6495 | r8153_aldps_en(tp, true); |
43779f8d | 6496 | } |
6497 | ||
65b82d69 | 6498 | static void rtl8153b_up(struct r8152 *tp) |
6499 | { | |
08997b5e HW |
6500 | u32 ocp_data; |
6501 | ||
715f67f3 | 6502 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
65b82d69 | 6503 | return; |
6504 | ||
6505 | r8153b_u1u2en(tp, false); | |
6506 | r8153_u2p3en(tp, false); | |
0e5b36bc | 6507 | r8153_aldps_en(tp, false); |
65b82d69 | 6508 | |
6509 | r8153_first_init(tp); | |
6510 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); | |
6511 | ||
08997b5e HW |
6512 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
6513 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6514 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6515 | ||
0e5b36bc | 6516 | r8153_aldps_en(tp, true); |
a0246daf | 6517 | |
7a0ae61a | 6518 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 6519 | r8153b_u1u2en(tp, true); |
65b82d69 | 6520 | } |
6521 | ||
6522 | static void rtl8153b_down(struct r8152 *tp) | |
6523 | { | |
08997b5e HW |
6524 | u32 ocp_data; |
6525 | ||
715f67f3 | 6526 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
65b82d69 | 6527 | rtl_drop_queued_tx(tp); |
6528 | return; | |
6529 | } | |
6530 | ||
08997b5e HW |
6531 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
6532 | ocp_data |= PLA_MCU_SPDWN_EN; | |
6533 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6534 | ||
65b82d69 | 6535 | r8153b_u1u2en(tp, false); |
6536 | r8153_u2p3en(tp, false); | |
6537 | r8153b_power_cut_en(tp, false); | |
0e5b36bc | 6538 | r8153_aldps_en(tp, false); |
65b82d69 | 6539 | r8153_enter_oob(tp); |
0e5b36bc | 6540 | r8153_aldps_en(tp, true); |
65b82d69 | 6541 | } |
6542 | ||
195aae32 | 6543 | static void rtl8153c_change_mtu(struct r8152 *tp) |
2dd49e0f | 6544 | { |
195aae32 HW |
6545 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); |
6546 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); | |
2dd49e0f | 6547 | |
195aae32 | 6548 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); |
2dd49e0f | 6549 | |
195aae32 HW |
6550 | /* Adjust the tx fifo free credit full threshold, otherwise |
6551 | * the fifo would be too small to send a jumbo frame packet. | |
6552 | */ | |
6553 | if (tp->netdev->mtu < 8000) | |
6554 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8); | |
2dd49e0f | 6555 | else |
195aae32 | 6556 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8); |
2dd49e0f | 6557 | } |
6558 | ||
195aae32 | 6559 | static void rtl8153c_up(struct r8152 *tp) |
2dd49e0f | 6560 | { |
195aae32 | 6561 | u32 ocp_data; |
2dd49e0f | 6562 | |
715f67f3 | 6563 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 | 6564 | return; |
ac718b69 | 6565 | |
195aae32 HW |
6566 | r8153b_u1u2en(tp, false); |
6567 | r8153_u2p3en(tp, false); | |
6568 | r8153_aldps_en(tp, false); | |
ac718b69 | 6569 | |
195aae32 HW |
6570 | rxdy_gated_en(tp, true); |
6571 | r8153_teredo_off(tp); | |
ac718b69 | 6572 | |
195aae32 HW |
6573 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
6574 | ocp_data &= ~RCR_ACPT_ALL; | |
6575 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
ac718b69 | 6576 | |
195aae32 HW |
6577 | rtl8152_nic_reset(tp); |
6578 | rtl_reset_bmu(tp); | |
a1f83fee | 6579 | |
195aae32 HW |
6580 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
6581 | ocp_data &= ~NOW_IS_OOB; | |
6582 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
9a4be1bd | 6583 | |
195aae32 HW |
6584 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6585 | ocp_data &= ~MCU_BORW_EN; | |
6586 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
ac718b69 | 6587 | |
195aae32 | 6588 | wait_oob_link_list_ready(tp); |
b5403273 | 6589 | |
195aae32 HW |
6590 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6591 | ocp_data |= RE_INIT_LL; | |
6592 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
ac718b69 | 6593 | |
195aae32 | 6594 | wait_oob_link_list_ready(tp); |
ac718b69 | 6595 | |
195aae32 | 6596 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
aa66a5f1 | 6597 | |
195aae32 | 6598 | rtl8153c_change_mtu(tp); |
b5403273 | 6599 | |
195aae32 | 6600 | rtl8152_nic_reset(tp); |
ac718b69 | 6601 | |
195aae32 HW |
6602 | /* rx share fifo credit full threshold */ |
6603 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); | |
6604 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); | |
6605 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
6606 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
a028a9e0 | 6607 | |
195aae32 | 6608 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); |
a028a9e0 | 6609 | |
195aae32 HW |
6610 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); |
6611 | ||
6612 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
6613 | ocp_data |= BIT(8); | |
6614 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
6615 | ||
6616 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
6617 | ||
6618 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6619 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6620 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6621 | ||
6622 | r8153_aldps_en(tp, true); | |
6623 | r8153b_u1u2en(tp, true); | |
6624 | } | |
6625 | ||
195aae32 HW |
6626 | static void rtl8156_change_mtu(struct r8152 *tp) |
6627 | { | |
6628 | u32 rx_max_size = mtu_to_size(tp->netdev->mtu); | |
6629 | ||
6630 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size); | |
6631 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
6632 | r8156_fc_parameter(tp); | |
6633 | ||
6634 | /* TX share fifo free credit full threshold */ | |
6635 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); | |
6636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, | |
6637 | ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); | |
6638 | } | |
6639 | ||
6640 | static void rtl8156_up(struct r8152 *tp) | |
6641 | { | |
6642 | u32 ocp_data; | |
6643 | ||
715f67f3 | 6644 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
6645 | return; |
6646 | ||
6647 | r8153b_u1u2en(tp, false); | |
6648 | r8153_u2p3en(tp, false); | |
6649 | r8153_aldps_en(tp, false); | |
6650 | ||
6651 | rxdy_gated_en(tp, true); | |
6652 | r8153_teredo_off(tp); | |
6653 | ||
6654 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6655 | ocp_data &= ~RCR_ACPT_ALL; | |
6656 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6657 | ||
6658 | rtl8152_nic_reset(tp); | |
6659 | rtl_reset_bmu(tp); | |
6660 | ||
6661 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6662 | ocp_data &= ~NOW_IS_OOB; | |
6663 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6664 | ||
6665 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
6666 | ocp_data &= ~MCU_BORW_EN; | |
6667 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6668 | ||
6669 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); | |
6670 | ||
6671 | rtl8156_change_mtu(tp); | |
6672 | ||
6673 | switch (tp->version) { | |
6674 | case RTL_TEST_01: | |
6675 | case RTL_VER_10: | |
6676 | case RTL_VER_11: | |
6677 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); | |
6678 | ocp_data |= ACT_ODMA; | |
6679 | ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); | |
6680 | break; | |
6681 | default: | |
6682 | break; | |
6683 | } | |
6684 | ||
6685 | /* share FIFO settings */ | |
6686 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); | |
6687 | ocp_data &= ~RXFIFO_FULL_MASK; | |
6688 | ocp_data |= 0x08; | |
6689 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); | |
6690 | ||
6691 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6692 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
6693 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6694 | ||
6695 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); | |
6696 | ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); | |
6697 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); | |
6698 | ||
6699 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); | |
6700 | ||
6701 | if (tp->saved_wolopts != __rtl_get_wol(tp)) { | |
6702 | netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); | |
6703 | __rtl_set_wol(tp, tp->saved_wolopts); | |
6704 | } | |
6705 | ||
6706 | r8153_aldps_en(tp, true); | |
6707 | r8153_u2p3en(tp, true); | |
6708 | ||
6709 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
6710 | r8153b_u1u2en(tp, true); | |
6711 | } | |
6712 | ||
6713 | static void rtl8156_down(struct r8152 *tp) | |
6714 | { | |
6715 | u32 ocp_data; | |
6716 | ||
715f67f3 | 6717 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
195aae32 HW |
6718 | rtl_drop_queued_tx(tp); |
6719 | return; | |
6720 | } | |
6721 | ||
6722 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
6723 | ocp_data |= PLA_MCU_SPDWN_EN; | |
6724 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
6725 | ||
6726 | r8153b_u1u2en(tp, false); | |
6727 | r8153_u2p3en(tp, false); | |
6728 | r8153b_power_cut_en(tp, false); | |
6729 | r8153_aldps_en(tp, false); | |
6730 | ||
6731 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6732 | ocp_data &= ~NOW_IS_OOB; | |
6733 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6734 | ||
b75d6120 HW |
6735 | /* RX FIFO settings for OOB */ |
6736 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); | |
6737 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16); | |
6738 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16); | |
6739 | ||
195aae32 HW |
6740 | rtl_disable(tp); |
6741 | rtl_reset_bmu(tp); | |
6742 | ||
cdf0b86b HW |
6743 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); |
6744 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); | |
6745 | ||
195aae32 HW |
6746 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup |
6747 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
6748 | * the events. Set them to all 1 to clear them. | |
6749 | */ | |
6750 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
6751 | ||
6752 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
6753 | ocp_data |= NOW_IS_OOB; | |
6754 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
6755 | ||
cdf0b86b HW |
6756 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); |
6757 | ocp_data |= MCU_BORW_EN; | |
6758 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
6759 | ||
195aae32 HW |
6760 | rtl_rx_vlan_en(tp, true); |
6761 | rxdy_gated_en(tp, false); | |
6762 | ||
6763 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
6764 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
6765 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
6766 | ||
6767 | r8153_aldps_en(tp, true); | |
6768 | } | |
6769 | ||
6770 | static bool rtl8152_in_nway(struct r8152 *tp) | |
6771 | { | |
6772 | u16 nway_state; | |
6773 | ||
6774 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
6775 | tp->ocp_base = 0x2000; | |
6776 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
6777 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
6778 | ||
6779 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
6780 | if (nway_state & 0xc000) | |
6781 | return false; | |
6782 | else | |
6783 | return true; | |
6784 | } | |
6785 | ||
6786 | static bool rtl8153_in_nway(struct r8152 *tp) | |
6787 | { | |
6788 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
6789 | ||
6790 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
6791 | return false; | |
6792 | else | |
6793 | return true; | |
6794 | } | |
6795 | ||
45bf944e HW |
6796 | static void r8156_mdio_force_mode(struct r8152 *tp) |
6797 | { | |
6798 | u16 data; | |
6799 | ||
6800 | /* Select force mode through 0xa5b4 bit 15 | |
6801 | * 0: MDIO force mode | |
6802 | * 1: MMD force mode | |
6803 | */ | |
6804 | data = ocp_reg_read(tp, 0xa5b4); | |
6805 | if (data & BIT(15)) { | |
6806 | data &= ~BIT(15); | |
6807 | ocp_reg_write(tp, 0xa5b4, data); | |
6808 | } | |
6809 | } | |
6810 | ||
195aae32 HW |
6811 | static void set_carrier(struct r8152 *tp) |
6812 | { | |
6813 | struct net_device *netdev = tp->netdev; | |
6814 | struct napi_struct *napi = &tp->napi; | |
6815 | u16 speed; | |
6816 | ||
6817 | speed = rtl8152_get_speed(tp); | |
6818 | ||
6819 | if (speed & LINK_STATUS) { | |
6820 | if (!netif_carrier_ok(netdev)) { | |
6821 | tp->rtl_ops.enable(tp); | |
6822 | netif_stop_queue(netdev); | |
6823 | napi_disable(napi); | |
6824 | netif_carrier_on(netdev); | |
6825 | rtl_start_rx(tp); | |
6826 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); | |
6827 | _rtl8152_set_rx_mode(netdev); | |
6828 | napi_enable(napi); | |
6829 | netif_wake_queue(netdev); | |
6830 | netif_info(tp, link, netdev, "carrier on\n"); | |
6831 | } else if (netif_queue_stopped(netdev) && | |
6832 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
6833 | netif_wake_queue(netdev); | |
6834 | } | |
6835 | } else { | |
6836 | if (netif_carrier_ok(netdev)) { | |
6837 | netif_carrier_off(netdev); | |
6838 | tasklet_disable(&tp->tx_tl); | |
6839 | napi_disable(napi); | |
6840 | tp->rtl_ops.disable(tp); | |
6841 | napi_enable(napi); | |
6842 | tasklet_enable(&tp->tx_tl); | |
6843 | netif_info(tp, link, netdev, "carrier off\n"); | |
6844 | } | |
6845 | } | |
6846 | } | |
6847 | ||
6848 | static void rtl_work_func_t(struct work_struct *work) | |
6849 | { | |
6850 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
6851 | ||
6852 | /* If the device is unplugged or !netif_running(), the workqueue | |
6853 | * doesn't need to wake the device, and could return directly. | |
6854 | */ | |
715f67f3 | 6855 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev)) |
195aae32 HW |
6856 | return; |
6857 | ||
6858 | if (usb_autopm_get_interface(tp->intf) < 0) | |
6859 | return; | |
6860 | ||
6861 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
6862 | goto out1; | |
6863 | ||
6864 | if (!mutex_trylock(&tp->control)) { | |
6865 | schedule_delayed_work(&tp->schedule, 0); | |
6866 | goto out1; | |
6867 | } | |
6868 | ||
6869 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) | |
6870 | set_carrier(tp); | |
6871 | ||
6872 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
6873 | _rtl8152_set_rx_mode(tp->netdev); | |
6874 | ||
6875 | /* don't schedule tasket before linking */ | |
6876 | if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && | |
6877 | netif_carrier_ok(tp->netdev)) | |
6878 | tasklet_schedule(&tp->tx_tl); | |
6879 | ||
baf33d7a HW |
6880 | if (test_and_clear_bit(RX_EPROTO, &tp->flags) && |
6881 | !list_empty(&tp->rx_done)) | |
6882 | napi_schedule(&tp->napi); | |
6883 | ||
195aae32 HW |
6884 | mutex_unlock(&tp->control); |
6885 | ||
6886 | out1: | |
6887 | usb_autopm_put_interface(tp->intf); | |
6888 | } | |
6889 | ||
6890 | static void rtl_hw_phy_work_func_t(struct work_struct *work) | |
6891 | { | |
6892 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
6893 | ||
715f67f3 | 6894 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
6895 | return; |
6896 | ||
6897 | if (usb_autopm_get_interface(tp->intf) < 0) | |
6898 | return; | |
a028a9e0 | 6899 | |
6900 | mutex_lock(&tp->control); | |
6901 | ||
9370f2d0 HW |
6902 | if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) { |
6903 | tp->rtl_fw.retry = false; | |
6904 | tp->rtl_fw.fw = NULL; | |
6905 | ||
6906 | /* Delay execution in case request_firmware() is not ready yet. | |
6907 | */ | |
6908 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10); | |
6909 | goto ignore_once; | |
6910 | } | |
6911 | ||
a028a9e0 | 6912 | tp->rtl_ops.hw_phy_cfg(tp); |
6913 | ||
771efeda HW |
6914 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex, |
6915 | tp->advertising); | |
9d21c0d8 | 6916 | |
9370f2d0 | 6917 | ignore_once: |
a028a9e0 | 6918 | mutex_unlock(&tp->control); |
6919 | ||
6920 | usb_autopm_put_interface(tp->intf); | |
6921 | } | |
6922 | ||
5ee3c60c | 6923 | #ifdef CONFIG_PM_SLEEP |
6924 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
6925 | void *data) | |
6926 | { | |
6927 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
6928 | ||
6929 | switch (action) { | |
6930 | case PM_HIBERNATION_PREPARE: | |
6931 | case PM_SUSPEND_PREPARE: | |
6932 | usb_autopm_get_interface(tp->intf); | |
6933 | break; | |
6934 | ||
6935 | case PM_POST_HIBERNATION: | |
6936 | case PM_POST_SUSPEND: | |
6937 | usb_autopm_put_interface(tp->intf); | |
6938 | break; | |
6939 | ||
6940 | case PM_POST_RESTORE: | |
6941 | case PM_RESTORE_PREPARE: | |
6942 | default: | |
6943 | break; | |
6944 | } | |
6945 | ||
6946 | return NOTIFY_DONE; | |
6947 | } | |
6948 | #endif | |
6949 | ||
ac718b69 | 6950 | static int rtl8152_open(struct net_device *netdev) |
6951 | { | |
6952 | struct r8152 *tp = netdev_priv(netdev); | |
6953 | int res = 0; | |
6954 | ||
9370f2d0 HW |
6955 | if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) { |
6956 | cancel_delayed_work_sync(&tp->hw_phy_work); | |
6957 | rtl_hw_phy_work_func_t(&tp->hw_phy_work.work); | |
6958 | } | |
6959 | ||
7e9da481 | 6960 | res = alloc_all_mem(tp); |
6961 | if (res) | |
6962 | goto out; | |
6963 | ||
9a4be1bd | 6964 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
6965 | if (res < 0) |
6966 | goto out_free; | |
9a4be1bd | 6967 | |
b5403273 | 6968 | mutex_lock(&tp->control); |
6969 | ||
7e9da481 | 6970 | tp->rtl_ops.up(tp); |
6971 | ||
3d55f44f | 6972 | netif_carrier_off(netdev); |
6973 | netif_start_queue(netdev); | |
6974 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 6975 | |
40a82917 | 6976 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
6977 | if (res) { | |
6978 | if (res == -ENODEV) | |
6979 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
6980 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
6981 | res); | |
ca0a7531 | 6982 | goto out_unlock; |
ac718b69 | 6983 | } |
ca0a7531 | 6984 | napi_enable(&tp->napi); |
d2187f8e | 6985 | tasklet_enable(&tp->tx_tl); |
ac718b69 | 6986 | |
b5403273 | 6987 | mutex_unlock(&tp->control); |
6988 | ||
9a4be1bd | 6989 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 6990 | #ifdef CONFIG_PM_SLEEP |
6991 | tp->pm_notifier.notifier_call = rtl_notifier; | |
6992 | register_pm_notifier(&tp->pm_notifier); | |
6993 | #endif | |
ca0a7531 | 6994 | return 0; |
ac718b69 | 6995 | |
ca0a7531 GR |
6996 | out_unlock: |
6997 | mutex_unlock(&tp->control); | |
6998 | usb_autopm_put_interface(tp->intf); | |
6999 | out_free: | |
7000 | free_all_mem(tp); | |
7e9da481 | 7001 | out: |
ac718b69 | 7002 | return res; |
7003 | } | |
7004 | ||
7005 | static int rtl8152_close(struct net_device *netdev) | |
7006 | { | |
7007 | struct r8152 *tp = netdev_priv(netdev); | |
7008 | int res = 0; | |
7009 | ||
5ee3c60c | 7010 | #ifdef CONFIG_PM_SLEEP |
7011 | unregister_pm_notifier(&tp->pm_notifier); | |
7012 | #endif | |
d2187f8e | 7013 | tasklet_disable(&tp->tx_tl); |
ac718b69 | 7014 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 7015 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 7016 | cancel_delayed_work_sync(&tp->schedule); |
84811412 | 7017 | napi_disable(&tp->napi); |
ac718b69 | 7018 | netif_stop_queue(netdev); |
9a4be1bd | 7019 | |
7020 | res = usb_autopm_get_interface(tp->intf); | |
715f67f3 | 7021 | if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { |
9a4be1bd | 7022 | rtl_drop_queued_tx(tp); |
d823ab68 | 7023 | rtl_stop_rx(tp); |
9a4be1bd | 7024 | } else { |
b5403273 | 7025 | mutex_lock(&tp->control); |
7026 | ||
9a4be1bd | 7027 | tp->rtl_ops.down(tp); |
b5403273 | 7028 | |
7029 | mutex_unlock(&tp->control); | |
9c23aa51 | 7030 | } |
b5403273 | 7031 | |
9c23aa51 | 7032 | if (!res) |
9a4be1bd | 7033 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 7034 | |
7e9da481 | 7035 | free_all_mem(tp); |
7036 | ||
ac718b69 | 7037 | return res; |
7038 | } | |
7039 | ||
4f1d4d54 | 7040 | static void rtl_tally_reset(struct r8152 *tp) |
7041 | { | |
7042 | u32 ocp_data; | |
7043 | ||
7044 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
7045 | ocp_data |= TALLY_RESET; | |
7046 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
7047 | } | |
7048 | ||
ac718b69 | 7049 | static void r8152b_init(struct r8152 *tp) |
7050 | { | |
ebc2ec48 | 7051 | u32 ocp_data; |
2dd436da | 7052 | u16 data; |
ac718b69 | 7053 | |
715f67f3 | 7054 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 7055 | return; |
7056 | ||
2dd436da | 7057 | data = r8152_mdio_read(tp, MII_BMCR); |
7058 | if (data & BMCR_PDOWN) { | |
7059 | data &= ~BMCR_PDOWN; | |
7060 | r8152_mdio_write(tp, MII_BMCR, data); | |
7061 | } | |
7062 | ||
cda9fb01 | 7063 | r8152_aldps_en(tp, false); |
d70b1137 | 7064 | |
ac718b69 | 7065 | if (tp->version == RTL_VER_01) { |
7066 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
7067 | ocp_data &= ~LED_MODE_MASK; | |
7068 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
7069 | } | |
7070 | ||
00a5e360 | 7071 | r8152_power_cut_en(tp, false); |
ac718b69 | 7072 | |
ac718b69 | 7073 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
7074 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
7075 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7076 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
7077 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
7078 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
7079 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
7080 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
7081 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
7082 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
7083 | ||
4f1d4d54 | 7084 | rtl_tally_reset(tp); |
ac718b69 | 7085 | |
ebc2ec48 | 7086 | /* enable rx aggregation */ |
ac718b69 | 7087 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 7088 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 7089 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
7090 | } | |
7091 | ||
195aae32 HW |
7092 | static void r8153_init(struct r8152 *tp) |
7093 | { | |
7094 | u32 ocp_data; | |
7095 | u16 data; | |
7096 | int i; | |
7097 | ||
715f67f3 | 7098 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7099 | return; |
7100 | ||
7101 | r8153_u1u2en(tp, false); | |
7102 | ||
7103 | for (i = 0; i < 500; i++) { | |
7104 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7105 | AUTOLOAD_DONE) | |
7106 | break; | |
7107 | ||
7108 | msleep(20); | |
715f67f3 | 7109 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7110 | break; |
7111 | } | |
7112 | ||
7113 | data = r8153_phy_status(tp, 0); | |
7114 | ||
7115 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || | |
7116 | tp->version == RTL_VER_05) | |
7117 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
7118 | ||
7119 | data = r8152_mdio_read(tp, MII_BMCR); | |
7120 | if (data & BMCR_PDOWN) { | |
7121 | data &= ~BMCR_PDOWN; | |
7122 | r8152_mdio_write(tp, MII_BMCR, data); | |
7123 | } | |
7124 | ||
7125 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7126 | ||
7127 | r8153_u2p3en(tp, false); | |
7128 | ||
7129 | if (tp->version == RTL_VER_04) { | |
7130 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
7131 | ocp_data &= ~pwd_dn_scale_mask; | |
7132 | ocp_data |= pwd_dn_scale(96); | |
7133 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
7134 | ||
7135 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
7136 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
7137 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
7138 | } else if (tp->version == RTL_VER_05) { | |
7139 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
7140 | ocp_data &= ~ECM_ALDPS; | |
7141 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
7142 | ||
7143 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); | |
7144 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
7145 | ocp_data &= ~DYNAMIC_BURST; | |
7146 | else | |
7147 | ocp_data |= DYNAMIC_BURST; | |
7148 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
7149 | } else if (tp->version == RTL_VER_06) { | |
7150 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); | |
7151 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
7152 | ocp_data &= ~DYNAMIC_BURST; | |
7153 | else | |
7154 | ocp_data |= DYNAMIC_BURST; | |
7155 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
7156 | ||
7157 | r8153_queue_wake(tp, false); | |
7158 | ||
7159 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
7160 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
7161 | ocp_data |= CUR_LINK_OK; | |
7162 | else | |
7163 | ocp_data &= ~CUR_LINK_OK; | |
7164 | ocp_data |= POLL_LINK_CHG; | |
7165 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
7166 | } | |
7167 | ||
7168 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
7169 | ocp_data |= EP4_FULL_FC; | |
7170 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
7171 | ||
7172 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
7173 | ocp_data &= ~TIMER11_EN; | |
7174 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
7175 | ||
7176 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
7177 | ocp_data &= ~LED_MODE_MASK; | |
7178 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
7179 | ||
7180 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; | |
7181 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) | |
7182 | ocp_data |= LPM_TIMER_500MS; | |
7183 | else | |
7184 | ocp_data |= LPM_TIMER_500US; | |
7185 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
7186 | ||
7187 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
7188 | ocp_data &= ~SEN_VAL_MASK; | |
7189 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
7190 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
7191 | ||
7192 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); | |
7193 | ||
7194 | r8153_power_cut_en(tp, false); | |
7195 | rtl_runtime_suspend_enable(tp, false); | |
7196 | r8153_mac_clk_speed_down(tp, false); | |
7197 | r8153_u1u2en(tp, true); | |
7198 | usb_enable_lpm(tp->udev); | |
7199 | ||
7200 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); | |
7201 | ocp_data |= LANWAKE_CLR_EN; | |
7202 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); | |
7203 | ||
7204 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); | |
7205 | ocp_data &= ~LANWAKE_PIN; | |
7206 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); | |
7207 | ||
7208 | /* rx aggregation */ | |
7209 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7210 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
9c68011b | 7211 | if (tp->dell_tb_rx_agg_bug) |
195aae32 HW |
7212 | ocp_data |= RX_AGG_DISABLE; |
7213 | ||
7214 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7215 | ||
7216 | rtl_tally_reset(tp); | |
7217 | ||
7218 | switch (tp->udev->speed) { | |
7219 | case USB_SPEED_SUPER: | |
7220 | case USB_SPEED_SUPER_PLUS: | |
7221 | tp->coalesce = COALESCE_SUPER; | |
7222 | break; | |
7223 | case USB_SPEED_HIGH: | |
7224 | tp->coalesce = COALESCE_HIGH; | |
7225 | break; | |
7226 | default: | |
7227 | tp->coalesce = COALESCE_SLOW; | |
7228 | break; | |
7229 | } | |
7230 | } | |
7231 | ||
7232 | static void r8153b_init(struct r8152 *tp) | |
7233 | { | |
7234 | u32 ocp_data; | |
7235 | u16 data; | |
7236 | int i; | |
7237 | ||
715f67f3 | 7238 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7239 | return; |
7240 | ||
7241 | r8153b_u1u2en(tp, false); | |
7242 | ||
7243 | for (i = 0; i < 500; i++) { | |
7244 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7245 | AUTOLOAD_DONE) | |
7246 | break; | |
7247 | ||
7248 | msleep(20); | |
715f67f3 | 7249 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7250 | break; |
7251 | } | |
7252 | ||
7253 | data = r8153_phy_status(tp, 0); | |
7254 | ||
7255 | data = r8152_mdio_read(tp, MII_BMCR); | |
7256 | if (data & BMCR_PDOWN) { | |
7257 | data &= ~BMCR_PDOWN; | |
7258 | r8152_mdio_write(tp, MII_BMCR, data); | |
7259 | } | |
7260 | ||
7261 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7262 | ||
7263 | r8153_u2p3en(tp, false); | |
7264 | ||
7265 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
7266 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
7267 | ||
7268 | r8153b_power_cut_en(tp, false); | |
7269 | r8153b_ups_en(tp, false); | |
7270 | r8153_queue_wake(tp, false); | |
7271 | rtl_runtime_suspend_enable(tp, false); | |
7272 | ||
7273 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
7274 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
7275 | ocp_data |= CUR_LINK_OK; | |
7276 | else | |
7277 | ocp_data &= ~CUR_LINK_OK; | |
7278 | ocp_data |= POLL_LINK_CHG; | |
7279 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
7280 | ||
7281 | if (tp->udev->speed >= USB_SPEED_SUPER) | |
7282 | r8153b_u1u2en(tp, true); | |
7283 | ||
7284 | usb_enable_lpm(tp->udev); | |
7285 | ||
7286 | /* MAC clock speed down */ | |
7287 | r8153_mac_clk_speed_down(tp, true); | |
7288 | ||
7289 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); | |
7290 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
7291 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
7292 | ||
7293 | if (tp->version == RTL_VER_09) { | |
7294 | /* Disable Test IO for 32QFN */ | |
7295 | if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { | |
7296 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7297 | ocp_data |= TEST_IO_OFF; | |
7298 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7299 | } | |
7300 | } | |
7301 | ||
7302 | set_bit(GREEN_ETHERNET, &tp->flags); | |
7303 | ||
7304 | /* rx aggregation */ | |
7305 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7306 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
7307 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7308 | ||
7309 | rtl_tally_reset(tp); | |
7310 | ||
7311 | tp->coalesce = 15000; /* 15 us */ | |
7312 | } | |
7313 | ||
7314 | static void r8153c_init(struct r8152 *tp) | |
7315 | { | |
7316 | u32 ocp_data; | |
7317 | u16 data; | |
7318 | int i; | |
7319 | ||
715f67f3 | 7320 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7321 | return; |
7322 | ||
7323 | r8153b_u1u2en(tp, false); | |
7324 | ||
7325 | /* Disable spi_en */ | |
7326 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
7327 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
7328 | ocp_data &= ~BIT(3); | |
7329 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
7330 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); | |
7331 | ocp_data |= BIT(1); | |
7332 | ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); | |
7333 | ||
7334 | for (i = 0; i < 500; i++) { | |
7335 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
7336 | AUTOLOAD_DONE) | |
7337 | break; | |
7338 | ||
7339 | msleep(20); | |
715f67f3 | 7340 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 HW |
7341 | return; |
7342 | } | |
7343 | ||
7344 | data = r8153_phy_status(tp, 0); | |
7345 | ||
7346 | data = r8152_mdio_read(tp, MII_BMCR); | |
7347 | if (data & BMCR_PDOWN) { | |
7348 | data &= ~BMCR_PDOWN; | |
7349 | r8152_mdio_write(tp, MII_BMCR, data); | |
7350 | } | |
7351 | ||
7352 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7353 | ||
7354 | r8153_u2p3en(tp, false); | |
7355 | ||
7356 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
7357 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
7358 | ||
7359 | r8153b_power_cut_en(tp, false); | |
7360 | r8153c_ups_en(tp, false); | |
7361 | r8153_queue_wake(tp, false); | |
7362 | rtl_runtime_suspend_enable(tp, false); | |
7363 | ||
7364 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); | |
7365 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
7366 | ocp_data |= CUR_LINK_OK; | |
7367 | else | |
7368 | ocp_data &= ~CUR_LINK_OK; | |
7369 | ||
7370 | ocp_data |= POLL_LINK_CHG; | |
7371 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
7372 | ||
7373 | r8153b_u1u2en(tp, true); | |
7374 | ||
7375 | usb_enable_lpm(tp->udev); | |
7376 | ||
7377 | /* MAC clock speed down */ | |
7378 | r8153_mac_clk_speed_down(tp, true); | |
7379 | ||
7380 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); | |
7381 | ocp_data &= ~BIT(7); | |
7382 | ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); | |
7383 | ||
7384 | set_bit(GREEN_ETHERNET, &tp->flags); | |
7385 | ||
7386 | /* rx aggregation */ | |
7387 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
7388 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
7389 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
7390 | ||
7391 | rtl_tally_reset(tp); | |
7392 | ||
7393 | tp->coalesce = 15000; /* 15 us */ | |
7394 | } | |
7395 | ||
7396 | static void r8156_hw_phy_cfg(struct r8152 *tp) | |
7397 | { | |
7398 | u32 ocp_data; | |
7399 | u16 data; | |
7400 | ||
7401 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
7402 | if (ocp_data & PCUT_STATUS) { | |
7403 | ocp_data &= ~PCUT_STATUS; | |
7404 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
7405 | } | |
7406 | ||
7407 | data = r8153_phy_status(tp, 0); | |
7408 | switch (data) { | |
7409 | case PHY_STAT_EXT_INIT: | |
7410 | rtl8152_apply_firmware(tp, true); | |
7411 | ||
7412 | data = ocp_reg_read(tp, 0xa468); | |
7413 | data &= ~(BIT(3) | BIT(1)); | |
7414 | ocp_reg_write(tp, 0xa468, data); | |
7415 | break; | |
7416 | case PHY_STAT_LAN_ON: | |
7417 | case PHY_STAT_PWRDN: | |
7418 | default: | |
7419 | rtl8152_apply_firmware(tp, false); | |
7420 | break; | |
7421 | } | |
7422 | ||
7423 | /* disable ALDPS before updating the PHY parameters */ | |
7424 | r8153_aldps_en(tp, false); | |
7425 | ||
7426 | /* disable EEE before updating the PHY parameters */ | |
7427 | rtl_eee_enable(tp, false); | |
7428 | ||
7429 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7430 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); | |
7431 | ||
7432 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7433 | ocp_data |= PFM_PWM_SWITCH; | |
7434 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7435 | ||
7436 | switch (tp->version) { | |
7437 | case RTL_VER_10: | |
7438 | data = ocp_reg_read(tp, 0xad40); | |
7439 | data &= ~0x3ff; | |
7440 | data |= BIT(7) | BIT(2); | |
7441 | ocp_reg_write(tp, 0xad40, data); | |
7442 | ||
7443 | data = ocp_reg_read(tp, 0xad4e); | |
7444 | data |= BIT(4); | |
7445 | ocp_reg_write(tp, 0xad4e, data); | |
7446 | data = ocp_reg_read(tp, 0xad16); | |
7447 | data &= ~0x3ff; | |
7448 | data |= 0x6; | |
7449 | ocp_reg_write(tp, 0xad16, data); | |
7450 | data = ocp_reg_read(tp, 0xad32); | |
7451 | data &= ~0x3f; | |
7452 | data |= 6; | |
7453 | ocp_reg_write(tp, 0xad32, data); | |
7454 | data = ocp_reg_read(tp, 0xac08); | |
7455 | data &= ~(BIT(12) | BIT(8)); | |
7456 | ocp_reg_write(tp, 0xac08, data); | |
7457 | data = ocp_reg_read(tp, 0xac8a); | |
7458 | data |= BIT(12) | BIT(13) | BIT(14); | |
7459 | data &= ~BIT(15); | |
7460 | ocp_reg_write(tp, 0xac8a, data); | |
7461 | data = ocp_reg_read(tp, 0xad18); | |
7462 | data |= BIT(10); | |
7463 | ocp_reg_write(tp, 0xad18, data); | |
7464 | data = ocp_reg_read(tp, 0xad1a); | |
7465 | data |= 0x3ff; | |
7466 | ocp_reg_write(tp, 0xad1a, data); | |
7467 | data = ocp_reg_read(tp, 0xad1c); | |
7468 | data |= 0x3ff; | |
7469 | ocp_reg_write(tp, 0xad1c, data); | |
7470 | ||
7471 | data = sram_read(tp, 0x80ea); | |
7472 | data &= ~0xff00; | |
7473 | data |= 0xc400; | |
7474 | sram_write(tp, 0x80ea, data); | |
7475 | data = sram_read(tp, 0x80eb); | |
7476 | data &= ~0x0700; | |
7477 | data |= 0x0300; | |
7478 | sram_write(tp, 0x80eb, data); | |
7479 | data = sram_read(tp, 0x80f8); | |
7480 | data &= ~0xff00; | |
7481 | data |= 0x1c00; | |
7482 | sram_write(tp, 0x80f8, data); | |
7483 | data = sram_read(tp, 0x80f1); | |
7484 | data &= ~0xff00; | |
7485 | data |= 0x3000; | |
7486 | sram_write(tp, 0x80f1, data); | |
7487 | ||
7488 | data = sram_read(tp, 0x80fe); | |
7489 | data &= ~0xff00; | |
7490 | data |= 0xa500; | |
7491 | sram_write(tp, 0x80fe, data); | |
7492 | data = sram_read(tp, 0x8102); | |
7493 | data &= ~0xff00; | |
7494 | data |= 0x5000; | |
7495 | sram_write(tp, 0x8102, data); | |
7496 | data = sram_read(tp, 0x8015); | |
7497 | data &= ~0xff00; | |
7498 | data |= 0x3300; | |
7499 | sram_write(tp, 0x8015, data); | |
7500 | data = sram_read(tp, 0x8100); | |
7501 | data &= ~0xff00; | |
7502 | data |= 0x7000; | |
7503 | sram_write(tp, 0x8100, data); | |
7504 | data = sram_read(tp, 0x8014); | |
7505 | data &= ~0xff00; | |
7506 | data |= 0xf000; | |
7507 | sram_write(tp, 0x8014, data); | |
7508 | data = sram_read(tp, 0x8016); | |
7509 | data &= ~0xff00; | |
7510 | data |= 0x6500; | |
7511 | sram_write(tp, 0x8016, data); | |
7512 | data = sram_read(tp, 0x80dc); | |
7513 | data &= ~0xff00; | |
7514 | data |= 0xed00; | |
7515 | sram_write(tp, 0x80dc, data); | |
7516 | data = sram_read(tp, 0x80df); | |
7517 | data |= BIT(8); | |
7518 | sram_write(tp, 0x80df, data); | |
7519 | data = sram_read(tp, 0x80e1); | |
7520 | data &= ~BIT(8); | |
7521 | sram_write(tp, 0x80e1, data); | |
7522 | ||
7523 | data = ocp_reg_read(tp, 0xbf06); | |
7524 | data &= ~0x003f; | |
7525 | data |= 0x0038; | |
7526 | ocp_reg_write(tp, 0xbf06, data); | |
7527 | ||
7528 | sram_write(tp, 0x819f, 0xddb6); | |
7529 | ||
7530 | ocp_reg_write(tp, 0xbc34, 0x5555); | |
7531 | data = ocp_reg_read(tp, 0xbf0a); | |
7532 | data &= ~0x0e00; | |
7533 | data |= 0x0a00; | |
7534 | ocp_reg_write(tp, 0xbf0a, data); | |
7535 | ||
7536 | data = ocp_reg_read(tp, 0xbd2c); | |
7537 | data &= ~BIT(13); | |
7538 | ocp_reg_write(tp, 0xbd2c, data); | |
7539 | break; | |
7540 | case RTL_VER_11: | |
7541 | data = ocp_reg_read(tp, 0xad16); | |
7542 | data |= 0x3ff; | |
7543 | ocp_reg_write(tp, 0xad16, data); | |
7544 | data = ocp_reg_read(tp, 0xad32); | |
7545 | data &= ~0x3f; | |
7546 | data |= 6; | |
7547 | ocp_reg_write(tp, 0xad32, data); | |
7548 | data = ocp_reg_read(tp, 0xac08); | |
7549 | data &= ~(BIT(12) | BIT(8)); | |
7550 | ocp_reg_write(tp, 0xac08, data); | |
7551 | data = ocp_reg_read(tp, 0xacc0); | |
7552 | data &= ~0x3; | |
7553 | data |= BIT(1); | |
7554 | ocp_reg_write(tp, 0xacc0, data); | |
7555 | data = ocp_reg_read(tp, 0xad40); | |
7556 | data &= ~0xe7; | |
7557 | data |= BIT(6) | BIT(2); | |
7558 | ocp_reg_write(tp, 0xad40, data); | |
7559 | data = ocp_reg_read(tp, 0xac14); | |
7560 | data &= ~BIT(7); | |
7561 | ocp_reg_write(tp, 0xac14, data); | |
7562 | data = ocp_reg_read(tp, 0xac80); | |
7563 | data &= ~(BIT(8) | BIT(9)); | |
7564 | ocp_reg_write(tp, 0xac80, data); | |
7565 | data = ocp_reg_read(tp, 0xac5e); | |
7566 | data &= ~0x7; | |
7567 | data |= BIT(1); | |
7568 | ocp_reg_write(tp, 0xac5e, data); | |
7569 | ocp_reg_write(tp, 0xad4c, 0x00a8); | |
7570 | ocp_reg_write(tp, 0xac5c, 0x01ff); | |
7571 | data = ocp_reg_read(tp, 0xac8a); | |
7572 | data &= ~0xf0; | |
7573 | data |= BIT(4) | BIT(5); | |
7574 | ocp_reg_write(tp, 0xac8a, data); | |
7575 | ocp_reg_write(tp, 0xb87c, 0x8157); | |
7576 | data = ocp_reg_read(tp, 0xb87e); | |
7577 | data &= ~0xff00; | |
7578 | data |= 0x0500; | |
7579 | ocp_reg_write(tp, 0xb87e, data); | |
7580 | ocp_reg_write(tp, 0xb87c, 0x8159); | |
7581 | data = ocp_reg_read(tp, 0xb87e); | |
7582 | data &= ~0xff00; | |
7583 | data |= 0x0700; | |
7584 | ocp_reg_write(tp, 0xb87e, data); | |
7585 | ||
7586 | /* AAGC */ | |
7587 | ocp_reg_write(tp, 0xb87c, 0x80a2); | |
7588 | ocp_reg_write(tp, 0xb87e, 0x0153); | |
7589 | ocp_reg_write(tp, 0xb87c, 0x809c); | |
7590 | ocp_reg_write(tp, 0xb87e, 0x0153); | |
7591 | ||
7592 | /* EEE parameter */ | |
7593 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); | |
7594 | ||
7595 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); | |
7596 | ocp_data |= EN_XG_LIP | EN_G_LIP; | |
7597 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); | |
7598 | ||
7599 | sram_write(tp, 0x8257, 0x020f); /* XG PLL */ | |
7600 | sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ | |
7601 | ||
7602 | if (rtl_phy_patch_request(tp, true, true)) | |
7603 | return; | |
7604 | ||
7605 | /* Advance EEE */ | |
7606 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
7607 | ocp_data |= EEE_SPDWN_EN; | |
7608 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
7609 | ||
7610 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
7611 | data &= ~(EN_EEE_100 | EN_EEE_1000); | |
7612 | data |= EN_10M_CLKDIV; | |
7613 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
7614 | tp->ups_info._10m_ckdiv = true; | |
7615 | tp->ups_info.eee_plloff_100 = false; | |
7616 | tp->ups_info.eee_plloff_giga = false; | |
7617 | ||
7618 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
7619 | data &= ~EEE_CLKDIV_EN; | |
7620 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
7621 | tp->ups_info.eee_ckdiv = false; | |
7622 | ||
7623 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
7624 | ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5)); | |
7625 | tp->ups_info._250m_ckdiv = false; | |
7626 | ||
7627 | rtl_phy_patch_request(tp, false, true); | |
7628 | ||
7629 | /* enable ADC Ibias Cal */ | |
7630 | data = ocp_reg_read(tp, 0xd068); | |
7631 | data |= BIT(13); | |
7632 | ocp_reg_write(tp, 0xd068, data); | |
7633 | ||
7634 | /* enable Thermal Sensor */ | |
7635 | data = sram_read(tp, 0x81a2); | |
7636 | data &= ~BIT(8); | |
7637 | sram_write(tp, 0x81a2, data); | |
7638 | data = ocp_reg_read(tp, 0xb54c); | |
7639 | data &= ~0xff00; | |
7640 | data |= 0xdb00; | |
7641 | ocp_reg_write(tp, 0xb54c, data); | |
7642 | ||
7643 | /* Nway 2.5G Lite */ | |
7644 | data = ocp_reg_read(tp, 0xa454); | |
7645 | data &= ~BIT(0); | |
7646 | ocp_reg_write(tp, 0xa454, data); | |
7647 | ||
7648 | /* CS DSP solution */ | |
7649 | data = ocp_reg_read(tp, OCP_10GBT_CTRL); | |
7650 | data |= RTL_ADV2_5G_F_R; | |
7651 | ocp_reg_write(tp, OCP_10GBT_CTRL, data); | |
7652 | data = ocp_reg_read(tp, 0xad4e); | |
7653 | data &= ~BIT(4); | |
7654 | ocp_reg_write(tp, 0xad4e, data); | |
7655 | data = ocp_reg_read(tp, 0xa86a); | |
7656 | data &= ~BIT(0); | |
7657 | ocp_reg_write(tp, 0xa86a, data); | |
7658 | ||
7659 | /* MDI SWAP */ | |
7660 | if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && | |
7661 | (ocp_reg_read(tp, 0xd068) & BIT(1))) { | |
7662 | u16 swap_a, swap_b; | |
7663 | ||
7664 | data = ocp_reg_read(tp, 0xd068); | |
7665 | data &= ~0x1f; | |
7666 | data |= 0x1; /* p0 */ | |
7667 | ocp_reg_write(tp, 0xd068, data); | |
7668 | swap_a = ocp_reg_read(tp, 0xd06a); | |
7669 | data &= ~0x18; | |
7670 | data |= 0x18; /* p3 */ | |
7671 | ocp_reg_write(tp, 0xd068, data); | |
7672 | swap_b = ocp_reg_read(tp, 0xd06a); | |
7673 | data &= ~0x18; /* p0 */ | |
7674 | ocp_reg_write(tp, 0xd068, data); | |
7675 | ocp_reg_write(tp, 0xd06a, | |
7676 | (swap_a & ~0x7ff) | (swap_b & 0x7ff)); | |
7677 | data |= 0x18; /* p3 */ | |
7678 | ocp_reg_write(tp, 0xd068, data); | |
7679 | ocp_reg_write(tp, 0xd06a, | |
7680 | (swap_b & ~0x7ff) | (swap_a & 0x7ff)); | |
7681 | data &= ~0x18; | |
7682 | data |= 0x08; /* p1 */ | |
7683 | ocp_reg_write(tp, 0xd068, data); | |
7684 | swap_a = ocp_reg_read(tp, 0xd06a); | |
7685 | data &= ~0x18; | |
7686 | data |= 0x10; /* p2 */ | |
7687 | ocp_reg_write(tp, 0xd068, data); | |
7688 | swap_b = ocp_reg_read(tp, 0xd06a); | |
7689 | data &= ~0x18; | |
7690 | data |= 0x08; /* p1 */ | |
7691 | ocp_reg_write(tp, 0xd068, data); | |
7692 | ocp_reg_write(tp, 0xd06a, | |
7693 | (swap_a & ~0x7ff) | (swap_b & 0x7ff)); | |
7694 | data &= ~0x18; | |
7695 | data |= 0x10; /* p2 */ | |
7696 | ocp_reg_write(tp, 0xd068, data); | |
7697 | ocp_reg_write(tp, 0xd06a, | |
7698 | (swap_b & ~0x7ff) | (swap_a & 0x7ff)); | |
7699 | swap_a = ocp_reg_read(tp, 0xbd5a); | |
7700 | swap_b = ocp_reg_read(tp, 0xbd5c); | |
7701 | ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | | |
7702 | ((swap_b & 0x1f) << 8) | | |
7703 | ((swap_b >> 8) & 0x1f)); | |
7704 | ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | | |
7705 | ((swap_a & 0x1f) << 8) | | |
7706 | ((swap_a >> 8) & 0x1f)); | |
7707 | swap_a = ocp_reg_read(tp, 0xbc18); | |
7708 | swap_b = ocp_reg_read(tp, 0xbc1a); | |
7709 | ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | | |
7710 | ((swap_b & 0x1f) << 8) | | |
7711 | ((swap_b >> 8) & 0x1f)); | |
7712 | ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | | |
7713 | ((swap_a & 0x1f) << 8) | | |
7714 | ((swap_a >> 8) & 0x1f)); | |
7715 | } | |
61b0ad6f HW |
7716 | |
7717 | /* Notify the MAC when the speed is changed to force mode. */ | |
7718 | data = ocp_reg_read(tp, OCP_INTR_EN); | |
7719 | data |= INTR_SPEED_FORCE; | |
7720 | ocp_reg_write(tp, OCP_INTR_EN, data); | |
195aae32 HW |
7721 | break; |
7722 | default: | |
7723 | break; | |
7724 | } | |
7725 | ||
7726 | rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
7727 | ||
7728 | data = ocp_reg_read(tp, 0xa428); | |
7729 | data &= ~BIT(9); | |
7730 | ocp_reg_write(tp, 0xa428, data); | |
7731 | data = ocp_reg_read(tp, 0xa5ea); | |
7732 | data &= ~BIT(0); | |
7733 | ocp_reg_write(tp, 0xa5ea, data); | |
7734 | tp->ups_info.lite_mode = 0; | |
7735 | ||
7736 | if (tp->eee_en) | |
7737 | rtl_eee_enable(tp, true); | |
7738 | ||
7739 | r8153_aldps_en(tp, true); | |
7740 | r8152b_enable_fc(tp); | |
7741 | r8153_u2p3en(tp, true); | |
7742 | ||
7743 | set_bit(PHY_RESET, &tp->flags); | |
7744 | } | |
7745 | ||
7746 | static void r8156b_hw_phy_cfg(struct r8152 *tp) | |
7747 | { | |
7748 | u32 ocp_data; | |
7749 | u16 data; | |
7750 | ||
7751 | switch (tp->version) { | |
7752 | case RTL_VER_12: | |
7753 | ocp_reg_write(tp, 0xbf86, 0x9000); | |
7754 | data = ocp_reg_read(tp, 0xc402); | |
7755 | data |= BIT(10); | |
7756 | ocp_reg_write(tp, 0xc402, data); | |
7757 | data &= ~BIT(10); | |
7758 | ocp_reg_write(tp, 0xc402, data); | |
7759 | ocp_reg_write(tp, 0xbd86, 0x1010); | |
7760 | ocp_reg_write(tp, 0xbd88, 0x1010); | |
7761 | data = ocp_reg_read(tp, 0xbd4e); | |
7762 | data &= ~(BIT(10) | BIT(11)); | |
7763 | data |= BIT(11); | |
7764 | ocp_reg_write(tp, 0xbd4e, data); | |
7765 | data = ocp_reg_read(tp, 0xbf46); | |
7766 | data &= ~0xf00; | |
7767 | data |= 0x700; | |
7768 | ocp_reg_write(tp, 0xbf46, data); | |
7769 | break; | |
7770 | case RTL_VER_13: | |
7771 | case RTL_VER_15: | |
7772 | r8156b_wait_loading_flash(tp); | |
7773 | break; | |
7774 | default: | |
7775 | break; | |
7776 | } | |
7777 | ||
7778 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
7779 | if (ocp_data & PCUT_STATUS) { | |
7780 | ocp_data &= ~PCUT_STATUS; | |
7781 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
7782 | } | |
7783 | ||
7784 | data = r8153_phy_status(tp, 0); | |
7785 | switch (data) { | |
7786 | case PHY_STAT_EXT_INIT: | |
7787 | rtl8152_apply_firmware(tp, true); | |
7788 | ||
7789 | data = ocp_reg_read(tp, 0xa466); | |
7790 | data &= ~BIT(0); | |
7791 | ocp_reg_write(tp, 0xa466, data); | |
7792 | ||
7793 | data = ocp_reg_read(tp, 0xa468); | |
7794 | data &= ~(BIT(3) | BIT(1)); | |
7795 | ocp_reg_write(tp, 0xa468, data); | |
7796 | break; | |
7797 | case PHY_STAT_LAN_ON: | |
7798 | case PHY_STAT_PWRDN: | |
7799 | default: | |
7800 | rtl8152_apply_firmware(tp, false); | |
7801 | break; | |
7802 | } | |
7803 | ||
7804 | data = r8152_mdio_read(tp, MII_BMCR); | |
7805 | if (data & BMCR_PDOWN) { | |
7806 | data &= ~BMCR_PDOWN; | |
7807 | r8152_mdio_write(tp, MII_BMCR, data); | |
7808 | } | |
7809 | ||
7810 | /* disable ALDPS before updating the PHY parameters */ | |
7811 | r8153_aldps_en(tp, false); | |
7812 | ||
7813 | /* disable EEE before updating the PHY parameters */ | |
7814 | rtl_eee_enable(tp, false); | |
7815 | ||
7816 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
7817 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); | |
7818 | ||
7819 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
7820 | ocp_data |= PFM_PWM_SWITCH; | |
7821 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
7822 | ||
7823 | switch (tp->version) { | |
7824 | case RTL_VER_12: | |
7825 | data = ocp_reg_read(tp, 0xbc08); | |
7826 | data |= BIT(3) | BIT(2); | |
7827 | ocp_reg_write(tp, 0xbc08, data); | |
7828 | ||
7829 | data = sram_read(tp, 0x8fff); | |
7830 | data &= ~0xff00; | |
7831 | data |= 0x0400; | |
7832 | sram_write(tp, 0x8fff, data); | |
7833 | ||
7834 | data = ocp_reg_read(tp, 0xacda); | |
7835 | data |= 0xff00; | |
7836 | ocp_reg_write(tp, 0xacda, data); | |
7837 | data = ocp_reg_read(tp, 0xacde); | |
7838 | data |= 0xf000; | |
7839 | ocp_reg_write(tp, 0xacde, data); | |
7840 | ocp_reg_write(tp, 0xac8c, 0x0ffc); | |
7841 | ocp_reg_write(tp, 0xac46, 0xb7b4); | |
7842 | ocp_reg_write(tp, 0xac50, 0x0fbc); | |
7843 | ocp_reg_write(tp, 0xac3c, 0x9240); | |
7844 | ocp_reg_write(tp, 0xac4e, 0x0db4); | |
7845 | ocp_reg_write(tp, 0xacc6, 0x0707); | |
7846 | ocp_reg_write(tp, 0xacc8, 0xa0d3); | |
7847 | ocp_reg_write(tp, 0xad08, 0x0007); | |
7848 | ||
7849 | ocp_reg_write(tp, 0xb87c, 0x8560); | |
7850 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7851 | ocp_reg_write(tp, 0xb87c, 0x8562); | |
7852 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7853 | ocp_reg_write(tp, 0xb87c, 0x8564); | |
7854 | ocp_reg_write(tp, 0xb87e, 0x19cc); | |
7855 | ocp_reg_write(tp, 0xb87c, 0x8566); | |
7856 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7857 | ocp_reg_write(tp, 0xb87c, 0x8568); | |
7858 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7859 | ocp_reg_write(tp, 0xb87c, 0x856a); | |
7860 | ocp_reg_write(tp, 0xb87e, 0x147d); | |
7861 | ocp_reg_write(tp, 0xb87c, 0x8ffe); | |
7862 | ocp_reg_write(tp, 0xb87e, 0x0907); | |
7863 | ocp_reg_write(tp, 0xb87c, 0x80d6); | |
7864 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7865 | ocp_reg_write(tp, 0xb87c, 0x80f2); | |
7866 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7867 | ocp_reg_write(tp, 0xb87c, 0x80f4); | |
7868 | ocp_reg_write(tp, 0xb87e, 0x6077); | |
7869 | ocp_reg_write(tp, 0xb506, 0x01e7); | |
7870 | ||
7871 | ocp_reg_write(tp, 0xb87c, 0x8013); | |
7872 | ocp_reg_write(tp, 0xb87e, 0x0700); | |
7873 | ocp_reg_write(tp, 0xb87c, 0x8fb9); | |
7874 | ocp_reg_write(tp, 0xb87e, 0x2801); | |
7875 | ocp_reg_write(tp, 0xb87c, 0x8fba); | |
7876 | ocp_reg_write(tp, 0xb87e, 0x0100); | |
7877 | ocp_reg_write(tp, 0xb87c, 0x8fbc); | |
7878 | ocp_reg_write(tp, 0xb87e, 0x1900); | |
7879 | ocp_reg_write(tp, 0xb87c, 0x8fbe); | |
7880 | ocp_reg_write(tp, 0xb87e, 0xe100); | |
7881 | ocp_reg_write(tp, 0xb87c, 0x8fc0); | |
7882 | ocp_reg_write(tp, 0xb87e, 0x0800); | |
7883 | ocp_reg_write(tp, 0xb87c, 0x8fc2); | |
7884 | ocp_reg_write(tp, 0xb87e, 0xe500); | |
7885 | ocp_reg_write(tp, 0xb87c, 0x8fc4); | |
7886 | ocp_reg_write(tp, 0xb87e, 0x0f00); | |
7887 | ocp_reg_write(tp, 0xb87c, 0x8fc6); | |
7888 | ocp_reg_write(tp, 0xb87e, 0xf100); | |
7889 | ocp_reg_write(tp, 0xb87c, 0x8fc8); | |
7890 | ocp_reg_write(tp, 0xb87e, 0x0400); | |
7891 | ocp_reg_write(tp, 0xb87c, 0x8fca); | |
7892 | ocp_reg_write(tp, 0xb87e, 0xf300); | |
7893 | ocp_reg_write(tp, 0xb87c, 0x8fcc); | |
7894 | ocp_reg_write(tp, 0xb87e, 0xfd00); | |
7895 | ocp_reg_write(tp, 0xb87c, 0x8fce); | |
7896 | ocp_reg_write(tp, 0xb87e, 0xff00); | |
7897 | ocp_reg_write(tp, 0xb87c, 0x8fd0); | |
7898 | ocp_reg_write(tp, 0xb87e, 0xfb00); | |
7899 | ocp_reg_write(tp, 0xb87c, 0x8fd2); | |
7900 | ocp_reg_write(tp, 0xb87e, 0x0100); | |
7901 | ocp_reg_write(tp, 0xb87c, 0x8fd4); | |
7902 | ocp_reg_write(tp, 0xb87e, 0xf400); | |
7903 | ocp_reg_write(tp, 0xb87c, 0x8fd6); | |
7904 | ocp_reg_write(tp, 0xb87e, 0xff00); | |
7905 | ocp_reg_write(tp, 0xb87c, 0x8fd8); | |
7906 | ocp_reg_write(tp, 0xb87e, 0xf600); | |
7907 | ||
7908 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); | |
7909 | ocp_data |= EN_XG_LIP | EN_G_LIP; | |
7910 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); | |
7911 | ocp_reg_write(tp, 0xb87c, 0x813d); | |
7912 | ocp_reg_write(tp, 0xb87e, 0x390e); | |
7913 | ocp_reg_write(tp, 0xb87c, 0x814f); | |
7914 | ocp_reg_write(tp, 0xb87e, 0x790e); | |
7915 | ocp_reg_write(tp, 0xb87c, 0x80b0); | |
7916 | ocp_reg_write(tp, 0xb87e, 0x0f31); | |
7917 | data = ocp_reg_read(tp, 0xbf4c); | |
7918 | data |= BIT(1); | |
7919 | ocp_reg_write(tp, 0xbf4c, data); | |
7920 | data = ocp_reg_read(tp, 0xbcca); | |
7921 | data |= BIT(9) | BIT(8); | |
7922 | ocp_reg_write(tp, 0xbcca, data); | |
7923 | ocp_reg_write(tp, 0xb87c, 0x8141); | |
7924 | ocp_reg_write(tp, 0xb87e, 0x320e); | |
7925 | ocp_reg_write(tp, 0xb87c, 0x8153); | |
7926 | ocp_reg_write(tp, 0xb87e, 0x720e); | |
7927 | ocp_reg_write(tp, 0xb87c, 0x8529); | |
7928 | ocp_reg_write(tp, 0xb87e, 0x050e); | |
7929 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
7930 | data &= ~CTAP_SHORT_EN; | |
7931 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
7932 | ||
7933 | sram_write(tp, 0x816c, 0xc4a0); | |
7934 | sram_write(tp, 0x8170, 0xc4a0); | |
7935 | sram_write(tp, 0x8174, 0x04a0); | |
7936 | sram_write(tp, 0x8178, 0x04a0); | |
7937 | sram_write(tp, 0x817c, 0x0719); | |
7938 | sram_write(tp, 0x8ff4, 0x0400); | |
7939 | sram_write(tp, 0x8ff1, 0x0404); | |
7940 | ||
7941 | ocp_reg_write(tp, 0xbf4a, 0x001b); | |
7942 | ocp_reg_write(tp, 0xb87c, 0x8033); | |
7943 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7944 | ocp_reg_write(tp, 0xb87c, 0x8037); | |
7945 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7946 | ocp_reg_write(tp, 0xb87c, 0x803b); | |
7947 | ocp_reg_write(tp, 0xb87e, 0xfc32); | |
7948 | ocp_reg_write(tp, 0xb87c, 0x803f); | |
7949 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7950 | ocp_reg_write(tp, 0xb87c, 0x8043); | |
7951 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7952 | ocp_reg_write(tp, 0xb87c, 0x8047); | |
7953 | ocp_reg_write(tp, 0xb87e, 0x7c13); | |
7954 | ||
7955 | ocp_reg_write(tp, 0xb87c, 0x8145); | |
7956 | ocp_reg_write(tp, 0xb87e, 0x370e); | |
7957 | ocp_reg_write(tp, 0xb87c, 0x8157); | |
7958 | ocp_reg_write(tp, 0xb87e, 0x770e); | |
7959 | ocp_reg_write(tp, 0xb87c, 0x8169); | |
7960 | ocp_reg_write(tp, 0xb87e, 0x0d0a); | |
7961 | ocp_reg_write(tp, 0xb87c, 0x817b); | |
7962 | ocp_reg_write(tp, 0xb87e, 0x1d0a); | |
7963 | ||
7964 | data = sram_read(tp, 0x8217); | |
7965 | data &= ~0xff00; | |
7966 | data |= 0x5000; | |
7967 | sram_write(tp, 0x8217, data); | |
7968 | data = sram_read(tp, 0x821a); | |
7969 | data &= ~0xff00; | |
7970 | data |= 0x5000; | |
7971 | sram_write(tp, 0x821a, data); | |
7972 | sram_write(tp, 0x80da, 0x0403); | |
7973 | data = sram_read(tp, 0x80dc); | |
7974 | data &= ~0xff00; | |
7975 | data |= 0x1000; | |
7976 | sram_write(tp, 0x80dc, data); | |
7977 | sram_write(tp, 0x80b3, 0x0384); | |
7978 | sram_write(tp, 0x80b7, 0x2007); | |
7979 | data = sram_read(tp, 0x80ba); | |
7980 | data &= ~0xff00; | |
7981 | data |= 0x6c00; | |
7982 | sram_write(tp, 0x80ba, data); | |
7983 | sram_write(tp, 0x80b5, 0xf009); | |
7984 | data = sram_read(tp, 0x80bd); | |
7985 | data &= ~0xff00; | |
7986 | data |= 0x9f00; | |
7987 | sram_write(tp, 0x80bd, data); | |
7988 | sram_write(tp, 0x80c7, 0xf083); | |
7989 | sram_write(tp, 0x80dd, 0x03f0); | |
7990 | data = sram_read(tp, 0x80df); | |
7991 | data &= ~0xff00; | |
7992 | data |= 0x1000; | |
7993 | sram_write(tp, 0x80df, data); | |
7994 | sram_write(tp, 0x80cb, 0x2007); | |
7995 | data = sram_read(tp, 0x80ce); | |
7996 | data &= ~0xff00; | |
7997 | data |= 0x6c00; | |
7998 | sram_write(tp, 0x80ce, data); | |
7999 | sram_write(tp, 0x80c9, 0x8009); | |
8000 | data = sram_read(tp, 0x80d1); | |
8001 | data &= ~0xff00; | |
8002 | data |= 0x8000; | |
8003 | sram_write(tp, 0x80d1, data); | |
8004 | sram_write(tp, 0x80a3, 0x200a); | |
8005 | sram_write(tp, 0x80a5, 0xf0ad); | |
8006 | sram_write(tp, 0x809f, 0x6073); | |
8007 | sram_write(tp, 0x80a1, 0x000b); | |
8008 | data = sram_read(tp, 0x80a9); | |
8009 | data &= ~0xff00; | |
8010 | data |= 0xc000; | |
8011 | sram_write(tp, 0x80a9, data); | |
8012 | ||
8013 | if (rtl_phy_patch_request(tp, true, true)) | |
8014 | return; | |
8015 | ||
8016 | data = ocp_reg_read(tp, 0xb896); | |
8017 | data &= ~BIT(0); | |
8018 | ocp_reg_write(tp, 0xb896, data); | |
8019 | data = ocp_reg_read(tp, 0xb892); | |
8020 | data &= ~0xff00; | |
8021 | ocp_reg_write(tp, 0xb892, data); | |
8022 | ocp_reg_write(tp, 0xb88e, 0xc23e); | |
8023 | ocp_reg_write(tp, 0xb890, 0x0000); | |
8024 | ocp_reg_write(tp, 0xb88e, 0xc240); | |
8025 | ocp_reg_write(tp, 0xb890, 0x0103); | |
8026 | ocp_reg_write(tp, 0xb88e, 0xc242); | |
8027 | ocp_reg_write(tp, 0xb890, 0x0507); | |
8028 | ocp_reg_write(tp, 0xb88e, 0xc244); | |
8029 | ocp_reg_write(tp, 0xb890, 0x090b); | |
8030 | ocp_reg_write(tp, 0xb88e, 0xc246); | |
8031 | ocp_reg_write(tp, 0xb890, 0x0c0e); | |
8032 | ocp_reg_write(tp, 0xb88e, 0xc248); | |
8033 | ocp_reg_write(tp, 0xb890, 0x1012); | |
8034 | ocp_reg_write(tp, 0xb88e, 0xc24a); | |
8035 | ocp_reg_write(tp, 0xb890, 0x1416); | |
8036 | data = ocp_reg_read(tp, 0xb896); | |
8037 | data |= BIT(0); | |
8038 | ocp_reg_write(tp, 0xb896, data); | |
8039 | ||
8040 | rtl_phy_patch_request(tp, false, true); | |
8041 | ||
8042 | data = ocp_reg_read(tp, 0xa86a); | |
8043 | data |= BIT(0); | |
8044 | ocp_reg_write(tp, 0xa86a, data); | |
8045 | data = ocp_reg_read(tp, 0xa6f0); | |
8046 | data |= BIT(0); | |
8047 | ocp_reg_write(tp, 0xa6f0, data); | |
8048 | ||
8049 | ocp_reg_write(tp, 0xbfa0, 0xd70d); | |
8050 | ocp_reg_write(tp, 0xbfa2, 0x4100); | |
8051 | ocp_reg_write(tp, 0xbfa4, 0xe868); | |
8052 | ocp_reg_write(tp, 0xbfa6, 0xdc59); | |
8053 | ocp_reg_write(tp, 0xb54c, 0x3c18); | |
8054 | data = ocp_reg_read(tp, 0xbfa4); | |
8055 | data &= ~BIT(5); | |
8056 | ocp_reg_write(tp, 0xbfa4, data); | |
8057 | data = sram_read(tp, 0x817d); | |
8058 | data |= BIT(12); | |
8059 | sram_write(tp, 0x817d, data); | |
8060 | break; | |
8061 | case RTL_VER_13: | |
8062 | /* 2.5G INRX */ | |
8063 | data = ocp_reg_read(tp, 0xac46); | |
8064 | data &= ~0x00f0; | |
8065 | data |= 0x0090; | |
8066 | ocp_reg_write(tp, 0xac46, data); | |
8067 | data = ocp_reg_read(tp, 0xad30); | |
8068 | data &= ~0x0003; | |
8069 | data |= 0x0001; | |
8070 | ocp_reg_write(tp, 0xad30, data); | |
8071 | fallthrough; | |
8072 | case RTL_VER_15: | |
8073 | /* EEE parameter */ | |
8074 | ocp_reg_write(tp, 0xb87c, 0x80f5); | |
8075 | ocp_reg_write(tp, 0xb87e, 0x760e); | |
8076 | ocp_reg_write(tp, 0xb87c, 0x8107); | |
8077 | ocp_reg_write(tp, 0xb87e, 0x360e); | |
8078 | ocp_reg_write(tp, 0xb87c, 0x8551); | |
8079 | data = ocp_reg_read(tp, 0xb87e); | |
8080 | data &= ~0xff00; | |
8081 | data |= 0x0800; | |
8082 | ocp_reg_write(tp, 0xb87e, data); | |
8083 | ||
8084 | /* ADC_PGA parameter */ | |
8085 | data = ocp_reg_read(tp, 0xbf00); | |
8086 | data &= ~0xe000; | |
8087 | data |= 0xa000; | |
8088 | ocp_reg_write(tp, 0xbf00, data); | |
8089 | data = ocp_reg_read(tp, 0xbf46); | |
8090 | data &= ~0x0f00; | |
8091 | data |= 0x0300; | |
8092 | ocp_reg_write(tp, 0xbf46, data); | |
8093 | ||
8094 | /* Green Table-PGA, 1G full viterbi */ | |
8095 | sram_write(tp, 0x8044, 0x2417); | |
8096 | sram_write(tp, 0x804a, 0x2417); | |
8097 | sram_write(tp, 0x8050, 0x2417); | |
8098 | sram_write(tp, 0x8056, 0x2417); | |
8099 | sram_write(tp, 0x805c, 0x2417); | |
8100 | sram_write(tp, 0x8062, 0x2417); | |
8101 | sram_write(tp, 0x8068, 0x2417); | |
8102 | sram_write(tp, 0x806e, 0x2417); | |
8103 | sram_write(tp, 0x8074, 0x2417); | |
8104 | sram_write(tp, 0x807a, 0x2417); | |
8105 | ||
8106 | /* XG PLL */ | |
8107 | data = ocp_reg_read(tp, 0xbf84); | |
8108 | data &= ~0xe000; | |
8109 | data |= 0xa000; | |
8110 | ocp_reg_write(tp, 0xbf84, data); | |
8111 | break; | |
8112 | default: | |
8113 | break; | |
8114 | } | |
8115 | ||
61b0ad6f HW |
8116 | /* Notify the MAC when the speed is changed to force mode. */ |
8117 | data = ocp_reg_read(tp, OCP_INTR_EN); | |
8118 | data |= INTR_SPEED_FORCE; | |
8119 | ocp_reg_write(tp, OCP_INTR_EN, data); | |
8120 | ||
195aae32 HW |
8121 | if (rtl_phy_patch_request(tp, true, true)) |
8122 | return; | |
8123 | ||
8124 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); | |
8125 | ocp_data |= EEE_SPDWN_EN; | |
8126 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); | |
8127 | ||
8128 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
8129 | data &= ~(EN_EEE_100 | EN_EEE_1000); | |
8130 | data |= EN_10M_CLKDIV; | |
8131 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
8132 | tp->ups_info._10m_ckdiv = true; | |
8133 | tp->ups_info.eee_plloff_100 = false; | |
8134 | tp->ups_info.eee_plloff_giga = false; | |
8135 | ||
8136 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
8137 | data &= ~EEE_CLKDIV_EN; | |
8138 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
8139 | tp->ups_info.eee_ckdiv = false; | |
8140 | ||
8141 | rtl_phy_patch_request(tp, false, true); | |
8142 | ||
8143 | rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
8144 | ||
8145 | data = ocp_reg_read(tp, 0xa428); | |
8146 | data &= ~BIT(9); | |
8147 | ocp_reg_write(tp, 0xa428, data); | |
8148 | data = ocp_reg_read(tp, 0xa5ea); | |
8149 | data &= ~BIT(0); | |
8150 | ocp_reg_write(tp, 0xa5ea, data); | |
8151 | tp->ups_info.lite_mode = 0; | |
8152 | ||
8153 | if (tp->eee_en) | |
8154 | rtl_eee_enable(tp, true); | |
8155 | ||
8156 | r8153_aldps_en(tp, true); | |
8157 | r8152b_enable_fc(tp); | |
8158 | r8153_u2p3en(tp, true); | |
8159 | ||
8160 | set_bit(PHY_RESET, &tp->flags); | |
8161 | } | |
8162 | ||
8163 | static void r8156_init(struct r8152 *tp) | |
43779f8d | 8164 | { |
8165 | u32 ocp_data; | |
2dd436da | 8166 | u16 data; |
43779f8d | 8167 | int i; |
8168 | ||
715f67f3 | 8169 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 8170 | return; |
8171 | ||
195aae32 HW |
8172 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); |
8173 | ocp_data &= ~EN_ALL_SPEED; | |
8174 | ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); | |
8175 | ||
8176 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); | |
8177 | ||
8178 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); | |
8179 | ocp_data |= BYPASS_MAC_RESET; | |
8180 | ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); | |
8181 | ||
8182 | r8153b_u1u2en(tp, false); | |
43779f8d | 8183 | |
8184 | for (i = 0; i < 500; i++) { | |
8185 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
8186 | AUTOLOAD_DONE) | |
8187 | break; | |
d64c7a08 | 8188 | |
43779f8d | 8189 | msleep(20); |
715f67f3 | 8190 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 | 8191 | return; |
43779f8d | 8192 | } |
8193 | ||
c564b871 | 8194 | data = r8153_phy_status(tp, 0); |
195aae32 HW |
8195 | if (data == PHY_STAT_EXT_INIT) { |
8196 | data = ocp_reg_read(tp, 0xa468); | |
8197 | data &= ~(BIT(3) | BIT(1)); | |
8198 | ocp_reg_write(tp, 0xa468, data); | |
8199 | } | |
2dd436da | 8200 | |
8201 | data = r8152_mdio_read(tp, MII_BMCR); | |
8202 | if (data & BMCR_PDOWN) { | |
8203 | data &= ~BMCR_PDOWN; | |
8204 | r8152_mdio_write(tp, MII_BMCR, data); | |
8205 | } | |
8206 | ||
c564b871 | 8207 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
195aae32 | 8208 | WARN_ON_ONCE(data != PHY_STAT_LAN_ON); |
2dd436da | 8209 | |
b9702723 | 8210 | r8153_u2p3en(tp, false); |
43779f8d | 8211 | |
195aae32 HW |
8212 | /* MSC timer = 0xfff * 8ms = 32760 ms */ |
8213 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
65bab84c | 8214 | |
195aae32 HW |
8215 | /* U1/U2/L1 idle timer. 500 us */ |
8216 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
a3914272 | 8217 | |
195aae32 HW |
8218 | r8153b_power_cut_en(tp, false); |
8219 | r8156_ups_en(tp, false); | |
8220 | r8153_queue_wake(tp, false); | |
8221 | rtl_runtime_suspend_enable(tp, false); | |
a3914272 | 8222 | |
195aae32 HW |
8223 | if (tp->udev->speed >= USB_SPEED_SUPER) |
8224 | r8153b_u1u2en(tp, true); | |
65bab84c | 8225 | |
195aae32 | 8226 | usb_enable_lpm(tp->udev); |
65bab84c | 8227 | |
195aae32 | 8228 | r8156_mac_clk_spd(tp, true); |
43779f8d | 8229 | |
195aae32 HW |
8230 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
8231 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
8232 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
43779f8d | 8233 | |
195aae32 HW |
8234 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
8235 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
8236 | ocp_data |= CUR_LINK_OK; | |
34203e25 | 8237 | else |
195aae32 HW |
8238 | ocp_data &= ~CUR_LINK_OK; |
8239 | ocp_data |= POLL_LINK_CHG; | |
8240 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
19813162 | 8241 | |
195aae32 | 8242 | set_bit(GREEN_ETHERNET, &tp->flags); |
19813162 | 8243 | |
e31f6367 | 8244 | /* rx aggregation */ |
8245 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
8246 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
8247 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
43779f8d | 8248 | |
195aae32 HW |
8249 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); |
8250 | ocp_data |= ACT_ODMA; | |
8251 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); | |
8252 | ||
45bf944e | 8253 | r8156_mdio_force_mode(tp); |
4f1d4d54 | 8254 | rtl_tally_reset(tp); |
49d10347 | 8255 | |
195aae32 | 8256 | tp->coalesce = 15000; /* 15 us */ |
43779f8d | 8257 | } |
8258 | ||
195aae32 | 8259 | static void r8156b_init(struct r8152 *tp) |
65b82d69 | 8260 | { |
8261 | u32 ocp_data; | |
8262 | u16 data; | |
8263 | int i; | |
8264 | ||
715f67f3 | 8265 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
65b82d69 | 8266 | return; |
8267 | ||
195aae32 HW |
8268 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); |
8269 | ocp_data &= ~EN_ALL_SPEED; | |
8270 | ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); | |
8271 | ||
8272 | ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); | |
8273 | ||
8274 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); | |
8275 | ocp_data |= BYPASS_MAC_RESET; | |
8276 | ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); | |
8277 | ||
8278 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
8279 | ocp_data |= RX_DETECT8; | |
8280 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
8281 | ||
65b82d69 | 8282 | r8153b_u1u2en(tp, false); |
8283 | ||
195aae32 HW |
8284 | switch (tp->version) { |
8285 | case RTL_VER_13: | |
8286 | case RTL_VER_15: | |
8287 | r8156b_wait_loading_flash(tp); | |
8288 | break; | |
8289 | default: | |
8290 | break; | |
8291 | } | |
8292 | ||
65b82d69 | 8293 | for (i = 0; i < 500; i++) { |
8294 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
8295 | AUTOLOAD_DONE) | |
8296 | break; | |
d64c7a08 | 8297 | |
65b82d69 | 8298 | msleep(20); |
715f67f3 | 8299 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
195aae32 | 8300 | return; |
65b82d69 | 8301 | } |
8302 | ||
8303 | data = r8153_phy_status(tp, 0); | |
195aae32 HW |
8304 | if (data == PHY_STAT_EXT_INIT) { |
8305 | data = ocp_reg_read(tp, 0xa468); | |
8306 | data &= ~(BIT(3) | BIT(1)); | |
8307 | ocp_reg_write(tp, 0xa468, data); | |
8308 | ||
8309 | data = ocp_reg_read(tp, 0xa466); | |
8310 | data &= ~BIT(0); | |
8311 | ocp_reg_write(tp, 0xa466, data); | |
8312 | } | |
65b82d69 | 8313 | |
8314 | data = r8152_mdio_read(tp, MII_BMCR); | |
8315 | if (data & BMCR_PDOWN) { | |
8316 | data &= ~BMCR_PDOWN; | |
8317 | r8152_mdio_write(tp, MII_BMCR, data); | |
8318 | } | |
8319 | ||
8320 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
8321 | ||
8322 | r8153_u2p3en(tp, false); | |
8323 | ||
8324 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
8325 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
8326 | ||
195aae32 HW |
8327 | /* U1/U2/L1 idle timer. 500 us */ |
8328 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
8329 | ||
65b82d69 | 8330 | r8153b_power_cut_en(tp, false); |
195aae32 | 8331 | r8156_ups_en(tp, false); |
13e04fbf | 8332 | r8153_queue_wake(tp, false); |
65b82d69 | 8333 | rtl_runtime_suspend_enable(tp, false); |
a3914272 | 8334 | |
7a0ae61a | 8335 | if (tp->udev->speed >= USB_SPEED_SUPER) |
a0246daf | 8336 | r8153b_u1u2en(tp, true); |
7a0ae61a | 8337 | |
65b82d69 | 8338 | usb_enable_lpm(tp->udev); |
8339 | ||
195aae32 HW |
8340 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); |
8341 | ocp_data &= ~SLOT_EN; | |
8342 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
8343 | ||
8344 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
8345 | ocp_data |= FLOW_CTRL_EN; | |
8346 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
8347 | ||
8348 | /* enable fc timer and set timer to 600 ms. */ | |
8349 | ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, | |
8350 | CTRL_TIMER_EN | (600 / 8)); | |
8351 | ||
8352 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); | |
8353 | if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) | |
8354 | ocp_data |= FLOW_CTRL_PATCH_2; | |
8355 | ocp_data &= ~AUTO_SPEEDUP; | |
8356 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); | |
8357 | ||
8358 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); | |
8359 | ocp_data |= FC_PATCH_TASK; | |
8360 | ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); | |
8361 | ||
8362 | r8156_mac_clk_spd(tp, true); | |
65b82d69 | 8363 | |
08997b5e HW |
8364 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); |
8365 | ocp_data &= ~PLA_MCU_SPDWN_EN; | |
8366 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); | |
8367 | ||
195aae32 HW |
8368 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); |
8369 | if (rtl8152_get_speed(tp) & LINK_STATUS) | |
8370 | ocp_data |= CUR_LINK_OK; | |
8371 | else | |
8372 | ocp_data &= ~CUR_LINK_OK; | |
8373 | ocp_data |= POLL_LINK_CHG; | |
8374 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); | |
d7f1b596 | 8375 | |
65b82d69 | 8376 | set_bit(GREEN_ETHERNET, &tp->flags); |
8377 | ||
8378 | /* rx aggregation */ | |
8379 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
8380 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
8381 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
8382 | ||
45bf944e | 8383 | r8156_mdio_force_mode(tp); |
65b82d69 | 8384 | rtl_tally_reset(tp); |
8385 | ||
8386 | tp->coalesce = 15000; /* 15 us */ | |
8387 | } | |
8388 | ||
1a44fb38 HW |
8389 | static bool rtl_check_vendor_ok(struct usb_interface *intf) |
8390 | { | |
8391 | struct usb_host_interface *alt = intf->cur_altsetting; | |
8392 | struct usb_endpoint_descriptor *in, *out, *intr; | |
8393 | ||
8394 | if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { | |
8395 | dev_err(&intf->dev, "Expected endpoints are not found\n"); | |
8396 | return false; | |
8397 | } | |
8398 | ||
8399 | /* Check Rx endpoint address */ | |
8400 | if (usb_endpoint_num(in) != 1) { | |
8401 | dev_err(&intf->dev, "Invalid Rx endpoint address\n"); | |
8402 | return false; | |
8403 | } | |
8404 | ||
8405 | /* Check Tx endpoint address */ | |
8406 | if (usb_endpoint_num(out) != 2) { | |
8407 | dev_err(&intf->dev, "Invalid Tx endpoint address\n"); | |
8408 | return false; | |
8409 | } | |
8410 | ||
8411 | /* Check interrupt endpoint address */ | |
8412 | if (usb_endpoint_num(intr) != 3) { | |
8413 | dev_err(&intf->dev, "Invalid interrupt endpoint address\n"); | |
8414 | return false; | |
8415 | } | |
8416 | ||
8417 | return true; | |
8418 | } | |
8419 | ||
e501139a | 8420 | static int rtl8152_pre_reset(struct usb_interface *intf) |
8421 | { | |
8422 | struct r8152 *tp = usb_get_intfdata(intf); | |
8423 | struct net_device *netdev; | |
8424 | ||
e62adaee DA |
8425 | rtnl_lock(); |
8426 | ||
d9962b0d | 8427 | if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) |
e501139a | 8428 | return 0; |
8429 | ||
8430 | netdev = tp->netdev; | |
8431 | if (!netif_running(netdev)) | |
8432 | return 0; | |
8433 | ||
de9bf29d | 8434 | netif_stop_queue(netdev); |
d2187f8e | 8435 | tasklet_disable(&tp->tx_tl); |
e501139a | 8436 | clear_bit(WORK_ENABLE, &tp->flags); |
8437 | usb_kill_urb(tp->intr_urb); | |
8438 | cancel_delayed_work_sync(&tp->schedule); | |
5b1d9c17 | 8439 | napi_disable(&tp->napi); |
e501139a | 8440 | if (netif_carrier_ok(netdev)) { |
e501139a | 8441 | mutex_lock(&tp->control); |
d9962b0d | 8442 | set_bit(IN_PRE_RESET, &tp->flags); |
e501139a | 8443 | tp->rtl_ops.disable(tp); |
d9962b0d | 8444 | clear_bit(IN_PRE_RESET, &tp->flags); |
e501139a | 8445 | mutex_unlock(&tp->control); |
8446 | } | |
8447 | ||
8448 | return 0; | |
8449 | } | |
8450 | ||
8451 | static int rtl8152_post_reset(struct usb_interface *intf) | |
8452 | { | |
8453 | struct r8152 *tp = usb_get_intfdata(intf); | |
8454 | struct net_device *netdev; | |
25766271 | 8455 | struct sockaddr sa; |
e501139a | 8456 | |
d9962b0d | 8457 | if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) |
e62adaee | 8458 | goto exit; |
e501139a | 8459 | |
d9962b0d DA |
8460 | rtl_set_accessible(tp); |
8461 | ||
f62c4f38 | 8462 | /* reset the MAC address in case of policy change */ |
e62adaee | 8463 | if (determine_ethernet_addr(tp, &sa) >= 0) |
25766271 | 8464 | dev_set_mac_address (tp->netdev, &sa, NULL); |
25766271 | 8465 | |
e501139a | 8466 | netdev = tp->netdev; |
8467 | if (!netif_running(netdev)) | |
e62adaee | 8468 | goto exit; |
e501139a | 8469 | |
8470 | set_bit(WORK_ENABLE, &tp->flags); | |
8471 | if (netif_carrier_ok(netdev)) { | |
8472 | mutex_lock(&tp->control); | |
8473 | tp->rtl_ops.enable(tp); | |
2c561b2b | 8474 | rtl_start_rx(tp); |
aece4770 | 8475 | _rtl8152_set_rx_mode(netdev); |
e501139a | 8476 | mutex_unlock(&tp->control); |
e501139a | 8477 | } |
8478 | ||
8479 | napi_enable(&tp->napi); | |
d2187f8e | 8480 | tasklet_enable(&tp->tx_tl); |
de9bf29d | 8481 | netif_wake_queue(netdev); |
2c561b2b | 8482 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 8483 | |
7489bdad | 8484 | if (!list_empty(&tp->rx_done)) |
8485 | napi_schedule(&tp->napi); | |
e501139a | 8486 | |
e62adaee DA |
8487 | exit: |
8488 | rtnl_unlock(); | |
e501139a | 8489 | return 0; |
43779f8d | 8490 | } |
8491 | ||
2dd49e0f | 8492 | static bool delay_autosuspend(struct r8152 *tp) |
8493 | { | |
8494 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
8495 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
8496 | ||
8497 | /* This means a linking change occurs and the driver doesn't detect it, | |
8498 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
8499 | * device wouldn't wake up by receiving any packet. | |
8500 | */ | |
8501 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
8502 | return true; | |
8503 | ||
8504 | /* If the linking down is occurred by nway, the device may miss the | |
8505 | * linking change event. And it wouldn't wake when linking on. | |
8506 | */ | |
8507 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
8508 | return true; | |
6a0b76c0 | 8509 | else if (!skb_queue_empty(&tp->tx_queue)) |
8510 | return true; | |
2dd49e0f | 8511 | else |
8512 | return false; | |
8513 | } | |
8514 | ||
21cbd0ec | 8515 | static int rtl8152_runtime_resume(struct r8152 *tp) |
8516 | { | |
8517 | struct net_device *netdev = tp->netdev; | |
8518 | ||
8519 | if (netif_running(netdev) && netdev->flags & IFF_UP) { | |
8520 | struct napi_struct *napi = &tp->napi; | |
8521 | ||
8522 | tp->rtl_ops.autosuspend_en(tp, false); | |
8523 | napi_disable(napi); | |
8524 | set_bit(WORK_ENABLE, &tp->flags); | |
8525 | ||
8526 | if (netif_carrier_ok(netdev)) { | |
8527 | if (rtl8152_get_speed(tp) & LINK_STATUS) { | |
8528 | rtl_start_rx(tp); | |
8529 | } else { | |
8530 | netif_carrier_off(netdev); | |
8531 | tp->rtl_ops.disable(tp); | |
8532 | netif_info(tp, link, netdev, "linking down\n"); | |
8533 | } | |
8534 | } | |
8535 | ||
8536 | napi_enable(napi); | |
8537 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
8538 | smp_mb__after_atomic(); | |
8539 | ||
8540 | if (!list_empty(&tp->rx_done)) | |
8541 | napi_schedule(&tp->napi); | |
8542 | ||
8543 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
8544 | } else { | |
8545 | if (netdev->flags & IFF_UP) | |
8546 | tp->rtl_ops.autosuspend_en(tp, false); | |
8547 | ||
8548 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
8549 | } | |
8550 | ||
8551 | return 0; | |
8552 | } | |
8553 | ||
8554 | static int rtl8152_system_resume(struct r8152 *tp) | |
8555 | { | |
8556 | struct net_device *netdev = tp->netdev; | |
8557 | ||
8558 | netif_device_attach(netdev); | |
8559 | ||
5b1d9c17 | 8560 | if (netif_running(netdev) && (netdev->flags & IFF_UP)) { |
21cbd0ec | 8561 | tp->rtl_ops.up(tp); |
8562 | netif_carrier_off(netdev); | |
8563 | set_bit(WORK_ENABLE, &tp->flags); | |
8564 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
8565 | } | |
8566 | ||
4933b066 DA |
8567 | /* If the device is RTL8152_INACCESSIBLE here then we should do a |
8568 | * reset. This is important because the usb_lock_device_for_reset() | |
8569 | * that happens as a result of usb_queue_reset_device() will silently | |
8570 | * fail if the device was suspended or if too much time passed. | |
8571 | * | |
8572 | * NOTE: The device is locked here so we can directly do the reset. | |
8573 | * We don't need usb_lock_device_for_reset() because that's just a | |
8574 | * wrapper over device_lock() and device_resume() (which calls us) | |
8575 | * does that for us. | |
8576 | */ | |
8577 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) | |
8578 | usb_reset_device(tp->udev); | |
8579 | ||
21cbd0ec | 8580 | return 0; |
8581 | } | |
8582 | ||
a9c54ad2 | 8583 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 8584 | { |
6cc69f2a | 8585 | struct net_device *netdev = tp->netdev; |
8586 | int ret = 0; | |
ac718b69 | 8587 | |
c79515e4 HW |
8588 | if (!tp->rtl_ops.autosuspend_en) |
8589 | return -EBUSY; | |
8590 | ||
26afec39 | 8591 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
8592 | smp_mb__after_atomic(); | |
8593 | ||
8fb28061 | 8594 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 8595 | u32 rcr = 0; |
8596 | ||
75dc692e | 8597 | if (netif_carrier_ok(netdev)) { |
8598 | u32 ocp_data; | |
8599 | ||
8600 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
8601 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
8602 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
8603 | rxdy_gated_en(tp, true); | |
8604 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
8605 | PLA_OOB_CTRL); | |
8606 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
8607 | rxdy_gated_en(tp, false); | |
8608 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 8609 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
8610 | smp_mb__after_atomic(); | |
75dc692e | 8611 | ret = -EBUSY; |
8612 | goto out1; | |
8613 | } | |
8614 | } | |
8615 | ||
8fb28061 | 8616 | clear_bit(WORK_ENABLE, &tp->flags); |
8617 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 8618 | |
8fb28061 | 8619 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 8620 | |
8621 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 8622 | struct napi_struct *napi = &tp->napi; |
8623 | ||
8624 | napi_disable(napi); | |
75dc692e | 8625 | rtl_stop_rx(tp); |
8626 | rxdy_gated_en(tp, false); | |
8627 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 8628 | napi_enable(napi); |
75dc692e | 8629 | } |
bd882982 | 8630 | |
8631 | if (delay_autosuspend(tp)) { | |
8632 | rtl8152_runtime_resume(tp); | |
8633 | ret = -EBUSY; | |
8634 | } | |
6cc69f2a | 8635 | } |
ac718b69 | 8636 | |
8fb28061 | 8637 | out1: |
8638 | return ret; | |
8639 | } | |
8640 | ||
8641 | static int rtl8152_system_suspend(struct r8152 *tp) | |
8642 | { | |
8643 | struct net_device *netdev = tp->netdev; | |
8fb28061 | 8644 | |
8645 | netif_device_detach(netdev); | |
8646 | ||
e3bd1a81 | 8647 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 8648 | struct napi_struct *napi = &tp->napi; |
8649 | ||
ac718b69 | 8650 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 8651 | usb_kill_urb(tp->intr_urb); |
d2187f8e | 8652 | tasklet_disable(&tp->tx_tl); |
ce594e98 | 8653 | napi_disable(napi); |
8fb28061 | 8654 | cancel_delayed_work_sync(&tp->schedule); |
8655 | tp->rtl_ops.down(tp); | |
ce594e98 | 8656 | napi_enable(napi); |
d2187f8e | 8657 | tasklet_enable(&tp->tx_tl); |
ac718b69 | 8658 | } |
8fb28061 | 8659 | |
8c1d92a7 DA |
8660 | /* If we're inaccessible here then some of the work that we did to |
8661 | * get the adapter ready for suspend didn't work. Queue up a wakeup | |
8662 | * event so we can try again. | |
8663 | */ | |
8664 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) | |
8665 | pm_wakeup_event(&tp->udev->dev, 0); | |
8666 | ||
f741917e | 8667 | return 0; |
8fb28061 | 8668 | } |
8669 | ||
8670 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
8671 | { | |
8672 | struct r8152 *tp = usb_get_intfdata(intf); | |
8673 | int ret; | |
8674 | ||
8675 | mutex_lock(&tp->control); | |
8676 | ||
8677 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 8678 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 8679 | else |
8680 | ret = rtl8152_system_suspend(tp); | |
8681 | ||
b5403273 | 8682 | mutex_unlock(&tp->control); |
8683 | ||
6cc69f2a | 8684 | return ret; |
ac718b69 | 8685 | } |
8686 | ||
8687 | static int rtl8152_resume(struct usb_interface *intf) | |
8688 | { | |
8689 | struct r8152 *tp = usb_get_intfdata(intf); | |
21cbd0ec | 8690 | int ret; |
ac718b69 | 8691 | |
b5403273 | 8692 | mutex_lock(&tp->control); |
8693 | ||
b24edca3 HW |
8694 | rtl_reset_ocp_base(tp); |
8695 | ||
21cbd0ec | 8696 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) |
8697 | ret = rtl8152_runtime_resume(tp); | |
8698 | else | |
8699 | ret = rtl8152_system_resume(tp); | |
ac718b69 | 8700 | |
b5403273 | 8701 | mutex_unlock(&tp->control); |
8702 | ||
21cbd0ec | 8703 | return ret; |
ac718b69 | 8704 | } |
8705 | ||
7ec2541a | 8706 | static int rtl8152_reset_resume(struct usb_interface *intf) |
8707 | { | |
8708 | struct r8152 *tp = usb_get_intfdata(intf); | |
8709 | ||
8710 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
b24edca3 | 8711 | rtl_reset_ocp_base(tp); |
befb2de1 | 8712 | tp->rtl_ops.init(tp); |
8713 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); | |
776ac63a | 8714 | set_ethernet_addr(tp, true); |
7ec2541a | 8715 | return rtl8152_resume(intf); |
8716 | } | |
8717 | ||
21ff2e89 | 8718 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
8719 | { | |
8720 | struct r8152 *tp = netdev_priv(dev); | |
8721 | ||
9a4be1bd | 8722 | if (usb_autopm_get_interface(tp->intf) < 0) |
8723 | return; | |
8724 | ||
7daed8dc | 8725 | if (!rtl_can_wakeup(tp)) { |
8726 | wol->supported = 0; | |
8727 | wol->wolopts = 0; | |
8728 | } else { | |
8729 | mutex_lock(&tp->control); | |
8730 | wol->supported = WAKE_ANY; | |
8731 | wol->wolopts = __rtl_get_wol(tp); | |
8732 | mutex_unlock(&tp->control); | |
8733 | } | |
b5403273 | 8734 | |
9a4be1bd | 8735 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 8736 | } |
8737 | ||
8738 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
8739 | { | |
8740 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 8741 | int ret; |
8742 | ||
7daed8dc | 8743 | if (!rtl_can_wakeup(tp)) |
8744 | return -EOPNOTSUPP; | |
8745 | ||
f2750df1 FF |
8746 | if (wol->wolopts & ~WAKE_ANY) |
8747 | return -EINVAL; | |
8748 | ||
9a4be1bd | 8749 | ret = usb_autopm_get_interface(tp->intf); |
8750 | if (ret < 0) | |
8751 | goto out_set_wol; | |
21ff2e89 | 8752 | |
b5403273 | 8753 | mutex_lock(&tp->control); |
8754 | ||
21ff2e89 | 8755 | __rtl_set_wol(tp, wol->wolopts); |
8756 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
8757 | ||
b5403273 | 8758 | mutex_unlock(&tp->control); |
8759 | ||
9a4be1bd | 8760 | usb_autopm_put_interface(tp->intf); |
8761 | ||
8762 | out_set_wol: | |
8763 | return ret; | |
21ff2e89 | 8764 | } |
8765 | ||
a5ec27c1 | 8766 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
8767 | { | |
8768 | struct r8152 *tp = netdev_priv(dev); | |
8769 | ||
8770 | return tp->msg_enable; | |
8771 | } | |
8772 | ||
8773 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
8774 | { | |
8775 | struct r8152 *tp = netdev_priv(dev); | |
8776 | ||
8777 | tp->msg_enable = value; | |
8778 | } | |
8779 | ||
ac718b69 | 8780 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
8781 | struct ethtool_drvinfo *info) | |
8782 | { | |
8783 | struct r8152 *tp = netdev_priv(netdev); | |
8784 | ||
fb3ceec1 WS |
8785 | strscpy(info->driver, MODULENAME, sizeof(info->driver)); |
8786 | strscpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 8787 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
9370f2d0 | 8788 | if (!IS_ERR_OR_NULL(tp->rtl_fw.fw)) |
fb3ceec1 | 8789 | strscpy(info->fw_version, tp->rtl_fw.version, |
9370f2d0 | 8790 | sizeof(info->fw_version)); |
ac718b69 | 8791 | } |
8792 | ||
8793 | static | |
06144dcf PR |
8794 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
8795 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 8796 | { |
8797 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 8798 | int ret; |
ac718b69 | 8799 | |
8800 | if (!tp->mii.mdio_read) | |
8801 | return -EOPNOTSUPP; | |
8802 | ||
8d4a4d72 | 8803 | ret = usb_autopm_get_interface(tp->intf); |
8804 | if (ret < 0) | |
8805 | goto out; | |
8806 | ||
b5403273 | 8807 | mutex_lock(&tp->control); |
8808 | ||
82c01a84 | 8809 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 8810 | |
195aae32 HW |
8811 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
8812 | cmd->link_modes.supported, tp->support_2500full); | |
8813 | ||
8814 | if (tp->support_2500full) { | |
8815 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, | |
8816 | cmd->link_modes.advertising, | |
8817 | ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); | |
8818 | ||
8819 | linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, | |
8820 | cmd->link_modes.lp_advertising, | |
8821 | ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); | |
8822 | ||
8823 | if (is_speed_2500(rtl8152_get_speed(tp))) | |
8824 | cmd->base.speed = SPEED_2500; | |
8825 | } | |
8826 | ||
b5403273 | 8827 | mutex_unlock(&tp->control); |
8828 | ||
8d4a4d72 | 8829 | usb_autopm_put_interface(tp->intf); |
8830 | ||
8831 | out: | |
8832 | return ret; | |
ac718b69 | 8833 | } |
8834 | ||
06144dcf PR |
8835 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
8836 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 8837 | { |
8838 | struct r8152 *tp = netdev_priv(dev); | |
771efeda | 8839 | u32 advertising = 0; |
9a4be1bd | 8840 | int ret; |
8841 | ||
8842 | ret = usb_autopm_get_interface(tp->intf); | |
8843 | if (ret < 0) | |
8844 | goto out; | |
ac718b69 | 8845 | |
771efeda HW |
8846 | if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, |
8847 | cmd->link_modes.advertising)) | |
8848 | advertising |= RTL_ADVERTISED_10_HALF; | |
8849 | ||
8850 | if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, | |
8851 | cmd->link_modes.advertising)) | |
8852 | advertising |= RTL_ADVERTISED_10_FULL; | |
8853 | ||
8854 | if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, | |
8855 | cmd->link_modes.advertising)) | |
8856 | advertising |= RTL_ADVERTISED_100_HALF; | |
8857 | ||
8858 | if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, | |
8859 | cmd->link_modes.advertising)) | |
8860 | advertising |= RTL_ADVERTISED_100_FULL; | |
8861 | ||
8862 | if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, | |
8863 | cmd->link_modes.advertising)) | |
8864 | advertising |= RTL_ADVERTISED_1000_HALF; | |
8865 | ||
8866 | if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, | |
8867 | cmd->link_modes.advertising)) | |
8868 | advertising |= RTL_ADVERTISED_1000_FULL; | |
8869 | ||
195aae32 HW |
8870 | if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
8871 | cmd->link_modes.advertising)) | |
8872 | advertising |= RTL_ADVERTISED_2500_FULL; | |
8873 | ||
b5403273 | 8874 | mutex_lock(&tp->control); |
8875 | ||
06144dcf | 8876 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
771efeda | 8877 | cmd->base.duplex, advertising); |
aa7e26b6 | 8878 | if (!ret) { |
06144dcf PR |
8879 | tp->autoneg = cmd->base.autoneg; |
8880 | tp->speed = cmd->base.speed; | |
8881 | tp->duplex = cmd->base.duplex; | |
771efeda | 8882 | tp->advertising = advertising; |
aa7e26b6 | 8883 | } |
9a4be1bd | 8884 | |
b5403273 | 8885 | mutex_unlock(&tp->control); |
8886 | ||
9a4be1bd | 8887 | usb_autopm_put_interface(tp->intf); |
8888 | ||
8889 | out: | |
8890 | return ret; | |
ac718b69 | 8891 | } |
8892 | ||
4f1d4d54 | 8893 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
8894 | "tx_packets", | |
8895 | "rx_packets", | |
8896 | "tx_errors", | |
8897 | "rx_errors", | |
8898 | "rx_missed", | |
8899 | "align_errors", | |
8900 | "tx_single_collisions", | |
8901 | "tx_multi_collisions", | |
8902 | "rx_unicast", | |
8903 | "rx_broadcast", | |
8904 | "rx_multicast", | |
8905 | "tx_aborted", | |
8906 | "tx_underrun", | |
8907 | }; | |
8908 | ||
8909 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
8910 | { | |
8911 | switch (sset) { | |
8912 | case ETH_SS_STATS: | |
8913 | return ARRAY_SIZE(rtl8152_gstrings); | |
8914 | default: | |
8915 | return -EOPNOTSUPP; | |
8916 | } | |
8917 | } | |
8918 | ||
8919 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
8920 | struct ethtool_stats *stats, u64 *data) | |
8921 | { | |
8922 | struct r8152 *tp = netdev_priv(dev); | |
8923 | struct tally_counter tally; | |
8924 | ||
0b030244 | 8925 | if (usb_autopm_get_interface(tp->intf) < 0) |
8926 | return; | |
8927 | ||
4f1d4d54 | 8928 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
8929 | ||
0b030244 | 8930 | usb_autopm_put_interface(tp->intf); |
8931 | ||
4f1d4d54 | 8932 | data[0] = le64_to_cpu(tally.tx_packets); |
8933 | data[1] = le64_to_cpu(tally.rx_packets); | |
8934 | data[2] = le64_to_cpu(tally.tx_errors); | |
8935 | data[3] = le32_to_cpu(tally.rx_errors); | |
8936 | data[4] = le16_to_cpu(tally.rx_missed); | |
8937 | data[5] = le16_to_cpu(tally.align_errors); | |
8938 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
8939 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
8940 | data[8] = le64_to_cpu(tally.rx_unicast); | |
8941 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
8942 | data[10] = le32_to_cpu(tally.rx_multicast); | |
8943 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 8944 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 8945 | } |
8946 | ||
8947 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
8948 | { | |
8949 | switch (stringset) { | |
8950 | case ETH_SS_STATS: | |
99718abd | 8951 | memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings)); |
4f1d4d54 | 8952 | break; |
8953 | } | |
8954 | } | |
8955 | ||
d80a5233 | 8956 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee) |
df35d283 | 8957 | { |
17206c11 | 8958 | __ETHTOOL_DECLARE_LINK_MODE_MASK(common); |
df35d283 | 8959 | u16 val; |
8960 | ||
8961 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
17206c11 | 8962 | mii_eee_cap1_mod_linkmode_t(eee->supported, val); |
df35d283 | 8963 | |
8964 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
17206c11 | 8965 | mii_eee_cap1_mod_linkmode_t(eee->advertised, val); |
df35d283 | 8966 | |
8967 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
17206c11 | 8968 | mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); |
df35d283 | 8969 | |
f4a93be6 | 8970 | eee->eee_enabled = tp->eee_en; |
17206c11 AL |
8971 | |
8972 | linkmode_and(common, eee->advertised, eee->lp_advertised); | |
8973 | eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); | |
df35d283 | 8974 | |
8975 | return 0; | |
8976 | } | |
8977 | ||
d80a5233 | 8978 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee) |
df35d283 | 8979 | { |
17206c11 | 8980 | u16 val = linkmode_to_mii_eee_cap1_t(eee->advertised); |
df35d283 | 8981 | |
f4a93be6 HW |
8982 | tp->eee_en = eee->eee_enabled; |
8983 | tp->eee_adv = val; | |
df35d283 | 8984 | |
e7bde56b | 8985 | rtl_eee_enable(tp, tp->eee_en); |
df35d283 | 8986 | |
8987 | return 0; | |
8988 | } | |
8989 | ||
d80a5233 | 8990 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee) |
df35d283 | 8991 | { |
17206c11 | 8992 | __ETHTOOL_DECLARE_LINK_MODE_MASK(common); |
df35d283 | 8993 | u16 val; |
8994 | ||
8995 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
17206c11 | 8996 | mii_eee_cap1_mod_linkmode_t(eee->supported, val); |
df35d283 | 8997 | |
8998 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
17206c11 | 8999 | mii_eee_cap1_mod_linkmode_t(eee->advertised, val); |
df35d283 | 9000 | |
9001 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
17206c11 | 9002 | mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); |
df35d283 | 9003 | |
f4a93be6 | 9004 | eee->eee_enabled = tp->eee_en; |
17206c11 AL |
9005 | |
9006 | linkmode_and(common, eee->advertised, eee->lp_advertised); | |
9007 | eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); | |
df35d283 | 9008 | |
9009 | return 0; | |
9010 | } | |
9011 | ||
df35d283 | 9012 | static int |
d80a5233 | 9013 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata) |
df35d283 | 9014 | { |
9015 | struct r8152 *tp = netdev_priv(net); | |
9016 | int ret; | |
9017 | ||
c79515e4 HW |
9018 | if (!tp->rtl_ops.eee_get) { |
9019 | ret = -EOPNOTSUPP; | |
9020 | goto out; | |
9021 | } | |
9022 | ||
df35d283 | 9023 | ret = usb_autopm_get_interface(tp->intf); |
9024 | if (ret < 0) | |
9025 | goto out; | |
9026 | ||
b5403273 | 9027 | mutex_lock(&tp->control); |
9028 | ||
df35d283 | 9029 | ret = tp->rtl_ops.eee_get(tp, edata); |
9030 | ||
b5403273 | 9031 | mutex_unlock(&tp->control); |
9032 | ||
df35d283 | 9033 | usb_autopm_put_interface(tp->intf); |
9034 | ||
9035 | out: | |
9036 | return ret; | |
9037 | } | |
9038 | ||
9039 | static int | |
d80a5233 | 9040 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata) |
df35d283 | 9041 | { |
9042 | struct r8152 *tp = netdev_priv(net); | |
9043 | int ret; | |
9044 | ||
c79515e4 HW |
9045 | if (!tp->rtl_ops.eee_set) { |
9046 | ret = -EOPNOTSUPP; | |
9047 | goto out; | |
9048 | } | |
9049 | ||
df35d283 | 9050 | ret = usb_autopm_get_interface(tp->intf); |
9051 | if (ret < 0) | |
9052 | goto out; | |
9053 | ||
b5403273 | 9054 | mutex_lock(&tp->control); |
9055 | ||
df35d283 | 9056 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 9057 | if (!ret) |
9058 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 9059 | |
b5403273 | 9060 | mutex_unlock(&tp->control); |
9061 | ||
df35d283 | 9062 | usb_autopm_put_interface(tp->intf); |
9063 | ||
9064 | out: | |
9065 | return ret; | |
9066 | } | |
9067 | ||
8884f507 | 9068 | static int rtl8152_nway_reset(struct net_device *dev) |
9069 | { | |
9070 | struct r8152 *tp = netdev_priv(dev); | |
9071 | int ret; | |
9072 | ||
9073 | ret = usb_autopm_get_interface(tp->intf); | |
9074 | if (ret < 0) | |
9075 | goto out; | |
9076 | ||
9077 | mutex_lock(&tp->control); | |
9078 | ||
9079 | ret = mii_nway_restart(&tp->mii); | |
9080 | ||
9081 | mutex_unlock(&tp->control); | |
9082 | ||
9083 | usb_autopm_put_interface(tp->intf); | |
9084 | ||
9085 | out: | |
9086 | return ret; | |
9087 | } | |
9088 | ||
efb3dd88 | 9089 | static int rtl8152_get_coalesce(struct net_device *netdev, |
f3ccfda1 YM |
9090 | struct ethtool_coalesce *coalesce, |
9091 | struct kernel_ethtool_coalesce *kernel_coal, | |
9092 | struct netlink_ext_ack *extack) | |
efb3dd88 | 9093 | { |
9094 | struct r8152 *tp = netdev_priv(netdev); | |
9095 | ||
9096 | switch (tp->version) { | |
9097 | case RTL_VER_01: | |
9098 | case RTL_VER_02: | |
c27b32c2 | 9099 | case RTL_VER_07: |
efb3dd88 | 9100 | return -EOPNOTSUPP; |
9101 | default: | |
9102 | break; | |
9103 | } | |
9104 | ||
9105 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
9106 | ||
9107 | return 0; | |
9108 | } | |
9109 | ||
9110 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
f3ccfda1 YM |
9111 | struct ethtool_coalesce *coalesce, |
9112 | struct kernel_ethtool_coalesce *kernel_coal, | |
9113 | struct netlink_ext_ack *extack) | |
efb3dd88 | 9114 | { |
9115 | struct r8152 *tp = netdev_priv(netdev); | |
9116 | int ret; | |
9117 | ||
9118 | switch (tp->version) { | |
9119 | case RTL_VER_01: | |
9120 | case RTL_VER_02: | |
c27b32c2 | 9121 | case RTL_VER_07: |
efb3dd88 | 9122 | return -EOPNOTSUPP; |
9123 | default: | |
9124 | break; | |
9125 | } | |
9126 | ||
9127 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
9128 | return -EINVAL; | |
9129 | ||
9130 | ret = usb_autopm_get_interface(tp->intf); | |
9131 | if (ret < 0) | |
9132 | return ret; | |
9133 | ||
9134 | mutex_lock(&tp->control); | |
9135 | ||
9136 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
9137 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
9138 | ||
9fae5418 HW |
9139 | if (netif_running(netdev) && netif_carrier_ok(netdev)) { |
9140 | netif_stop_queue(netdev); | |
9141 | napi_disable(&tp->napi); | |
9142 | tp->rtl_ops.disable(tp); | |
9143 | tp->rtl_ops.enable(tp); | |
9144 | rtl_start_rx(tp); | |
9145 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); | |
9146 | _rtl8152_set_rx_mode(netdev); | |
9147 | napi_enable(&tp->napi); | |
9148 | netif_wake_queue(netdev); | |
9149 | } | |
efb3dd88 | 9150 | } |
9151 | ||
9152 | mutex_unlock(&tp->control); | |
9153 | ||
9154 | usb_autopm_put_interface(tp->intf); | |
9155 | ||
9156 | return ret; | |
9157 | } | |
9158 | ||
e4a5017a HW |
9159 | static int rtl8152_get_tunable(struct net_device *netdev, |
9160 | const struct ethtool_tunable *tunable, void *d) | |
9161 | { | |
9162 | struct r8152 *tp = netdev_priv(netdev); | |
9163 | ||
9164 | switch (tunable->id) { | |
9165 | case ETHTOOL_RX_COPYBREAK: | |
9166 | *(u32 *)d = tp->rx_copybreak; | |
9167 | break; | |
9168 | default: | |
9169 | return -EOPNOTSUPP; | |
9170 | } | |
9171 | ||
9172 | return 0; | |
9173 | } | |
9174 | ||
9175 | static int rtl8152_set_tunable(struct net_device *netdev, | |
9176 | const struct ethtool_tunable *tunable, | |
9177 | const void *d) | |
9178 | { | |
9179 | struct r8152 *tp = netdev_priv(netdev); | |
9180 | u32 val; | |
9181 | ||
9182 | switch (tunable->id) { | |
9183 | case ETHTOOL_RX_COPYBREAK: | |
9184 | val = *(u32 *)d; | |
9185 | if (val < ETH_ZLEN) { | |
9186 | netif_err(tp, rx_err, netdev, | |
9187 | "Invalid rx copy break value\n"); | |
9188 | return -EINVAL; | |
9189 | } | |
9190 | ||
9191 | if (tp->rx_copybreak != val) { | |
5b1d9c17 HW |
9192 | if (netdev->flags & IFF_UP) { |
9193 | mutex_lock(&tp->control); | |
9194 | napi_disable(&tp->napi); | |
9195 | tp->rx_copybreak = val; | |
9196 | napi_enable(&tp->napi); | |
9197 | mutex_unlock(&tp->control); | |
9198 | } else { | |
9199 | tp->rx_copybreak = val; | |
9200 | } | |
e4a5017a HW |
9201 | } |
9202 | break; | |
9203 | default: | |
9204 | return -EOPNOTSUPP; | |
9205 | } | |
9206 | ||
9207 | return 0; | |
9208 | } | |
9209 | ||
9210 | static void rtl8152_get_ringparam(struct net_device *netdev, | |
74624944 HC |
9211 | struct ethtool_ringparam *ring, |
9212 | struct kernel_ethtool_ringparam *kernel_ring, | |
9213 | struct netlink_ext_ack *extack) | |
e4a5017a HW |
9214 | { |
9215 | struct r8152 *tp = netdev_priv(netdev); | |
9216 | ||
9217 | ring->rx_max_pending = RTL8152_RX_MAX_PENDING; | |
9218 | ring->rx_pending = tp->rx_pending; | |
9219 | } | |
9220 | ||
9221 | static int rtl8152_set_ringparam(struct net_device *netdev, | |
74624944 HC |
9222 | struct ethtool_ringparam *ring, |
9223 | struct kernel_ethtool_ringparam *kernel_ring, | |
9224 | struct netlink_ext_ack *extack) | |
e4a5017a HW |
9225 | { |
9226 | struct r8152 *tp = netdev_priv(netdev); | |
9227 | ||
9228 | if (ring->rx_pending < (RTL8152_MAX_RX * 2)) | |
9229 | return -EINVAL; | |
9230 | ||
9231 | if (tp->rx_pending != ring->rx_pending) { | |
5b1d9c17 HW |
9232 | if (netdev->flags & IFF_UP) { |
9233 | mutex_lock(&tp->control); | |
9234 | napi_disable(&tp->napi); | |
9235 | tp->rx_pending = ring->rx_pending; | |
9236 | napi_enable(&tp->napi); | |
9237 | mutex_unlock(&tp->control); | |
9238 | } else { | |
9239 | tp->rx_pending = ring->rx_pending; | |
9240 | } | |
e4a5017a HW |
9241 | } |
9242 | ||
9243 | return 0; | |
9244 | } | |
9245 | ||
163d01c5 HW |
9246 | static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) |
9247 | { | |
9248 | struct r8152 *tp = netdev_priv(netdev); | |
9249 | u16 bmcr, lcladv, rmtadv; | |
9250 | u8 cap; | |
9251 | ||
9252 | if (usb_autopm_get_interface(tp->intf) < 0) | |
9253 | return; | |
9254 | ||
9255 | mutex_lock(&tp->control); | |
9256 | ||
9257 | bmcr = r8152_mdio_read(tp, MII_BMCR); | |
9258 | lcladv = r8152_mdio_read(tp, MII_ADVERTISE); | |
9259 | rmtadv = r8152_mdio_read(tp, MII_LPA); | |
9260 | ||
9261 | mutex_unlock(&tp->control); | |
9262 | ||
9263 | usb_autopm_put_interface(tp->intf); | |
9264 | ||
9265 | if (!(bmcr & BMCR_ANENABLE)) { | |
9266 | pause->autoneg = 0; | |
9267 | pause->rx_pause = 0; | |
9268 | pause->tx_pause = 0; | |
9269 | return; | |
9270 | } | |
9271 | ||
9272 | pause->autoneg = 1; | |
9273 | ||
9274 | cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); | |
9275 | ||
9276 | if (cap & FLOW_CTRL_RX) | |
9277 | pause->rx_pause = 1; | |
9278 | ||
9279 | if (cap & FLOW_CTRL_TX) | |
9280 | pause->tx_pause = 1; | |
9281 | } | |
9282 | ||
9283 | static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) | |
9284 | { | |
9285 | struct r8152 *tp = netdev_priv(netdev); | |
9286 | u16 old, new1; | |
9287 | u8 cap = 0; | |
9288 | int ret; | |
9289 | ||
9290 | ret = usb_autopm_get_interface(tp->intf); | |
9291 | if (ret < 0) | |
9292 | return ret; | |
9293 | ||
9294 | mutex_lock(&tp->control); | |
9295 | ||
9296 | if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) { | |
9297 | ret = -EINVAL; | |
9298 | goto out; | |
9299 | } | |
9300 | ||
9301 | if (pause->rx_pause) | |
9302 | cap |= FLOW_CTRL_RX; | |
9303 | ||
9304 | if (pause->tx_pause) | |
9305 | cap |= FLOW_CTRL_TX; | |
9306 | ||
9307 | old = r8152_mdio_read(tp, MII_ADVERTISE); | |
9308 | new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap); | |
9309 | if (old != new1) | |
9310 | r8152_mdio_write(tp, MII_ADVERTISE, new1); | |
9311 | ||
9312 | out: | |
9313 | mutex_unlock(&tp->control); | |
9314 | usb_autopm_put_interface(tp->intf); | |
9315 | ||
9316 | return ret; | |
9317 | } | |
9318 | ||
407a471d | 9319 | static const struct ethtool_ops ops = { |
e52a646b | 9320 | .supported_coalesce_params = ETHTOOL_COALESCE_USECS, |
ac718b69 | 9321 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 9322 | .get_link = ethtool_op_get_link, |
8884f507 | 9323 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 9324 | .get_msglevel = rtl8152_get_msglevel, |
9325 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 9326 | .get_wol = rtl8152_get_wol, |
9327 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 9328 | .get_strings = rtl8152_get_strings, |
9329 | .get_sset_count = rtl8152_get_sset_count, | |
9330 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 9331 | .get_coalesce = rtl8152_get_coalesce, |
9332 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 9333 | .get_eee = rtl_ethtool_get_eee, |
9334 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
9335 | .get_link_ksettings = rtl8152_get_link_ksettings, |
9336 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
e4a5017a HW |
9337 | .get_tunable = rtl8152_get_tunable, |
9338 | .set_tunable = rtl8152_set_tunable, | |
9339 | .get_ringparam = rtl8152_get_ringparam, | |
9340 | .set_ringparam = rtl8152_set_ringparam, | |
163d01c5 HW |
9341 | .get_pauseparam = rtl8152_get_pauseparam, |
9342 | .set_pauseparam = rtl8152_set_pauseparam, | |
ac718b69 | 9343 | }; |
9344 | ||
9345 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
9346 | { | |
9347 | struct r8152 *tp = netdev_priv(netdev); | |
9348 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 9349 | int res; |
9350 | ||
715f67f3 | 9351 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 9352 | return -ENODEV; |
9353 | ||
9a4be1bd | 9354 | res = usb_autopm_get_interface(tp->intf); |
9355 | if (res < 0) | |
9356 | goto out; | |
ac718b69 | 9357 | |
9358 | switch (cmd) { | |
9359 | case SIOCGMIIPHY: | |
9360 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
9361 | break; | |
9362 | ||
9363 | case SIOCGMIIREG: | |
b5403273 | 9364 | mutex_lock(&tp->control); |
ac718b69 | 9365 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 9366 | mutex_unlock(&tp->control); |
ac718b69 | 9367 | break; |
9368 | ||
9369 | case SIOCSMIIREG: | |
9370 | if (!capable(CAP_NET_ADMIN)) { | |
9371 | res = -EPERM; | |
9372 | break; | |
9373 | } | |
b5403273 | 9374 | mutex_lock(&tp->control); |
ac718b69 | 9375 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 9376 | mutex_unlock(&tp->control); |
ac718b69 | 9377 | break; |
9378 | ||
9379 | default: | |
9380 | res = -EOPNOTSUPP; | |
9381 | } | |
9382 | ||
9a4be1bd | 9383 | usb_autopm_put_interface(tp->intf); |
9384 | ||
9385 | out: | |
ac718b69 | 9386 | return res; |
9387 | } | |
9388 | ||
69b4b7a4 | 9389 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
9390 | { | |
9391 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 9392 | int ret; |
69b4b7a4 | 9393 | |
9394 | switch (tp->version) { | |
9395 | case RTL_VER_01: | |
9396 | case RTL_VER_02: | |
c27b32c2 | 9397 | case RTL_VER_07: |
1eb2cded | 9398 | WRITE_ONCE(dev->mtu, new_mtu); |
a52ad514 | 9399 | return 0; |
69b4b7a4 | 9400 | default: |
9401 | break; | |
9402 | } | |
9403 | ||
396e2e23 | 9404 | ret = usb_autopm_get_interface(tp->intf); |
9405 | if (ret < 0) | |
9406 | return ret; | |
9407 | ||
9408 | mutex_lock(&tp->control); | |
9409 | ||
1eb2cded | 9410 | WRITE_ONCE(dev->mtu, new_mtu); |
69b4b7a4 | 9411 | |
210c4f70 | 9412 | if (netif_running(dev)) { |
67ce1a80 HW |
9413 | if (tp->rtl_ops.change_mtu) |
9414 | tp->rtl_ops.change_mtu(tp); | |
210c4f70 | 9415 | |
67ce1a80 HW |
9416 | if (netif_carrier_ok(dev)) { |
9417 | netif_stop_queue(dev); | |
9418 | napi_disable(&tp->napi); | |
9419 | tasklet_disable(&tp->tx_tl); | |
9420 | tp->rtl_ops.disable(tp); | |
9421 | tp->rtl_ops.enable(tp); | |
9422 | rtl_start_rx(tp); | |
9423 | tasklet_enable(&tp->tx_tl); | |
9424 | napi_enable(&tp->napi); | |
9425 | rtl8152_set_rx_mode(dev); | |
9426 | netif_wake_queue(dev); | |
9427 | } | |
210c4f70 | 9428 | } |
396e2e23 | 9429 | |
9430 | mutex_unlock(&tp->control); | |
9431 | ||
9432 | usb_autopm_put_interface(tp->intf); | |
9433 | ||
9434 | return ret; | |
69b4b7a4 | 9435 | } |
9436 | ||
ac718b69 | 9437 | static const struct net_device_ops rtl8152_netdev_ops = { |
9438 | .ndo_open = rtl8152_open, | |
9439 | .ndo_stop = rtl8152_close, | |
a7605370 | 9440 | .ndo_eth_ioctl = rtl8152_ioctl, |
ac718b69 | 9441 | .ndo_start_xmit = rtl8152_start_xmit, |
9442 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 9443 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 9444 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
9445 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 9446 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 9447 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 9448 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 9449 | }; |
9450 | ||
e3fe0b1a | 9451 | static void rtl8152_unload(struct r8152 *tp) |
9452 | { | |
715f67f3 | 9453 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 9454 | return; |
9455 | ||
00a5e360 | 9456 | if (tp->version != RTL_VER_01) |
9457 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 9458 | } |
9459 | ||
43779f8d | 9460 | static void rtl8153_unload(struct r8152 *tp) |
9461 | { | |
715f67f3 | 9462 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
6871438c | 9463 | return; |
9464 | ||
49be1723 | 9465 | r8153_power_cut_en(tp, false); |
43779f8d | 9466 | } |
9467 | ||
65b82d69 | 9468 | static void rtl8153b_unload(struct r8152 *tp) |
9469 | { | |
715f67f3 | 9470 | if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) |
65b82d69 | 9471 | return; |
9472 | ||
9473 | r8153b_power_cut_en(tp, false); | |
9474 | } | |
9475 | ||
55b65475 | 9476 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 9477 | { |
9478 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 9479 | int ret = 0; |
9480 | ||
9481 | switch (tp->version) { | |
9482 | case RTL_VER_01: | |
9483 | case RTL_VER_02: | |
c27b32c2 | 9484 | case RTL_VER_07: |
55b65475 | 9485 | ops->init = r8152b_init; |
9486 | ops->enable = rtl8152_enable; | |
9487 | ops->disable = rtl8152_disable; | |
9488 | ops->up = rtl8152_up; | |
9489 | ops->down = rtl8152_down; | |
9490 | ops->unload = rtl8152_unload; | |
9491 | ops->eee_get = r8152_get_eee; | |
9492 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 9493 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 9494 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 9495 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
ec5791c2 | 9496 | tp->rx_buf_sz = 16 * 1024; |
f4a93be6 HW |
9497 | tp->eee_en = true; |
9498 | tp->eee_adv = MDIO_EEE_100TX; | |
43779f8d | 9499 | break; |
9500 | ||
55b65475 | 9501 | case RTL_VER_03: |
9502 | case RTL_VER_04: | |
9503 | case RTL_VER_05: | |
fb02eb4a | 9504 | case RTL_VER_06: |
55b65475 | 9505 | ops->init = r8153_init; |
9506 | ops->enable = rtl8153_enable; | |
9507 | ops->disable = rtl8153_disable; | |
9508 | ops->up = rtl8153_up; | |
9509 | ops->down = rtl8153_down; | |
9510 | ops->unload = rtl8153_unload; | |
9511 | ops->eee_get = r8153_get_eee; | |
e7bde56b | 9512 | ops->eee_set = r8152_set_eee; |
2dd49e0f | 9513 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 9514 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 9515 | ops->autosuspend_en = rtl8153_runtime_enable; |
67ce1a80 | 9516 | ops->change_mtu = rtl8153_change_mtu; |
f91a50d8 HW |
9517 | if (tp->udev->speed < USB_SPEED_SUPER) |
9518 | tp->rx_buf_sz = 16 * 1024; | |
9519 | else | |
9520 | tp->rx_buf_sz = 32 * 1024; | |
f4a93be6 HW |
9521 | tp->eee_en = true; |
9522 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
c81229c9 | 9523 | break; |
9524 | ||
65b82d69 | 9525 | case RTL_VER_08: |
9526 | case RTL_VER_09: | |
9527 | ops->init = r8153b_init; | |
9528 | ops->enable = rtl8153_enable; | |
0e5b36bc | 9529 | ops->disable = rtl8153_disable; |
65b82d69 | 9530 | ops->up = rtl8153b_up; |
9531 | ops->down = rtl8153b_down; | |
9532 | ops->unload = rtl8153b_unload; | |
9533 | ops->eee_get = r8153_get_eee; | |
e7bde56b | 9534 | ops->eee_set = r8152_set_eee; |
65b82d69 | 9535 | ops->in_nway = rtl8153_in_nway; |
9536 | ops->hw_phy_cfg = r8153b_hw_phy_cfg; | |
9537 | ops->autosuspend_en = rtl8153b_runtime_enable; | |
67ce1a80 | 9538 | ops->change_mtu = rtl8153_change_mtu; |
ec5791c2 | 9539 | tp->rx_buf_sz = 32 * 1024; |
f4a93be6 HW |
9540 | tp->eee_en = true; |
9541 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
65b82d69 | 9542 | break; |
9543 | ||
195aae32 HW |
9544 | case RTL_VER_11: |
9545 | tp->eee_en = true; | |
9546 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9547 | fallthrough; | |
9548 | case RTL_VER_10: | |
9549 | ops->init = r8156_init; | |
9550 | ops->enable = rtl8156_enable; | |
8ceda6d5 | 9551 | ops->disable = rtl8156_disable; |
195aae32 HW |
9552 | ops->up = rtl8156_up; |
9553 | ops->down = rtl8156_down; | |
9554 | ops->unload = rtl8153_unload; | |
9555 | ops->eee_get = r8153_get_eee; | |
9556 | ops->eee_set = r8152_set_eee; | |
9557 | ops->in_nway = rtl8153_in_nway; | |
9558 | ops->hw_phy_cfg = r8156_hw_phy_cfg; | |
9559 | ops->autosuspend_en = rtl8156_runtime_enable; | |
9560 | ops->change_mtu = rtl8156_change_mtu; | |
9561 | tp->rx_buf_sz = 48 * 1024; | |
9562 | tp->support_2500full = 1; | |
9563 | break; | |
9564 | ||
9565 | case RTL_VER_12: | |
9566 | case RTL_VER_13: | |
9567 | tp->support_2500full = 1; | |
9568 | fallthrough; | |
9569 | case RTL_VER_15: | |
9570 | tp->eee_en = true; | |
9571 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9572 | ops->init = r8156b_init; | |
9573 | ops->enable = rtl8156b_enable; | |
9574 | ops->disable = rtl8153_disable; | |
9575 | ops->up = rtl8156_up; | |
9576 | ops->down = rtl8156_down; | |
9577 | ops->unload = rtl8153_unload; | |
9578 | ops->eee_get = r8153_get_eee; | |
9579 | ops->eee_set = r8152_set_eee; | |
9580 | ops->in_nway = rtl8153_in_nway; | |
9581 | ops->hw_phy_cfg = r8156b_hw_phy_cfg; | |
9582 | ops->autosuspend_en = rtl8156_runtime_enable; | |
9583 | ops->change_mtu = rtl8156_change_mtu; | |
9584 | tp->rx_buf_sz = 48 * 1024; | |
9585 | break; | |
9586 | ||
9587 | case RTL_VER_14: | |
9588 | ops->init = r8153c_init; | |
9589 | ops->enable = rtl8153_enable; | |
9590 | ops->disable = rtl8153_disable; | |
9591 | ops->up = rtl8153c_up; | |
9592 | ops->down = rtl8153b_down; | |
9593 | ops->unload = rtl8153_unload; | |
9594 | ops->eee_get = r8153_get_eee; | |
9595 | ops->eee_set = r8152_set_eee; | |
9596 | ops->in_nway = rtl8153_in_nway; | |
9597 | ops->hw_phy_cfg = r8153c_hw_phy_cfg; | |
9598 | ops->autosuspend_en = rtl8153c_runtime_enable; | |
9599 | ops->change_mtu = rtl8153c_change_mtu; | |
9600 | tp->rx_buf_sz = 32 * 1024; | |
9601 | tp->eee_en = true; | |
9602 | tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; | |
9603 | break; | |
9604 | ||
c81229c9 | 9605 | default: |
55b65475 | 9606 | ret = -ENODEV; |
156c3207 | 9607 | dev_err(&tp->intf->dev, "Unknown Device\n"); |
c81229c9 | 9608 | break; |
9609 | } | |
9610 | ||
9611 | return ret; | |
9612 | } | |
9613 | ||
9370f2d0 HW |
9614 | #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw" |
9615 | #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" | |
9616 | #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" | |
9617 | #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" | |
195aae32 | 9618 | #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" |
4a51b0e8 HW |
9619 | #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw" |
9620 | #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw" | |
9370f2d0 HW |
9621 | |
9622 | MODULE_FIRMWARE(FIRMWARE_8153A_2); | |
9623 | MODULE_FIRMWARE(FIRMWARE_8153A_3); | |
9624 | MODULE_FIRMWARE(FIRMWARE_8153A_4); | |
9625 | MODULE_FIRMWARE(FIRMWARE_8153B_2); | |
195aae32 | 9626 | MODULE_FIRMWARE(FIRMWARE_8153C_1); |
4a51b0e8 HW |
9627 | MODULE_FIRMWARE(FIRMWARE_8156A_2); |
9628 | MODULE_FIRMWARE(FIRMWARE_8156B_2); | |
9370f2d0 HW |
9629 | |
9630 | static int rtl_fw_init(struct r8152 *tp) | |
9631 | { | |
9632 | struct rtl_fw *rtl_fw = &tp->rtl_fw; | |
9633 | ||
9634 | switch (tp->version) { | |
9635 | case RTL_VER_04: | |
9636 | rtl_fw->fw_name = FIRMWARE_8153A_2; | |
9637 | rtl_fw->pre_fw = r8153_pre_firmware_1; | |
9638 | rtl_fw->post_fw = r8153_post_firmware_1; | |
9639 | break; | |
9640 | case RTL_VER_05: | |
9641 | rtl_fw->fw_name = FIRMWARE_8153A_3; | |
9642 | rtl_fw->pre_fw = r8153_pre_firmware_2; | |
9643 | rtl_fw->post_fw = r8153_post_firmware_2; | |
9644 | break; | |
9645 | case RTL_VER_06: | |
9646 | rtl_fw->fw_name = FIRMWARE_8153A_4; | |
9647 | rtl_fw->post_fw = r8153_post_firmware_3; | |
9648 | break; | |
9649 | case RTL_VER_09: | |
9650 | rtl_fw->fw_name = FIRMWARE_8153B_2; | |
9651 | rtl_fw->pre_fw = r8153b_pre_firmware_1; | |
9652 | rtl_fw->post_fw = r8153b_post_firmware_1; | |
9653 | break; | |
4a51b0e8 HW |
9654 | case RTL_VER_11: |
9655 | rtl_fw->fw_name = FIRMWARE_8156A_2; | |
9656 | rtl_fw->post_fw = r8156a_post_firmware_1; | |
9657 | break; | |
9658 | case RTL_VER_13: | |
9659 | case RTL_VER_15: | |
9660 | rtl_fw->fw_name = FIRMWARE_8156B_2; | |
9661 | break; | |
195aae32 HW |
9662 | case RTL_VER_14: |
9663 | rtl_fw->fw_name = FIRMWARE_8153C_1; | |
9664 | rtl_fw->pre_fw = r8153b_pre_firmware_1; | |
9665 | rtl_fw->post_fw = r8153c_post_firmware_1; | |
9666 | break; | |
9370f2d0 HW |
9667 | default: |
9668 | break; | |
9669 | } | |
9670 | ||
9671 | return 0; | |
9672 | } | |
9673 | ||
0d4cda80 | 9674 | static u8 __rtl_get_hw_ver(struct usb_device *udev) |
33928eed | 9675 | { |
33928eed | 9676 | u32 ocp_data = 0; |
9677 | __le32 *tmp; | |
9678 | u8 version; | |
9679 | int ret; | |
d9962b0d | 9680 | int i; |
33928eed | 9681 | |
9682 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
9683 | if (!tmp) | |
9684 | return 0; | |
9685 | ||
d9962b0d DA |
9686 | /* Retry up to 3 times in case there is a transitory error. We do this |
9687 | * since retrying a read of the version is always safe and this | |
9688 | * function doesn't take advantage of r8152_control_msg(). | |
9689 | */ | |
9690 | for (i = 0; i < 3; i++) { | |
9691 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
9692 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
9693 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), | |
9694 | USB_CTRL_GET_TIMEOUT); | |
9695 | if (ret > 0) { | |
9696 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
9697 | break; | |
9698 | } | |
9699 | } | |
9700 | ||
9701 | if (i != 0 && ret > 0) | |
9702 | dev_warn(&udev->dev, "Needed %d retries to read version\n", i); | |
33928eed | 9703 | |
9704 | kfree(tmp); | |
9705 | ||
9706 | switch (ocp_data) { | |
9707 | case 0x4c00: | |
9708 | version = RTL_VER_01; | |
9709 | break; | |
9710 | case 0x4c10: | |
9711 | version = RTL_VER_02; | |
9712 | break; | |
9713 | case 0x5c00: | |
9714 | version = RTL_VER_03; | |
9715 | break; | |
9716 | case 0x5c10: | |
9717 | version = RTL_VER_04; | |
9718 | break; | |
9719 | case 0x5c20: | |
9720 | version = RTL_VER_05; | |
9721 | break; | |
9722 | case 0x5c30: | |
9723 | version = RTL_VER_06; | |
9724 | break; | |
c27b32c2 | 9725 | case 0x4800: |
9726 | version = RTL_VER_07; | |
9727 | break; | |
65b82d69 | 9728 | case 0x6000: |
9729 | version = RTL_VER_08; | |
9730 | break; | |
9731 | case 0x6010: | |
9732 | version = RTL_VER_09; | |
9733 | break; | |
195aae32 HW |
9734 | case 0x7010: |
9735 | version = RTL_TEST_01; | |
9736 | break; | |
9737 | case 0x7020: | |
9738 | version = RTL_VER_10; | |
9739 | break; | |
9740 | case 0x7030: | |
9741 | version = RTL_VER_11; | |
9742 | break; | |
9743 | case 0x7400: | |
9744 | version = RTL_VER_12; | |
9745 | break; | |
9746 | case 0x7410: | |
9747 | version = RTL_VER_13; | |
9748 | break; | |
9749 | case 0x6400: | |
9750 | version = RTL_VER_14; | |
9751 | break; | |
9752 | case 0x7420: | |
9753 | version = RTL_VER_15; | |
9754 | break; | |
33928eed | 9755 | default: |
9756 | version = RTL_VER_UNKNOWN; | |
0d4cda80 | 9757 | dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); |
33928eed | 9758 | break; |
9759 | } | |
9760 | ||
0d4cda80 HW |
9761 | return version; |
9762 | } | |
9763 | ||
9764 | u8 rtl8152_get_version(struct usb_interface *intf) | |
9765 | { | |
9766 | u8 version; | |
9767 | ||
9768 | version = __rtl_get_hw_ver(interface_to_usbdev(intf)); | |
9769 | ||
eb3c28c1 ON |
9770 | dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); |
9771 | ||
33928eed | 9772 | return version; |
9773 | } | |
c1aedf01 | 9774 | EXPORT_SYMBOL_GPL(rtl8152_get_version); |
33928eed | 9775 | |
f01cdcf8 DO |
9776 | static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev) |
9777 | { | |
9778 | int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor); | |
9779 | int product_id = le16_to_cpu(udev->descriptor.idProduct); | |
9780 | int vendor_id = le16_to_cpu(udev->descriptor.idVendor); | |
9781 | ||
9782 | if (vendor_id == VENDOR_ID_LENOVO) { | |
9783 | switch (product_id) { | |
e26c2584 | 9784 | case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB: |
76d7df94 | 9785 | case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK: |
f01cdcf8 DO |
9786 | case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2: |
9787 | case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2: | |
9788 | case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3: | |
9789 | case DEVICE_ID_THINKPAD_USB_C_DONGLE: | |
9790 | return 1; | |
9791 | } | |
9792 | } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) { | |
9793 | switch (product_id) { | |
9794 | case 0x8153: | |
9795 | return 1; | |
9796 | } | |
9797 | } | |
9798 | return 0; | |
9799 | } | |
9800 | ||
d9962b0d DA |
9801 | static int rtl8152_probe_once(struct usb_interface *intf, |
9802 | const struct usb_device_id *id, u8 version) | |
ac718b69 | 9803 | { |
9804 | struct usb_device *udev = interface_to_usbdev(intf); | |
9805 | struct r8152 *tp; | |
9806 | struct net_device *netdev; | |
ebc2ec48 | 9807 | int ret; |
ac718b69 | 9808 | |
10c32717 | 9809 | usb_reset_device(udev); |
ac718b69 | 9810 | netdev = alloc_etherdev(sizeof(struct r8152)); |
9811 | if (!netdev) { | |
4a8deae2 | 9812 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 9813 | return -ENOMEM; |
9814 | } | |
9815 | ||
ebc2ec48 | 9816 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 9817 | tp = netdev_priv(netdev); |
9818 | tp->msg_enable = 0x7FFF; | |
9819 | ||
e3ad412a | 9820 | tp->udev = udev; |
9821 | tp->netdev = netdev; | |
9822 | tp->intf = intf; | |
33928eed | 9823 | tp->version = version; |
9824 | ||
b67fda9a HW |
9825 | tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); |
9826 | tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); | |
9827 | tp->pipe_in = usb_rcvbulkpipe(udev, 1); | |
9828 | tp->pipe_out = usb_sndbulkpipe(udev, 2); | |
9829 | tp->pipe_intr = usb_rcvintpipe(udev, 3); | |
9830 | ||
33928eed | 9831 | switch (version) { |
9832 | case RTL_VER_01: | |
9833 | case RTL_VER_02: | |
c27b32c2 | 9834 | case RTL_VER_07: |
33928eed | 9835 | tp->mii.supports_gmii = 0; |
9836 | break; | |
9837 | default: | |
9838 | tp->mii.supports_gmii = 1; | |
9839 | break; | |
9840 | } | |
e3ad412a | 9841 | |
55b65475 | 9842 | ret = rtl_ops_init(tp); |
31ca1dec | 9843 | if (ret) |
9844 | goto out; | |
c81229c9 | 9845 | |
9370f2d0 HW |
9846 | rtl_fw_init(tp); |
9847 | ||
b5403273 | 9848 | mutex_init(&tp->control); |
ac718b69 | 9849 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 9850 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
f3163f1c | 9851 | tasklet_setup(&tp->tx_tl, bottom_half); |
d2187f8e | 9852 | tasklet_disable(&tp->tx_tl); |
ac718b69 | 9853 | |
ac718b69 | 9854 | netdev->netdev_ops = &rtl8152_netdev_ops; |
9855 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 9856 | |
60c89071 | 9857 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 9858 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 9859 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
9860 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 9861 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 9862 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 9863 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 9864 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 9865 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
9866 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
9867 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 9868 | |
19c0f40d | 9869 | if (tp->version == RTL_VER_01) { |
9870 | netdev->features &= ~NETIF_F_RXCSUM; | |
9871 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
9872 | } | |
9873 | ||
f01cdcf8 | 9874 | tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev); |
9647722b | 9875 | |
176eb614 | 9876 | if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && |
151ea094 PM |
9877 | (!strcmp(udev->serial, "000001000000") || |
9878 | !strcmp(udev->serial, "000002000000"))) { | |
0b165514 | 9879 | dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); |
9c68011b | 9880 | tp->dell_tb_rx_agg_bug = 1; |
0b165514 KHF |
9881 | } |
9882 | ||
7ad24ea4 | 9883 | netdev->ethtool_ops = &ops; |
ee8b7a11 | 9884 | netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 9885 | |
f77f0aee JW |
9886 | /* MTU range: 68 - 1500 or 9194 */ |
9887 | netdev->min_mtu = ETH_MIN_MTU; | |
9888 | switch (tp->version) { | |
195aae32 HW |
9889 | case RTL_VER_03: |
9890 | case RTL_VER_04: | |
9891 | case RTL_VER_05: | |
9892 | case RTL_VER_06: | |
9893 | case RTL_VER_08: | |
9894 | case RTL_VER_09: | |
9895 | case RTL_VER_14: | |
9896 | netdev->max_mtu = size_to_mtu(9 * 1024); | |
9897 | break; | |
9898 | case RTL_VER_10: | |
9899 | case RTL_VER_11: | |
9900 | netdev->max_mtu = size_to_mtu(15 * 1024); | |
9901 | break; | |
9902 | case RTL_VER_12: | |
9903 | case RTL_VER_13: | |
9904 | case RTL_VER_15: | |
9905 | netdev->max_mtu = size_to_mtu(16 * 1024); | |
9906 | break; | |
f77f0aee JW |
9907 | case RTL_VER_01: |
9908 | case RTL_VER_02: | |
195aae32 | 9909 | case RTL_VER_07: |
f77f0aee | 9910 | default: |
195aae32 | 9911 | netdev->max_mtu = ETH_DATA_LEN; |
f77f0aee JW |
9912 | break; |
9913 | } | |
9914 | ||
ac718b69 | 9915 | tp->mii.dev = netdev; |
9916 | tp->mii.mdio_read = read_mii_word; | |
9917 | tp->mii.mdio_write = write_mii_word; | |
9918 | tp->mii.phy_id_mask = 0x3f; | |
9919 | tp->mii.reg_num_mask = 0x1f; | |
9920 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 9921 | |
aa7e26b6 | 9922 | tp->autoneg = AUTONEG_ENABLE; |
771efeda HW |
9923 | tp->speed = SPEED_100; |
9924 | tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | | |
9925 | RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; | |
9926 | if (tp->mii.supports_gmii) { | |
195aae32 HW |
9927 | if (tp->support_2500full && |
9928 | tp->udev->speed >= USB_SPEED_SUPER) { | |
9929 | tp->speed = SPEED_2500; | |
9930 | tp->advertising |= RTL_ADVERTISED_2500_FULL; | |
9931 | } else { | |
9932 | tp->speed = SPEED_1000; | |
9933 | } | |
771efeda HW |
9934 | tp->advertising |= RTL_ADVERTISED_1000_FULL; |
9935 | } | |
aa7e26b6 | 9936 | tp->duplex = DUPLEX_FULL; |
9937 | ||
e4a5017a HW |
9938 | tp->rx_copybreak = RTL8152_RXFG_HEADSZ; |
9939 | tp->rx_pending = 10 * RTL8152_MAX_RX; | |
9940 | ||
9a4be1bd | 9941 | intf->needs_remote_wakeup = 1; |
9942 | ||
9583a363 HW |
9943 | if (!rtl_can_wakeup(tp)) |
9944 | __rtl_set_wol(tp, 0); | |
9945 | else | |
9946 | tp->saved_wolopts = __rtl_get_wol(tp); | |
9947 | ||
c81229c9 | 9948 | tp->rtl_ops.init(tp); |
9370f2d0 HW |
9949 | #if IS_BUILTIN(CONFIG_USB_RTL8152) |
9950 | /* Retry in case request_firmware() is not ready yet. */ | |
9951 | tp->rtl_fw.retry = true; | |
9952 | #endif | |
a028a9e0 | 9953 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
776ac63a | 9954 | set_ethernet_addr(tp, false); |
ac718b69 | 9955 | |
ac718b69 | 9956 | usb_set_intfdata(intf, tp); |
195aae32 | 9957 | |
cf74eb5a | 9958 | netif_napi_add(netdev, &tp->napi, r8152_poll); |
ac718b69 | 9959 | |
ebc2ec48 | 9960 | ret = register_netdev(netdev); |
9961 | if (ret != 0) { | |
156c3207 | 9962 | dev_err(&intf->dev, "couldn't register the device\n"); |
ebc2ec48 | 9963 | goto out1; |
ac718b69 | 9964 | } |
9965 | ||
21ff2e89 | 9966 | if (tp->saved_wolopts) |
9967 | device_set_wakeup_enable(&udev->dev, true); | |
9968 | else | |
9969 | device_set_wakeup_enable(&udev->dev, false); | |
9970 | ||
d9962b0d DA |
9971 | /* If we saw a control transfer error while probing then we may |
9972 | * want to try probe() again. Consider this an error. | |
9973 | */ | |
9974 | if (test_bit(PROBE_SHOULD_RETRY, &tp->flags)) | |
9975 | goto out2; | |
9976 | ||
9977 | set_bit(PROBED_WITH_NO_ERRORS, &tp->flags); | |
4a8deae2 | 9978 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 9979 | |
9980 | return 0; | |
9981 | ||
d9962b0d DA |
9982 | out2: |
9983 | unregister_netdev(netdev); | |
9984 | ||
ac718b69 | 9985 | out1: |
d2187f8e | 9986 | tasklet_kill(&tp->tx_tl); |
bb8adff9 | 9987 | cancel_delayed_work_sync(&tp->hw_phy_work); |
5dd17689 DA |
9988 | if (tp->rtl_ops.unload) |
9989 | tp->rtl_ops.unload(tp); | |
b8d35024 | 9990 | rtl8152_release_firmware(tp); |
ebc2ec48 | 9991 | usb_set_intfdata(intf, NULL); |
ac718b69 | 9992 | out: |
d9962b0d DA |
9993 | if (test_bit(PROBE_SHOULD_RETRY, &tp->flags)) |
9994 | ret = -EAGAIN; | |
9995 | ||
ac718b69 | 9996 | free_netdev(netdev); |
ebc2ec48 | 9997 | return ret; |
ac718b69 | 9998 | } |
9999 | ||
d9962b0d DA |
10000 | #define RTL8152_PROBE_TRIES 3 |
10001 | ||
10002 | static int rtl8152_probe(struct usb_interface *intf, | |
10003 | const struct usb_device_id *id) | |
10004 | { | |
10005 | u8 version; | |
10006 | int ret; | |
10007 | int i; | |
10008 | ||
10009 | if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) | |
10010 | return -ENODEV; | |
10011 | ||
10012 | if (!rtl_check_vendor_ok(intf)) | |
10013 | return -ENODEV; | |
10014 | ||
10015 | version = rtl8152_get_version(intf); | |
10016 | if (version == RTL_VER_UNKNOWN) | |
10017 | return -ENODEV; | |
10018 | ||
10019 | for (i = 0; i < RTL8152_PROBE_TRIES; i++) { | |
10020 | ret = rtl8152_probe_once(intf, id, version); | |
10021 | if (ret != -EAGAIN) | |
10022 | break; | |
10023 | } | |
10024 | if (ret == -EAGAIN) { | |
10025 | dev_err(&intf->dev, | |
10026 | "r8152 failed probe after %d tries; giving up\n", i); | |
10027 | return -ENODEV; | |
10028 | } | |
10029 | ||
10030 | return ret; | |
10031 | } | |
10032 | ||
ac718b69 | 10033 | static void rtl8152_disconnect(struct usb_interface *intf) |
10034 | { | |
10035 | struct r8152 *tp = usb_get_intfdata(intf); | |
10036 | ||
10037 | usb_set_intfdata(intf, NULL); | |
10038 | if (tp) { | |
ffa9fec3 | 10039 | rtl_set_unplug(tp); |
f561de33 | 10040 | |
ac718b69 | 10041 | unregister_netdev(tp->netdev); |
d2187f8e | 10042 | tasklet_kill(&tp->tx_tl); |
a028a9e0 | 10043 | cancel_delayed_work_sync(&tp->hw_phy_work); |
195aae32 HW |
10044 | if (tp->rtl_ops.unload) |
10045 | tp->rtl_ops.unload(tp); | |
9370f2d0 | 10046 | rtl8152_release_firmware(tp); |
ac718b69 | 10047 | free_netdev(tp->netdev); |
10048 | } | |
10049 | } | |
10050 | ||
10051 | /* table of devices that work with this driver */ | |
9b4355fb | 10052 | static const struct usb_device_id rtl8152_table[] = { |
195aae32 | 10053 | /* Realtek */ |
ec51fbd1 BM |
10054 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) }, |
10055 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) }, | |
10056 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) }, | |
10057 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, | |
10058 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, | |
10059 | { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, | |
195aae32 HW |
10060 | |
10061 | /* Microsoft */ | |
ec51fbd1 BM |
10062 | { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, |
10063 | { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) }, | |
10064 | { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) }, | |
a99da46a | 10065 | { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) }, |
ec51fbd1 BM |
10066 | { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) }, |
10067 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) }, | |
10068 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) }, | |
10069 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) }, | |
10070 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) }, | |
10071 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) }, | |
10072 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) }, | |
10073 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) }, | |
10074 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) }, | |
10075 | { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) }, | |
10076 | { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) }, | |
10077 | { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, | |
10078 | { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, | |
10079 | { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, | |
72f93a31 | 10080 | { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) }, |
7037d95a | 10081 | { USB_DEVICE(VENDOR_ID_ASUS, 0x1976) }, |
ac718b69 | 10082 | {} |
10083 | }; | |
10084 | ||
10085 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
10086 | ||
10087 | static struct usb_driver rtl8152_driver = { | |
10088 | .name = MODULENAME, | |
ebc2ec48 | 10089 | .id_table = rtl8152_table, |
ac718b69 | 10090 | .probe = rtl8152_probe, |
10091 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 10092 | .suspend = rtl8152_suspend, |
ebc2ec48 | 10093 | .resume = rtl8152_resume, |
7ec2541a | 10094 | .reset_resume = rtl8152_reset_resume, |
e501139a | 10095 | .pre_reset = rtl8152_pre_reset, |
10096 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 10097 | .supports_autosuspend = 1, |
a634782f | 10098 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 10099 | }; |
10100 | ||
aa4f2b3e | 10101 | static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev) |
ec51fbd1 BM |
10102 | { |
10103 | struct usb_host_config *c; | |
10104 | int i, num_configs; | |
10105 | ||
0d4cda80 HW |
10106 | /* Switch the device to vendor mode, if and only if the vendor mode |
10107 | * driver supports it. | |
10108 | */ | |
10109 | if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN) | |
46590b54 | 10110 | return -ENODEV; |
0d4cda80 | 10111 | |
ec51fbd1 BM |
10112 | /* The vendor mode is not always config #1, so to find it out. */ |
10113 | c = udev->config; | |
10114 | num_configs = udev->descriptor.bNumConfigurations; | |
10115 | for (i = 0; i < num_configs; (i++, c++)) { | |
10116 | struct usb_interface_descriptor *desc = NULL; | |
10117 | ||
10118 | if (!c->desc.bNumInterfaces) | |
10119 | continue; | |
10120 | desc = &c->intf_cache[0]->altsetting->desc; | |
10121 | if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) | |
10122 | break; | |
10123 | } | |
10124 | ||
10125 | if (i == num_configs) | |
10126 | return -ENODEV; | |
10127 | ||
aa4f2b3e | 10128 | return c->desc.bConfigurationValue; |
ec51fbd1 BM |
10129 | } |
10130 | ||
10131 | static struct usb_device_driver rtl8152_cfgselector_driver = { | |
aa4f2b3e DA |
10132 | .name = MODULENAME "-cfgselector", |
10133 | .choose_configuration = rtl8152_cfgselector_choose_configuration, | |
10134 | .id_table = rtl8152_table, | |
ec51fbd1 | 10135 | .generic_subclass = 1, |
0fbd79c0 | 10136 | .supports_autosuspend = 1, |
ec51fbd1 BM |
10137 | }; |
10138 | ||
10139 | static int __init rtl8152_driver_init(void) | |
10140 | { | |
10141 | int ret; | |
10142 | ||
10143 | ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE); | |
10144 | if (ret) | |
10145 | return ret; | |
10146 | return usb_register(&rtl8152_driver); | |
10147 | } | |
10148 | ||
10149 | static void __exit rtl8152_driver_exit(void) | |
10150 | { | |
10151 | usb_deregister(&rtl8152_driver); | |
10152 | usb_deregister_device_driver(&rtl8152_cfgselector_driver); | |
10153 | } | |
10154 | ||
10155 | module_init(rtl8152_driver_init); | |
10156 | module_exit(rtl8152_driver_exit); | |
ac718b69 | 10157 | |
10158 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
10159 | MODULE_DESCRIPTION(DRIVER_DESC); | |
10160 | MODULE_LICENSE("GPL"); | |
c961e877 | 10161 | MODULE_VERSION(DRIVER_VERSION); |