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319da621 CL |
1 | /* |
2 | * Atheros CARL9170 driver | |
3 | * | |
4 | * PHY and RF code | |
5 | * | |
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, see | |
20 | * http://www.gnu.org/licenses/. | |
21 | * | |
22 | * This file incorporates work covered by the following copyright and | |
23 | * permission notice: | |
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | |
25 | * | |
26 | * Permission to use, copy, modify, and/or distribute this software for any | |
27 | * purpose with or without fee is hereby granted, provided that the above | |
28 | * copyright notice and this permission notice appear in all copies. | |
29 | * | |
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
37 | */ | |
38 | ||
39 | #include <linux/bitrev.h> | |
40 | #include "carl9170.h" | |
41 | #include "cmd.h" | |
42 | #include "phy.h" | |
43 | ||
44 | static int carl9170_init_power_cal(struct ar9170 *ar) | |
45 | { | |
46 | carl9170_regwrite_begin(ar); | |
47 | ||
48 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); | |
49 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); | |
50 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); | |
51 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); | |
52 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); | |
53 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); | |
54 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); | |
55 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); | |
56 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); | |
57 | carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); | |
58 | ||
59 | carl9170_regwrite_finish(); | |
60 | return carl9170_regwrite_result(); | |
61 | } | |
62 | ||
63 | struct carl9170_phy_init { | |
64 | u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20; | |
65 | }; | |
66 | ||
67 | static struct carl9170_phy_init ar5416_phy_init[] = { | |
68 | { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | |
69 | { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, }, | |
70 | { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
71 | { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, }, | |
72 | { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, }, | |
73 | { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, }, | |
74 | { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, }, | |
75 | { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
76 | { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, }, | |
77 | { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, }, | |
78 | { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, }, | |
79 | { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, }, | |
80 | { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
81 | { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, }, | |
82 | { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | |
83 | { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, }, | |
84 | { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, }, | |
85 | { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, }, | |
86 | { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, }, | |
87 | { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, }, | |
c807666a | 88 | { 0x1c5850, 0x6c48b4e4, 0x6d48b4e4, 0x6d48b0e4, 0x6c48b0e4, }, |
319da621 CL |
89 | { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, }, |
90 | { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, }, | |
c807666a | 91 | { 0x1c585c, 0x31395c5e, 0x3139605e, 0x3139605e, 0x31395c5e, }, |
319da621 | 92 | { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, }, |
c807666a | 93 | { 0x1c5864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, }, |
319da621 CL |
94 | { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, }, |
95 | { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, }, | |
96 | { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
97 | { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
98 | { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
99 | { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
100 | { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, }, | |
101 | { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, }, | |
102 | { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, }, | |
103 | { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, }, | |
104 | { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, }, | |
105 | { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | |
106 | { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, }, | |
107 | { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
108 | { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
109 | { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, }, | |
110 | { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, }, | |
111 | { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, }, | |
112 | { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, }, | |
113 | { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, }, | |
114 | { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, }, | |
115 | { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | |
116 | { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, }, | |
117 | { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, }, | |
118 | { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
119 | { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | |
120 | { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
121 | { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
122 | { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
123 | { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
124 | { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
125 | { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
126 | { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
127 | { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
128 | { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
129 | { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
130 | { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | |
131 | { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, }, | |
132 | { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, }, | |
133 | { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, }, | |
134 | { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, }, | |
c807666a | 135 | { 0x1c59bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, }, |
319da621 CL |
136 | { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, }, |
137 | { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, }, | |
c807666a | 138 | { 0x1c59c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, }, |
319da621 CL |
139 | { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, }, |
140 | { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, }, | |
141 | { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
142 | { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
143 | { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
144 | { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, }, | |
145 | { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, }, | |
146 | { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, }, | |
147 | { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, }, | |
148 | { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
149 | { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, }, | |
150 | { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
151 | { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, }, | |
152 | { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, }, | |
153 | { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, }, | |
154 | { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, }, | |
155 | { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, }, | |
156 | { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, }, | |
157 | { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, }, | |
158 | { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, }, | |
159 | { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, }, | |
160 | { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, }, | |
161 | { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, }, | |
162 | { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, }, | |
163 | { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, }, | |
164 | { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, }, | |
165 | { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, }, | |
166 | { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, }, | |
167 | { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, }, | |
168 | { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, }, | |
169 | { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, }, | |
170 | { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, }, | |
171 | { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, }, | |
172 | { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, }, | |
173 | { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, }, | |
174 | { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, }, | |
175 | { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, }, | |
176 | { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, }, | |
177 | { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, }, | |
178 | { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, }, | |
179 | { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, }, | |
180 | { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, }, | |
181 | { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, }, | |
182 | { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, }, | |
183 | { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, }, | |
184 | { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, }, | |
185 | { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, }, | |
186 | { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, }, | |
187 | { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, }, | |
188 | { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, }, | |
189 | { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, }, | |
190 | { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
191 | { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
192 | { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
193 | { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
194 | { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
195 | { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
196 | { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
197 | { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
198 | { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
199 | { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
200 | { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
201 | { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
202 | { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
203 | { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
204 | { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
205 | { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
206 | { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
207 | { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
208 | { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
209 | { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
210 | { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
211 | { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
212 | { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
213 | { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | |
214 | { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
215 | { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | |
216 | { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, }, | |
217 | { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, }, | |
218 | { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, }, | |
219 | { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, }, | |
220 | { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, }, | |
221 | { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, }, | |
222 | { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, }, | |
223 | { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, }, | |
224 | { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, }, | |
225 | { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, }, | |
226 | { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, }, | |
227 | { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, }, | |
228 | { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, }, | |
229 | { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, }, | |
230 | { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, }, | |
231 | { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, }, | |
232 | { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, }, | |
233 | { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, }, | |
234 | { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, }, | |
235 | { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, }, | |
236 | { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, }, | |
237 | { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, }, | |
238 | { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, }, | |
239 | { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, }, | |
240 | { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, }, | |
241 | { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, }, | |
242 | { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, }, | |
243 | { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, }, | |
244 | { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, }, | |
245 | { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, }, | |
246 | { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, }, | |
247 | { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, }, | |
248 | { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, }, | |
249 | { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, }, | |
250 | { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, }, | |
251 | { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, }, | |
252 | { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, }, | |
253 | { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, }, | |
254 | { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, }, | |
255 | { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
256 | { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
257 | { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
258 | { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
259 | { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
260 | { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
261 | { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
262 | { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
263 | { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
264 | { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
265 | { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
266 | { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
267 | { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
268 | { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
269 | { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
270 | { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
271 | { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
272 | { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
273 | { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
274 | { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
275 | { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | |
276 | { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, }, | |
277 | { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, }, | |
278 | { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
279 | { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
280 | { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
281 | { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
282 | { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
283 | { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
284 | { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
285 | { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
286 | { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
287 | { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
288 | { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
289 | { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
290 | { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
291 | { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
292 | { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
293 | { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
294 | { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
295 | { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
296 | { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, }, | |
297 | { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, }, | |
298 | { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, }, | |
299 | { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | |
300 | { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, }, | |
301 | { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, }, | |
302 | { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, }, | |
303 | { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, }, | |
304 | { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, }, | |
305 | { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, }, | |
306 | { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, }, | |
307 | { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
308 | { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, }, | |
309 | { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
310 | { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
311 | { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, }, | |
312 | { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, }, | |
313 | { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, }, | |
314 | { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, }, | |
315 | { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | |
316 | { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, }, | |
317 | { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
318 | { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, }, | |
319 | { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, }, | |
320 | { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, }, | |
321 | { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, }, | |
322 | { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
323 | { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | |
324 | { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, }, | |
325 | { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | |
326 | { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, }, | |
327 | { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, }, | |
328 | { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, }, | |
329 | { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, }, | |
330 | { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, }, | |
331 | { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, }, | |
332 | { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, }, | |
333 | { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, }, | |
334 | { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, }, | |
335 | { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, }, | |
336 | { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, }, | |
337 | { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, }, | |
338 | { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
339 | { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
340 | { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
341 | { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
342 | { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
343 | { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
344 | { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
345 | { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | |
346 | { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | |
347 | { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | |
348 | { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, }, | |
349 | { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, }, | |
350 | { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, }, | |
351 | { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
352 | { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
353 | { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | |
354 | { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, }, | |
355 | { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | |
356 | { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
357 | { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
358 | { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
359 | { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
360 | { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
361 | { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
362 | { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
363 | { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
364 | { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
365 | { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
366 | { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
367 | { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
368 | { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
369 | { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | |
370 | { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | |
371 | { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | |
372 | { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, }, | |
373 | { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, }, | |
374 | { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, }, | |
375 | { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | |
376 | { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | |
377 | { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | |
378 | { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, }, | |
379 | { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, }, | |
380 | { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | |
381 | { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | |
382 | { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | |
383 | /* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */ | |
384 | { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, }, | |
385 | { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, }, | |
386 | { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, }, | |
387 | { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, }, | |
388 | { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, }, | |
389 | { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, }, | |
390 | { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, }, | |
391 | { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, }, | |
392 | { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, }, | |
393 | { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, }, | |
394 | { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, }, | |
395 | { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, }, | |
396 | { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, }, | |
397 | { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, }, | |
398 | { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, }, | |
399 | { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, } | |
400 | }; | |
401 | ||
402 | /* | |
403 | * look up a certain register in ar5416_phy_init[] and return the init. value | |
404 | * for the band and bandwidth given. Return 0 if register address not found. | |
405 | */ | |
406 | static u32 carl9170_def_val(u32 reg, bool is_2ghz, bool is_40mhz) | |
407 | { | |
408 | unsigned int i; | |
409 | for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) { | |
410 | if (ar5416_phy_init[i].reg != reg) | |
411 | continue; | |
412 | ||
413 | if (is_2ghz) { | |
414 | if (is_40mhz) | |
415 | return ar5416_phy_init[i]._2ghz_40; | |
416 | else | |
417 | return ar5416_phy_init[i]._2ghz_20; | |
418 | } else { | |
419 | if (is_40mhz) | |
420 | return ar5416_phy_init[i]._5ghz_40; | |
421 | else | |
422 | return ar5416_phy_init[i]._5ghz_20; | |
423 | } | |
424 | } | |
425 | return 0; | |
426 | } | |
427 | ||
428 | /* | |
429 | * initialize some phy regs from eeprom values in modal_header[] | |
25985edc | 430 | * acc. to band and bandwidth |
319da621 CL |
431 | */ |
432 | static int carl9170_init_phy_from_eeprom(struct ar9170 *ar, | |
433 | bool is_2ghz, bool is_40mhz) | |
434 | { | |
435 | static const u8 xpd2pd[16] = { | |
436 | 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, | |
437 | 0x2, 0x3, 0x7, 0x2, 0xb, 0x2, 0x2, 0x2 | |
438 | }; | |
439 | /* pointer to the modal_header acc. to band */ | |
440 | struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz]; | |
441 | u32 val; | |
442 | ||
443 | carl9170_regwrite_begin(ar); | |
444 | ||
445 | /* ant common control (index 0) */ | |
446 | carl9170_regwrite(AR9170_PHY_REG_SWITCH_COM, | |
447 | le32_to_cpu(m->antCtrlCommon)); | |
448 | ||
449 | /* ant control chain 0 (index 1) */ | |
450 | carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_0, | |
451 | le32_to_cpu(m->antCtrlChain[0])); | |
452 | ||
453 | /* ant control chain 2 (index 2) */ | |
454 | carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_2, | |
455 | le32_to_cpu(m->antCtrlChain[1])); | |
456 | ||
457 | /* SwSettle (index 3) */ | |
458 | if (!is_40mhz) { | |
459 | val = carl9170_def_val(AR9170_PHY_REG_SETTLING, | |
460 | is_2ghz, is_40mhz); | |
461 | SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling); | |
462 | carl9170_regwrite(AR9170_PHY_REG_SETTLING, val); | |
463 | } | |
464 | ||
465 | /* adcDesired, pdaDesired (index 4) */ | |
466 | val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz); | |
467 | SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize); | |
468 | SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize); | |
469 | carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val); | |
470 | ||
471 | /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */ | |
472 | val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz); | |
473 | SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff); | |
474 | SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff); | |
475 | SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn); | |
476 | SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn); | |
477 | carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val); | |
478 | ||
479 | /* TxEndToRxOn (index 6) */ | |
480 | val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz); | |
481 | SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn); | |
482 | carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val); | |
483 | ||
484 | /* thresh62 (index 7) */ | |
485 | val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz); | |
486 | val = (val & ~0x7f000) | (m->thresh62 << 12); | |
487 | carl9170_regwrite(0x1c8864, val); | |
488 | ||
489 | /* tx/rx attenuation chain 0 (index 8) */ | |
490 | val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz); | |
491 | SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]); | |
492 | carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val); | |
493 | ||
494 | /* tx/rx attenuation chain 2 (index 9) */ | |
495 | val = carl9170_def_val(AR9170_PHY_REG_RXGAIN_CHAIN_2, | |
496 | is_2ghz, is_40mhz); | |
497 | SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]); | |
498 | carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val); | |
499 | ||
500 | /* tx/rx margin chain 0 (index 10) */ | |
501 | val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz); | |
502 | SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]); | |
503 | /* bsw margin chain 0 for 5GHz only */ | |
504 | if (!is_2ghz) | |
505 | SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]); | |
506 | carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val); | |
507 | ||
508 | /* tx/rx margin chain 2 (index 11) */ | |
509 | val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, | |
510 | is_2ghz, is_40mhz); | |
511 | SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]); | |
512 | carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val); | |
513 | ||
514 | /* iqCall, iqCallq chain 0 (index 12) */ | |
515 | val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(0), | |
516 | is_2ghz, is_40mhz); | |
517 | SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]); | |
518 | SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]); | |
519 | carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val); | |
520 | ||
521 | /* iqCall, iqCallq chain 2 (index 13) */ | |
522 | val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(2), | |
523 | is_2ghz, is_40mhz); | |
524 | SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]); | |
525 | SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]); | |
526 | carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val); | |
527 | ||
528 | /* xpd gain mask (index 14) */ | |
529 | val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz); | |
530 | SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val, | |
531 | xpd2pd[m->xpdGain & 0xf] & 3); | |
532 | SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val, | |
533 | xpd2pd[m->xpdGain & 0xf] >> 2); | |
534 | carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val); | |
319da621 | 535 | |
9dec6f9c CL |
536 | carl9170_regwrite(AR9170_PHY_REG_RX_CHAINMASK, ar->eeprom.rx_mask); |
537 | carl9170_regwrite(AR9170_PHY_REG_CAL_CHAINMASK, ar->eeprom.rx_mask); | |
538 | ||
539 | carl9170_regwrite_finish(); | |
319da621 CL |
540 | return carl9170_regwrite_result(); |
541 | } | |
542 | ||
543 | static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band) | |
544 | { | |
545 | int i, err; | |
546 | u32 val; | |
547 | bool is_2ghz = band == IEEE80211_BAND_2GHZ; | |
548 | bool is_40mhz = conf_is_ht40(&ar->hw->conf); | |
549 | ||
550 | carl9170_regwrite_begin(ar); | |
551 | ||
552 | for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) { | |
553 | if (is_40mhz) { | |
554 | if (is_2ghz) | |
555 | val = ar5416_phy_init[i]._2ghz_40; | |
556 | else | |
557 | val = ar5416_phy_init[i]._5ghz_40; | |
558 | } else { | |
559 | if (is_2ghz) | |
560 | val = ar5416_phy_init[i]._2ghz_20; | |
561 | else | |
562 | val = ar5416_phy_init[i]._5ghz_20; | |
563 | } | |
564 | ||
565 | carl9170_regwrite(ar5416_phy_init[i].reg, val); | |
566 | } | |
567 | ||
568 | carl9170_regwrite_finish(); | |
569 | err = carl9170_regwrite_result(); | |
570 | if (err) | |
571 | return err; | |
572 | ||
573 | err = carl9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz); | |
574 | if (err) | |
575 | return err; | |
576 | ||
577 | err = carl9170_init_power_cal(ar); | |
578 | if (err) | |
579 | return err; | |
580 | ||
581 | /* XXX: remove magic! */ | |
582 | if (is_2ghz) | |
583 | err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163); | |
584 | else | |
585 | err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143); | |
586 | ||
587 | return err; | |
588 | } | |
589 | ||
590 | struct carl9170_rf_initvals { | |
591 | u32 reg, _5ghz, _2ghz; | |
592 | }; | |
593 | ||
594 | static struct carl9170_rf_initvals carl9170_rf_initval[] = { | |
595 | /* bank 0 */ | |
596 | { 0x1c58b0, 0x1e5795e5, 0x1e5795e5}, | |
597 | { 0x1c58e0, 0x02008020, 0x02008020}, | |
598 | /* bank 1 */ | |
599 | { 0x1c58b0, 0x02108421, 0x02108421}, | |
600 | { 0x1c58ec, 0x00000008, 0x00000008}, | |
601 | /* bank 2 */ | |
602 | { 0x1c58b0, 0x0e73ff17, 0x0e73ff17}, | |
603 | { 0x1c58e0, 0x00000420, 0x00000420}, | |
604 | /* bank 3 */ | |
605 | { 0x1c58f0, 0x01400018, 0x01c00018}, | |
606 | /* bank 4 */ | |
607 | { 0x1c58b0, 0x000001a1, 0x000001a1}, | |
608 | { 0x1c58e8, 0x00000001, 0x00000001}, | |
609 | /* bank 5 */ | |
610 | { 0x1c58b0, 0x00000013, 0x00000013}, | |
611 | { 0x1c58e4, 0x00000002, 0x00000002}, | |
612 | /* bank 6 */ | |
613 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
614 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
615 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
616 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
617 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
618 | { 0x1c58b0, 0x00004000, 0x00004000}, | |
619 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | |
620 | { 0x1c58b0, 0x00002c00, 0x00002c00}, | |
621 | { 0x1c58b0, 0x00004800, 0x00004800}, | |
622 | { 0x1c58b0, 0x00004000, 0x00004000}, | |
623 | { 0x1c58b0, 0x00006000, 0x00006000}, | |
624 | { 0x1c58b0, 0x00001000, 0x00001000}, | |
625 | { 0x1c58b0, 0x00004000, 0x00004000}, | |
626 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
627 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
628 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
629 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
630 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
631 | { 0x1c58b0, 0x00087c00, 0x00087c00}, | |
632 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
633 | { 0x1c58b0, 0x00005400, 0x00005400}, | |
634 | { 0x1c58b0, 0x00000c00, 0x00000c00}, | |
635 | { 0x1c58b0, 0x00001800, 0x00001800}, | |
636 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
637 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | |
638 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | |
639 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | |
640 | { 0x1c58b0, 0x00002c00, 0x00002c00}, | |
641 | { 0x1c58b0, 0x00003c00, 0x00003c00}, | |
642 | { 0x1c58b0, 0x00003800, 0x00003800}, | |
643 | { 0x1c58b0, 0x00001c00, 0x00001c00}, | |
644 | { 0x1c58b0, 0x00000800, 0x00000800}, | |
645 | { 0x1c58b0, 0x00000408, 0x00000408}, | |
646 | { 0x1c58b0, 0x00004c15, 0x00004c15}, | |
647 | { 0x1c58b0, 0x00004188, 0x00004188}, | |
648 | { 0x1c58b0, 0x0000201e, 0x0000201e}, | |
649 | { 0x1c58b0, 0x00010408, 0x00010408}, | |
650 | { 0x1c58b0, 0x00000801, 0x00000801}, | |
651 | { 0x1c58b0, 0x00000c08, 0x00000c08}, | |
652 | { 0x1c58b0, 0x0000181e, 0x0000181e}, | |
653 | { 0x1c58b0, 0x00001016, 0x00001016}, | |
654 | { 0x1c58b0, 0x00002800, 0x00002800}, | |
655 | { 0x1c58b0, 0x00004010, 0x00004010}, | |
656 | { 0x1c58b0, 0x0000081c, 0x0000081c}, | |
657 | { 0x1c58b0, 0x00000115, 0x00000115}, | |
658 | { 0x1c58b0, 0x00000015, 0x00000015}, | |
659 | { 0x1c58b0, 0x00000066, 0x00000066}, | |
660 | { 0x1c58b0, 0x0000001c, 0x0000001c}, | |
661 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
662 | { 0x1c58b0, 0x00000004, 0x00000004}, | |
663 | { 0x1c58b0, 0x00000015, 0x00000015}, | |
664 | { 0x1c58b0, 0x0000001f, 0x0000001f}, | |
665 | { 0x1c58e0, 0x00000000, 0x00000400}, | |
666 | /* bank 7 */ | |
667 | { 0x1c58b0, 0x000000a0, 0x000000a0}, | |
668 | { 0x1c58b0, 0x00000000, 0x00000000}, | |
669 | { 0x1c58b0, 0x00000040, 0x00000040}, | |
670 | { 0x1c58f0, 0x0000001c, 0x0000001c}, | |
671 | }; | |
672 | ||
673 | static int carl9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz) | |
674 | { | |
675 | int err, i; | |
676 | ||
677 | carl9170_regwrite_begin(ar); | |
678 | ||
679 | for (i = 0; i < ARRAY_SIZE(carl9170_rf_initval); i++) | |
680 | carl9170_regwrite(carl9170_rf_initval[i].reg, | |
681 | band5ghz ? carl9170_rf_initval[i]._5ghz | |
682 | : carl9170_rf_initval[i]._2ghz); | |
683 | ||
684 | carl9170_regwrite_finish(); | |
685 | err = carl9170_regwrite_result(); | |
686 | if (err) | |
687 | wiphy_err(ar->hw->wiphy, "rf init failed\n"); | |
688 | ||
689 | return err; | |
690 | } | |
691 | ||
692 | struct carl9170_phy_freq_params { | |
693 | u8 coeff_exp; | |
694 | u16 coeff_man; | |
695 | u8 coeff_exp_shgi; | |
696 | u16 coeff_man_shgi; | |
697 | }; | |
698 | ||
699 | enum carl9170_bw { | |
700 | CARL9170_BW_20, | |
701 | CARL9170_BW_40_BELOW, | |
702 | CARL9170_BW_40_ABOVE, | |
703 | ||
704 | __CARL9170_NUM_BW, | |
705 | }; | |
706 | ||
707 | struct carl9170_phy_freq_entry { | |
708 | u16 freq; | |
709 | struct carl9170_phy_freq_params params[__CARL9170_NUM_BW]; | |
710 | }; | |
711 | ||
712 | /* NB: must be in sync with channel tables in main! */ | |
713 | static const struct carl9170_phy_freq_entry carl9170_phy_freq_params[] = { | |
714 | /* | |
715 | * freq, | |
716 | * 20MHz, | |
717 | * 40MHz (below), | |
718 | * 40Mhz (above), | |
719 | */ | |
720 | { 2412, { | |
721 | { 3, 21737, 3, 19563, }, | |
722 | { 3, 21827, 3, 19644, }, | |
723 | { 3, 21647, 3, 19482, }, | |
724 | } }, | |
725 | { 2417, { | |
726 | { 3, 21692, 3, 19523, }, | |
727 | { 3, 21782, 3, 19604, }, | |
728 | { 3, 21602, 3, 19442, }, | |
729 | } }, | |
730 | { 2422, { | |
731 | { 3, 21647, 3, 19482, }, | |
732 | { 3, 21737, 3, 19563, }, | |
733 | { 3, 21558, 3, 19402, }, | |
734 | } }, | |
735 | { 2427, { | |
736 | { 3, 21602, 3, 19442, }, | |
737 | { 3, 21692, 3, 19523, }, | |
738 | { 3, 21514, 3, 19362, }, | |
739 | } }, | |
740 | { 2432, { | |
741 | { 3, 21558, 3, 19402, }, | |
742 | { 3, 21647, 3, 19482, }, | |
743 | { 3, 21470, 3, 19323, }, | |
744 | } }, | |
745 | { 2437, { | |
746 | { 3, 21514, 3, 19362, }, | |
747 | { 3, 21602, 3, 19442, }, | |
748 | { 3, 21426, 3, 19283, }, | |
749 | } }, | |
750 | { 2442, { | |
751 | { 3, 21470, 3, 19323, }, | |
752 | { 3, 21558, 3, 19402, }, | |
753 | { 3, 21382, 3, 19244, }, | |
754 | } }, | |
755 | { 2447, { | |
756 | { 3, 21426, 3, 19283, }, | |
757 | { 3, 21514, 3, 19362, }, | |
758 | { 3, 21339, 3, 19205, }, | |
759 | } }, | |
760 | { 2452, { | |
761 | { 3, 21382, 3, 19244, }, | |
762 | { 3, 21470, 3, 19323, }, | |
763 | { 3, 21295, 3, 19166, }, | |
764 | } }, | |
765 | { 2457, { | |
766 | { 3, 21339, 3, 19205, }, | |
767 | { 3, 21426, 3, 19283, }, | |
768 | { 3, 21252, 3, 19127, }, | |
769 | } }, | |
770 | { 2462, { | |
771 | { 3, 21295, 3, 19166, }, | |
772 | { 3, 21382, 3, 19244, }, | |
773 | { 3, 21209, 3, 19088, }, | |
774 | } }, | |
775 | { 2467, { | |
776 | { 3, 21252, 3, 19127, }, | |
777 | { 3, 21339, 3, 19205, }, | |
778 | { 3, 21166, 3, 19050, }, | |
779 | } }, | |
780 | { 2472, { | |
781 | { 3, 21209, 3, 19088, }, | |
782 | { 3, 21295, 3, 19166, }, | |
783 | { 3, 21124, 3, 19011, }, | |
784 | } }, | |
785 | { 2484, { | |
786 | { 3, 21107, 3, 18996, }, | |
787 | { 3, 21192, 3, 19073, }, | |
788 | { 3, 21022, 3, 18920, }, | |
789 | } }, | |
790 | { 4920, { | |
791 | { 4, 21313, 4, 19181, }, | |
792 | { 4, 21356, 4, 19220, }, | |
793 | { 4, 21269, 4, 19142, }, | |
794 | } }, | |
795 | { 4940, { | |
796 | { 4, 21226, 4, 19104, }, | |
797 | { 4, 21269, 4, 19142, }, | |
798 | { 4, 21183, 4, 19065, }, | |
799 | } }, | |
800 | { 4960, { | |
801 | { 4, 21141, 4, 19027, }, | |
802 | { 4, 21183, 4, 19065, }, | |
803 | { 4, 21098, 4, 18988, }, | |
804 | } }, | |
805 | { 4980, { | |
806 | { 4, 21056, 4, 18950, }, | |
807 | { 4, 21098, 4, 18988, }, | |
808 | { 4, 21014, 4, 18912, }, | |
809 | } }, | |
810 | { 5040, { | |
811 | { 4, 20805, 4, 18725, }, | |
812 | { 4, 20846, 4, 18762, }, | |
813 | { 4, 20764, 4, 18687, }, | |
814 | } }, | |
815 | { 5060, { | |
816 | { 4, 20723, 4, 18651, }, | |
817 | { 4, 20764, 4, 18687, }, | |
818 | { 4, 20682, 4, 18614, }, | |
819 | } }, | |
820 | { 5080, { | |
821 | { 4, 20641, 4, 18577, }, | |
822 | { 4, 20682, 4, 18614, }, | |
823 | { 4, 20601, 4, 18541, }, | |
824 | } }, | |
825 | { 5180, { | |
826 | { 4, 20243, 4, 18219, }, | |
827 | { 4, 20282, 4, 18254, }, | |
828 | { 4, 20204, 4, 18183, }, | |
829 | } }, | |
830 | { 5200, { | |
831 | { 4, 20165, 4, 18148, }, | |
832 | { 4, 20204, 4, 18183, }, | |
833 | { 4, 20126, 4, 18114, }, | |
834 | } }, | |
835 | { 5220, { | |
836 | { 4, 20088, 4, 18079, }, | |
837 | { 4, 20126, 4, 18114, }, | |
838 | { 4, 20049, 4, 18044, }, | |
839 | } }, | |
840 | { 5240, { | |
841 | { 4, 20011, 4, 18010, }, | |
842 | { 4, 20049, 4, 18044, }, | |
843 | { 4, 19973, 4, 17976, }, | |
844 | } }, | |
845 | { 5260, { | |
846 | { 4, 19935, 4, 17941, }, | |
847 | { 4, 19973, 4, 17976, }, | |
848 | { 4, 19897, 4, 17907, }, | |
849 | } }, | |
850 | { 5280, { | |
851 | { 4, 19859, 4, 17873, }, | |
852 | { 4, 19897, 4, 17907, }, | |
853 | { 4, 19822, 4, 17840, }, | |
854 | } }, | |
855 | { 5300, { | |
856 | { 4, 19784, 4, 17806, }, | |
857 | { 4, 19822, 4, 17840, }, | |
858 | { 4, 19747, 4, 17772, }, | |
859 | } }, | |
860 | { 5320, { | |
861 | { 4, 19710, 4, 17739, }, | |
862 | { 4, 19747, 4, 17772, }, | |
863 | { 4, 19673, 4, 17706, }, | |
864 | } }, | |
865 | { 5500, { | |
866 | { 4, 19065, 4, 17159, }, | |
867 | { 4, 19100, 4, 17190, }, | |
868 | { 4, 19030, 4, 17127, }, | |
869 | } }, | |
870 | { 5520, { | |
871 | { 4, 18996, 4, 17096, }, | |
872 | { 4, 19030, 4, 17127, }, | |
873 | { 4, 18962, 4, 17065, }, | |
874 | } }, | |
875 | { 5540, { | |
876 | { 4, 18927, 4, 17035, }, | |
877 | { 4, 18962, 4, 17065, }, | |
878 | { 4, 18893, 4, 17004, }, | |
879 | } }, | |
880 | { 5560, { | |
881 | { 4, 18859, 4, 16973, }, | |
882 | { 4, 18893, 4, 17004, }, | |
883 | { 4, 18825, 4, 16943, }, | |
884 | } }, | |
885 | { 5580, { | |
886 | { 4, 18792, 4, 16913, }, | |
887 | { 4, 18825, 4, 16943, }, | |
888 | { 4, 18758, 4, 16882, }, | |
889 | } }, | |
890 | { 5600, { | |
891 | { 4, 18725, 4, 16852, }, | |
892 | { 4, 18758, 4, 16882, }, | |
893 | { 4, 18691, 4, 16822, }, | |
894 | } }, | |
895 | { 5620, { | |
896 | { 4, 18658, 4, 16792, }, | |
897 | { 4, 18691, 4, 16822, }, | |
898 | { 4, 18625, 4, 16762, }, | |
899 | } }, | |
900 | { 5640, { | |
901 | { 4, 18592, 4, 16733, }, | |
902 | { 4, 18625, 4, 16762, }, | |
903 | { 4, 18559, 4, 16703, }, | |
904 | } }, | |
905 | { 5660, { | |
906 | { 4, 18526, 4, 16673, }, | |
907 | { 4, 18559, 4, 16703, }, | |
908 | { 4, 18493, 4, 16644, }, | |
909 | } }, | |
910 | { 5680, { | |
911 | { 4, 18461, 4, 16615, }, | |
912 | { 4, 18493, 4, 16644, }, | |
913 | { 4, 18428, 4, 16586, }, | |
914 | } }, | |
915 | { 5700, { | |
916 | { 4, 18396, 4, 16556, }, | |
917 | { 4, 18428, 4, 16586, }, | |
918 | { 4, 18364, 4, 16527, }, | |
919 | } }, | |
920 | { 5745, { | |
921 | { 4, 18252, 4, 16427, }, | |
922 | { 4, 18284, 4, 16455, }, | |
923 | { 4, 18220, 4, 16398, }, | |
924 | } }, | |
925 | { 5765, { | |
926 | { 4, 18189, 5, 32740, }, | |
927 | { 4, 18220, 4, 16398, }, | |
928 | { 4, 18157, 5, 32683, }, | |
929 | } }, | |
930 | { 5785, { | |
931 | { 4, 18126, 5, 32626, }, | |
932 | { 4, 18157, 5, 32683, }, | |
933 | { 4, 18094, 5, 32570, }, | |
934 | } }, | |
935 | { 5805, { | |
936 | { 4, 18063, 5, 32514, }, | |
937 | { 4, 18094, 5, 32570, }, | |
938 | { 4, 18032, 5, 32458, }, | |
939 | } }, | |
940 | { 5825, { | |
941 | { 4, 18001, 5, 32402, }, | |
942 | { 4, 18032, 5, 32458, }, | |
943 | { 4, 17970, 5, 32347, }, | |
944 | } }, | |
945 | { 5170, { | |
946 | { 4, 20282, 4, 18254, }, | |
947 | { 4, 20321, 4, 18289, }, | |
948 | { 4, 20243, 4, 18219, }, | |
949 | } }, | |
950 | { 5190, { | |
951 | { 4, 20204, 4, 18183, }, | |
952 | { 4, 20243, 4, 18219, }, | |
953 | { 4, 20165, 4, 18148, }, | |
954 | } }, | |
955 | { 5210, { | |
956 | { 4, 20126, 4, 18114, }, | |
957 | { 4, 20165, 4, 18148, }, | |
958 | { 4, 20088, 4, 18079, }, | |
959 | } }, | |
960 | { 5230, { | |
961 | { 4, 20049, 4, 18044, }, | |
962 | { 4, 20088, 4, 18079, }, | |
963 | { 4, 20011, 4, 18010, }, | |
964 | } }, | |
965 | }; | |
966 | ||
967 | static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, | |
968 | u32 freq, enum carl9170_bw bw) | |
969 | { | |
970 | int err; | |
971 | u32 d0, d1, td0, td1, fd0, fd1; | |
972 | u8 chansel; | |
973 | u8 refsel0 = 1, refsel1 = 0; | |
974 | u8 lf_synth = 0; | |
975 | ||
976 | switch (bw) { | |
977 | case CARL9170_BW_40_ABOVE: | |
978 | freq += 10; | |
979 | break; | |
980 | case CARL9170_BW_40_BELOW: | |
981 | freq -= 10; | |
982 | break; | |
983 | case CARL9170_BW_20: | |
984 | break; | |
985 | default: | |
986 | BUG(); | |
987 | return -ENOSYS; | |
988 | } | |
989 | ||
990 | if (band5ghz) { | |
991 | if (freq % 10) { | |
992 | chansel = (freq - 4800) / 5; | |
993 | } else { | |
994 | chansel = ((freq - 4800) / 10) * 2; | |
995 | refsel0 = 0; | |
996 | refsel1 = 1; | |
997 | } | |
998 | chansel = byte_rev_table[chansel]; | |
999 | } else { | |
1000 | if (freq == 2484) { | |
1001 | chansel = 10 + (freq - 2274) / 5; | |
1002 | lf_synth = 1; | |
1003 | } else | |
1004 | chansel = 16 + (freq - 2272) / 5; | |
1005 | chansel *= 4; | |
1006 | chansel = byte_rev_table[chansel]; | |
1007 | } | |
1008 | ||
1009 | d1 = chansel; | |
1010 | d0 = 0x21 | | |
1011 | refsel0 << 3 | | |
1012 | refsel1 << 2 | | |
1013 | lf_synth << 1; | |
1014 | td0 = d0 & 0x1f; | |
1015 | td1 = d1 & 0x1f; | |
1016 | fd0 = td1 << 5 | td0; | |
1017 | ||
1018 | td0 = (d0 >> 5) & 0x7; | |
1019 | td1 = (d1 >> 5) & 0x7; | |
1020 | fd1 = td1 << 5 | td0; | |
1021 | ||
1022 | carl9170_regwrite_begin(ar); | |
1023 | ||
1024 | carl9170_regwrite(0x1c58b0, fd0); | |
1025 | carl9170_regwrite(0x1c58e8, fd1); | |
1026 | ||
1027 | carl9170_regwrite_finish(); | |
1028 | err = carl9170_regwrite_result(); | |
1029 | if (err) | |
1030 | return err; | |
1031 | ||
319da621 CL |
1032 | return 0; |
1033 | } | |
1034 | ||
1035 | static const struct carl9170_phy_freq_params * | |
1036 | carl9170_get_hw_dyn_params(struct ieee80211_channel *channel, | |
1037 | enum carl9170_bw bw) | |
1038 | { | |
1039 | unsigned int chanidx = 0; | |
1040 | u16 freq = 2412; | |
1041 | ||
1042 | if (channel) { | |
1043 | chanidx = channel->hw_value; | |
1044 | freq = channel->center_freq; | |
1045 | } | |
1046 | ||
1047 | BUG_ON(chanidx >= ARRAY_SIZE(carl9170_phy_freq_params)); | |
1048 | ||
1049 | BUILD_BUG_ON(__CARL9170_NUM_BW != 3); | |
1050 | ||
1051 | WARN_ON(carl9170_phy_freq_params[chanidx].freq != freq); | |
1052 | ||
1053 | return &carl9170_phy_freq_params[chanidx].params[bw]; | |
1054 | } | |
1055 | ||
1056 | static int carl9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f) | |
1057 | { | |
1058 | int idx = nfreqs - 2; | |
1059 | ||
1060 | while (idx >= 0) { | |
1061 | if (f >= freqs[idx]) | |
1062 | return idx; | |
1063 | idx--; | |
1064 | } | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static s32 carl9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) | |
1070 | { | |
1071 | /* nothing to interpolate, it's horizontal */ | |
1072 | if (y2 == y1) | |
1073 | return y1; | |
1074 | ||
1075 | /* check if we hit one of the edges */ | |
1076 | if (x == x1) | |
1077 | return y1; | |
1078 | if (x == x2) | |
1079 | return y2; | |
1080 | ||
1081 | /* x1 == x2 is bad, hopefully == x */ | |
1082 | if (x2 == x1) | |
1083 | return y1; | |
1084 | ||
1085 | return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1)); | |
1086 | } | |
1087 | ||
1088 | static u8 carl9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2) | |
1089 | { | |
1090 | #define SHIFT 8 | |
1091 | s32 y; | |
1092 | ||
1093 | y = carl9170_interpolate_s32(x << SHIFT, x1 << SHIFT, | |
1094 | y1 << SHIFT, x2 << SHIFT, y2 << SHIFT); | |
1095 | ||
1096 | /* | |
1097 | * XXX: unwrap this expression | |
1098 | * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)? | |
1099 | * Can we rely on the compiler to optimise away the div? | |
1100 | */ | |
1101 | return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1)); | |
1102 | #undef SHIFT | |
1103 | } | |
1104 | ||
1105 | static u8 carl9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array) | |
1106 | { | |
1107 | int i; | |
1108 | ||
1109 | for (i = 0; i < 3; i++) { | |
1110 | if (x <= x_array[i + 1]) | |
1111 | break; | |
1112 | } | |
1113 | ||
1114 | return carl9170_interpolate_u8(x, x_array[i], y_array[i], | |
1115 | x_array[i + 1], y_array[i + 1]); | |
1116 | } | |
1117 | ||
1118 | static int carl9170_set_freq_cal_data(struct ar9170 *ar, | |
1119 | struct ieee80211_channel *channel) | |
1120 | { | |
1121 | u8 *cal_freq_pier; | |
1122 | u8 vpds[2][AR5416_PD_GAIN_ICEPTS]; | |
1123 | u8 pwrs[2][AR5416_PD_GAIN_ICEPTS]; | |
1124 | int chain, idx, i; | |
1125 | u32 phy_data = 0; | |
1126 | u8 f, tmp; | |
1127 | ||
1128 | switch (channel->band) { | |
1129 | case IEEE80211_BAND_2GHZ: | |
1130 | f = channel->center_freq - 2300; | |
1131 | cal_freq_pier = ar->eeprom.cal_freq_pier_2G; | |
1132 | i = AR5416_NUM_2G_CAL_PIERS - 1; | |
1133 | break; | |
1134 | ||
1135 | case IEEE80211_BAND_5GHZ: | |
1136 | f = (channel->center_freq - 4800) / 5; | |
1137 | cal_freq_pier = ar->eeprom.cal_freq_pier_5G; | |
1138 | i = AR5416_NUM_5G_CAL_PIERS - 1; | |
1139 | break; | |
1140 | ||
1141 | default: | |
1142 | return -EINVAL; | |
1143 | break; | |
1144 | } | |
1145 | ||
1146 | for (; i >= 0; i--) { | |
1147 | if (cal_freq_pier[i] != 0xff) | |
1148 | break; | |
1149 | } | |
1150 | if (i < 0) | |
1151 | return -EINVAL; | |
1152 | ||
1153 | idx = carl9170_find_freq_idx(i, cal_freq_pier, f); | |
1154 | ||
1155 | carl9170_regwrite_begin(ar); | |
1156 | ||
1157 | for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) { | |
1158 | for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) { | |
1159 | struct ar9170_calibration_data_per_freq *cal_pier_data; | |
1160 | int j; | |
1161 | ||
1162 | switch (channel->band) { | |
1163 | case IEEE80211_BAND_2GHZ: | |
1164 | cal_pier_data = &ar->eeprom. | |
1165 | cal_pier_data_2G[chain][idx]; | |
1166 | break; | |
1167 | ||
1168 | case IEEE80211_BAND_5GHZ: | |
1169 | cal_pier_data = &ar->eeprom. | |
1170 | cal_pier_data_5G[chain][idx]; | |
1171 | break; | |
1172 | ||
1173 | default: | |
1174 | return -EINVAL; | |
1175 | } | |
1176 | ||
1177 | for (j = 0; j < 2; j++) { | |
1178 | vpds[j][i] = carl9170_interpolate_u8(f, | |
1179 | cal_freq_pier[idx], | |
1180 | cal_pier_data->vpd_pdg[j][i], | |
1181 | cal_freq_pier[idx + 1], | |
1182 | cal_pier_data[1].vpd_pdg[j][i]); | |
1183 | ||
1184 | pwrs[j][i] = carl9170_interpolate_u8(f, | |
1185 | cal_freq_pier[idx], | |
1186 | cal_pier_data->pwr_pdg[j][i], | |
1187 | cal_freq_pier[idx + 1], | |
1188 | cal_pier_data[1].pwr_pdg[j][i]) / 2; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | for (i = 0; i < 76; i++) { | |
1193 | if (i < 25) { | |
1194 | tmp = carl9170_interpolate_val(i, &pwrs[0][0], | |
1195 | &vpds[0][0]); | |
1196 | } else { | |
1197 | tmp = carl9170_interpolate_val(i - 12, | |
1198 | &pwrs[1][0], | |
1199 | &vpds[1][0]); | |
1200 | } | |
1201 | ||
1202 | phy_data |= tmp << ((i & 3) << 3); | |
1203 | if ((i & 3) == 3) { | |
1204 | carl9170_regwrite(0x1c6280 + chain * 0x1000 + | |
1205 | (i & ~3), phy_data); | |
1206 | phy_data = 0; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | for (i = 19; i < 32; i++) | |
1211 | carl9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2), | |
1212 | 0x0); | |
1213 | } | |
1214 | ||
1215 | carl9170_regwrite_finish(); | |
1216 | return carl9170_regwrite_result(); | |
1217 | } | |
1218 | ||
1219 | static u8 carl9170_get_max_edge_power(struct ar9170 *ar, | |
1220 | u32 freq, struct ar9170_calctl_edges edges[]) | |
1221 | { | |
1222 | int i; | |
1223 | u8 rc = AR5416_MAX_RATE_POWER; | |
1224 | u8 f; | |
1225 | if (freq < 3000) | |
1226 | f = freq - 2300; | |
1227 | else | |
1228 | f = (freq - 4800) / 5; | |
1229 | ||
1230 | for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) { | |
1231 | if (edges[i].channel == 0xff) | |
1232 | break; | |
1233 | if (f == edges[i].channel) { | |
1234 | /* exact freq match */ | |
1235 | rc = edges[i].power_flags & ~AR9170_CALCTL_EDGE_FLAGS; | |
1236 | break; | |
1237 | } | |
1238 | if (i > 0 && f < edges[i].channel) { | |
1239 | if (f > edges[i - 1].channel && | |
1240 | edges[i - 1].power_flags & | |
1241 | AR9170_CALCTL_EDGE_FLAGS) { | |
1242 | /* lower channel has the inband flag set */ | |
1243 | rc = edges[i - 1].power_flags & | |
1244 | ~AR9170_CALCTL_EDGE_FLAGS; | |
1245 | } | |
1246 | break; | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | if (i == AR5416_NUM_BAND_EDGES) { | |
1251 | if (f > edges[i - 1].channel && | |
1252 | edges[i - 1].power_flags & AR9170_CALCTL_EDGE_FLAGS) { | |
1253 | /* lower channel has the inband flag set */ | |
1254 | rc = edges[i - 1].power_flags & | |
1255 | ~AR9170_CALCTL_EDGE_FLAGS; | |
1256 | } | |
1257 | } | |
1258 | return rc; | |
1259 | } | |
1260 | ||
1261 | static u8 carl9170_get_heavy_clip(struct ar9170 *ar, u32 freq, | |
1262 | enum carl9170_bw bw, struct ar9170_calctl_edges edges[]) | |
1263 | { | |
1264 | u8 f; | |
1265 | int i; | |
1266 | u8 rc = 0; | |
1267 | ||
1268 | if (freq < 3000) | |
1269 | f = freq - 2300; | |
1270 | else | |
1271 | f = (freq - 4800) / 5; | |
1272 | ||
1273 | if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE) | |
1274 | rc |= 0xf0; | |
1275 | ||
1276 | for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) { | |
1277 | if (edges[i].channel == 0xff) | |
1278 | break; | |
1279 | if (f == edges[i].channel) { | |
1280 | if (!(edges[i].power_flags & AR9170_CALCTL_EDGE_FLAGS)) | |
1281 | rc |= 0x0f; | |
1282 | break; | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | return rc; | |
1287 | } | |
1288 | ||
1289 | /* | |
1290 | * calculate the conformance test limits and the heavy clip parameter | |
1291 | * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706) | |
1292 | */ | |
1293 | static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw) | |
1294 | { | |
1295 | u8 ctl_grp; /* CTL group */ | |
1296 | u8 ctl_idx; /* CTL index */ | |
1297 | int i, j; | |
1298 | struct ctl_modes { | |
1299 | u8 ctl_mode; | |
1300 | u8 max_power; | |
1301 | u8 *pwr_cal_data; | |
1302 | int pwr_cal_len; | |
1303 | } *modes; | |
1304 | ||
1305 | /* | |
1306 | * order is relevant in the mode_list_*: we fall back to the | |
1307 | * lower indices if any mode is missed in the EEPROM. | |
1308 | */ | |
1309 | struct ctl_modes mode_list_2ghz[] = { | |
1310 | { CTL_11B, 0, ar->power_2G_cck, 4 }, | |
1311 | { CTL_11G, 0, ar->power_2G_ofdm, 4 }, | |
1312 | { CTL_2GHT20, 0, ar->power_2G_ht20, 8 }, | |
1313 | { CTL_2GHT40, 0, ar->power_2G_ht40, 8 }, | |
1314 | }; | |
1315 | struct ctl_modes mode_list_5ghz[] = { | |
1316 | { CTL_11A, 0, ar->power_5G_leg, 4 }, | |
1317 | { CTL_5GHT20, 0, ar->power_5G_ht20, 8 }, | |
1318 | { CTL_5GHT40, 0, ar->power_5G_ht40, 8 }, | |
1319 | }; | |
1320 | int nr_modes; | |
1321 | ||
1322 | #define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n]) | |
1323 | ||
1324 | ar->heavy_clip = 0; | |
1325 | ||
1326 | /* | |
1327 | * TODO: investigate the differences between OTUS' | |
1328 | * hpreg.c::zfHpGetRegulatoryDomain() and | |
1329 | * ath/regd.c::ath_regd_get_band_ctl() - | |
1330 | * e.g. for FCC3_WORLD the OTUS procedure | |
1331 | * always returns CTL_FCC, while the one in ath/ delivers | |
1332 | * CTL_ETSI for 2GHz and CTL_FCC for 5GHz. | |
1333 | */ | |
1334 | ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory, | |
1335 | ar->hw->conf.channel->band); | |
1336 | ||
1337 | /* ctl group not found - either invalid band (NO_CTL) or ww roaming */ | |
1338 | if (ctl_grp == NO_CTL || ctl_grp == SD_NO_CTL) | |
1339 | ctl_grp = CTL_FCC; | |
1340 | ||
1341 | if (ctl_grp != CTL_FCC) | |
1342 | /* skip CTL and heavy clip for CTL_MKK and CTL_ETSI */ | |
1343 | return; | |
1344 | ||
1345 | if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) { | |
1346 | modes = mode_list_2ghz; | |
1347 | nr_modes = ARRAY_SIZE(mode_list_2ghz); | |
1348 | } else { | |
1349 | modes = mode_list_5ghz; | |
1350 | nr_modes = ARRAY_SIZE(mode_list_5ghz); | |
1351 | } | |
1352 | ||
1353 | for (i = 0; i < nr_modes; i++) { | |
1354 | u8 c = ctl_grp | modes[i].ctl_mode; | |
1355 | for (ctl_idx = 0; ctl_idx < AR5416_NUM_CTLS; ctl_idx++) | |
1356 | if (c == ar->eeprom.ctl_index[ctl_idx]) | |
1357 | break; | |
1358 | if (ctl_idx < AR5416_NUM_CTLS) { | |
1359 | int f_off = 0; | |
1360 | ||
1361 | /* | |
1362 | * determine heavy clip parameter | |
1363 | * from the 11G edges array | |
1364 | */ | |
1365 | if (modes[i].ctl_mode == CTL_11G) { | |
1366 | ar->heavy_clip = | |
1367 | carl9170_get_heavy_clip(ar, | |
1368 | freq, bw, EDGES(ctl_idx, 1)); | |
1369 | } | |
1370 | ||
1371 | /* adjust freq for 40MHz */ | |
1372 | if (modes[i].ctl_mode == CTL_2GHT40 || | |
1373 | modes[i].ctl_mode == CTL_5GHT40) { | |
1374 | if (bw == CARL9170_BW_40_BELOW) | |
1375 | f_off = -10; | |
1376 | else | |
1377 | f_off = 10; | |
1378 | } | |
1379 | ||
1380 | modes[i].max_power = | |
1381 | carl9170_get_max_edge_power(ar, | |
1382 | freq+f_off, EDGES(ctl_idx, 1)); | |
1383 | ||
1384 | /* | |
1385 | * TODO: check if the regulatory max. power is | |
1386 | * controlled by cfg80211 for DFS. | |
1387 | * (hpmain applies it to max_power itself for DFS freq) | |
1388 | */ | |
1389 | ||
1390 | } else { | |
1391 | /* | |
1392 | * Workaround in otus driver, hpmain.c, line 3906: | |
1393 | * if no data for 5GHT20 are found, take the | |
1394 | * legacy 5G value. We extend this here to fallback | |
1395 | * from any other HT* or 11G, too. | |
1396 | */ | |
1397 | int k = i; | |
1398 | ||
1399 | modes[i].max_power = AR5416_MAX_RATE_POWER; | |
1400 | while (k-- > 0) { | |
1401 | if (modes[k].max_power != | |
1402 | AR5416_MAX_RATE_POWER) { | |
1403 | modes[i].max_power = modes[k].max_power; | |
1404 | break; | |
1405 | } | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | /* apply max power to pwr_cal_data (ar->power_*) */ | |
1410 | for (j = 0; j < modes[i].pwr_cal_len; j++) { | |
1411 | modes[i].pwr_cal_data[j] = min(modes[i].pwr_cal_data[j], | |
1412 | modes[i].max_power); | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | if (ar->heavy_clip & 0xf0) { | |
1417 | ar->power_2G_ht40[0]--; | |
1418 | ar->power_2G_ht40[1]--; | |
1419 | ar->power_2G_ht40[2]--; | |
1420 | } | |
1421 | if (ar->heavy_clip & 0xf) { | |
1422 | ar->power_2G_ht20[0]++; | |
1423 | ar->power_2G_ht20[1]++; | |
1424 | ar->power_2G_ht20[2]++; | |
1425 | } | |
1426 | ||
1427 | #undef EDGES | |
1428 | } | |
1429 | ||
1430 | static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq, | |
1431 | enum carl9170_bw bw) | |
1432 | { | |
1433 | struct ar9170_calibration_target_power_legacy *ctpl; | |
1434 | struct ar9170_calibration_target_power_ht *ctph; | |
1435 | u8 *ctpres; | |
1436 | int ntargets; | |
1437 | int idx, i, n; | |
1438 | u8 ackpower, ackchains, f; | |
1439 | u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS]; | |
1440 | ||
1441 | if (freq < 3000) | |
1442 | f = freq - 2300; | |
1443 | else | |
1444 | f = (freq - 4800)/5; | |
1445 | ||
1446 | /* | |
1447 | * cycle through the various modes | |
1448 | * | |
1449 | * legacy modes first: 5G, 2G CCK, 2G OFDM | |
1450 | */ | |
1451 | for (i = 0; i < 3; i++) { | |
1452 | switch (i) { | |
1453 | case 0: /* 5 GHz legacy */ | |
1454 | ctpl = &ar->eeprom.cal_tgt_pwr_5G[0]; | |
1455 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | |
1456 | ctpres = ar->power_5G_leg; | |
1457 | break; | |
1458 | case 1: /* 2.4 GHz CCK */ | |
1459 | ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0]; | |
1460 | ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS; | |
1461 | ctpres = ar->power_2G_cck; | |
1462 | break; | |
1463 | case 2: /* 2.4 GHz OFDM */ | |
1464 | ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0]; | |
1465 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | |
1466 | ctpres = ar->power_2G_ofdm; | |
1467 | break; | |
1468 | default: | |
1469 | BUG(); | |
1470 | } | |
1471 | ||
1472 | for (n = 0; n < ntargets; n++) { | |
1473 | if (ctpl[n].freq == 0xff) | |
1474 | break; | |
1475 | pwr_freqs[n] = ctpl[n].freq; | |
1476 | } | |
1477 | ntargets = n; | |
1478 | idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f); | |
1479 | for (n = 0; n < 4; n++) | |
1480 | ctpres[n] = carl9170_interpolate_u8(f, | |
1481 | ctpl[idx + 0].freq, ctpl[idx + 0].power[n], | |
1482 | ctpl[idx + 1].freq, ctpl[idx + 1].power[n]); | |
1483 | } | |
1484 | ||
1485 | /* HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40 */ | |
1486 | for (i = 0; i < 4; i++) { | |
1487 | switch (i) { | |
1488 | case 0: /* 5 GHz HT 20 */ | |
1489 | ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0]; | |
1490 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | |
1491 | ctpres = ar->power_5G_ht20; | |
1492 | break; | |
1493 | case 1: /* 5 GHz HT 40 */ | |
1494 | ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0]; | |
1495 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | |
1496 | ctpres = ar->power_5G_ht40; | |
1497 | break; | |
1498 | case 2: /* 2.4 GHz HT 20 */ | |
1499 | ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0]; | |
1500 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | |
1501 | ctpres = ar->power_2G_ht20; | |
1502 | break; | |
1503 | case 3: /* 2.4 GHz HT 40 */ | |
1504 | ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0]; | |
1505 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | |
1506 | ctpres = ar->power_2G_ht40; | |
1507 | break; | |
1508 | default: | |
1509 | BUG(); | |
1510 | } | |
1511 | ||
1512 | for (n = 0; n < ntargets; n++) { | |
1513 | if (ctph[n].freq == 0xff) | |
1514 | break; | |
1515 | pwr_freqs[n] = ctph[n].freq; | |
1516 | } | |
1517 | ntargets = n; | |
1518 | idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f); | |
1519 | for (n = 0; n < 8; n++) | |
1520 | ctpres[n] = carl9170_interpolate_u8(f, | |
1521 | ctph[idx + 0].freq, ctph[idx + 0].power[n], | |
1522 | ctph[idx + 1].freq, ctph[idx + 1].power[n]); | |
1523 | } | |
1524 | ||
1525 | /* calc. conformance test limits and apply to ar->power*[] */ | |
1526 | carl9170_calc_ctl(ar, freq, bw); | |
1527 | ||
1528 | /* set ACK/CTS TX power */ | |
1529 | carl9170_regwrite_begin(ar); | |
1530 | ||
1531 | if (ar->eeprom.tx_mask != 1) | |
1532 | ackchains = AR9170_TX_PHY_TXCHAIN_2; | |
1533 | else | |
1534 | ackchains = AR9170_TX_PHY_TXCHAIN_1; | |
1535 | ||
1536 | if (freq < 3000) | |
1537 | ackpower = ar->power_2G_ofdm[0] & 0x3f; | |
1538 | else | |
1539 | ackpower = ar->power_5G_leg[0] & 0x3f; | |
1540 | ||
1541 | carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, | |
1542 | 0x3c1e | ackpower << 20 | ackchains << 26); | |
1543 | carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC, | |
1544 | ackpower << 5 | ackchains << 11 | | |
1545 | ackpower << 21 | ackchains << 27); | |
1546 | ||
1547 | carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC, | |
1548 | ackpower << 5 | ackchains << 11 | | |
1549 | ackpower << 21 | ackchains << 27); | |
1550 | ||
1551 | carl9170_regwrite_finish(); | |
1552 | return carl9170_regwrite_result(); | |
1553 | } | |
1554 | ||
319da621 CL |
1555 | int carl9170_get_noisefloor(struct ar9170 *ar) |
1556 | { | |
1557 | static const u32 phy_regs[] = { | |
9adc9e0f CL |
1558 | AR9170_PHY_REG_CCA, AR9170_PHY_REG_CH2_CCA, |
1559 | AR9170_PHY_REG_EXT_CCA, AR9170_PHY_REG_CH2_EXT_CCA }; | |
319da621 CL |
1560 | u32 phy_res[ARRAY_SIZE(phy_regs)]; |
1561 | int err, i; | |
1562 | ||
1563 | BUILD_BUG_ON(ARRAY_SIZE(phy_regs) != ARRAY_SIZE(ar->noise)); | |
1564 | ||
1565 | err = carl9170_read_mreg(ar, ARRAY_SIZE(phy_regs), phy_regs, phy_res); | |
1566 | if (err) | |
1567 | return err; | |
1568 | ||
9adc9e0f | 1569 | for (i = 0; i < 2; i++) { |
b1d771ee CL |
1570 | ar->noise[i] = sign_extend32(GET_VAL( |
1571 | AR9170_PHY_CCA_MIN_PWR, phy_res[i]), 8); | |
319da621 | 1572 | |
b1d771ee CL |
1573 | ar->noise[i + 2] = sign_extend32(GET_VAL( |
1574 | AR9170_PHY_EXT_CCA_MIN_PWR, phy_res[i + 2]), 8); | |
319da621 CL |
1575 | } |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
1580 | static enum carl9170_bw nl80211_to_carl(enum nl80211_channel_type type) | |
1581 | { | |
1582 | switch (type) { | |
1583 | case NL80211_CHAN_NO_HT: | |
1584 | case NL80211_CHAN_HT20: | |
1585 | return CARL9170_BW_20; | |
1586 | case NL80211_CHAN_HT40MINUS: | |
1587 | return CARL9170_BW_40_BELOW; | |
1588 | case NL80211_CHAN_HT40PLUS: | |
1589 | return CARL9170_BW_40_ABOVE; | |
1590 | default: | |
1591 | BUG(); | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel, | |
1596 | enum nl80211_channel_type _bw, | |
1597 | enum carl9170_rf_init_mode rfi) | |
1598 | { | |
1599 | const struct carl9170_phy_freq_params *freqpar; | |
1600 | struct carl9170_rf_init_result rf_res; | |
1601 | struct carl9170_rf_init rf; | |
73576110 | 1602 | u32 cmd, tmp, offs = 0, new_ht = 0; |
319da621 CL |
1603 | int err; |
1604 | enum carl9170_bw bw; | |
1605 | bool warm_reset; | |
1606 | struct ieee80211_channel *old_channel = NULL; | |
1607 | ||
1608 | bw = nl80211_to_carl(_bw); | |
1609 | ||
73576110 CL |
1610 | if (conf_is_ht(&ar->hw->conf)) |
1611 | new_ht |= CARL9170FW_PHY_HT_ENABLE; | |
1612 | ||
1613 | if (conf_is_ht40(&ar->hw->conf)) | |
1614 | new_ht |= CARL9170FW_PHY_HT_DYN2040; | |
1615 | ||
319da621 CL |
1616 | /* may be NULL at first setup */ |
1617 | if (ar->channel) { | |
1618 | old_channel = ar->channel; | |
1619 | warm_reset = (old_channel->band != channel->band) || | |
1620 | (old_channel->center_freq == | |
73576110 CL |
1621 | channel->center_freq) || |
1622 | (ar->ht_settings != new_ht); | |
319da621 CL |
1623 | |
1624 | ar->channel = NULL; | |
1625 | } else { | |
1626 | warm_reset = true; | |
1627 | } | |
1628 | ||
1629 | /* HW workaround */ | |
1630 | if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] && | |
1631 | channel->center_freq <= 2417) | |
1632 | warm_reset = true; | |
1633 | ||
1634 | if (rfi != CARL9170_RFI_NONE || warm_reset) { | |
1635 | u32 val; | |
1636 | ||
1637 | if (rfi == CARL9170_RFI_COLD) | |
1638 | val = AR9170_PWR_RESET_BB_COLD_RESET; | |
1639 | else | |
1640 | val = AR9170_PWR_RESET_BB_WARM_RESET; | |
1641 | ||
1642 | /* warm/cold reset BB/ADDA */ | |
1643 | err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, val); | |
1644 | if (err) | |
1645 | return err; | |
1646 | ||
1647 | err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, 0x0); | |
1648 | if (err) | |
1649 | return err; | |
1650 | ||
1651 | err = carl9170_init_phy(ar, channel->band); | |
1652 | if (err) | |
1653 | return err; | |
1654 | ||
1655 | err = carl9170_init_rf_banks_0_7(ar, | |
1656 | channel->band == IEEE80211_BAND_5GHZ); | |
1657 | if (err) | |
1658 | return err; | |
1659 | ||
1660 | cmd = CARL9170_CMD_RF_INIT; | |
319da621 CL |
1661 | } else { |
1662 | cmd = CARL9170_CMD_FREQUENCY; | |
1663 | } | |
1664 | ||
1665 | err = carl9170_exec_cmd(ar, CARL9170_CMD_FREQ_START, 0, NULL, 0, NULL); | |
1666 | if (err) | |
1667 | return err; | |
1668 | ||
1669 | err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE, | |
1670 | 0x200); | |
c9e57f0f CL |
1671 | if (err) |
1672 | return err; | |
319da621 CL |
1673 | |
1674 | err = carl9170_init_rf_bank4_pwr(ar, | |
1675 | channel->band == IEEE80211_BAND_5GHZ, | |
1676 | channel->center_freq, bw); | |
1677 | if (err) | |
1678 | return err; | |
1679 | ||
1680 | tmp = AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 | | |
1681 | AR9170_PHY_TURBO_FC_HT_EN; | |
1682 | ||
1683 | switch (bw) { | |
1684 | case CARL9170_BW_20: | |
1685 | break; | |
1686 | case CARL9170_BW_40_BELOW: | |
1687 | tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN | | |
1688 | AR9170_PHY_TURBO_FC_SHORT_GI_40; | |
1689 | offs = 3; | |
1690 | break; | |
1691 | case CARL9170_BW_40_ABOVE: | |
1692 | tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN | | |
1693 | AR9170_PHY_TURBO_FC_SHORT_GI_40 | | |
1694 | AR9170_PHY_TURBO_FC_DYN2040_PRI_CH; | |
1695 | offs = 1; | |
1696 | break; | |
1697 | default: | |
1698 | BUG(); | |
1699 | return -ENOSYS; | |
1700 | } | |
1701 | ||
1702 | if (ar->eeprom.tx_mask != 1) | |
1703 | tmp |= AR9170_PHY_TURBO_FC_WALSH; | |
1704 | ||
1705 | err = carl9170_write_reg(ar, AR9170_PHY_REG_TURBO, tmp); | |
1706 | if (err) | |
1707 | return err; | |
1708 | ||
1709 | err = carl9170_set_freq_cal_data(ar, channel); | |
1710 | if (err) | |
1711 | return err; | |
1712 | ||
1713 | err = carl9170_set_power_cal(ar, channel->center_freq, bw); | |
1714 | if (err) | |
1715 | return err; | |
1716 | ||
1717 | freqpar = carl9170_get_hw_dyn_params(channel, bw); | |
1718 | ||
73576110 CL |
1719 | rf.ht_settings = new_ht; |
1720 | if (conf_is_ht40(&ar->hw->conf)) | |
1721 | SET_VAL(CARL9170FW_PHY_HT_EXT_CHAN_OFF, rf.ht_settings, offs); | |
319da621 CL |
1722 | |
1723 | rf.freq = cpu_to_le32(channel->center_freq * 1000); | |
1724 | rf.delta_slope_coeff_exp = cpu_to_le32(freqpar->coeff_exp); | |
1725 | rf.delta_slope_coeff_man = cpu_to_le32(freqpar->coeff_man); | |
1726 | rf.delta_slope_coeff_exp_shgi = cpu_to_le32(freqpar->coeff_exp_shgi); | |
1727 | rf.delta_slope_coeff_man_shgi = cpu_to_le32(freqpar->coeff_man_shgi); | |
1728 | ||
1729 | if (rfi != CARL9170_RFI_NONE) | |
1730 | rf.finiteLoopCount = cpu_to_le32(2000); | |
1731 | else | |
1732 | rf.finiteLoopCount = cpu_to_le32(1000); | |
1733 | ||
1734 | err = carl9170_exec_cmd(ar, cmd, sizeof(rf), &rf, | |
1735 | sizeof(rf_res), &rf_res); | |
1736 | if (err) | |
1737 | return err; | |
1738 | ||
1739 | err = le32_to_cpu(rf_res.ret); | |
1740 | if (err != 0) { | |
1741 | ar->chan_fail++; | |
1742 | ar->total_chan_fail++; | |
1743 | ||
1744 | wiphy_err(ar->hw->wiphy, "channel change: %d -> %d " | |
1745 | "failed (%d).\n", old_channel ? | |
1746 | old_channel->center_freq : -1, channel->center_freq, | |
1747 | err); | |
1748 | ||
1749 | if ((rfi == CARL9170_RFI_COLD) || (ar->chan_fail > 3)) { | |
1750 | /* | |
1751 | * We have tried very hard to change to _another_ | |
1752 | * channel and we've failed to do so! | |
1753 | * Chances are that the PHY/RF is no longer | |
1754 | * operable (due to corruptions/fatal events/bugs?) | |
1755 | * and we need to reset at a higher level. | |
1756 | */ | |
1757 | carl9170_restart(ar, CARL9170_RR_TOO_MANY_PHY_ERRORS); | |
1758 | return 0; | |
1759 | } | |
1760 | ||
1761 | err = carl9170_set_channel(ar, channel, _bw, | |
1762 | CARL9170_RFI_COLD); | |
1763 | if (err) | |
1764 | return err; | |
1765 | } else { | |
1766 | ar->chan_fail = 0; | |
1767 | } | |
1768 | ||
1769 | err = carl9170_get_noisefloor(ar); | |
1770 | if (err) | |
1771 | return err; | |
1772 | ||
1773 | if (ar->heavy_clip) { | |
1774 | err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE, | |
1775 | 0x200 | ar->heavy_clip); | |
1776 | if (err) { | |
1777 | if (net_ratelimit()) { | |
1778 | wiphy_err(ar->hw->wiphy, "failed to set " | |
1779 | "heavy clip\n"); | |
1780 | } | |
1781 | ||
1782 | return err; | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | /* FIXME: PSM does not work in 5GHz Band */ | |
1787 | if (channel->band == IEEE80211_BAND_5GHZ) | |
1788 | ar->ps.off_override |= PS_OFF_5GHZ; | |
1789 | else | |
1790 | ar->ps.off_override &= ~PS_OFF_5GHZ; | |
1791 | ||
1792 | ar->channel = channel; | |
73576110 | 1793 | ar->ht_settings = new_ht; |
319da621 CL |
1794 | return 0; |
1795 | } |