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iwlwifi: earlier rx allocation
[people/ms/linux.git] / drivers / net / wireless / b43legacy / dma.c
CommitLineData
75388acd
LF		 1/*
2
3 Broadcom B43legacy wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43legacy.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
40#include <net/dst.h>
41
42/* 32bit DMA ops. */
43static
44struct b43legacy_dmadesc_generic *op32_idx2desc(
45 struct b43legacy_dmaring *ring,
46 int slot,
47 struct b43legacy_dmadesc_meta **meta)
48{
49 struct b43legacy_dmadesc32 *desc;
50
51 *meta = &(ring->meta[slot]);
52 desc = ring->descbase;
53 desc = &(desc[slot]);
54
55 return (struct b43legacy_dmadesc_generic *)desc;
56}
57
58static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59 struct b43legacy_dmadesc_generic *desc,
60 dma_addr_t dmaaddr, u16 bufsize,
61 int start, int end, int irq)
62{
63 struct b43legacy_dmadesc32 *descbase = ring->descbase;
64 int slot;
65 u32 ctl;
66 u32 addr;
67 u32 addrext;
68
69 slot = (int)(&(desc->dma32) - descbase);
70 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74 >> SSB_DMA_TRANSLATION_SHIFT;
75 addr |= ssb_dma_translation(ring->dev->dev);
76 ctl = (bufsize - ring->frameoffset)
77 & B43legacy_DMA32_DCTL_BYTECNT;
78 if (slot == ring->nr_slots - 1)
79 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
80 if (start)
81 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
82 if (end)
83 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
84 if (irq)
85 ctl |= B43legacy_DMA32_DCTL_IRQ;
86 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87 & B43legacy_DMA32_DCTL_ADDREXT_MASK;
88
89 desc->dma32.control = cpu_to_le32(ctl);
90 desc->dma32.address = cpu_to_le32(addr);
91}
92
93static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
94{
95 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
97}
98
99static void op32_tx_suspend(struct b43legacy_dmaring *ring)
100{
101 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103 | B43legacy_DMA32_TXSUSPEND);
104}
105
106static void op32_tx_resume(struct b43legacy_dmaring *ring)
107{
108 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110 & ~B43legacy_DMA32_TXSUSPEND);
111}
112
113static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
114{
115 u32 val;
116
117 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118 val &= B43legacy_DMA32_RXDPTR;
119
120 return (val / sizeof(struct b43legacy_dmadesc32));
121}
122
123static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
124 int slot)
125{
126 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
128}
129
130static const struct b43legacy_dma_ops dma32_ops = {
131 .idx2desc = op32_idx2desc,
132 .fill_descriptor = op32_fill_descriptor,
133 .poke_tx = op32_poke_tx,
134 .tx_suspend = op32_tx_suspend,
135 .tx_resume = op32_tx_resume,
136 .get_current_rxslot = op32_get_current_rxslot,
137 .set_current_rxslot = op32_set_current_rxslot,
138};
139
140/* 64bit DMA ops. */
141static
142struct b43legacy_dmadesc_generic *op64_idx2desc(
143 struct b43legacy_dmaring *ring,
144 int slot,
145 struct b43legacy_dmadesc_meta
146 **meta)
147{
148 struct b43legacy_dmadesc64 *desc;
149
150 *meta = &(ring->meta[slot]);
151 desc = ring->descbase;
152 desc = &(desc[slot]);
153
154 return (struct b43legacy_dmadesc_generic *)desc;
155}
156
157static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
158 struct b43legacy_dmadesc_generic *desc,
159 dma_addr_t dmaaddr, u16 bufsize,
160 int start, int end, int irq)
161{
162 struct b43legacy_dmadesc64 *descbase = ring->descbase;
163 int slot;
164 u32 ctl0 = 0;
165 u32 ctl1 = 0;
166 u32 addrlo;
167 u32 addrhi;
168 u32 addrext;
169
170 slot = (int)(&(desc->dma64) - descbase);
171 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173 addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= ssb_dma_translation(ring->dev->dev);
178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
180 if (start)
181 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
182 if (end)
183 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
184 if (irq)
185 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
186 ctl1 |= (bufsize - ring->frameoffset)
187 & B43legacy_DMA64_DCTL1_BYTECNT;
188 ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
189 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
190
191 desc->dma64.control0 = cpu_to_le32(ctl0);
192 desc->dma64.control1 = cpu_to_le32(ctl1);
193 desc->dma64.address_low = cpu_to_le32(addrlo);
194 desc->dma64.address_high = cpu_to_le32(addrhi);
195}
196
197static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
198{
199 b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
200 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
201}
202
203static void op64_tx_suspend(struct b43legacy_dmaring *ring)
204{
205 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
206 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
207 | B43legacy_DMA64_TXSUSPEND);
208}
209
210static void op64_tx_resume(struct b43legacy_dmaring *ring)
211{
212 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
213 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
214 & ~B43legacy_DMA64_TXSUSPEND);
215}
216
217static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
218{
219 u32 val;
220
221 val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
222 val &= B43legacy_DMA64_RXSTATDPTR;
223
224 return (val / sizeof(struct b43legacy_dmadesc64));
225}
226
227static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
228 int slot)
229{
230 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
231 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
232}
233
234static const struct b43legacy_dma_ops dma64_ops = {
235 .idx2desc = op64_idx2desc,
236 .fill_descriptor = op64_fill_descriptor,
237 .poke_tx = op64_poke_tx,
238 .tx_suspend = op64_tx_suspend,
239 .tx_resume = op64_tx_resume,
240 .get_current_rxslot = op64_get_current_rxslot,
241 .set_current_rxslot = op64_set_current_rxslot,
242};
243
244
245static inline int free_slots(struct b43legacy_dmaring *ring)
246{
247 return (ring->nr_slots - ring->used_slots);
248}
249
250static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
251{
252 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
253 if (slot == ring->nr_slots - 1)
254 return 0;
255 return slot + 1;
256}
257
258static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
259{
260 B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
261 if (slot == 0)
262 return ring->nr_slots - 1;
263 return slot - 1;
264}
265
266#ifdef CONFIG_B43LEGACY_DEBUG
267static void update_max_used_slots(struct b43legacy_dmaring *ring,
268 int current_used_slots)
269{
270 if (current_used_slots <= ring->max_used_slots)
271 return;
272 ring->max_used_slots = current_used_slots;
273 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
274 b43legacydbg(ring->dev->wl,
275 "max_used_slots increased to %d on %s ring %d\n",
276 ring->max_used_slots,
277 ring->tx ? "TX" : "RX",
278 ring->index);
279}
280#else
281static inline
282void update_max_used_slots(struct b43legacy_dmaring *ring,
283 int current_used_slots)
284{ }
285#endif /* DEBUG */
286
287/* Request a slot for usage. */
288static inline
289int request_slot(struct b43legacy_dmaring *ring)
290{
291 int slot;
292
293 B43legacy_WARN_ON(!ring->tx);
294 B43legacy_WARN_ON(ring->stopped);
295 B43legacy_WARN_ON(free_slots(ring) == 0);
296
297 slot = next_slot(ring, ring->current_slot);
298 ring->current_slot = slot;
299 ring->used_slots++;
300
301 update_max_used_slots(ring, ring->used_slots);
302
303 return slot;
304}
305
306/* Mac80211-queue to b43legacy-ring mapping */
307static struct b43legacy_dmaring *priority_to_txring(
308 struct b43legacy_wldev *dev,
309 int queue_priority)
310{
311 struct b43legacy_dmaring *ring;
312
313/*FIXME: For now we always run on TX-ring-1 */
314return dev->dma.tx_ring1;
315
316 /* 0 = highest priority */
317 switch (queue_priority) {
318 default:
319 B43legacy_WARN_ON(1);
320 /* fallthrough */
321 case 0:
322 ring = dev->dma.tx_ring3;
323 break;
324 case 1:
325 ring = dev->dma.tx_ring2;
326 break;
327 case 2:
328 ring = dev->dma.tx_ring1;
329 break;
330 case 3:
331 ring = dev->dma.tx_ring0;
332 break;
333 case 4:
334 ring = dev->dma.tx_ring4;
335 break;
336 case 5:
337 ring = dev->dma.tx_ring5;
338 break;
339 }
340
341 return ring;
342}
343
344/* Bcm4301-ring to mac80211-queue mapping */
345static inline int txring_to_priority(struct b43legacy_dmaring *ring)
346{
347 static const u8 idx_to_prio[] =
348 { 3, 2, 1, 0, 4, 5, };
349
350/*FIXME: have only one queue, for now */
351return 0;
352
353 return idx_to_prio[ring->index];
354}
355
356
357u16 b43legacy_dmacontroller_base(int dma64bit, int controller_idx)
358{
359 static const u16 map64[] = {
360 B43legacy_MMIO_DMA64_BASE0,
361 B43legacy_MMIO_DMA64_BASE1,
362 B43legacy_MMIO_DMA64_BASE2,
363 B43legacy_MMIO_DMA64_BASE3,
364 B43legacy_MMIO_DMA64_BASE4,
365 B43legacy_MMIO_DMA64_BASE5,
366 };
367 static const u16 map32[] = {
368 B43legacy_MMIO_DMA32_BASE0,
369 B43legacy_MMIO_DMA32_BASE1,
370 B43legacy_MMIO_DMA32_BASE2,
371 B43legacy_MMIO_DMA32_BASE3,
372 B43legacy_MMIO_DMA32_BASE4,
373 B43legacy_MMIO_DMA32_BASE5,
374 };
375
376 if (dma64bit) {
377 B43legacy_WARN_ON(!(controller_idx >= 0 &&
378 controller_idx < ARRAY_SIZE(map64)));
379 return map64[controller_idx];
380 }
381 B43legacy_WARN_ON(!(controller_idx >= 0 &&
382 controller_idx < ARRAY_SIZE(map32)));
383 return map32[controller_idx];
384}
385
386static inline
387dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
388 unsigned char *buf,
389 size_t len,
390 int tx)
391{
392 dma_addr_t dmaaddr;
393
394 if (tx)
395 dmaaddr = dma_map_single(ring->dev->dev->dev,
396 buf, len,
397 DMA_TO_DEVICE);
398 else
399 dmaaddr = dma_map_single(ring->dev->dev->dev,
400 buf, len,
401 DMA_FROM_DEVICE);
402
403 return dmaaddr;
404}
405
406static inline
407void unmap_descbuffer(struct b43legacy_dmaring *ring,
408 dma_addr_t addr,
409 size_t len,
410 int tx)
411{
412 if (tx)
413 dma_unmap_single(ring->dev->dev->dev,
414 addr, len,
415 DMA_TO_DEVICE);
416 else
417 dma_unmap_single(ring->dev->dev->dev,
418 addr, len,
419 DMA_FROM_DEVICE);
420}
421
422static inline
423void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
424 dma_addr_t addr,
425 size_t len)
426{
427 B43legacy_WARN_ON(ring->tx);
428
429 dma_sync_single_for_cpu(ring->dev->dev->dev,
430 addr, len, DMA_FROM_DEVICE);
431}
432
433static inline
434void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
435 dma_addr_t addr,
436 size_t len)
437{
438 B43legacy_WARN_ON(ring->tx);
439
440 dma_sync_single_for_device(ring->dev->dev->dev,
441 addr, len, DMA_FROM_DEVICE);
442}
443
444static inline
445void free_descriptor_buffer(struct b43legacy_dmaring *ring,
446 struct b43legacy_dmadesc_meta *meta,
447 int irq_context)
448{
449 if (meta->skb) {
450 if (irq_context)
451 dev_kfree_skb_irq(meta->skb);
452 else
453 dev_kfree_skb(meta->skb);
454 meta->skb = NULL;
455 }
456}
457
458static int alloc_ringmemory(struct b43legacy_dmaring *ring)
459{
460 struct device *dev = ring->dev->dev->dev;
461
462 ring->descbase = dma_alloc_coherent(dev, B43legacy_DMA_RINGMEMSIZE,
463 &(ring->dmabase), GFP_KERNEL);
464 if (!ring->descbase) {
465 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
466 " failed\n");
467 return -ENOMEM;
468 }
469 memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
470
471 return 0;
472}
473
474static void free_ringmemory(struct b43legacy_dmaring *ring)
475{
476 struct device *dev = ring->dev->dev->dev;
477
478 dma_free_coherent(dev, B43legacy_DMA_RINGMEMSIZE,
479 ring->descbase, ring->dmabase);
480}
481
482/* Reset the RX DMA channel */
483int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
484 u16 mmio_base, int dma64)
485{
486 int i;
487 u32 value;
488 u16 offset;
489
490 might_sleep();
491
492 offset = dma64 ? B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
493 b43legacy_write32(dev, mmio_base + offset, 0);
494 for (i = 0; i < 10; i++) {
495 offset = dma64 ? B43legacy_DMA64_RXSTATUS :
496 B43legacy_DMA32_RXSTATUS;
497 value = b43legacy_read32(dev, mmio_base + offset);
498 if (dma64) {
499 value &= B43legacy_DMA64_RXSTAT;
500 if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
501 i = -1;
502 break;
503 }
504 } else {
505 value &= B43legacy_DMA32_RXSTATE;
506 if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
507 i = -1;
508 break;
509 }
510 }
511 msleep(1);
512 }
513 if (i != -1) {
514 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
515 return -ENODEV;
516 }
517
518 return 0;
519}
520
521/* Reset the RX DMA channel */
522int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
523 u16 mmio_base, int dma64)
524{
525 int i;
526 u32 value;
527 u16 offset;
528
529 might_sleep();
530
531 for (i = 0; i < 10; i++) {
532 offset = dma64 ? B43legacy_DMA64_TXSTATUS :
533 B43legacy_DMA32_TXSTATUS;
534 value = b43legacy_read32(dev, mmio_base + offset);
535 if (dma64) {
536 value &= B43legacy_DMA64_TXSTAT;
537 if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
538 value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
539 value == B43legacy_DMA64_TXSTAT_STOPPED)
540 break;
541 } else {
542 value &= B43legacy_DMA32_TXSTATE;
543 if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
544 value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
545 value == B43legacy_DMA32_TXSTAT_STOPPED)
546 break;
547 }
548 msleep(1);
549 }
550 offset = dma64 ? B43legacy_DMA64_TXCTL : B43legacy_DMA32_TXCTL;
551 b43legacy_write32(dev, mmio_base + offset, 0);
552 for (i = 0; i < 10; i++) {
553 offset = dma64 ? B43legacy_DMA64_TXSTATUS :
554 B43legacy_DMA32_TXSTATUS;
555 value = b43legacy_read32(dev, mmio_base + offset);
556 if (dma64) {
557 value &= B43legacy_DMA64_TXSTAT;
558 if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
559 i = -1;
560 break;
561 }
562 } else {
563 value &= B43legacy_DMA32_TXSTATE;
564 if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
565 i = -1;
566 break;
567 }
568 }
569 msleep(1);
570 }
571 if (i != -1) {
572 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
573 return -ENODEV;
574 }
575 /* ensure the reset is completed. */
576 msleep(1);
577
578 return 0;
579}
580
581static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
582 struct b43legacy_dmadesc_generic *desc,
583 struct b43legacy_dmadesc_meta *meta,
584 gfp_t gfp_flags)
585{
586 struct b43legacy_rxhdr_fw3 *rxhdr;
587 struct b43legacy_hwtxstatus *txstat;
588 dma_addr_t dmaaddr;
589 struct sk_buff *skb;
590
591 B43legacy_WARN_ON(ring->tx);
592
593 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
594 if (unlikely(!skb))
595 return -ENOMEM;
596 dmaaddr = map_descbuffer(ring, skb->data,
597 ring->rx_buffersize, 0);
598 if (dma_mapping_error(dmaaddr)) {
599 /* ugh. try to realloc in zone_dma */
600 gfp_flags |= GFP_DMA;
601
602 dev_kfree_skb_any(skb);
603
604 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
605 if (unlikely(!skb))
606 return -ENOMEM;
607 dmaaddr = map_descbuffer(ring, skb->data,
608 ring->rx_buffersize, 0);
609 }
610
611 if (dma_mapping_error(dmaaddr)) {
612 dev_kfree_skb_any(skb);
613 return -EIO;
614 }
615
616 meta->skb = skb;
617 meta->dmaaddr = dmaaddr;
618 ring->ops->fill_descriptor(ring, desc, dmaaddr,
619 ring->rx_buffersize, 0, 0, 0);
620
621 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
622 rxhdr->frame_len = 0;
623 txstat = (struct b43legacy_hwtxstatus *)(skb->data);
624 txstat->cookie = 0;
625
626 return 0;
627}
628
629/* Allocate the initial descbuffers.
630 * This is used for an RX ring only.
631 */
632static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
633{
634 int i;
635 int err = -ENOMEM;
636 struct b43legacy_dmadesc_generic *desc;
637 struct b43legacy_dmadesc_meta *meta;
638
639 for (i = 0; i < ring->nr_slots; i++) {
640 desc = ring->ops->idx2desc(ring, i, &meta);
641
642 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
643 if (err) {
644 b43legacyerr(ring->dev->wl,
645 "Failed to allocate initial descbuffers\n");
646 goto err_unwind;
647 }
648 }
649 mb(); /* all descbuffer setup before next line */
650 ring->used_slots = ring->nr_slots;
651 err = 0;
652out:
653 return err;
654
655err_unwind:
656 for (i--; i >= 0; i--) {
657 desc = ring->ops->idx2desc(ring, i, &meta);
658
659 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
660 dev_kfree_skb(meta->skb);
661 }
662 goto out;
663}
664
665/* Do initial setup of the DMA controller.
666 * Reset the controller, write the ring busaddress
667 * and switch the "enable" bit on.
668 */
669static int dmacontroller_setup(struct b43legacy_dmaring *ring)
670{
671 int err = 0;
672 u32 value;
673 u32 addrext;
674 u32 trans = ssb_dma_translation(ring->dev->dev);
675
676 if (ring->tx) {
677 if (ring->dma64) {
678 u64 ringbase = (u64)(ring->dmabase);
679
680 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
681 >> SSB_DMA_TRANSLATION_SHIFT;
682 value = B43legacy_DMA64_TXENABLE;
683 value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
684 & B43legacy_DMA64_TXADDREXT_MASK;
685 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
686 value);
687 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
688 (ringbase & 0xFFFFFFFF));
689 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
690 ((ringbase >> 32)
691 & ~SSB_DMA_TRANSLATION_MASK)
692 | trans);
693 } else {
694 u32 ringbase = (u32)(ring->dmabase);
695
696 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
697 >> SSB_DMA_TRANSLATION_SHIFT;
698 value = B43legacy_DMA32_TXENABLE;
699 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
700 & B43legacy_DMA32_TXADDREXT_MASK;
701 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
702 value);
703 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
704 (ringbase &
705 ~SSB_DMA_TRANSLATION_MASK)
706 | trans);
707 }
708 } else {
709 err = alloc_initial_descbuffers(ring);
710 if (err)
711 goto out;
712 if (ring->dma64) {
713 u64 ringbase = (u64)(ring->dmabase);
714
715 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
716 >> SSB_DMA_TRANSLATION_SHIFT;
717 value = (ring->frameoffset <<
718 B43legacy_DMA64_RXFROFF_SHIFT);
719 value |= B43legacy_DMA64_RXENABLE;
720 value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
721 & B43legacy_DMA64_RXADDREXT_MASK;
722 b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
723 value);
724 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
725 (ringbase & 0xFFFFFFFF));
726 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
727 ((ringbase >> 32) &
728 ~SSB_DMA_TRANSLATION_MASK) |
729 trans);
730 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
731 200);
732 } else {
733 u32 ringbase = (u32)(ring->dmabase);
734
735 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
736 >> SSB_DMA_TRANSLATION_SHIFT;
737 value = (ring->frameoffset <<
738 B43legacy_DMA32_RXFROFF_SHIFT);
739 value |= B43legacy_DMA32_RXENABLE;
740 value |= (addrext <<
741 B43legacy_DMA32_RXADDREXT_SHIFT)
742 & B43legacy_DMA32_RXADDREXT_MASK;
743 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
744 value);
745 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
746 (ringbase &
747 ~SSB_DMA_TRANSLATION_MASK)
748 | trans);
749 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
750 200);
751 }
752 }
753
754out:
755 return err;
756}
757
758/* Shutdown the DMA controller. */
759static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
760{
761 if (ring->tx) {
762 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
763 ring->dma64);
764 if (ring->dma64) {
765 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
766 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
767 } else
768 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
769 } else {
770 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
771 ring->dma64);
772 if (ring->dma64) {
773 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
774 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
775 } else
776 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
777 }
778}
779
780static void free_all_descbuffers(struct b43legacy_dmaring *ring)
781{
782 struct b43legacy_dmadesc_generic *desc;
783 struct b43legacy_dmadesc_meta *meta;
784 int i;
785
786 if (!ring->used_slots)
787 return;
788 for (i = 0; i < ring->nr_slots; i++) {
789 desc = ring->ops->idx2desc(ring, i, &meta);
790
791 if (!meta->skb) {
792 B43legacy_WARN_ON(!ring->tx);
793 continue;
794 }
795 if (ring->tx)
796 unmap_descbuffer(ring, meta->dmaaddr,
797 meta->skb->len, 1);
798 else
799 unmap_descbuffer(ring, meta->dmaaddr,
800 ring->rx_buffersize, 0);
801 free_descriptor_buffer(ring, meta, 0);
802 }
803}
804
805static u64 supported_dma_mask(struct b43legacy_wldev *dev)
806{
807 u32 tmp;
808 u16 mmio_base;
809
810 tmp = b43legacy_read32(dev, SSB_TMSHIGH);
811 if (tmp & SSB_TMSHIGH_DMA64)
812 return DMA_64BIT_MASK;
813 mmio_base = b43legacy_dmacontroller_base(0, 0);
814 b43legacy_write32(dev,
815 mmio_base + B43legacy_DMA32_TXCTL,
816 B43legacy_DMA32_TXADDREXT_MASK);
817 tmp = b43legacy_read32(dev, mmio_base +
818 B43legacy_DMA32_TXCTL);
819 if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
820 return DMA_32BIT_MASK;
821
822 return DMA_30BIT_MASK;
823}
824
825/* Main initialization function. */
826static
827struct b43legacy_dmaring *b43legacy_setup_dmaring(
828 struct b43legacy_wldev *dev,
829 int controller_index,
830 int for_tx,
831 int dma64)
832{
833 struct b43legacy_dmaring *ring;
834 int err;
835 int nr_slots;
836 dma_addr_t dma_test;
837
838 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
839 if (!ring)
840 goto out;
841
842 nr_slots = B43legacy_RXRING_SLOTS;
843 if (for_tx)
844 nr_slots = B43legacy_TXRING_SLOTS;
845
846 ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
847 GFP_KERNEL);
848 if (!ring->meta)
849 goto err_kfree_ring;
850 if (for_tx) {
851 ring->txhdr_cache = kcalloc(nr_slots,
852 sizeof(struct b43legacy_txhdr_fw3),
853 GFP_KERNEL);
854 if (!ring->txhdr_cache)
855 goto err_kfree_meta;
856
857 /* test for ability to dma to txhdr_cache */
858 dma_test = dma_map_single(dev->dev->dev,
859 ring->txhdr_cache,
860 sizeof(struct b43legacy_txhdr_fw3),
861 DMA_TO_DEVICE);
862
863 if (dma_mapping_error(dma_test)) {
864 /* ugh realloc */
865 kfree(ring->txhdr_cache);
866 ring->txhdr_cache = kcalloc(nr_slots,
867 sizeof(struct b43legacy_txhdr_fw3),
868 GFP_KERNEL | GFP_DMA);
869 if (!ring->txhdr_cache)
870 goto err_kfree_meta;
871
872 dma_test = dma_map_single(dev->dev->dev,
873 ring->txhdr_cache,
874 sizeof(struct b43legacy_txhdr_fw3),
875 DMA_TO_DEVICE);
876
877 if (dma_mapping_error(dma_test))
878 goto err_kfree_txhdr_cache;
879 }
880
881 dma_unmap_single(dev->dev->dev,
882 dma_test, sizeof(struct b43legacy_txhdr_fw3),
883 DMA_TO_DEVICE);
884 }
885
886 ring->dev = dev;
887 ring->nr_slots = nr_slots;
888 ring->mmio_base = b43legacy_dmacontroller_base(dma64,
889 controller_index);
890 ring->index = controller_index;
891 ring->dma64 = !!dma64;
892 if (dma64)
893 ring->ops = &dma64_ops;
894 else
895 ring->ops = &dma32_ops;
896 if (for_tx) {
897 ring->tx = 1;
898 ring->current_slot = -1;
899 } else {
900 if (ring->index == 0) {
901 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
902 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
903 } else if (ring->index == 3) {
904 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
905 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
906 } else
907 B43legacy_WARN_ON(1);
908 }
909 spin_lock_init(&ring->lock);
910#ifdef CONFIG_B43LEGACY_DEBUG
911 ring->last_injected_overflow = jiffies;
912#endif
913
914 err = alloc_ringmemory(ring);
915 if (err)
916 goto err_kfree_txhdr_cache;
917 err = dmacontroller_setup(ring);
918 if (err)
919 goto err_free_ringmemory;
920
921out:
922 return ring;
923
924err_free_ringmemory:
925 free_ringmemory(ring);
926err_kfree_txhdr_cache:
927 kfree(ring->txhdr_cache);
928err_kfree_meta:
929 kfree(ring->meta);
930err_kfree_ring:
931 kfree(ring);
932 ring = NULL;
933 goto out;
934}
935
936/* Main cleanup function. */
937static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
938{
939 if (!ring)
940 return;
941
942 b43legacydbg(ring->dev->wl, "DMA-%s 0x%04X (%s) max used slots:"
943 " %d/%d\n", (ring->dma64) ? "64" : "32", ring->mmio_base,
944 (ring->tx) ? "TX" : "RX",
945 ring->max_used_slots, ring->nr_slots);
946 /* Device IRQs are disabled prior entering this function,
947 * so no need to take care of concurrency with rx handler stuff.
948 */
949 dmacontroller_cleanup(ring);
950 free_all_descbuffers(ring);
951 free_ringmemory(ring);
952
953 kfree(ring->txhdr_cache);
954 kfree(ring->meta);
955 kfree(ring);
956}
957
958void b43legacy_dma_free(struct b43legacy_wldev *dev)
959{
960 struct b43legacy_dma *dma;
961
962 if (b43legacy_using_pio(dev))
963 return;
964 dma = &dev->dma;
965
966 b43legacy_destroy_dmaring(dma->rx_ring3);
967 dma->rx_ring3 = NULL;
968 b43legacy_destroy_dmaring(dma->rx_ring0);
969 dma->rx_ring0 = NULL;
970
971 b43legacy_destroy_dmaring(dma->tx_ring5);
972 dma->tx_ring5 = NULL;
973 b43legacy_destroy_dmaring(dma->tx_ring4);
974 dma->tx_ring4 = NULL;
975 b43legacy_destroy_dmaring(dma->tx_ring3);
976 dma->tx_ring3 = NULL;
977 b43legacy_destroy_dmaring(dma->tx_ring2);
978 dma->tx_ring2 = NULL;
979 b43legacy_destroy_dmaring(dma->tx_ring1);
980 dma->tx_ring1 = NULL;
981 b43legacy_destroy_dmaring(dma->tx_ring0);
982 dma->tx_ring0 = NULL;
983}
984
985int b43legacy_dma_init(struct b43legacy_wldev *dev)
986{
987 struct b43legacy_dma *dma = &dev->dma;
988 struct b43legacy_dmaring *ring;
989 int err;
990 u64 dmamask;
991 int dma64 = 0;
992
993 dmamask = supported_dma_mask(dev);
994 if (dmamask == DMA_64BIT_MASK)
995 dma64 = 1;
996
997 err = ssb_dma_set_mask(dev->dev, dmamask);
998 if (err) {
354807e0 999#ifdef CONFIG_B43LEGACY_PIO
75388acd
LF		 1000 b43legacywarn(dev->wl, "DMA for this device not supported. "
1001 "Falling back to PIO\n");
1002 dev->__using_pio = 1;
1003 return -EAGAIN;
1004#else
1005 b43legacyerr(dev->wl, "DMA for this device not supported and "
1006 "no PIO support compiled in\n");
1007 return -EOPNOTSUPP;
1008#endif
1009 }
1010
1011 err = -ENOMEM;
1012 /* setup TX DMA channels. */
1013 ring = b43legacy_setup_dmaring(dev, 0, 1, dma64);
1014 if (!ring)
1015 goto out;
1016 dma->tx_ring0 = ring;
1017
1018 ring = b43legacy_setup_dmaring(dev, 1, 1, dma64);
1019 if (!ring)
1020 goto err_destroy_tx0;
1021 dma->tx_ring1 = ring;
1022
1023 ring = b43legacy_setup_dmaring(dev, 2, 1, dma64);
1024 if (!ring)
1025 goto err_destroy_tx1;
1026 dma->tx_ring2 = ring;
1027
1028 ring = b43legacy_setup_dmaring(dev, 3, 1, dma64);
1029 if (!ring)
1030 goto err_destroy_tx2;
1031 dma->tx_ring3 = ring;
1032
1033 ring = b43legacy_setup_dmaring(dev, 4, 1, dma64);
1034 if (!ring)
1035 goto err_destroy_tx3;
1036 dma->tx_ring4 = ring;
1037
1038 ring = b43legacy_setup_dmaring(dev, 5, 1, dma64);
1039 if (!ring)
1040 goto err_destroy_tx4;
1041 dma->tx_ring5 = ring;
1042
1043 /* setup RX DMA channels. */
1044 ring = b43legacy_setup_dmaring(dev, 0, 0, dma64);
1045 if (!ring)
1046 goto err_destroy_tx5;
1047 dma->rx_ring0 = ring;
1048
1049 if (dev->dev->id.revision < 5) {
1050 ring = b43legacy_setup_dmaring(dev, 3, 0, dma64);
1051 if (!ring)
1052 goto err_destroy_rx0;
1053 dma->rx_ring3 = ring;
1054 }
1055
1056 b43legacydbg(dev->wl, "%d-bit DMA initialized\n",
1057 (dmamask == DMA_64BIT_MASK) ? 64 :
1058 (dmamask == DMA_32BIT_MASK) ? 32 : 30);
1059 err = 0;
1060out:
1061 return err;
1062
1063err_destroy_rx0:
1064 b43legacy_destroy_dmaring(dma->rx_ring0);
1065 dma->rx_ring0 = NULL;
1066err_destroy_tx5:
1067 b43legacy_destroy_dmaring(dma->tx_ring5);
1068 dma->tx_ring5 = NULL;
1069err_destroy_tx4:
1070 b43legacy_destroy_dmaring(dma->tx_ring4);
1071 dma->tx_ring4 = NULL;
1072err_destroy_tx3:
1073 b43legacy_destroy_dmaring(dma->tx_ring3);
1074 dma->tx_ring3 = NULL;
1075err_destroy_tx2:
1076 b43legacy_destroy_dmaring(dma->tx_ring2);
1077 dma->tx_ring2 = NULL;
1078err_destroy_tx1:
1079 b43legacy_destroy_dmaring(dma->tx_ring1);
1080 dma->tx_ring1 = NULL;
1081err_destroy_tx0:
1082 b43legacy_destroy_dmaring(dma->tx_ring0);
1083 dma->tx_ring0 = NULL;
1084 goto out;
1085}
1086
1087/* Generate a cookie for the TX header. */
1088static u16 generate_cookie(struct b43legacy_dmaring *ring,
1089 int slot)
1090{
1091 u16 cookie = 0x1000;
1092
1093 /* Use the upper 4 bits of the cookie as
1094 * DMA controller ID and store the slot number
1095 * in the lower 12 bits.
1096 * Note that the cookie must never be 0, as this
1097 * is a special value used in RX path.
1098 */
1099 switch (ring->index) {
1100 case 0:
1101 cookie = 0xA000;
1102 break;
1103 case 1:
1104 cookie = 0xB000;
1105 break;
1106 case 2:
1107 cookie = 0xC000;
1108 break;
1109 case 3:
1110 cookie = 0xD000;
1111 break;
1112 case 4:
1113 cookie = 0xE000;
1114 break;
1115 case 5:
1116 cookie = 0xF000;
1117 break;
1118 }
1119 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1120 cookie |= (u16)slot;
1121
1122 return cookie;
1123}
1124
1125/* Inspect a cookie and find out to which controller/slot it belongs. */
1126static
1127struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1128 u16 cookie, int *slot)
1129{
1130 struct b43legacy_dma *dma = &dev->dma;
1131 struct b43legacy_dmaring *ring = NULL;
1132
1133 switch (cookie & 0xF000) {
1134 case 0xA000:
1135 ring = dma->tx_ring0;
1136 break;
1137 case 0xB000:
1138 ring = dma->tx_ring1;
1139 break;
1140 case 0xC000:
1141 ring = dma->tx_ring2;
1142 break;
1143 case 0xD000:
1144 ring = dma->tx_ring3;
1145 break;
1146 case 0xE000:
1147 ring = dma->tx_ring4;
1148 break;
1149 case 0xF000:
1150 ring = dma->tx_ring5;
1151 break;
1152 default:
1153 B43legacy_WARN_ON(1);
1154 }
1155 *slot = (cookie & 0x0FFF);
1156 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1157
1158 return ring;
1159}
1160
1161static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1162 struct sk_buff *skb,
1163 struct ieee80211_tx_control *ctl)
1164{
1165 const struct b43legacy_dma_ops *ops = ring->ops;
1166 u8 *header;
8dd0100c 1167 int slot, old_top_slot, old_used_slots;
75388acd
LF		 1168 int err;
1169 struct b43legacy_dmadesc_generic *desc;
1170 struct b43legacy_dmadesc_meta *meta;
1171 struct b43legacy_dmadesc_meta *meta_hdr;
1172 struct sk_buff *bounce_skb;
1173
1174#define SLOTS_PER_PACKET 2
1175 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1176
8dd0100c
SB		 1177 old_top_slot = ring->current_slot;
1178 old_used_slots = ring->used_slots;
1179
75388acd
LF		 1180 /* Get a slot for the header. */
1181 slot = request_slot(ring);
1182 desc = ops->idx2desc(ring, slot, &meta_hdr);
1183 memset(meta_hdr, 0, sizeof(*meta_hdr));
1184
1185 header = &(ring->txhdr_cache[slot * sizeof(
1186 struct b43legacy_txhdr_fw3)]);
9eca9a8e 1187 err = b43legacy_generate_txhdr(ring->dev, header,
75388acd
LF		 1188 skb->data, skb->len, ctl,
1189 generate_cookie(ring, slot));
8dd0100c
SB		 1190 if (unlikely(err)) {
1191 ring->current_slot = old_top_slot;
1192 ring->used_slots = old_used_slots;
9eca9a8e 1193 return err;
8dd0100c 1194 }
75388acd
LF		 1195
1196 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1197 sizeof(struct b43legacy_txhdr_fw3), 1);
1198 if (dma_mapping_error(meta_hdr->dmaaddr))
1199 return -EIO;
1200 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1201 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1202
1203 /* Get a slot for the payload. */
1204 slot = request_slot(ring);
1205 desc = ops->idx2desc(ring, slot, &meta);
1206 memset(meta, 0, sizeof(*meta));
1207
1208 memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1209 meta->skb = skb;
1210 meta->is_last_fragment = 1;
1211
1212 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1213 /* create a bounce buffer in zone_dma on mapping failure. */
1214 if (dma_mapping_error(meta->dmaaddr)) {
1215 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1216 if (!bounce_skb) {
8dd0100c
SB		 1217 ring->current_slot = old_top_slot;
1218 ring->used_slots = old_used_slots;
75388acd
LF		 1219 err = -ENOMEM;
1220 goto out_unmap_hdr;
1221 }
1222
1223 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1224 dev_kfree_skb_any(skb);
1225 skb = bounce_skb;
1226 meta->skb = skb;
1227 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1228 if (dma_mapping_error(meta->dmaaddr)) {
8dd0100c
SB		 1229 ring->current_slot = old_top_slot;
1230 ring->used_slots = old_used_slots;
75388acd
LF		 1231 err = -EIO;
1232 goto out_free_bounce;
1233 }
1234 }
1235
1236 ops->fill_descriptor(ring, desc, meta->dmaaddr,
1237 skb->len, 0, 1, 1);
1238
1239 wmb(); /* previous stuff MUST be done */
1240 /* Now transfer the whole frame. */
1241 ops->poke_tx(ring, next_slot(ring, slot));
1242 return 0;
1243
1244out_free_bounce:
1245 dev_kfree_skb_any(skb);
1246out_unmap_hdr:
1247 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1248 sizeof(struct b43legacy_txhdr_fw3), 1);
1249 return err;
1250}
1251
1252static inline
1253int should_inject_overflow(struct b43legacy_dmaring *ring)
1254{
1255#ifdef CONFIG_B43LEGACY_DEBUG
1256 if (unlikely(b43legacy_debug(ring->dev,
1257 B43legacy_DBG_DMAOVERFLOW))) {
1258 /* Check if we should inject another ringbuffer overflow
1259 * to test handling of this situation in the stack. */
1260 unsigned long next_overflow;
1261
1262 next_overflow = ring->last_injected_overflow + HZ;
1263 if (time_after(jiffies, next_overflow)) {
1264 ring->last_injected_overflow = jiffies;
1265 b43legacydbg(ring->dev->wl,
1266 "Injecting TX ring overflow on "
1267 "DMA controller %d\n", ring->index);
1268 return 1;
1269 }
1270 }
1271#endif /* CONFIG_B43LEGACY_DEBUG */
1272 return 0;
1273}
1274
1275int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1276 struct sk_buff *skb,
1277 struct ieee80211_tx_control *ctl)
1278{
1279 struct b43legacy_dmaring *ring;
1280 int err = 0;
1281 unsigned long flags;
1282
1283 ring = priority_to_txring(dev, ctl->queue);
1284 spin_lock_irqsave(&ring->lock, flags);
1285 B43legacy_WARN_ON(!ring->tx);
1286 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1287 b43legacywarn(dev->wl, "DMA queue overflow\n");
1288 err = -ENOSPC;
1289 goto out_unlock;
1290 }
1291 /* Check if the queue was stopped in mac80211,
1292 * but we got called nevertheless.
1293 * That would be a mac80211 bug. */
1294 B43legacy_BUG_ON(ring->stopped);
1295
1296 err = dma_tx_fragment(ring, skb, ctl);
9eca9a8e
SB		 1297 if (unlikely(err == -ENOKEY)) {
1298 /* Drop this packet, as we don't have the encryption key
1299 * anymore and must not transmit it unencrypted. */
1300 dev_kfree_skb_any(skb);
1301 err = 0;
1302 goto out_unlock;
1303 }
75388acd
LF		 1304 if (unlikely(err)) {
1305 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1306 goto out_unlock;
1307 }
1308 ring->nr_tx_packets++;
1309 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1310 should_inject_overflow(ring)) {
1311 /* This TX ring is full. */
1312 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1313 ring->stopped = 1;
1314 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1315 b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1316 ring->index);
1317 }
1318out_unlock:
1319 spin_unlock_irqrestore(&ring->lock, flags);
1320
1321 return err;
1322}
1323
1324void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1325 const struct b43legacy_txstatus *status)
1326{
1327 const struct b43legacy_dma_ops *ops;
1328 struct b43legacy_dmaring *ring;
1329 struct b43legacy_dmadesc_generic *desc;
1330 struct b43legacy_dmadesc_meta *meta;
1331 int slot;
1332
1333 ring = parse_cookie(dev, status->cookie, &slot);
1334 if (unlikely(!ring))
1335 return;
1336 B43legacy_WARN_ON(!irqs_disabled());
1337 spin_lock(&ring->lock);
1338
1339 B43legacy_WARN_ON(!ring->tx);
1340 ops = ring->ops;
1341 while (1) {
1342 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1343 desc = ops->idx2desc(ring, slot, &meta);
1344
1345 if (meta->skb)
1346 unmap_descbuffer(ring, meta->dmaaddr,
1347 meta->skb->len, 1);
1348 else
1349 unmap_descbuffer(ring, meta->dmaaddr,
1350 sizeof(struct b43legacy_txhdr_fw3),
1351 1);
1352
1353 if (meta->is_last_fragment) {
1354 B43legacy_WARN_ON(!meta->skb);
1355 /* Call back to inform the ieee80211 subsystem about the
1356 * status of the transmission.
1357 * Some fields of txstat are already filled in dma_tx().
1358 */
1359 if (status->acked) {
1360 meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
1361 } else {
1362 if (!(meta->txstat.control.flags
1363 & IEEE80211_TXCTL_NO_ACK))
1364 meta->txstat.excessive_retries = 1;
1365 }
1366 if (status->frame_count == 0) {
1367 /* The frame was not transmitted at all. */
1368 meta->txstat.retry_count = 0;
1369 } else
1370 meta->txstat.retry_count = status->frame_count
1371 - 1;
1372 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1373 &(meta->txstat));
1374 /* skb is freed by ieee80211_tx_status_irqsafe() */
1375 meta->skb = NULL;
1376 } else {
1377 /* No need to call free_descriptor_buffer here, as
1378 * this is only the txhdr, which is not allocated.
1379 */
1380 B43legacy_WARN_ON(meta->skb != NULL);
1381 }
1382
1383 /* Everything unmapped and free'd. So it's not used anymore. */
1384 ring->used_slots--;
1385
1386 if (meta->is_last_fragment)
1387 break;
1388 slot = next_slot(ring, slot);
1389 }
1390 dev->stats.last_tx = jiffies;
1391 if (ring->stopped) {
1392 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1393 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1394 ring->stopped = 0;
1395 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1396 b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1397 ring->index);
1398 }
1399
1400 spin_unlock(&ring->lock);
1401}
1402
1403void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1404 struct ieee80211_tx_queue_stats *stats)
1405{
1406 const int nr_queues = dev->wl->hw->queues;
1407 struct b43legacy_dmaring *ring;
1408 struct ieee80211_tx_queue_stats_data *data;
1409 unsigned long flags;
1410 int i;
1411
1412 for (i = 0; i < nr_queues; i++) {
1413 data = &(stats->data[i]);
1414 ring = priority_to_txring(dev, i);
1415
1416 spin_lock_irqsave(&ring->lock, flags);
1417 data->len = ring->used_slots / SLOTS_PER_PACKET;
1418 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1419 data->count = ring->nr_tx_packets;
1420 spin_unlock_irqrestore(&ring->lock, flags);
1421 }
1422}
1423
1424static void dma_rx(struct b43legacy_dmaring *ring,
1425 int *slot)
1426{
1427 const struct b43legacy_dma_ops *ops = ring->ops;
1428 struct b43legacy_dmadesc_generic *desc;
1429 struct b43legacy_dmadesc_meta *meta;
1430 struct b43legacy_rxhdr_fw3 *rxhdr;
1431 struct sk_buff *skb;
1432 u16 len;
1433 int err;
1434 dma_addr_t dmaaddr;
1435
1436 desc = ops->idx2desc(ring, *slot, &meta);
1437
1438 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1439 skb = meta->skb;
1440
1441 if (ring->index == 3) {
1442 /* We received an xmit status. */
1443 struct b43legacy_hwtxstatus *hw =
1444 (struct b43legacy_hwtxstatus *)skb->data;
1445 int i = 0;
1446
1447 while (hw->cookie == 0) {
1448 if (i > 100)
1449 break;
1450 i++;
1451 udelay(2);
1452 barrier();
1453 }
1454 b43legacy_handle_hwtxstatus(ring->dev, hw);
1455 /* recycle the descriptor buffer. */
1456 sync_descbuffer_for_device(ring, meta->dmaaddr,
1457 ring->rx_buffersize);
1458
1459 return;
1460 }
1461 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1462 len = le16_to_cpu(rxhdr->frame_len);
1463 if (len == 0) {
1464 int i = 0;
1465
1466 do {
1467 udelay(2);
1468 barrier();
1469 len = le16_to_cpu(rxhdr->frame_len);
1470 } while (len == 0 && i++ < 5);
1471 if (unlikely(len == 0)) {
1472 /* recycle the descriptor buffer. */
1473 sync_descbuffer_for_device(ring, meta->dmaaddr,
1474 ring->rx_buffersize);
1475 goto drop;
1476 }
1477 }
1478 if (unlikely(len > ring->rx_buffersize)) {
1479 /* The data did not fit into one descriptor buffer
1480 * and is split over multiple buffers.
1481 * This should never happen, as we try to allocate buffers
1482 * big enough. So simply ignore this packet.
1483 */
1484 int cnt = 0;
1485 s32 tmp = len;
1486
1487 while (1) {
1488 desc = ops->idx2desc(ring, *slot, &meta);
1489 /* recycle the descriptor buffer. */
1490 sync_descbuffer_for_device(ring, meta->dmaaddr,
1491 ring->rx_buffersize);
1492 *slot = next_slot(ring, *slot);
1493 cnt++;
1494 tmp -= ring->rx_buffersize;
1495 if (tmp <= 0)
1496 break;
1497 }
1498 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1499 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1500 len, ring->rx_buffersize, cnt);
1501 goto drop;
1502 }
1503
1504 dmaaddr = meta->dmaaddr;
1505 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1506 if (unlikely(err)) {
1507 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1508 " failed\n");
1509 sync_descbuffer_for_device(ring, dmaaddr,
1510 ring->rx_buffersize);
1511 goto drop;
1512 }
1513
1514 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1515 skb_put(skb, len + ring->frameoffset);
1516 skb_pull(skb, ring->frameoffset);
1517
1518 b43legacy_rx(ring->dev, skb, rxhdr);
1519drop:
1520 return;
1521}
1522
1523void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1524{
1525 const struct b43legacy_dma_ops *ops = ring->ops;
1526 int slot;
1527 int current_slot;
1528 int used_slots = 0;
1529
1530 B43legacy_WARN_ON(ring->tx);
1531 current_slot = ops->get_current_rxslot(ring);
1532 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1533 ring->nr_slots));
1534
1535 slot = ring->current_slot;
1536 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1537 dma_rx(ring, &slot);
1538 update_max_used_slots(ring, ++used_slots);
1539 }
1540 ops->set_current_rxslot(ring, slot);
1541 ring->current_slot = slot;
1542}
1543
1544static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1545{
1546 unsigned long flags;
1547
1548 spin_lock_irqsave(&ring->lock, flags);
1549 B43legacy_WARN_ON(!ring->tx);
1550 ring->ops->tx_suspend(ring);
1551 spin_unlock_irqrestore(&ring->lock, flags);
1552}
1553
1554static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1555{
1556 unsigned long flags;
1557
1558 spin_lock_irqsave(&ring->lock, flags);
1559 B43legacy_WARN_ON(!ring->tx);
1560 ring->ops->tx_resume(ring);
1561 spin_unlock_irqrestore(&ring->lock, flags);
1562}
1563
1564void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1565{
1566 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1567 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1568 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1569 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1570 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1571 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1572 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1573}
1574
1575void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1576{
1577 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1578 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1579 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1580 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1581 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1582 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1583 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1584}
Michael's Linux tree.