]> git.ipfire.org Git - people/arne_f/kernel.git/blame - drivers/net/wireless/iwlwifi/iwl3945-base.c
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[people/arne_f/kernel.git] / drivers / net / wireless / iwlwifi / iwl3945-base.c
CommitLineData
b481de9c
ZY
1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY
30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY
32#include <linux/init.h>
33#include <linux/pci.h>
5a0e3ad6 34#include <linux/slab.h>
b481de9c
ZY
35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
d43c36dc 37#include <linux/sched.h>
b481de9c
ZY
38#include <linux/skbuff.h>
39#include <linux/netdevice.h>
40#include <linux/wireless.h>
41#include <linux/firmware.h>
b481de9c
ZY
42#include <linux/etherdevice.h>
43#include <linux/if_arp.h>
44
45#include <net/ieee80211_radiotap.h>
46#include <net/mac80211.h>
47
48#include <asm/div64.h>
49
a3139c59
SO
50#define DRV_NAME "iwl3945"
51
dbb6654c
WT
52#include "iwl-fh.h"
53#include "iwl-3945-fh.h"
600c0e11 54#include "iwl-commands.h"
17f841cd 55#include "iwl-sta.h"
b481de9c 56#include "iwl-3945.h"
5747d47f 57#include "iwl-core.h"
4a6547c7 58#include "iwl-helpers.h"
d20b3c65 59#include "iwl-dev.h"
81963d68 60#include "iwl-spectrum.h"
b481de9c 61
b481de9c
ZY
62/*
63 * module name, copyright, version, etc.
b481de9c
ZY
64 */
65
66#define DRV_DESCRIPTION \
67"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
68
d08853a3 69#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
70#define VD "d"
71#else
72#define VD
73#endif
74
81963d68
RC
75/*
76 * add "s" to indicate spectrum measurement included.
77 * we add it here to be consistent with previous releases in which
78 * this was configurable.
79 */
80#define DRV_VERSION IWLWIFI_VERSION VD "s"
1f447808 81#define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
a7b75207 82#define DRV_AUTHOR "<ilw@linux.intel.com>"
b481de9c
ZY
83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY
87MODULE_LICENSE("GPL");
88
df878d8f
KA
89 /* module parameters */
90struct iwl_mod_params iwl3945_mod_params = {
9c74d9fb 91 .sw_crypto = 1,
af48d048 92 .restart_fw = 1,
df878d8f
KA
93 /* the rest are 0 by default */
94};
95
7e4bca5e
SO
96/**
97 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
98 * @priv: eeprom and antenna fields are used to determine antenna flags
99 *
100 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
101 * iwl3945_mod_params.antenna specifies the antenna diversity mode:
102 *
103 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
104 * IWL_ANTENNA_MAIN - Force MAIN antenna
105 * IWL_ANTENNA_AUX - Force AUX antenna
106 */
107__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
108{
109 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
110
111 switch (iwl3945_mod_params.antenna) {
112 case IWL_ANTENNA_DIVERSITY:
113 return 0;
114
115 case IWL_ANTENNA_MAIN:
116 if (eeprom->antenna_switch_type)
117 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
118 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
119
120 case IWL_ANTENNA_AUX:
121 if (eeprom->antenna_switch_type)
122 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
123 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
124 }
125
126 /* bad antenna selector value */
127 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
128 iwl3945_mod_params.antenna);
129
130 return 0; /* "diversity" is default if error */
131}
132
6e21f15c 133static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
b481de9c
ZY
134 struct ieee80211_key_conf *keyconf,
135 u8 sta_id)
136{
137 unsigned long flags;
138 __le16 key_flags = 0;
6e21f15c
AK
139 int ret;
140
141 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
142 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
143
144 if (sta_id == priv->hw_params.bcast_sta_id)
145 key_flags |= STA_KEY_MULTICAST_MSK;
146
147 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
148 keyconf->hw_key_idx = keyconf->keyidx;
149 key_flags &= ~STA_KEY_FLG_INVALID;
b481de9c 150
b481de9c 151 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
152 priv->stations[sta_id].keyinfo.alg = keyconf->alg;
153 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
154 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
b481de9c
ZY
155 keyconf->keylen);
156
c587de0b 157 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
b481de9c 158 keyconf->keylen);
6e21f15c 159
c587de0b 160 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
6e21f15c 161 == STA_KEY_FLG_NO_ENC)
c587de0b 162 priv->stations[sta_id].sta.key.key_offset =
6e21f15c
AK
163 iwl_get_free_ucode_key_index(priv);
164 /* else, we are overriding an existing key => no need to allocated room
165 * in uCode. */
166
c587de0b 167 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
6e21f15c
AK
168 "no space for a new key");
169
c587de0b
TW
170 priv->stations[sta_id].sta.key.key_flags = key_flags;
171 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
172 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c 173
6e21f15c
AK
174 IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
175
c587de0b 176 ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
6e21f15c 177
b481de9c
ZY
178 spin_unlock_irqrestore(&priv->sta_lock, flags);
179
6e21f15c
AK
180 return ret;
181}
182
183static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
184 struct ieee80211_key_conf *keyconf,
185 u8 sta_id)
186{
187 return -EOPNOTSUPP;
188}
189
190static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
191 struct ieee80211_key_conf *keyconf,
192 u8 sta_id)
193{
194 return -EOPNOTSUPP;
b481de9c
ZY
195}
196
4a8a4322 197static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
b481de9c
ZY
198{
199 unsigned long flags;
200
201 spin_lock_irqsave(&priv->sta_lock, flags);
c587de0b
TW
202 memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
203 memset(&priv->stations[sta_id].sta.key, 0,
4c897253 204 sizeof(struct iwl4965_keyinfo));
c587de0b
TW
205 priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
206 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
207 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
b481de9c
ZY
208 spin_unlock_irqrestore(&priv->sta_lock, flags);
209
e1623446 210 IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
c587de0b 211 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, 0);
b481de9c
ZY
212 return 0;
213}
214
fa11d525 215static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
6e21f15c
AK
216 struct ieee80211_key_conf *keyconf, u8 sta_id)
217{
218 int ret = 0;
219
220 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
221
222 switch (keyconf->alg) {
223 case ALG_CCMP:
224 ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
225 break;
226 case ALG_TKIP:
227 ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
228 break;
229 case ALG_WEP:
230 ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
231 break;
232 default:
1e680233 233 IWL_ERR(priv, "Unknown alg: %s alg = %d\n", __func__, keyconf->alg);
6e21f15c
AK
234 ret = -EINVAL;
235 }
236
237 IWL_DEBUG_WEP(priv, "Set dynamic key: alg= %d len=%d idx=%d sta=%d ret=%d\n",
238 keyconf->alg, keyconf->keylen, keyconf->keyidx,
239 sta_id, ret);
240
241 return ret;
242}
243
244static int iwl3945_remove_static_key(struct iwl_priv *priv)
245{
246 int ret = -EOPNOTSUPP;
247
248 return ret;
249}
250
251static int iwl3945_set_static_key(struct iwl_priv *priv,
252 struct ieee80211_key_conf *key)
253{
254 if (key->alg == ALG_WEP)
255 return -EOPNOTSUPP;
256
257 IWL_ERR(priv, "Static key invalid: alg %d\n", key->alg);
258 return -EINVAL;
259}
260
4a8a4322 261static void iwl3945_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY
262{
263 struct list_head *element;
264
e1623446 265 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY
266 priv->frames_count);
267
268 while (!list_empty(&priv->free_frames)) {
269 element = priv->free_frames.next;
270 list_del(element);
bb8c093b 271 kfree(list_entry(element, struct iwl3945_frame, list));
b481de9c
ZY
272 priv->frames_count--;
273 }
274
275 if (priv->frames_count) {
39aadf8c 276 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY
277 priv->frames_count);
278 priv->frames_count = 0;
279 }
280}
281
4a8a4322 282static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
b481de9c 283{
bb8c093b 284 struct iwl3945_frame *frame;
b481de9c
ZY
285 struct list_head *element;
286 if (list_empty(&priv->free_frames)) {
287 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
288 if (!frame) {
15b1687c 289 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY
290 return NULL;
291 }
292
293 priv->frames_count++;
294 return frame;
295 }
296
297 element = priv->free_frames.next;
298 list_del(element);
bb8c093b 299 return list_entry(element, struct iwl3945_frame, list);
b481de9c
ZY
300}
301
4a8a4322 302static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
b481de9c
ZY
303{
304 memset(frame, 0, sizeof(*frame));
305 list_add(&frame->list, &priv->free_frames);
306}
307
4a8a4322 308unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
b481de9c 309 struct ieee80211_hdr *hdr,
73ec1cc2 310 int left)
b481de9c
ZY
311{
312
8ccde88a 313 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
314 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
315 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY
316 return 0;
317
318 if (priv->ibss_beacon->len > left)
319 return 0;
320
321 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
322
323 return priv->ibss_beacon->len;
324}
325
4a8a4322 326static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 327{
bb8c093b 328 struct iwl3945_frame *frame;
b481de9c
ZY
329 unsigned int frame_size;
330 int rc;
331 u8 rate;
332
bb8c093b 333 frame = iwl3945_get_free_frame(priv);
b481de9c
ZY
334
335 if (!frame) {
15b1687c 336 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY
337 "command.\n");
338 return -ENOMEM;
339 }
340
8ccde88a 341 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 342
bb8c093b 343 frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 344
518099a8 345 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY
346 &frame->u.cmd[0]);
347
bb8c093b 348 iwl3945_free_frame(priv, frame);
b481de9c
ZY
349
350 return rc;
351}
352
4a8a4322 353static void iwl3945_unset_hw_params(struct iwl_priv *priv)
b481de9c 354{
3832ec9d 355 if (priv->shared_virt)
f36d04ab
SG
356 dma_free_coherent(&priv->pci_dev->dev,
357 sizeof(struct iwl3945_shared),
358 priv->shared_virt,
359 priv->shared_phys);
b481de9c
ZY
360}
361
4a8a4322 362static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
e039fa4a 363 struct ieee80211_tx_info *info,
c2acea8e 364 struct iwl_device_cmd *cmd,
b481de9c 365 struct sk_buff *skb_frag,
6e21f15c 366 int sta_id)
b481de9c 367{
9744c91f 368 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
c587de0b 369 struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
b481de9c
ZY
370
371 switch (keyinfo->alg) {
372 case ALG_CCMP:
9744c91f
AK
373 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
374 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
e1623446 375 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
b481de9c
ZY
376 break;
377
378 case ALG_TKIP:
b481de9c
ZY
379 break;
380
381 case ALG_WEP:
9744c91f 382 tx_cmd->sec_ctl = TX_CMD_SEC_WEP |
e039fa4a 383 (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
b481de9c
ZY
384
385 if (keyinfo->keylen == 13)
9744c91f 386 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
b481de9c 387
9744c91f 388 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
b481de9c 389
e1623446 390 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
e039fa4a 391 "with key %d\n", info->control.hw_key->hw_key_idx);
b481de9c
ZY
392 break;
393
b481de9c 394 default:
978785a3 395 IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
b481de9c
ZY
396 break;
397 }
398}
399
400/*
401 * handle build REPLY_TX command notification.
402 */
4a8a4322 403static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
c2acea8e 404 struct iwl_device_cmd *cmd,
e039fa4a 405 struct ieee80211_tx_info *info,
e52119c5 406 struct ieee80211_hdr *hdr, u8 std_id)
b481de9c 407{
9744c91f
AK
408 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
409 __le32 tx_flags = tx_cmd->tx_flags;
fd7c8a40 410 __le16 fc = hdr->frame_control;
b481de9c 411
9744c91f 412 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
e039fa4a 413 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
b481de9c 414 tx_flags |= TX_CMD_FLG_ACK_MSK;
fd7c8a40 415 if (ieee80211_is_mgmt(fc))
b481de9c 416 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
fd7c8a40 417 if (ieee80211_is_probe_resp(fc) &&
b481de9c
ZY
418 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
419 tx_flags |= TX_CMD_FLG_TSF_MSK;
420 } else {
421 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
422 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
423 }
424
9744c91f 425 tx_cmd->sta_id = std_id;
8b7b1e05 426 if (ieee80211_has_morefrags(fc))
b481de9c
ZY
427 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
428
fd7c8a40
HH
429 if (ieee80211_is_data_qos(fc)) {
430 u8 *qc = ieee80211_get_qos_ctl(hdr);
9744c91f 431 tx_cmd->tid_tspec = qc[0] & 0xf;
b481de9c 432 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 433 } else {
b481de9c 434 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
54dbb525 435 }
b481de9c 436
37dc70fe 437 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
b481de9c
ZY
438
439 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
440 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
441
442 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
fd7c8a40
HH
443 if (ieee80211_is_mgmt(fc)) {
444 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
9744c91f 445 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
b481de9c 446 else
9744c91f 447 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
ab53d8af 448 } else {
9744c91f 449 tx_cmd->timeout.pm_frame_timeout = 0;
ab53d8af 450 }
b481de9c 451
9744c91f
AK
452 tx_cmd->driver_txop = 0;
453 tx_cmd->tx_flags = tx_flags;
454 tx_cmd->next_frame_len = 0;
b481de9c
ZY
455}
456
b481de9c
ZY
457/*
458 * start REPLY_TX command process
459 */
4a8a4322 460static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
b481de9c
ZY
461{
462 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e039fa4a 463 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
9744c91f 464 struct iwl3945_tx_cmd *tx_cmd;
188cf6c7 465 struct iwl_tx_queue *txq = NULL;
d20b3c65 466 struct iwl_queue *q = NULL;
c2acea8e
JB
467 struct iwl_device_cmd *out_cmd;
468 struct iwl_cmd_meta *out_meta;
b481de9c
ZY
469 dma_addr_t phys_addr;
470 dma_addr_t txcmd_phys;
e52119c5 471 int txq_id = skb_get_queue_mapping(skb);
df833b1d 472 u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
54dbb525
TW
473 u8 id;
474 u8 unicast;
b481de9c 475 u8 sta_id;
54dbb525 476 u8 tid = 0;
b481de9c 477 u16 seq_number = 0;
fd7c8a40 478 __le16 fc;
b481de9c 479 u8 wait_write_ptr = 0;
54dbb525 480 u8 *qc = NULL;
b481de9c 481 unsigned long flags;
b481de9c
ZY
482
483 spin_lock_irqsave(&priv->lock, flags);
775a6e27 484 if (iwl_is_rfkill(priv)) {
e1623446 485 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
b481de9c
ZY
486 goto drop_unlock;
487 }
488
e039fa4a 489 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
15b1687c 490 IWL_ERR(priv, "ERROR: No TX rate available.\n");
b481de9c
ZY
491 goto drop_unlock;
492 }
493
494 unicast = !is_multicast_ether_addr(hdr->addr1);
495 id = 0;
496
fd7c8a40 497 fc = hdr->frame_control;
b481de9c 498
d08853a3 499#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c 500 if (ieee80211_is_auth(fc))
e1623446 501 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
fd7c8a40 502 else if (ieee80211_is_assoc_req(fc))
e1623446 503 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
fd7c8a40 504 else if (ieee80211_is_reassoc_req(fc))
e1623446 505 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
b481de9c
ZY
506#endif
507
aa065263 508 /* drop all non-injected data frame if we are not associated */
914233d6 509 if (ieee80211_is_data(fc) &&
aa065263 510 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
8ccde88a 511 (!iwl_is_associated(priv) ||
05c914fe 512 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
e1623446 513 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
b481de9c
ZY
514 goto drop_unlock;
515 }
516
517 spin_unlock_irqrestore(&priv->lock, flags);
518
7294ec95 519 hdr_len = ieee80211_hdrlen(fc);
6440adb5
CB
520
521 /* Find (or create) index into station table for destination station */
aa065263
GS
522 if (info->flags & IEEE80211_TX_CTL_INJECTED)
523 sta_id = priv->hw_params.bcast_sta_id;
524 else
525 sta_id = iwl_get_sta_id(priv, hdr);
b481de9c 526 if (sta_id == IWL_INVALID_STATION) {
e1623446 527 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
e174961c 528 hdr->addr1);
b481de9c
ZY
529 goto drop;
530 }
531
e1623446 532 IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
b481de9c 533
fd7c8a40
HH
534 if (ieee80211_is_data_qos(fc)) {
535 qc = ieee80211_get_qos_ctl(hdr);
7294ec95 536 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
e6a6cf4c
RC
537 if (unlikely(tid >= MAX_TID_COUNT))
538 goto drop;
c587de0b 539 seq_number = priv->stations[sta_id].tid[tid].seq_number &
b481de9c
ZY
540 IEEE80211_SCTL_SEQ;
541 hdr->seq_ctrl = cpu_to_le16(seq_number) |
542 (hdr->seq_ctrl &
c1b4aa3f 543 cpu_to_le16(IEEE80211_SCTL_FRAG));
b481de9c
ZY
544 seq_number += 0x10;
545 }
6440adb5
CB
546
547 /* Descriptor for chosen Tx queue */
188cf6c7 548 txq = &priv->txq[txq_id];
b481de9c
ZY
549 q = &txq->q;
550
dc57a303
ZY
551 if ((iwl_queue_space(q) < q->high_mark))
552 goto drop;
553
b481de9c
ZY
554 spin_lock_irqsave(&priv->lock, flags);
555
fc4b6853 556 idx = get_cmd_index(q, q->write_ptr, 0);
b481de9c 557
6440adb5 558 /* Set up driver data for this TFD */
dbb6654c 559 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
fc4b6853 560 txq->txb[q->write_ptr].skb[0] = skb;
6440adb5
CB
561
562 /* Init first empty entry in queue's array of Tx/cmd buffers */
188cf6c7 563 out_cmd = txq->cmd[idx];
c2acea8e 564 out_meta = &txq->meta[idx];
9744c91f 565 tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
b481de9c 566 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
9744c91f 567 memset(tx_cmd, 0, sizeof(*tx_cmd));
6440adb5
CB
568
569 /*
570 * Set up the Tx-command (not MAC!) header.
571 * Store the chosen Tx queue and TFD index within the sequence field;
572 * after Tx, uCode's Tx response will return this value so driver can
573 * locate the frame within the tx queue and do post-tx processing.
574 */
b481de9c
ZY
575 out_cmd->hdr.cmd = REPLY_TX;
576 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
fc4b6853 577 INDEX_TO_SEQ(q->write_ptr)));
6440adb5
CB
578
579 /* Copy MAC header from skb into command buffer */
9744c91f 580 memcpy(tx_cmd->hdr, hdr, hdr_len);
b481de9c 581
df833b1d
RC
582
583 if (info->control.hw_key)
584 iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
585
586 /* TODO need this for burst mode later on */
587 iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
588
589 /* set is_hcca to 0; it probably will never be implemented */
590 iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
591
592 /* Total # bytes to be transmitted */
593 len = (u16)skb->len;
9744c91f 594 tx_cmd->len = cpu_to_le16(len);
df833b1d 595
20594eb0 596 iwl_dbg_log_tx_data_frame(priv, len, hdr);
22fdf3c9 597 iwl_update_stats(priv, true, fc, len);
9744c91f
AK
598 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
599 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
df833b1d
RC
600
601 if (!ieee80211_has_morefrags(hdr->frame_control)) {
602 txq->need_update = 1;
603 if (qc)
c587de0b 604 priv->stations[sta_id].tid[tid].seq_number = seq_number;
df833b1d
RC
605 } else {
606 wait_write_ptr = 1;
607 txq->need_update = 0;
608 }
609
610 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
611 le16_to_cpu(out_cmd->hdr.sequence));
9744c91f
AK
612 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
613 iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
614 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
df833b1d
RC
615 ieee80211_hdrlen(fc));
616
6440adb5
CB
617 /*
618 * Use the first empty entry in this queue's command buffer array
619 * to contain the Tx command and MAC header concatenated together
620 * (payload data will be in another buffer).
621 * Size of this varies, due to varying MAC header length.
622 * If end is not dword aligned, we'll have 2 extra bytes at the end
623 * of the MAC header (device reads on dword boundaries).
624 * We'll tell device about this padding later.
625 */
3832ec9d 626 len = sizeof(struct iwl3945_tx_cmd) +
4c897253 627 sizeof(struct iwl_cmd_header) + hdr_len;
b481de9c
ZY
628
629 len_org = len;
630 len = (len + 3) & ~3;
631
632 if (len_org != len)
633 len_org = 1;
634 else
635 len_org = 0;
636
6440adb5
CB
637 /* Physical address of this Tx command's header (not MAC header!),
638 * within command buffer array. */
df833b1d
RC
639 txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
640 len, PCI_DMA_TODEVICE);
641 /* we do not map meta data ... so we can safely access address to
642 * provide to unmap command*/
c2acea8e
JB
643 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
644 pci_unmap_len_set(out_meta, len, len);
b481de9c 645
6440adb5
CB
646 /* Add buffer containing Tx command and MAC(!) header to TFD's
647 * first entry */
7aaa1d79
SO
648 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
649 txcmd_phys, len, 1, 0);
b481de9c 650
b481de9c 651
6440adb5
CB
652 /* Set up TFD's 2nd entry to point directly to remainder of skb,
653 * if any (802.11 null frames have no payload). */
b481de9c
ZY
654 len = skb->len - hdr_len;
655 if (len) {
656 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
657 len, PCI_DMA_TODEVICE);
7aaa1d79
SO
658 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
659 phys_addr, len,
660 0, U32_PAD(len));
b481de9c
ZY
661 }
662
b481de9c 663
6440adb5 664 /* Tell device the write index *just past* this latest filled TFD */
c54b679d 665 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
7bfedc59 666 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
667 spin_unlock_irqrestore(&priv->lock, flags);
668
d20b3c65 669 if ((iwl_queue_space(q) < q->high_mark)
b481de9c
ZY
670 && priv->mac80211_registered) {
671 if (wait_write_ptr) {
672 spin_lock_irqsave(&priv->lock, flags);
673 txq->need_update = 1;
4f3602c8 674 iwl_txq_update_write_ptr(priv, txq);
b481de9c
ZY
675 spin_unlock_irqrestore(&priv->lock, flags);
676 }
677
e4e72fb4 678 iwl_stop_queue(priv, skb_get_queue_mapping(skb));
b481de9c
ZY
679 }
680
681 return 0;
682
683drop_unlock:
684 spin_unlock_irqrestore(&priv->lock, flags);
685drop:
686 return -1;
687}
688
b481de9c
ZY
689#define BEACON_TIME_MASK_LOW 0x00FFFFFF
690#define BEACON_TIME_MASK_HIGH 0xFF000000
691#define TIME_UNIT 1024
692
693/*
694 * extended beacon time format
695 * time in usec will be changed into a 32-bit value in 8:24 format
696 * the high 1 byte is the beacon counts
697 * the lower 3 bytes is the time in usec within one beacon interval
698 */
699
bb8c093b 700static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
b481de9c
ZY
701{
702 u32 quot;
703 u32 rem;
704 u32 interval = beacon_interval * 1024;
705
706 if (!interval || !usec)
707 return 0;
708
709 quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
710 rem = (usec % interval) & BEACON_TIME_MASK_LOW;
711
712 return (quot << 24) + rem;
713}
714
715/* base is usually what we get from ucode with each received frame,
716 * the same as HW timer counter counting down
717 */
718
bb8c093b 719static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
b481de9c
ZY
720{
721 u32 base_low = base & BEACON_TIME_MASK_LOW;
722 u32 addon_low = addon & BEACON_TIME_MASK_LOW;
723 u32 interval = beacon_interval * TIME_UNIT;
724 u32 res = (base & BEACON_TIME_MASK_HIGH) +
725 (addon & BEACON_TIME_MASK_HIGH);
726
727 if (base_low > addon_low)
728 res += base_low - addon_low;
729 else if (base_low < addon_low) {
730 res += interval + base_low - addon_low;
731 res += (1 << 24);
732 } else
733 res += (1 << 24);
734
735 return cpu_to_le32(res);
736}
737
4a8a4322 738static int iwl3945_get_measurement(struct iwl_priv *priv,
b481de9c
ZY
739 struct ieee80211_measurement_params *params,
740 u8 type)
741{
600c0e11 742 struct iwl_spectrum_cmd spectrum;
2f301227 743 struct iwl_rx_packet *pkt;
c2d79b48 744 struct iwl_host_cmd cmd = {
b481de9c
ZY
745 .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
746 .data = (void *)&spectrum,
c2acea8e 747 .flags = CMD_WANT_SKB,
b481de9c
ZY
748 };
749 u32 add_time = le64_to_cpu(params->start_time);
750 int rc;
751 int spectrum_resp_status;
752 int duration = le16_to_cpu(params->duration);
753
8ccde88a 754 if (iwl_is_associated(priv))
b481de9c 755 add_time =
bb8c093b 756 iwl3945_usecs_to_beacons(
b481de9c
ZY
757 le64_to_cpu(params->start_time) - priv->last_tsf,
758 le16_to_cpu(priv->rxon_timing.beacon_interval));
759
760 memset(&spectrum, 0, sizeof(spectrum));
761
762 spectrum.channel_count = cpu_to_le16(1);
763 spectrum.flags =
764 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
765 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
766 cmd.len = sizeof(spectrum);
767 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
768
8ccde88a 769 if (iwl_is_associated(priv))
b481de9c 770 spectrum.start_time =
bb8c093b 771 iwl3945_add_beacon_time(priv->last_beacon_time,
b481de9c
ZY
772 add_time,
773 le16_to_cpu(priv->rxon_timing.beacon_interval));
774 else
775 spectrum.start_time = 0;
776
777 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
778 spectrum.channels[0].channel = params->channel;
779 spectrum.channels[0].type = type;
8ccde88a 780 if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
b481de9c
ZY
781 spectrum.flags |= RXON_FLG_BAND_24G_MSK |
782 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
783
518099a8 784 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
785 if (rc)
786 return rc;
787
2f301227
ZY
788 pkt = (struct iwl_rx_packet *)cmd.reply_page;
789 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
15b1687c 790 IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
b481de9c
ZY
791 rc = -EIO;
792 }
793
2f301227 794 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
b481de9c
ZY
795 switch (spectrum_resp_status) {
796 case 0: /* Command will be handled */
2f301227 797 if (pkt->u.spectrum.id != 0xff) {
e1623446 798 IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
2f301227 799 pkt->u.spectrum.id);
b481de9c
ZY
800 priv->measurement_status &= ~MEASUREMENT_READY;
801 }
802 priv->measurement_status |= MEASUREMENT_ACTIVE;
803 rc = 0;
804 break;
805
806 case 1: /* Command will not be handled */
807 rc = -EAGAIN;
808 break;
809 }
810
64a76b50 811 iwl_free_pages(priv, cmd.reply_page);
b481de9c
ZY
812
813 return rc;
814}
b481de9c 815
4a8a4322 816static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
6100b588 817 struct iwl_rx_mem_buffer *rxb)
b481de9c 818{
2f301227 819 struct iwl_rx_packet *pkt = rxb_addr(rxb);
3d24a9f7 820 struct iwl_alive_resp *palive;
b481de9c
ZY
821 struct delayed_work *pwork;
822
823 palive = &pkt->u.alive_frame;
824
e1623446 825 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
826 "0x%01X 0x%01X\n",
827 palive->is_valid, palive->ver_type,
828 palive->ver_subtype);
829
830 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 831 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
3d24a9f7
TW
832 memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
833 sizeof(struct iwl_alive_resp));
b481de9c
ZY
834 pwork = &priv->init_alive_start;
835 } else {
e1623446 836 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 837 memcpy(&priv->card_alive, &pkt->u.alive_frame,
3d24a9f7 838 sizeof(struct iwl_alive_resp));
b481de9c 839 pwork = &priv->alive_start;
bb8c093b 840 iwl3945_disable_events(priv);
b481de9c
ZY
841 }
842
843 /* We delay the ALIVE response by 5ms to
844 * give the HW RF Kill time to activate... */
845 if (palive->is_valid == UCODE_VALID_OK)
846 queue_delayed_work(priv->workqueue, pwork,
847 msecs_to_jiffies(5));
848 else
39aadf8c 849 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
850}
851
4a8a4322 852static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
6100b588 853 struct iwl_rx_mem_buffer *rxb)
b481de9c 854{
c7e035a9 855#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 856 struct iwl_rx_packet *pkt = rxb_addr(rxb);
c7e035a9 857#endif
b481de9c 858
e1623446 859 IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
b481de9c
ZY
860 return;
861}
862
bb8c093b 863static void iwl3945_bg_beacon_update(struct work_struct *work)
b481de9c 864{
4a8a4322
AK
865 struct iwl_priv *priv =
866 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
867 struct sk_buff *beacon;
868
869 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 870 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
871
872 if (!beacon) {
15b1687c 873 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
874 return;
875 }
876
877 mutex_lock(&priv->mutex);
878 /* new beacon skb is allocated every time; dispose previous.*/
879 if (priv->ibss_beacon)
880 dev_kfree_skb(priv->ibss_beacon);
881
882 priv->ibss_beacon = beacon;
883 mutex_unlock(&priv->mutex);
884
bb8c093b 885 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
886}
887
4a8a4322 888static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
6100b588 889 struct iwl_rx_mem_buffer *rxb)
b481de9c 890{
d08853a3 891#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 892 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b 893 struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
b481de9c
ZY
894 u8 rate = beacon->beacon_notify_hdr.rate;
895
e1623446 896 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c
ZY
897 "tsf %d %d rate %d\n",
898 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
899 beacon->beacon_notify_hdr.failure_frame,
900 le32_to_cpu(beacon->ibss_mgr_status),
901 le32_to_cpu(beacon->high_tsf),
902 le32_to_cpu(beacon->low_tsf), rate);
903#endif
904
05c914fe 905 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
906 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
907 queue_work(priv->workqueue, &priv->beacon_update);
908}
909
b481de9c
ZY
910/* Handle notification from uCode that card's power state is changing
911 * due to software, hardware, or critical temperature RFKILL */
4a8a4322 912static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
6100b588 913 struct iwl_rx_mem_buffer *rxb)
b481de9c 914{
2f301227 915 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
916 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
917 unsigned long status = priv->status;
918
4c423a2b 919 IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
920 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
921 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
922
5d49f498 923 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
924 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
925
926 if (flags & HW_CARD_DISABLED)
927 set_bit(STATUS_RF_KILL_HW, &priv->status);
928 else
929 clear_bit(STATUS_RF_KILL_HW, &priv->status);
930
931
af0053d6 932 iwl_scan_cancel(priv);
b481de9c
ZY
933
934 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
935 test_bit(STATUS_RF_KILL_HW, &priv->status)))
936 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
937 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
938 else
939 wake_up_interruptible(&priv->wait_command_queue);
940}
941
942/**
bb8c093b 943 * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
944 *
945 * Setup the RX handlers for each of the reply types sent from the uCode
946 * to the host.
947 *
948 * This function chains into the hardware specific files for them to setup
949 * any hardware specific handlers as well.
950 */
4a8a4322 951static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 952{
bb8c093b
CH
953 priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
954 priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
261b9c33 955 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
8ccde88a 956 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC
957 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
958 iwl_rx_spectrum_measure_notif;
030f05ed 959 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 960 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
030f05ed 961 iwl_rx_pm_debug_statistics_notif;
bb8c093b 962 priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
b481de9c 963
9fbab516
BC
964 /*
965 * The same handler is used for both the REPLY to a discrete
966 * statistics request from the host as well as for the periodic
967 * statistics notifications (after received beacons) from the uCode.
b481de9c 968 */
bb8c093b
CH
969 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
970 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
b481de9c 971
cade0eb2 972 iwl_setup_rx_scan_handlers(priv);
bb8c093b 973 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
b481de9c 974
9fbab516 975 /* Set up hardware specific Rx handlers */
bb8c093b 976 iwl3945_hw_rx_handler_setup(priv);
b481de9c
ZY
977}
978
b481de9c
ZY
979/************************** RX-FUNCTIONS ****************************/
980/*
981 * Rx theory of operation
982 *
983 * The host allocates 32 DMA target addresses and passes the host address
984 * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
985 * 0 to 31
986 *
987 * Rx Queue Indexes
988 * The host/firmware share two index registers for managing the Rx buffers.
989 *
990 * The READ index maps to the first position that the firmware may be writing
991 * to -- the driver can read up to (but not including) this position and get
992 * good data.
993 * The READ index is managed by the firmware once the card is enabled.
994 *
995 * The WRITE index maps to the last position the driver has read from -- the
996 * position preceding WRITE is the last slot the firmware can place a packet.
997 *
998 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
999 * WRITE = READ.
1000 *
9fbab516 1001 * During initialization, the host sets up the READ queue position to the first
b481de9c
ZY
1002 * INDEX position, and WRITE to the last (READ - 1 wrapped)
1003 *
9fbab516 1004 * When the firmware places a packet in a buffer, it will advance the READ index
b481de9c
ZY
1005 * and fire the RX interrupt. The driver can then query the READ index and
1006 * process as many packets as possible, moving the WRITE index forward as it
1007 * resets the Rx queue buffers with new memory.
1008 *
1009 * The management in the driver is as follows:
1010 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
1011 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
01ebd063 1012 * to replenish the iwl->rxq->rx_free.
bb8c093b 1013 * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
b481de9c
ZY
1014 * iwl->rxq is replenished and the READ INDEX is updated (updating the
1015 * 'processed' and 'read' driver indexes as well)
1016 * + A received packet is processed and handed to the kernel network stack,
1017 * detached from the iwl->rxq. The driver 'processed' index is updated.
1018 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
1019 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
1020 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
1021 * were enough free buffers and RX_STALLED is set it is cleared.
1022 *
1023 *
1024 * Driver sequence:
1025 *
9fbab516 1026 * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
bb8c093b 1027 * iwl3945_rx_queue_restock
9fbab516 1028 * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
b481de9c
ZY
1029 * queue, updates firmware pointers, and updates
1030 * the WRITE index. If insufficient rx_free buffers
bb8c093b 1031 * are available, schedules iwl3945_rx_replenish
b481de9c
ZY
1032 *
1033 * -- enable interrupts --
6100b588 1034 * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
b481de9c
ZY
1035 * READ INDEX, detaching the SKB from the pool.
1036 * Moves the packet buffer from queue to rx_used.
bb8c093b 1037 * Calls iwl3945_rx_queue_restock to refill any empty
b481de9c
ZY
1038 * slots.
1039 * ...
1040 *
1041 */
1042
b481de9c 1043/**
9fbab516 1044 * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
b481de9c 1045 */
4a8a4322 1046static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
b481de9c
ZY
1047 dma_addr_t dma_addr)
1048{
1049 return cpu_to_le32((u32)dma_addr);
1050}
1051
1052/**
bb8c093b 1053 * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
b481de9c 1054 *
9fbab516 1055 * If there are slots in the RX queue that need to be restocked,
b481de9c 1056 * and we have free pre-allocated buffers, fill the ranks as much
9fbab516 1057 * as we can, pulling from rx_free.
b481de9c
ZY
1058 *
1059 * This moves the 'write' index forward to catch up with 'processed', and
1060 * also updates the memory address in the firmware to reference the new
1061 * target buffer.
1062 */
7bfedc59 1063static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
b481de9c 1064{
cc2f362c 1065 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1066 struct list_head *element;
6100b588 1067 struct iwl_rx_mem_buffer *rxb;
b481de9c 1068 unsigned long flags;
7bfedc59 1069 int write;
b481de9c
ZY
1070
1071 spin_lock_irqsave(&rxq->lock, flags);
1072 write = rxq->write & ~0x7;
37d68317 1073 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6440adb5 1074 /* Get next free Rx buffer, remove from free list */
b481de9c 1075 element = rxq->rx_free.next;
6100b588 1076 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
b481de9c 1077 list_del(element);
6440adb5
CB
1078
1079 /* Point to Rx buffer via next RBD in circular buffer */
2f301227 1080 rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
b481de9c
ZY
1081 rxq->queue[rxq->write] = rxb;
1082 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
1083 rxq->free_count--;
1084 }
1085 spin_unlock_irqrestore(&rxq->lock, flags);
1086 /* If the pre-allocated buffer pool is dropping low, schedule to
1087 * refill it */
1088 if (rxq->free_count <= RX_LOW_WATERMARK)
1089 queue_work(priv->workqueue, &priv->rx_replenish);
1090
1091
6440adb5
CB
1092 /* If we've added more space for the firmware to place data, tell it.
1093 * Increment device's write pointer in multiples of 8. */
d14d4440 1094 if ((rxq->write_actual != (rxq->write & ~0x7))
b481de9c
ZY
1095 || (abs(rxq->write - rxq->read) > 7)) {
1096 spin_lock_irqsave(&rxq->lock, flags);
1097 rxq->need_update = 1;
1098 spin_unlock_irqrestore(&rxq->lock, flags);
7bfedc59 1099 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c 1100 }
b481de9c
ZY
1101}
1102
1103/**
bb8c093b 1104 * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
b481de9c
ZY
1105 *
1106 * When moving to rx_free an SKB is allocated for the slot.
1107 *
bb8c093b 1108 * Also restock the Rx queue via iwl3945_rx_queue_restock.
01ebd063 1109 * This is called as a scheduled work item (except for during initialization)
b481de9c 1110 */
d14d4440 1111static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
b481de9c 1112{
cc2f362c 1113 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c 1114 struct list_head *element;
6100b588 1115 struct iwl_rx_mem_buffer *rxb;
2f301227 1116 struct page *page;
b481de9c 1117 unsigned long flags;
29b1b268 1118 gfp_t gfp_mask = priority;
72240498
AK
1119
1120 while (1) {
1121 spin_lock_irqsave(&rxq->lock, flags);
1122
1123 if (list_empty(&rxq->rx_used)) {
1124 spin_unlock_irqrestore(&rxq->lock, flags);
1125 return;
1126 }
72240498 1127 spin_unlock_irqrestore(&rxq->lock, flags);
6440adb5 1128
f82a924c 1129 if (rxq->free_count > RX_LOW_WATERMARK)
29b1b268 1130 gfp_mask |= __GFP_NOWARN;
2f301227
ZY
1131
1132 if (priv->hw_params.rx_page_order > 0)
29b1b268 1133 gfp_mask |= __GFP_COMP;
2f301227 1134
6440adb5 1135 /* Alloc a new receive buffer */
29b1b268 1136 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
2f301227 1137 if (!page) {
b481de9c 1138 if (net_ratelimit())
f82a924c
RC
1139 IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
1140 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
1141 net_ratelimit())
1142 IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
1143 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
1144 rxq->free_count);
b481de9c
ZY
1145 /* We don't reschedule replenish work here -- we will
1146 * call the restock method and if it still needs
1147 * more buffers it will schedule replenish */
1148 break;
1149 }
12342c47 1150
de0bd508
RC
1151 spin_lock_irqsave(&rxq->lock, flags);
1152 if (list_empty(&rxq->rx_used)) {
1153 spin_unlock_irqrestore(&rxq->lock, flags);
2f301227 1154 __free_pages(page, priv->hw_params.rx_page_order);
de0bd508
RC
1155 return;
1156 }
1157 element = rxq->rx_used.next;
1158 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
1159 list_del(element);
1160 spin_unlock_irqrestore(&rxq->lock, flags);
1161
2f301227 1162 rxb->page = page;
6440adb5 1163 /* Get physical address of RB/SKB */
2f301227
ZY
1164 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
1165 PAGE_SIZE << priv->hw_params.rx_page_order,
1166 PCI_DMA_FROMDEVICE);
72240498
AK
1167
1168 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1169
b481de9c
ZY
1170 list_add_tail(&rxb->list, &rxq->rx_free);
1171 rxq->free_count++;
2f301227
ZY
1172 priv->alloc_rxb_page++;
1173
72240498 1174 spin_unlock_irqrestore(&rxq->lock, flags);
b481de9c 1175 }
5c0eef96
MA
1176}
1177
df833b1d
RC
1178void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1179{
1180 unsigned long flags;
1181 int i;
1182 spin_lock_irqsave(&rxq->lock, flags);
1183 INIT_LIST_HEAD(&rxq->rx_free);
1184 INIT_LIST_HEAD(&rxq->rx_used);
1185 /* Fill the rx_used queue with _all_ of the Rx buffers */
1186 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1187 /* In the reset function, these buffers may have been allocated
1188 * to an SKB, so we need to unmap and free potential storage */
2f301227
ZY
1189 if (rxq->pool[i].page != NULL) {
1190 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1191 PAGE_SIZE << priv->hw_params.rx_page_order,
1192 PCI_DMA_FROMDEVICE);
64a76b50 1193 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1194 rxq->pool[i].page = NULL;
df833b1d
RC
1195 }
1196 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1197 }
1198
1199 /* Set us so that we have processed and used all buffers, but have
1200 * not restocked the Rx queue with fresh buffers */
1201 rxq->read = rxq->write = 0;
d14d4440 1202 rxq->write_actual = 0;
2f301227 1203 rxq->free_count = 0;
df833b1d
RC
1204 spin_unlock_irqrestore(&rxq->lock, flags);
1205}
df833b1d 1206
5c0eef96
MA
1207void iwl3945_rx_replenish(void *data)
1208{
4a8a4322 1209 struct iwl_priv *priv = data;
5c0eef96
MA
1210 unsigned long flags;
1211
d14d4440 1212 iwl3945_rx_allocate(priv, GFP_KERNEL);
b481de9c
ZY
1213
1214 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1215 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1216 spin_unlock_irqrestore(&priv->lock, flags);
1217}
1218
d14d4440
AK
1219static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
1220{
1221 iwl3945_rx_allocate(priv, GFP_ATOMIC);
1222
1223 iwl3945_rx_queue_restock(priv);
1224}
1225
1226
df833b1d
RC
1227/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
1228 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
1229 * This free routine walks the list of POOL entries and if SKB is set to
1230 * non NULL it is unmapped and freed
1231 */
1232static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
1233{
1234 int i;
1235 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
2f301227
ZY
1236 if (rxq->pool[i].page != NULL) {
1237 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
1238 PAGE_SIZE << priv->hw_params.rx_page_order,
1239 PCI_DMA_FROMDEVICE);
64a76b50 1240 __iwl_free_pages(priv, rxq->pool[i].page);
2f301227 1241 rxq->pool[i].page = NULL;
df833b1d
RC
1242 }
1243 }
1244
f36d04ab
SG
1245 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1246 rxq->dma_addr);
1247 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
1248 rxq->rb_stts, rxq->rb_stts_dma);
df833b1d
RC
1249 rxq->bd = NULL;
1250 rxq->rb_stts = NULL;
1251}
df833b1d
RC
1252
1253
b481de9c
ZY
1254/* Convert linear signal-to-noise ratio into dB */
1255static u8 ratio2dB[100] = {
1256/* 0 1 2 3 4 5 6 7 8 9 */
1257 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
1258 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
1259 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
1260 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
1261 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
1262 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
1263 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
1264 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
1265 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
1266 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
1267};
1268
1269/* Calculates a relative dB value from a ratio of linear
1270 * (i.e. not dB) signal levels.
1271 * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
bb8c093b 1272int iwl3945_calc_db_from_ratio(int sig_ratio)
b481de9c 1273{
221c80cf
AB
1274 /* 1000:1 or higher just report as 60 dB */
1275 if (sig_ratio >= 1000)
b481de9c
ZY
1276 return 60;
1277
221c80cf 1278 /* 100:1 or higher, divide by 10 and use table,
b481de9c 1279 * add 20 dB to make up for divide by 10 */
221c80cf 1280 if (sig_ratio >= 100)
3ac7f146 1281 return 20 + (int)ratio2dB[sig_ratio/10];
b481de9c
ZY
1282
1283 /* We shouldn't see this */
1284 if (sig_ratio < 1)
1285 return 0;
1286
1287 /* Use table for ratios 1:1 - 99:1 */
1288 return (int)ratio2dB[sig_ratio];
1289}
1290
b481de9c 1291/**
9fbab516 1292 * iwl3945_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
1293 *
1294 * Uses the priv->rx_handlers callback function array to invoke
1295 * the appropriate handlers, including command responses,
1296 * frame-received notifications, and other notifications.
1297 */
4a8a4322 1298static void iwl3945_rx_handle(struct iwl_priv *priv)
b481de9c 1299{
6100b588 1300 struct iwl_rx_mem_buffer *rxb;
3d24a9f7 1301 struct iwl_rx_packet *pkt;
cc2f362c 1302 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
1303 u32 r, i;
1304 int reclaim;
1305 unsigned long flags;
5c0eef96 1306 u8 fill_rx = 0;
d68ab680 1307 u32 count = 8;
d14d4440 1308 int total_empty = 0;
b481de9c 1309
6440adb5
CB
1310 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1311 * buffer that the driver may process (last buffer filled by ucode). */
8cd812bc 1312 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
1313 i = rxq->read;
1314
d14d4440 1315 /* calculate total frames need to be restock after handling RX */
7300515d 1316 total_empty = r - rxq->write_actual;
d14d4440
AK
1317 if (total_empty < 0)
1318 total_empty += RX_QUEUE_SIZE;
1319
1320 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96 1321 fill_rx = 1;
b481de9c
ZY
1322 /* Rx interrupt, but nothing sent from uCode */
1323 if (i == r)
af472a95 1324 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c
ZY
1325
1326 while (i != r) {
1327 rxb = rxq->queue[i];
1328
9fbab516 1329 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
1330 * then a bug has been introduced in the queue refilling
1331 * routines -- catch it here */
1332 BUG_ON(rxb == NULL);
1333
1334 rxq->queue[i] = NULL;
1335
2f301227
ZY
1336 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1337 PAGE_SIZE << priv->hw_params.rx_page_order,
1338 PCI_DMA_FROMDEVICE);
1339 pkt = rxb_addr(rxb);
b481de9c 1340
be1a71a1
JB
1341 trace_iwlwifi_dev_rx(priv, pkt,
1342 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
1343
b481de9c
ZY
1344 /* Reclaim a command buffer only if this packet is a response
1345 * to a (driver-originated) command.
1346 * If the packet (e.g. Rx frame) originated from uCode,
1347 * there is no command buffer to reclaim.
1348 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1349 * but apparently a few don't get set; catch them here. */
1350 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1351 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1352 (pkt->hdr.cmd != REPLY_TX);
1353
1354 /* Based on type of command response or notification,
1355 * handle those that need handling via function in
bb8c093b 1356 * rx_handlers table. See iwl3945_setup_rx_handlers() */
b481de9c 1357 if (priv->rx_handlers[pkt->hdr.cmd]) {
af472a95 1358 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
b481de9c 1359 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
86ddbf62 1360 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1361 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
1362 } else {
1363 /* No handling needed */
2f301227
ZY
1364 IWL_DEBUG_RX(priv,
1365 "r %d i %d No handler needed for %s, 0x%02x\n",
b481de9c
ZY
1366 r, i, get_cmd_string(pkt->hdr.cmd),
1367 pkt->hdr.cmd);
1368 }
1369
29b1b268
ZY
1370 /*
1371 * XXX: After here, we should always check rxb->page
1372 * against NULL before touching it or its virtual
1373 * memory (pkt). Because some rx_handler might have
1374 * already taken or freed the pages.
1375 */
1376
b481de9c 1377 if (reclaim) {
2f301227
ZY
1378 /* Invoke any callbacks, transfer the buffer to caller,
1379 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1380 * as we reclaim the driver command queue */
29b1b268 1381 if (rxb->page)
732587ab 1382 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1383 else
39aadf8c 1384 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
1385 }
1386
7300515d
ZY
1387 /* Reuse the page if possible. For notification packets and
1388 * SKBs that fail to Rx correctly, add them back into the
1389 * rx_free list for reuse later. */
1390 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1391 if (rxb->page != NULL) {
7300515d
ZY
1392 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1393 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1394 PCI_DMA_FROMDEVICE);
1395 list_add_tail(&rxb->list, &rxq->rx_free);
1396 rxq->free_count++;
1397 } else
1398 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1399
b481de9c 1400 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1401
b481de9c 1402 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
1403 /* If there are a lot of unused frames,
1404 * restock the Rx queue so ucode won't assert. */
1405 if (fill_rx) {
1406 count++;
1407 if (count >= 8) {
7300515d 1408 rxq->read = i;
d14d4440 1409 iwl3945_rx_replenish_now(priv);
5c0eef96
MA
1410 count = 0;
1411 }
1412 }
b481de9c
ZY
1413 }
1414
1415 /* Backtrack one entry */
7300515d 1416 rxq->read = i;
d14d4440
AK
1417 if (fill_rx)
1418 iwl3945_rx_replenish_now(priv);
1419 else
1420 iwl3945_rx_queue_restock(priv);
b481de9c
ZY
1421}
1422
0359facc 1423/* call this function to flush any scheduled tasklet */
4a8a4322 1424static inline void iwl_synchronize_irq(struct iwl_priv *priv)
0359facc 1425{
a96a27f9 1426 /* wait to make sure we flush pending tasklet*/
0359facc
MA
1427 synchronize_irq(priv->pci_dev->irq);
1428 tasklet_kill(&priv->irq_tasklet);
1429}
1430
b481de9c
ZY
1431static const char *desc_lookup(int i)
1432{
1433 switch (i) {
1434 case 1:
1435 return "FAIL";
1436 case 2:
1437 return "BAD_PARAM";
1438 case 3:
1439 return "BAD_CHECKSUM";
1440 case 4:
1441 return "NMI_INTERRUPT";
1442 case 5:
1443 return "SYSASSERT";
1444 case 6:
1445 return "FATAL_ERROR";
1446 }
1447
1448 return "UNKNOWN";
1449}
1450
1451#define ERROR_START_OFFSET (1 * sizeof(u32))
1452#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1453
b7a79404 1454void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
b481de9c
ZY
1455{
1456 u32 i;
1457 u32 desc, time, count, base, data1;
1458 u32 blink1, blink2, ilink1, ilink2;
b481de9c
ZY
1459
1460 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1461
bb8c093b 1462 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1463 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
b481de9c
ZY
1464 return;
1465 }
1466
b481de9c 1467
5d49f498 1468 count = iwl_read_targ_mem(priv, base);
b481de9c
ZY
1469
1470 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
15b1687c
WT
1471 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1472 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1473 priv->status, count);
b481de9c
ZY
1474 }
1475
15b1687c 1476 IWL_ERR(priv, "Desc Time asrtPC blink2 "
b481de9c
ZY
1477 "ilink1 nmiPC Line\n");
1478 for (i = ERROR_START_OFFSET;
1479 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1480 i += ERROR_ELEM_SIZE) {
5d49f498 1481 desc = iwl_read_targ_mem(priv, base + i);
b481de9c 1482 time =
5d49f498 1483 iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
b481de9c 1484 blink1 =
5d49f498 1485 iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
b481de9c 1486 blink2 =
5d49f498 1487 iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
b481de9c 1488 ilink1 =
5d49f498 1489 iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
b481de9c 1490 ilink2 =
5d49f498 1491 iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
b481de9c 1492 data1 =
5d49f498 1493 iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
b481de9c 1494
15b1687c
WT
1495 IWL_ERR(priv,
1496 "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1497 desc_lookup(desc), desc, time, blink1, blink2,
1498 ilink1, ilink2, data1);
be1a71a1
JB
1499 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
1500 0, blink1, blink2, ilink1, ilink2);
b481de9c 1501 }
b481de9c
ZY
1502}
1503
f58177b9 1504#define EVENT_START_OFFSET (6 * sizeof(u32))
b481de9c
ZY
1505
1506/**
bb8c093b 1507 * iwl3945_print_event_log - Dump error event log to syslog
b481de9c 1508 *
b481de9c 1509 */
b03d7d0f
WYG
1510static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1511 u32 num_events, u32 mode,
1512 int pos, char **buf, size_t bufsz)
b481de9c
ZY
1513{
1514 u32 i;
1515 u32 base; /* SRAM byte address of event log header */
1516 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1517 u32 ptr; /* SRAM byte address of log data */
1518 u32 ev, time, data; /* event log data */
e5854471 1519 unsigned long reg_flags;
b481de9c
ZY
1520
1521 if (num_events == 0)
b03d7d0f 1522 return pos;
b481de9c
ZY
1523
1524 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1525
1526 if (mode == 0)
1527 event_size = 2 * sizeof(u32);
1528 else
1529 event_size = 3 * sizeof(u32);
1530
1531 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1532
e5854471
BC
1533 /* Make sure device is powered up for SRAM reads */
1534 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1535 iwl_grab_nic_access(priv);
1536
1537 /* Set starting address; reads will auto-increment */
1538 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1539 rmb();
1540
b481de9c
ZY
1541 /* "time" is actually "data" for mode 0 (no timestamp).
1542 * place event id # at far right for easier visual parsing. */
1543 for (i = 0; i < num_events; i++) {
e5854471
BC
1544 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1545 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
15b1687c
WT
1546 if (mode == 0) {
1547 /* data, ev */
b03d7d0f
WYG
1548 if (bufsz) {
1549 pos += scnprintf(*buf + pos, bufsz - pos,
1550 "0x%08x:%04u\n",
1551 time, ev);
1552 } else {
1553 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1554 trace_iwlwifi_dev_ucode_event(priv, 0,
1555 time, ev);
1556 }
15b1687c 1557 } else {
e5854471 1558 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1559 if (bufsz) {
1560 pos += scnprintf(*buf + pos, bufsz - pos,
1561 "%010u:0x%08x:%04u\n",
1562 time, data, ev);
1563 } else {
1564 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1565 time, data, ev);
1566 trace_iwlwifi_dev_ucode_event(priv, time,
1567 data, ev);
1568 }
b481de9c
ZY
1569 }
1570 }
e5854471
BC
1571
1572 /* Allow device to power down */
1573 iwl_release_nic_access(priv);
1574 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1575 return pos;
b481de9c
ZY
1576}
1577
c341ddb2
WYG
1578/**
1579 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1580 */
b03d7d0f 1581static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
c341ddb2 1582 u32 num_wraps, u32 next_entry,
b03d7d0f
WYG
1583 u32 size, u32 mode,
1584 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1585{
1586 /*
1587 * display the newest DEFAULT_LOG_ENTRIES entries
1588 * i.e the entries just before the next ont that uCode would fill.
1589 */
1590 if (num_wraps) {
1591 if (next_entry < size) {
b03d7d0f
WYG
1592 pos = iwl3945_print_event_log(priv,
1593 capacity - (size - next_entry),
1594 size - next_entry, mode,
1595 pos, buf, bufsz);
1596 pos = iwl3945_print_event_log(priv, 0,
1597 next_entry, mode,
1598 pos, buf, bufsz);
c341ddb2 1599 } else
b03d7d0f
WYG
1600 pos = iwl3945_print_event_log(priv, next_entry - size,
1601 size, mode,
1602 pos, buf, bufsz);
c341ddb2
WYG
1603 } else {
1604 if (next_entry < size)
b03d7d0f
WYG
1605 pos = iwl3945_print_event_log(priv, 0,
1606 next_entry, mode,
1607 pos, buf, bufsz);
c341ddb2 1608 else
b03d7d0f
WYG
1609 pos = iwl3945_print_event_log(priv, next_entry - size,
1610 size, mode,
1611 pos, buf, bufsz);
c341ddb2 1612 }
b03d7d0f 1613 return pos;
c341ddb2
WYG
1614}
1615
84c40692
BC
1616/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1617#define IWL3945_MAX_EVENT_LOG_SIZE (512)
1618
c341ddb2
WYG
1619#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1620
b03d7d0f
WYG
1621int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1622 char **buf, bool display)
b481de9c 1623{
b481de9c
ZY
1624 u32 base; /* SRAM byte address of event log header */
1625 u32 capacity; /* event log capacity in # entries */
1626 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1627 u32 num_wraps; /* # times uCode wrapped to top of log */
1628 u32 next_entry; /* index of next entry to be written by uCode */
1629 u32 size; /* # entries that we'll print */
b03d7d0f
WYG
1630 int pos = 0;
1631 size_t bufsz = 0;
b481de9c
ZY
1632
1633 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 1634 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 1635 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
937c397e 1636 return -EINVAL;
b481de9c
ZY
1637 }
1638
b481de9c 1639 /* event log header */
5d49f498
AK
1640 capacity = iwl_read_targ_mem(priv, base);
1641 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1642 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1643 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
b481de9c 1644
84c40692
BC
1645 if (capacity > IWL3945_MAX_EVENT_LOG_SIZE) {
1646 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1647 capacity, IWL3945_MAX_EVENT_LOG_SIZE);
1648 capacity = IWL3945_MAX_EVENT_LOG_SIZE;
1649 }
1650
1651 if (next_entry > IWL3945_MAX_EVENT_LOG_SIZE) {
1652 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1653 next_entry, IWL3945_MAX_EVENT_LOG_SIZE);
1654 next_entry = IWL3945_MAX_EVENT_LOG_SIZE;
1655 }
1656
b481de9c
ZY
1657 size = num_wraps ? capacity : next_entry;
1658
1659 /* bail out if nothing in log */
1660 if (size == 0) {
15b1687c 1661 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1662 return pos;
b481de9c
ZY
1663 }
1664
c341ddb2 1665#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1666 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1667 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1668 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1669#else
1670 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1671 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1672#endif
1673
1674 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1675 size);
b481de9c 1676
c341ddb2 1677#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1678 if (display) {
1679 if (full_log)
1680 bufsz = capacity * 48;
1681 else
1682 bufsz = size * 48;
1683 *buf = kmalloc(bufsz, GFP_KERNEL);
1684 if (!*buf)
937c397e 1685 return -ENOMEM;
b03d7d0f 1686 }
c341ddb2
WYG
1687 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1688 /* if uCode has wrapped back to top of log,
1689 * start at the oldest entry,
1690 * i.e the next one that uCode would fill.
1691 */
1692 if (num_wraps)
b03d7d0f
WYG
1693 pos = iwl3945_print_event_log(priv, next_entry,
1694 capacity - next_entry, mode,
1695 pos, buf, bufsz);
c341ddb2
WYG
1696
1697 /* (then/else) start at top of log */
b03d7d0f
WYG
1698 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1699 pos, buf, bufsz);
c341ddb2 1700 } else
b03d7d0f
WYG
1701 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1702 next_entry, size, mode,
1703 pos, buf, bufsz);
b7a79404 1704#else
b03d7d0f
WYG
1705 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1706 next_entry, size, mode,
1707 pos, buf, bufsz);
c341ddb2 1708#endif
b03d7d0f 1709 return pos;
b7a79404
RC
1710}
1711
4a8a4322 1712static void iwl3945_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY
1713{
1714 u32 inta, handled = 0;
1715 u32 inta_fh;
1716 unsigned long flags;
d08853a3 1717#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
1718 u32 inta_mask;
1719#endif
1720
1721 spin_lock_irqsave(&priv->lock, flags);
1722
1723 /* Ack/clear/reset pending uCode interrupts.
1724 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1725 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
5d49f498
AK
1726 inta = iwl_read32(priv, CSR_INT);
1727 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
1728
1729 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1730 * Any new interrupts that happen after this, either while we're
1731 * in this tasklet, or later, will show up in next ISR/tasklet. */
5d49f498
AK
1732 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1733 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1734
d08853a3 1735#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1736 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1737 /* just for debug */
5d49f498 1738 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1739 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
1740 inta, inta_mask, inta_fh);
1741 }
1742#endif
1743
2f301227
ZY
1744 spin_unlock_irqrestore(&priv->lock, flags);
1745
b481de9c
ZY
1746 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1747 * atomic, make sure that inta covers all the interrupts that
1748 * we've discovered, even if FH interrupt came in just after
1749 * reading CSR_INT. */
6f83eaa1 1750 if (inta_fh & CSR39_FH_INT_RX_MASK)
b481de9c 1751 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1752 if (inta_fh & CSR39_FH_INT_TX_MASK)
b481de9c
ZY
1753 inta |= CSR_INT_BIT_FH_TX;
1754
1755 /* Now service all interrupt bits discovered above. */
1756 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1757 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
1758
1759 /* Tell the device to stop sending interrupts */
ed3b932e 1760 iwl_disable_interrupts(priv);
b481de9c 1761
86ddbf62 1762 priv->isr_stats.hw++;
8ccde88a 1763 iwl_irq_handle_error(priv);
b481de9c
ZY
1764
1765 handled |= CSR_INT_BIT_HW_ERR;
1766
b481de9c
ZY
1767 return;
1768 }
1769
d08853a3 1770#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1771 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1772 /* NIC fires this, but we don't use it, redundant with WAKEUP */
86ddbf62 1773 if (inta & CSR_INT_BIT_SCD) {
e1623446 1774 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1775 "the frame/frames.\n");
86ddbf62
AK
1776 priv->isr_stats.sch++;
1777 }
b481de9c
ZY
1778
1779 /* Alive notification via Rx interrupt will do the real work */
86ddbf62 1780 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1781 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
86ddbf62
AK
1782 priv->isr_stats.alive++;
1783 }
b481de9c
ZY
1784 }
1785#endif
1786 /* Safely ignore these bits for debug checks below */
25c03d8e 1787 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1788
b481de9c
ZY
1789 /* Error detected by uCode */
1790 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1791 IWL_ERR(priv, "Microcode SW error detected. "
1792 "Restarting 0x%X.\n", inta);
86ddbf62
AK
1793 priv->isr_stats.sw++;
1794 priv->isr_stats.sw_err = inta;
8ccde88a 1795 iwl_irq_handle_error(priv);
b481de9c
ZY
1796 handled |= CSR_INT_BIT_SW_ERR;
1797 }
1798
1799 /* uCode wakes up after power-down sleep */
1800 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1801 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
141c43a3 1802 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
4f3602c8
SO
1803 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1804 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1805 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1806 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1807 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1808 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1809
86ddbf62 1810 priv->isr_stats.wakeup++;
b481de9c
ZY
1811 handled |= CSR_INT_BIT_WAKEUP;
1812 }
1813
1814 /* All uCode command responses, including Tx command responses,
1815 * Rx "responses" (frame-received notification), and other
1816 * notifications from uCode come through here*/
1817 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
bb8c093b 1818 iwl3945_rx_handle(priv);
86ddbf62 1819 priv->isr_stats.rx++;
b481de9c
ZY
1820 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1821 }
1822
1823 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1824 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
86ddbf62 1825 priv->isr_stats.tx++;
b481de9c 1826
5d49f498 1827 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
a8b50a0a
MA
1828 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1829 (FH39_SRVC_CHNL), 0x0);
b481de9c
ZY
1830 handled |= CSR_INT_BIT_FH_TX;
1831 }
1832
86ddbf62 1833 if (inta & ~handled) {
15b1687c 1834 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
86ddbf62
AK
1835 priv->isr_stats.unhandled++;
1836 }
b481de9c 1837
40cefda9 1838 if (inta & ~priv->inta_mask) {
39aadf8c 1839 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1840 inta & ~priv->inta_mask);
39aadf8c 1841 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1842 }
1843
1844 /* Re-enable all interrupts */
0359facc
MA
1845 /* only Re-enable if disabled by irq */
1846 if (test_bit(STATUS_INT_ENABLED, &priv->status))
ed3b932e 1847 iwl_enable_interrupts(priv);
b481de9c 1848
d08853a3 1849#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1850 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
5d49f498
AK
1851 inta = iwl_read32(priv, CSR_INT);
1852 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1853 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1854 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1855 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1856 }
1857#endif
b481de9c
ZY
1858}
1859
4a8a4322 1860static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
8318d78a 1861 enum ieee80211_band band,
f9340520 1862 u8 is_active, u8 n_probes,
bb8c093b 1863 struct iwl3945_scan_channel *scan_ch)
b481de9c 1864{
4e05c234 1865 struct ieee80211_channel *chan;
8318d78a 1866 const struct ieee80211_supported_band *sband;
d20b3c65 1867 const struct iwl_channel_info *ch_info;
b481de9c
ZY
1868 u16 passive_dwell = 0;
1869 u16 active_dwell = 0;
1870 int added, i;
1871
cbba18c6 1872 sband = iwl_get_hw_mode(priv, band);
8318d78a 1873 if (!sband)
b481de9c
ZY
1874 return 0;
1875
77fecfb8
SO
1876 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1877 passive_dwell = iwl_get_passive_dwell_time(priv, band);
b481de9c 1878
8f4807a1
AK
1879 if (passive_dwell <= active_dwell)
1880 passive_dwell = active_dwell + 1;
1881
4e05c234
JB
1882 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1883 chan = priv->scan_request->channels[i];
1884
1885 if (chan->band != band)
182e2e66
JB
1886 continue;
1887
4e05c234 1888 scan_ch->channel = chan->hw_value;
b481de9c 1889
e6148917 1890 ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
b481de9c 1891 if (!is_channel_valid(ch_info)) {
e1623446 1892 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
b481de9c
ZY
1893 scan_ch->channel);
1894 continue;
1895 }
1896
011a0330
AK
1897 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1898 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1899 /* If passive , set up for auto-switch
1900 * and use long active_dwell time.
1901 */
b481de9c 1902 if (!is_active || is_channel_passive(ch_info) ||
4e05c234 1903 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
b481de9c 1904 scan_ch->type = 0; /* passive */
011a0330
AK
1905 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1906 scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
1907 } else {
b481de9c 1908 scan_ch->type = 1; /* active */
011a0330 1909 }
b481de9c 1910
011a0330
AK
1911 /* Set direct probe bits. These may be used both for active
1912 * scan channels (probes gets sent right away),
1913 * or for passive channels (probes get se sent only after
1914 * hearing clear Rx packet).*/
1915 if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
1916 if (n_probes)
0d21044e 1917 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330
AK
1918 } else {
1919 /* uCode v1 does not allow setting direct probe bits on
1920 * passive channel. */
1921 if ((scan_ch->type & 1) && n_probes)
0d21044e 1922 scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
011a0330 1923 }
b481de9c 1924
9fbab516 1925 /* Set txpower levels to defaults */
b481de9c
ZY
1926 scan_ch->tpc.dsp_atten = 110;
1927 /* scan_pwr_info->tpc.dsp_atten; */
1928
1929 /*scan_pwr_info->tpc.tx_gain; */
8318d78a 1930 if (band == IEEE80211_BAND_5GHZ)
b481de9c
ZY
1931 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1932 else {
1933 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1934 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
9fbab516 1935 * power level:
8a1b0245 1936 * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
b481de9c
ZY
1937 */
1938 }
1939
e1623446 1940 IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
b481de9c
ZY
1941 scan_ch->channel,
1942 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1943 (scan_ch->type & 1) ?
1944 active_dwell : passive_dwell);
1945
1946 scan_ch++;
1947 added++;
1948 }
1949
e1623446 1950 IWL_DEBUG_SCAN(priv, "total channels to scan %d \n", added);
b481de9c
ZY
1951 return added;
1952}
1953
4a8a4322 1954static void iwl3945_init_hw_rates(struct iwl_priv *priv,
b481de9c
ZY
1955 struct ieee80211_rate *rates)
1956{
1957 int i;
1958
1959 for (i = 0; i < IWL_RATE_COUNT; i++) {
8318d78a
JB
1960 rates[i].bitrate = iwl3945_rates[i].ieee * 5;
1961 rates[i].hw_value = i; /* Rate scaling will work on indexes */
1962 rates[i].hw_value_short = i;
1963 rates[i].flags = 0;
d9829a67 1964 if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
b481de9c 1965 /*
8318d78a 1966 * If CCK != 1M then set short preamble rate flag.
b481de9c 1967 */
bb8c093b 1968 rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
8318d78a 1969 0 : IEEE80211_RATE_SHORT_PREAMBLE;
b481de9c 1970 }
b481de9c
ZY
1971 }
1972}
1973
b481de9c
ZY
1974/******************************************************************************
1975 *
1976 * uCode download functions
1977 *
1978 ******************************************************************************/
1979
4a8a4322 1980static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1981{
98c92211
TW
1982 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1983 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1984 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1985 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1986 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1987 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1988}
1989
1990/**
bb8c093b 1991 * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
b481de9c
ZY
1992 * looking at all data.
1993 */
4a8a4322 1994static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
1995{
1996 u32 val;
1997 u32 save_len = len;
1998 int rc = 0;
1999 u32 errcnt;
2000
e1623446 2001 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2002
5d49f498 2003 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2004 IWL39_RTC_INST_LOWER_BOUND);
b481de9c
ZY
2005
2006 errcnt = 0;
2007 for (; len > 0; len -= sizeof(u32), image++) {
2008 /* read data comes through single port, auto-incr addr */
2009 /* NOTE: Use the debugless read so we don't flood kernel log
2010 * if IWL_DL_IO is set */
5d49f498 2011 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c 2012 if (val != le32_to_cpu(*image)) {
15b1687c 2013 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2014 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2015 save_len - len, val, le32_to_cpu(*image));
2016 rc = -EIO;
2017 errcnt++;
2018 if (errcnt >= 20)
2019 break;
2020 }
2021 }
2022
b481de9c
ZY
2023
2024 if (!errcnt)
e1623446
TW
2025 IWL_DEBUG_INFO(priv,
2026 "ucode image in INSTRUCTION memory is good\n");
b481de9c
ZY
2027
2028 return rc;
2029}
2030
2031
2032/**
bb8c093b 2033 * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
b481de9c
ZY
2034 * using sample data 100 bytes apart. If these sample points are good,
2035 * it's a pretty good bet that everything between them is good, too.
2036 */
4a8a4322 2037static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
b481de9c
ZY
2038{
2039 u32 val;
2040 int rc = 0;
2041 u32 errcnt = 0;
2042 u32 i;
2043
e1623446 2044 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
b481de9c 2045
b481de9c
ZY
2046 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2047 /* read data comes through single port, auto-incr addr */
2048 /* NOTE: Use the debugless read so we don't flood kernel log
2049 * if IWL_DL_IO is set */
5d49f498 2050 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
250bdd21 2051 i + IWL39_RTC_INST_LOWER_BOUND);
5d49f498 2052 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b481de9c
ZY
2053 if (val != le32_to_cpu(*image)) {
2054#if 0 /* Enable this if you want to see details */
15b1687c 2055 IWL_ERR(priv, "uCode INST section is invalid at "
b481de9c
ZY
2056 "offset 0x%x, is 0x%x, s/b 0x%x\n",
2057 i, val, *image);
2058#endif
2059 rc = -EIO;
2060 errcnt++;
2061 if (errcnt >= 3)
2062 break;
2063 }
2064 }
2065
b481de9c
ZY
2066 return rc;
2067}
2068
2069
2070/**
bb8c093b 2071 * iwl3945_verify_ucode - determine which instruction image is in SRAM,
b481de9c
ZY
2072 * and verify its contents
2073 */
4a8a4322 2074static int iwl3945_verify_ucode(struct iwl_priv *priv)
b481de9c
ZY
2075{
2076 __le32 *image;
2077 u32 len;
2078 int rc = 0;
2079
2080 /* Try bootstrap */
2081 image = (__le32 *)priv->ucode_boot.v_addr;
2082 len = priv->ucode_boot.len;
bb8c093b 2083 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2084 if (rc == 0) {
e1623446 2085 IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
b481de9c
ZY
2086 return 0;
2087 }
2088
2089 /* Try initialize */
2090 image = (__le32 *)priv->ucode_init.v_addr;
2091 len = priv->ucode_init.len;
bb8c093b 2092 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2093 if (rc == 0) {
e1623446 2094 IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
b481de9c
ZY
2095 return 0;
2096 }
2097
2098 /* Try runtime/protocol */
2099 image = (__le32 *)priv->ucode_code.v_addr;
2100 len = priv->ucode_code.len;
bb8c093b 2101 rc = iwl3945_verify_inst_sparse(priv, image, len);
b481de9c 2102 if (rc == 0) {
e1623446 2103 IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
b481de9c
ZY
2104 return 0;
2105 }
2106
15b1687c 2107 IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
b481de9c 2108
9fbab516
BC
2109 /* Since nothing seems to match, show first several data entries in
2110 * instruction SRAM, so maybe visual inspection will give a clue.
2111 * Selection of bootstrap image (vs. other images) is arbitrary. */
b481de9c
ZY
2112 image = (__le32 *)priv->ucode_boot.v_addr;
2113 len = priv->ucode_boot.len;
bb8c093b 2114 rc = iwl3945_verify_inst_full(priv, image, len);
b481de9c
ZY
2115
2116 return rc;
2117}
2118
4a8a4322 2119static void iwl3945_nic_start(struct iwl_priv *priv)
b481de9c
ZY
2120{
2121 /* Remove all resets to allow NIC to operate */
5d49f498 2122 iwl_write32(priv, CSR_RESET, 0);
b481de9c
ZY
2123}
2124
2125/**
bb8c093b 2126 * iwl3945_read_ucode - Read uCode images from disk file.
b481de9c
ZY
2127 *
2128 * Copy into buffers for card to fetch via bus-mastering
2129 */
4a8a4322 2130static int iwl3945_read_ucode(struct iwl_priv *priv)
b481de9c 2131{
cc0f555d 2132 const struct iwl_ucode_header *ucode;
a0987a8d 2133 int ret = -EINVAL, index;
b481de9c
ZY
2134 const struct firmware *ucode_raw;
2135 /* firmware file name contains uCode/driver compatibility version */
a0987a8d
RC
2136 const char *name_pre = priv->cfg->fw_name_pre;
2137 const unsigned int api_max = priv->cfg->ucode_api_max;
2138 const unsigned int api_min = priv->cfg->ucode_api_min;
2139 char buf[25];
b481de9c
ZY
2140 u8 *src;
2141 size_t len;
a0987a8d 2142 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
2143
2144 /* Ask kernel firmware_class module to get the boot firmware off disk.
2145 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
2146 for (index = api_max; index >= api_min; index--) {
2147 sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
2148 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
2149 if (ret < 0) {
15b1687c 2150 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
2151 buf, ret);
2152 if (ret == -ENOENT)
2153 continue;
2154 else
2155 goto error;
2156 } else {
2157 if (index < api_max)
15b1687c
WT
2158 IWL_ERR(priv, "Loaded firmware %s, "
2159 "which is deprecated. "
2160 " Please use API v%u instead.\n",
a0987a8d 2161 buf, api_max);
e1623446
TW
2162 IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
2163 "(%zd bytes) from disk\n",
a0987a8d
RC
2164 buf, ucode_raw->size);
2165 break;
2166 }
b481de9c
ZY
2167 }
2168
a0987a8d
RC
2169 if (ret < 0)
2170 goto error;
b481de9c
ZY
2171
2172 /* Make sure that we got at least our header! */
cc0f555d 2173 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 2174 IWL_ERR(priv, "File size way too small!\n");
90e759d1 2175 ret = -EINVAL;
b481de9c
ZY
2176 goto err_release;
2177 }
2178
2179 /* Data from ucode file: header followed by uCode images */
cc0f555d 2180 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2181
c02b3acd 2182 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 2183 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
2184 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
2185 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
2186 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
2187 init_data_size =
2188 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
2189 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
2190 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 2191
a0987a8d
RC
2192 /* api_ver should match the api version forming part of the
2193 * firmware filename ... but we don't check for that and only rely
877d0310 2194 * on the API version read from firmware header from here on forward */
a0987a8d
RC
2195
2196 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2197 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
2198 "Driver supports v%u, firmware is v%u.\n",
2199 api_max, api_ver);
2200 priv->ucode_ver = 0;
2201 ret = -EINVAL;
2202 goto err_release;
2203 }
2204 if (api_ver != api_max)
15b1687c 2205 IWL_ERR(priv, "Firmware has old API version. Expected %u, "
a0987a8d
RC
2206 "got %u. New firmware can be obtained "
2207 "from http://www.intellinuxwireless.org.\n",
2208 api_max, api_ver);
2209
978785a3
TW
2210 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
2211 IWL_UCODE_MAJOR(priv->ucode_ver),
2212 IWL_UCODE_MINOR(priv->ucode_ver),
2213 IWL_UCODE_API(priv->ucode_ver),
2214 IWL_UCODE_SERIAL(priv->ucode_ver));
2215
5ebeb5a6
RC
2216 snprintf(priv->hw->wiphy->fw_version,
2217 sizeof(priv->hw->wiphy->fw_version),
2218 "%u.%u.%u.%u",
2219 IWL_UCODE_MAJOR(priv->ucode_ver),
2220 IWL_UCODE_MINOR(priv->ucode_ver),
2221 IWL_UCODE_API(priv->ucode_ver),
2222 IWL_UCODE_SERIAL(priv->ucode_ver));
2223
e1623446 2224 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 2225 priv->ucode_ver);
e1623446
TW
2226 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
2227 inst_size);
2228 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
2229 data_size);
2230 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
2231 init_size);
2232 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
2233 init_data_size);
2234 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
2235 boot_size);
b481de9c 2236
a0987a8d 2237
b481de9c 2238 /* Verify size of file vs. image size info in file's header */
cc0f555d 2239 if (ucode_raw->size != priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
2240 inst_size + data_size + init_size +
2241 init_data_size + boot_size) {
2242
cc0f555d
JS
2243 IWL_DEBUG_INFO(priv,
2244 "uCode file size %zd does not match expected size\n",
2245 ucode_raw->size);
90e759d1 2246 ret = -EINVAL;
b481de9c
ZY
2247 goto err_release;
2248 }
2249
2250 /* Verify that uCode images will fit in card's SRAM */
250bdd21 2251 if (inst_size > IWL39_MAX_INST_SIZE) {
e1623446 2252 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
2253 inst_size);
2254 ret = -EINVAL;
b481de9c
ZY
2255 goto err_release;
2256 }
2257
250bdd21 2258 if (data_size > IWL39_MAX_DATA_SIZE) {
e1623446 2259 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
2260 data_size);
2261 ret = -EINVAL;
b481de9c
ZY
2262 goto err_release;
2263 }
250bdd21 2264 if (init_size > IWL39_MAX_INST_SIZE) {
e1623446
TW
2265 IWL_DEBUG_INFO(priv,
2266 "uCode init instr len %d too large to fit in\n",
90e759d1
TW
2267 init_size);
2268 ret = -EINVAL;
b481de9c
ZY
2269 goto err_release;
2270 }
250bdd21 2271 if (init_data_size > IWL39_MAX_DATA_SIZE) {
e1623446
TW
2272 IWL_DEBUG_INFO(priv,
2273 "uCode init data len %d too large to fit in\n",
90e759d1
TW
2274 init_data_size);
2275 ret = -EINVAL;
b481de9c
ZY
2276 goto err_release;
2277 }
250bdd21 2278 if (boot_size > IWL39_MAX_BSM_SIZE) {
e1623446
TW
2279 IWL_DEBUG_INFO(priv,
2280 "uCode boot instr len %d too large to fit in\n",
90e759d1
TW
2281 boot_size);
2282 ret = -EINVAL;
b481de9c
ZY
2283 goto err_release;
2284 }
2285
2286 /* Allocate ucode buffers for card's bus-master loading ... */
2287
2288 /* Runtime instructions and 2 copies of data:
2289 * 1) unmodified from disk
2290 * 2) backup cache for save/restore during power-downs */
2291 priv->ucode_code.len = inst_size;
98c92211 2292 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
2293
2294 priv->ucode_data.len = data_size;
98c92211 2295 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
2296
2297 priv->ucode_data_backup.len = data_size;
98c92211 2298 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2299
90e759d1
TW
2300 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2301 !priv->ucode_data_backup.v_addr)
2302 goto err_pci_alloc;
b481de9c
ZY
2303
2304 /* Initialization instructions and data */
90e759d1
TW
2305 if (init_size && init_data_size) {
2306 priv->ucode_init.len = init_size;
98c92211 2307 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
2308
2309 priv->ucode_init_data.len = init_data_size;
98c92211 2310 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
2311
2312 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2313 goto err_pci_alloc;
2314 }
b481de9c
ZY
2315
2316 /* Bootstrap (instructions only, no data) */
90e759d1
TW
2317 if (boot_size) {
2318 priv->ucode_boot.len = boot_size;
98c92211 2319 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2320
90e759d1
TW
2321 if (!priv->ucode_boot.v_addr)
2322 goto err_pci_alloc;
2323 }
b481de9c
ZY
2324
2325 /* Copy images into buffers for card's bus-master reads ... */
2326
2327 /* Runtime instructions (first block of data in file) */
cc0f555d 2328 len = inst_size;
e1623446
TW
2329 IWL_DEBUG_INFO(priv,
2330 "Copying (but not loading) uCode instr len %zd\n", len);
b481de9c 2331 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
2332 src += len;
2333
e1623446 2334 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
2335 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2336
2337 /* Runtime data (2nd block)
bb8c093b 2338 * NOTE: Copy into backup buffer will be done in iwl3945_up() */
cc0f555d 2339 len = data_size;
e1623446
TW
2340 IWL_DEBUG_INFO(priv,
2341 "Copying (but not loading) uCode data len %zd\n", len);
b481de9c
ZY
2342 memcpy(priv->ucode_data.v_addr, src, len);
2343 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 2344 src += len;
b481de9c
ZY
2345
2346 /* Initialization instructions (3rd block) */
2347 if (init_size) {
cc0f555d 2348 len = init_size;
e1623446
TW
2349 IWL_DEBUG_INFO(priv,
2350 "Copying (but not loading) init instr len %zd\n", len);
b481de9c 2351 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 2352 src += len;
b481de9c
ZY
2353 }
2354
2355 /* Initialization data (4th block) */
2356 if (init_data_size) {
cc0f555d 2357 len = init_data_size;
e1623446
TW
2358 IWL_DEBUG_INFO(priv,
2359 "Copying (but not loading) init data len %zd\n", len);
b481de9c 2360 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 2361 src += len;
b481de9c
ZY
2362 }
2363
2364 /* Bootstrap instructions (5th block) */
cc0f555d 2365 len = boot_size;
e1623446
TW
2366 IWL_DEBUG_INFO(priv,
2367 "Copying (but not loading) boot instr len %zd\n", len);
b481de9c
ZY
2368 memcpy(priv->ucode_boot.v_addr, src, len);
2369
2370 /* We have our copies now, allow OS release its copies */
2371 release_firmware(ucode_raw);
2372 return 0;
2373
2374 err_pci_alloc:
15b1687c 2375 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 2376 ret = -ENOMEM;
bb8c093b 2377 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
2378
2379 err_release:
2380 release_firmware(ucode_raw);
2381
2382 error:
90e759d1 2383 return ret;
b481de9c
ZY
2384}
2385
2386
2387/**
bb8c093b 2388 * iwl3945_set_ucode_ptrs - Set uCode address location
b481de9c
ZY
2389 *
2390 * Tell initialization uCode where to find runtime uCode.
2391 *
2392 * BSM registers initially contain pointers to initialization uCode.
2393 * We need to replace them to load runtime uCode inst and data,
2394 * and to save runtime data when powering down.
2395 */
4a8a4322 2396static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
b481de9c
ZY
2397{
2398 dma_addr_t pinst;
2399 dma_addr_t pdata;
b481de9c
ZY
2400
2401 /* bits 31:0 for 3945 */
2402 pinst = priv->ucode_code.p_addr;
2403 pdata = priv->ucode_data_backup.p_addr;
2404
b481de9c 2405 /* Tell bootstrap uCode where to find image to load */
5d49f498
AK
2406 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2407 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2408 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
b481de9c
ZY
2409 priv->ucode_data.len);
2410
a96a27f9 2411 /* Inst byte count must be last to set up, bit 31 signals uCode
b481de9c 2412 * that all new ptr/size info is in place */
5d49f498 2413 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
b481de9c
ZY
2414 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2415
e1623446 2416 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
b481de9c 2417
a8b50a0a 2418 return 0;
b481de9c
ZY
2419}
2420
2421/**
bb8c093b 2422 * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
b481de9c
ZY
2423 *
2424 * Called after REPLY_ALIVE notification received from "initialize" uCode.
2425 *
b481de9c 2426 * Tell "initialize" uCode to go ahead and load the runtime uCode.
9fbab516 2427 */
4a8a4322 2428static void iwl3945_init_alive_start(struct iwl_priv *priv)
b481de9c
ZY
2429{
2430 /* Check alive response for "valid" sign from uCode */
2431 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
2432 /* We had an error bringing up the hardware, so take it
2433 * all the way back down so we can try again */
e1623446 2434 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
b481de9c
ZY
2435 goto restart;
2436 }
2437
2438 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
2439 * This is a paranoid check, because we would not have gotten the
2440 * "initialize" alive if code weren't properly loaded. */
bb8c093b 2441 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2442 /* Runtime instruction load was bad;
2443 * take it all the way back down so we can try again */
e1623446 2444 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
b481de9c
ZY
2445 goto restart;
2446 }
2447
2448 /* Send pointers to protocol/runtime uCode image ... init code will
2449 * load and launch runtime uCode, which will send us another "Alive"
2450 * notification. */
e1623446 2451 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
bb8c093b 2452 if (iwl3945_set_ucode_ptrs(priv)) {
b481de9c
ZY
2453 /* Runtime instruction load won't happen;
2454 * take it all the way back down so we can try again */
e1623446 2455 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
b481de9c
ZY
2456 goto restart;
2457 }
2458 return;
2459
2460 restart:
2461 queue_work(priv->workqueue, &priv->restart);
2462}
2463
b481de9c 2464/**
bb8c093b 2465 * iwl3945_alive_start - called after REPLY_ALIVE notification received
b481de9c 2466 * from protocol/runtime uCode (initialization uCode's
bb8c093b 2467 * Alive gets handled by iwl3945_init_alive_start()).
b481de9c 2468 */
4a8a4322 2469static void iwl3945_alive_start(struct iwl_priv *priv)
b481de9c 2470{
b481de9c
ZY
2471 int thermal_spin = 0;
2472 u32 rfkill;
2473
e1623446 2474 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
2475
2476 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2477 /* We had an error bringing up the hardware, so take it
2478 * all the way back down so we can try again */
e1623446 2479 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
2480 goto restart;
2481 }
2482
2483 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2484 * This is a paranoid check, because we would not have gotten the
2485 * "runtime" alive if code weren't properly loaded. */
bb8c093b 2486 if (iwl3945_verify_ucode(priv)) {
b481de9c
ZY
2487 /* Runtime instruction load was bad;
2488 * take it all the way back down so we can try again */
e1623446 2489 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
2490 goto restart;
2491 }
2492
c587de0b 2493 iwl_clear_stations_table(priv);
b481de9c 2494
5d49f498 2495 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
e1623446 2496 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
b481de9c
ZY
2497
2498 if (rfkill & 0x1) {
2499 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a96a27f9 2500 /* if RFKILL is not on, then wait for thermal
b481de9c 2501 * sensor in adapter to kick in */
bb8c093b 2502 while (iwl3945_hw_get_temperature(priv) == 0) {
b481de9c
ZY
2503 thermal_spin++;
2504 udelay(10);
2505 }
2506
2507 if (thermal_spin)
e1623446 2508 IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
b481de9c
ZY
2509 thermal_spin * 10);
2510 } else
2511 set_bit(STATUS_RF_KILL_HW, &priv->status);
2512
9fbab516 2513 /* After the ALIVE response, we can send commands to 3945 uCode */
b481de9c
ZY
2514 set_bit(STATUS_ALIVE, &priv->status);
2515
775a6e27 2516 if (iwl_is_rfkill(priv))
b481de9c
ZY
2517 return;
2518
36d6825b 2519 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
2520
2521 priv->active_rate = priv->rates_mask;
2522 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
2523
4d6ccbf5 2524 iwl_power_update_mode(priv, true);
b481de9c 2525
8ccde88a 2526 if (iwl_is_associated(priv)) {
bb8c093b 2527 struct iwl3945_rxon_cmd *active_rxon =
8ccde88a 2528 (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
b481de9c 2529
8a9b9926 2530 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2531 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2532 } else {
2533 /* Initialize our rx_config data */
8ccde88a 2534 iwl_connection_init_rx_config(priv, priv->iw_mode);
b481de9c
ZY
2535 }
2536
9fbab516 2537 /* Configure Bluetooth device coexistence support */
17f841cd 2538 iwl_send_bt_config(priv);
b481de9c
ZY
2539
2540 /* Configure the adapter for unassociated operation */
e0158e61 2541 iwlcore_commit_rxon(priv);
b481de9c 2542
b481de9c
ZY
2543 iwl3945_reg_txpower_periodic(priv);
2544
e932a609 2545 iwl_leds_init(priv);
fe00b5a5 2546
e1623446 2547 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2548 set_bit(STATUS_READY, &priv->status);
5a66926a 2549 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2550
9bdf5eca
MA
2551 /* reassociate for ADHOC mode */
2552 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
2553 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
2554 priv->vif);
2555 if (beacon)
9944b938 2556 iwl_mac_beacon_update(priv->hw, beacon);
9bdf5eca
MA
2557 }
2558
f45c2714 2559 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
727882d6 2560 iwl_set_mode(priv, priv->iw_mode);
f45c2714 2561
b481de9c
ZY
2562 return;
2563
2564 restart:
2565 queue_work(priv->workqueue, &priv->restart);
2566}
2567
4a8a4322 2568static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2569
4a8a4322 2570static void __iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2571{
2572 unsigned long flags;
2573 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2574 struct ieee80211_conf *conf = NULL;
2575
e1623446 2576 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c
ZY
2577
2578 conf = ieee80211_get_hw_conf(priv->hw);
2579
2580 if (!exit_pending)
2581 set_bit(STATUS_EXIT_PENDING, &priv->status);
2582
c587de0b 2583 iwl_clear_stations_table(priv);
b481de9c
ZY
2584
2585 /* Unblock any waiting calls */
2586 wake_up_interruptible_all(&priv->wait_command_queue);
2587
b481de9c
ZY
2588 /* Wipe out the EXIT_PENDING status bit if we are not actually
2589 * exiting the module */
2590 if (!exit_pending)
2591 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2592
2593 /* stop and reset the on-board processor */
5d49f498 2594 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
2595
2596 /* tell the device to stop sending interrupts */
0359facc 2597 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 2598 iwl_disable_interrupts(priv);
0359facc
MA
2599 spin_unlock_irqrestore(&priv->lock, flags);
2600 iwl_synchronize_irq(priv);
b481de9c
ZY
2601
2602 if (priv->mac80211_registered)
2603 ieee80211_stop_queues(priv->hw);
2604
bb8c093b 2605 /* If we have not previously called iwl3945_init() then
6da3a13e 2606 * clear all bits but the RF Kill bits and return */
775a6e27 2607 if (!iwl_is_init(priv)) {
b481de9c
ZY
2608 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2609 STATUS_RF_KILL_HW |
9788864e
RC
2610 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2611 STATUS_GEO_CONFIGURED |
ebef2008
AK
2612 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2613 STATUS_EXIT_PENDING;
b481de9c
ZY
2614 goto exit;
2615 }
2616
6da3a13e 2617 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2618 * bit and continue taking the NIC down. */
b481de9c
ZY
2619 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2620 STATUS_RF_KILL_HW |
9788864e
RC
2621 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2622 STATUS_GEO_CONFIGURED |
b481de9c 2623 test_bit(STATUS_FW_ERROR, &priv->status) <<
ebef2008
AK
2624 STATUS_FW_ERROR |
2625 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2626 STATUS_EXIT_PENDING;
b481de9c 2627
bb8c093b
CH
2628 iwl3945_hw_txq_ctx_stop(priv);
2629 iwl3945_hw_rxq_stop(priv);
b481de9c 2630
309e731a
BC
2631 /* Power-down device's busmaster DMA clocks */
2632 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
2633 udelay(5);
2634
4d2ccdb9
BC
2635 /* Stop the device, and put it in low power state */
2636 priv->cfg->ops->lib->apm_ops.stop(priv);
e9414b6b 2637
b481de9c 2638 exit:
3d24a9f7 2639 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
2640
2641 if (priv->ibss_beacon)
2642 dev_kfree_skb(priv->ibss_beacon);
2643 priv->ibss_beacon = NULL;
2644
2645 /* clear out any free frames */
bb8c093b 2646 iwl3945_clear_free_frames(priv);
b481de9c
ZY
2647}
2648
4a8a4322 2649static void iwl3945_down(struct iwl_priv *priv)
b481de9c
ZY
2650{
2651 mutex_lock(&priv->mutex);
bb8c093b 2652 __iwl3945_down(priv);
b481de9c 2653 mutex_unlock(&priv->mutex);
b24d22b1 2654
bb8c093b 2655 iwl3945_cancel_deferred_work(priv);
b481de9c
ZY
2656}
2657
2658#define MAX_HW_RESTARTS 5
2659
4a8a4322 2660static int __iwl3945_up(struct iwl_priv *priv)
b481de9c
ZY
2661{
2662 int rc, i;
2663
2664 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2665 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2666 return -EIO;
2667 }
2668
e903fbd4 2669 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2670 IWL_ERR(priv, "ucode not available for device bring up\n");
e903fbd4
RC
2671 return -EIO;
2672 }
2673
e655b9f0 2674 /* If platform's RF_KILL switch is NOT set to KILL */
5d49f498 2675 if (iwl_read32(priv, CSR_GP_CNTRL) &
e655b9f0
ZY
2676 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2677 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2678 else {
2679 set_bit(STATUS_RF_KILL_HW, &priv->status);
6da3a13e
WYG
2680 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2681 return -ENODEV;
b481de9c 2682 }
80fcc9e2 2683
5d49f498 2684 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2685
bb8c093b 2686 rc = iwl3945_hw_nic_init(priv);
b481de9c 2687 if (rc) {
15b1687c 2688 IWL_ERR(priv, "Unable to int nic\n");
b481de9c
ZY
2689 return rc;
2690 }
2691
2692 /* make sure rfkill handshake bits are cleared */
5d49f498
AK
2693 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2694 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2695 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2696
2697 /* clear (again), then enable host interrupts */
5d49f498 2698 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
ed3b932e 2699 iwl_enable_interrupts(priv);
b481de9c
ZY
2700
2701 /* really make sure rfkill handshake bits are cleared */
5d49f498
AK
2702 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2703 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2704
2705 /* Copy original ucode data image from disk into backup cache.
2706 * This will be used to initialize the on-board processor's
2707 * data SRAM for a clean start when the runtime program first loads. */
2708 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2709 priv->ucode_data.len);
b481de9c 2710
e655b9f0
ZY
2711 /* We return success when we resume from suspend and rf_kill is on. */
2712 if (test_bit(STATUS_RF_KILL_HW, &priv->status))
2713 return 0;
2714
b481de9c
ZY
2715 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2716
c587de0b 2717 iwl_clear_stations_table(priv);
b481de9c
ZY
2718
2719 /* load bootstrap state machine,
2720 * load bootstrap program into processor's memory,
2721 * prepare to load the "initialize" uCode */
0164b9b4 2722 priv->cfg->ops->lib->load_ucode(priv);
b481de9c
ZY
2723
2724 if (rc) {
15b1687c
WT
2725 IWL_ERR(priv,
2726 "Unable to set up bootstrap uCode: %d\n", rc);
b481de9c
ZY
2727 continue;
2728 }
2729
2730 /* start card; "initialize" will load runtime ucode */
bb8c093b 2731 iwl3945_nic_start(priv);
b481de9c 2732
e1623446 2733 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2734
2735 return 0;
2736 }
2737
2738 set_bit(STATUS_EXIT_PENDING, &priv->status);
bb8c093b 2739 __iwl3945_down(priv);
ebef2008 2740 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2741
2742 /* tried to restart and config the device for as long as our
2743 * patience could withstand */
15b1687c 2744 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2745 return -EIO;
2746}
2747
2748
2749/*****************************************************************************
2750 *
2751 * Workqueue callbacks
2752 *
2753 *****************************************************************************/
2754
bb8c093b 2755static void iwl3945_bg_init_alive_start(struct work_struct *data)
b481de9c 2756{
4a8a4322
AK
2757 struct iwl_priv *priv =
2758 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2759
2760 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2761 return;
2762
2763 mutex_lock(&priv->mutex);
bb8c093b 2764 iwl3945_init_alive_start(priv);
b481de9c
ZY
2765 mutex_unlock(&priv->mutex);
2766}
2767
bb8c093b 2768static void iwl3945_bg_alive_start(struct work_struct *data)
b481de9c 2769{
4a8a4322
AK
2770 struct iwl_priv *priv =
2771 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2772
2773 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2774 return;
2775
2776 mutex_lock(&priv->mutex);
bb8c093b 2777 iwl3945_alive_start(priv);
b481de9c
ZY
2778 mutex_unlock(&priv->mutex);
2779}
2780
743cdf1b
BC
2781/*
2782 * 3945 cannot interrupt driver when hardware rf kill switch toggles;
2783 * driver must poll CSR_GP_CNTRL_REG register for change. This register
2784 * *is* readable even when device has been SW_RESET into low power mode
2785 * (e.g. during RF KILL).
2786 */
2663516d
HS
2787static void iwl3945_rfkill_poll(struct work_struct *data)
2788{
2789 struct iwl_priv *priv =
2790 container_of(data, struct iwl_priv, rfkill_poll.work);
743cdf1b
BC
2791 bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
2792 bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
2793 & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2663516d 2794
743cdf1b
BC
2795 if (new_rfkill != old_rfkill) {
2796 if (new_rfkill)
2797 set_bit(STATUS_RF_KILL_HW, &priv->status);
2798 else
2799 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2663516d 2800
743cdf1b
BC
2801 wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
2802
2803 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
2804 new_rfkill ? "disable radio" : "enable radio");
2805 }
2663516d 2806
743cdf1b
BC
2807 /* Keep this running, even if radio now enabled. This will be
2808 * cancelled in mac_start() if system decides to start again */
2663516d
HS
2809 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
2810 round_jiffies_relative(2 * HZ));
2811
2812}
2813
b481de9c 2814#define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
bb8c093b 2815static void iwl3945_bg_request_scan(struct work_struct *data)
b481de9c 2816{
4a8a4322
AK
2817 struct iwl_priv *priv =
2818 container_of(data, struct iwl_priv, request_scan);
c2d79b48 2819 struct iwl_host_cmd cmd = {
b481de9c 2820 .id = REPLY_SCAN_CMD,
bb8c093b 2821 .len = sizeof(struct iwl3945_scan_cmd),
c2acea8e 2822 .flags = CMD_SIZE_HUGE,
b481de9c
ZY
2823 };
2824 int rc = 0;
bb8c093b 2825 struct iwl3945_scan_cmd *scan;
b481de9c 2826 struct ieee80211_conf *conf = NULL;
1ecf9fc1 2827 u8 n_probes = 0;
8318d78a 2828 enum ieee80211_band band;
1ecf9fc1 2829 bool is_active = false;
b481de9c
ZY
2830
2831 conf = ieee80211_get_hw_conf(priv->hw);
2832
2833 mutex_lock(&priv->mutex);
2834
fbc9f97b
RC
2835 cancel_delayed_work(&priv->scan_check);
2836
775a6e27 2837 if (!iwl_is_ready(priv)) {
39aadf8c 2838 IWL_WARN(priv, "request scan called when driver not ready.\n");
b481de9c
ZY
2839 goto done;
2840 }
2841
a96a27f9 2842 /* Make sure the scan wasn't canceled before this queued work
b481de9c
ZY
2843 * was given the chance to run... */
2844 if (!test_bit(STATUS_SCANNING, &priv->status))
2845 goto done;
2846
2847 /* This should never be called or scheduled if there is currently
2848 * a scan active in the hardware. */
2849 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
e1623446
TW
2850 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests "
2851 "Ignoring second request.\n");
b481de9c
ZY
2852 rc = -EIO;
2853 goto done;
2854 }
2855
2856 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
e1623446 2857 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
b481de9c
ZY
2858 goto done;
2859 }
2860
2861 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
e1623446
TW
2862 IWL_DEBUG_HC(priv,
2863 "Scan request while abort pending. Queuing.\n");
b481de9c
ZY
2864 goto done;
2865 }
2866
775a6e27 2867 if (iwl_is_rfkill(priv)) {
e1623446 2868 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
b481de9c
ZY
2869 goto done;
2870 }
2871
2872 if (!test_bit(STATUS_READY, &priv->status)) {
e1623446
TW
2873 IWL_DEBUG_HC(priv,
2874 "Scan request while uninitialized. Queuing.\n");
b481de9c
ZY
2875 goto done;
2876 }
2877
2878 if (!priv->scan_bands) {
e1623446 2879 IWL_DEBUG_HC(priv, "Aborting scan due to no requested bands\n");
b481de9c
ZY
2880 goto done;
2881 }
2882
805cee5b
WT
2883 if (!priv->scan) {
2884 priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
b481de9c 2885 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
805cee5b 2886 if (!priv->scan) {
b481de9c
ZY
2887 rc = -ENOMEM;
2888 goto done;
2889 }
2890 }
805cee5b 2891 scan = priv->scan;
bb8c093b 2892 memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
b481de9c
ZY
2893
2894 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
2895 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2896
8ccde88a 2897 if (iwl_is_associated(priv)) {
b481de9c
ZY
2898 u16 interval = 0;
2899 u32 extra;
2900 u32 suspend_time = 100;
2901 u32 scan_suspend_time = 100;
2902 unsigned long flags;
2903
e1623446 2904 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
b481de9c
ZY
2905
2906 spin_lock_irqsave(&priv->lock, flags);
2907 interval = priv->beacon_int;
2908 spin_unlock_irqrestore(&priv->lock, flags);
2909
2910 scan->suspend_time = 0;
15e869d8 2911 scan->max_out_time = cpu_to_le32(200 * 1024);
b481de9c
ZY
2912 if (!interval)
2913 interval = suspend_time;
2914 /*
2915 * suspend time format:
2916 * 0-19: beacon interval in usec (time before exec.)
2917 * 20-23: 0
2918 * 24-31: number of beacons (suspend between channels)
2919 */
2920
2921 extra = (suspend_time / interval) << 24;
2922 scan_suspend_time = 0xFF0FFFFF &
2923 (extra | ((suspend_time % interval) * 1024));
2924
2925 scan->suspend_time = cpu_to_le32(scan_suspend_time);
e1623446 2926 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
b481de9c
ZY
2927 scan_suspend_time, interval);
2928 }
2929
1ecf9fc1
JB
2930 if (priv->scan_request->n_ssids) {
2931 int i, p = 0;
2932 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2933 for (i = 0; i < priv->scan_request->n_ssids; i++) {
2934 /* always does wildcard anyway */
2935 if (!priv->scan_request->ssids[i].ssid_len)
2936 continue;
2937 scan->direct_scan[p].id = WLAN_EID_SSID;
2938 scan->direct_scan[p].len =
2939 priv->scan_request->ssids[i].ssid_len;
2940 memcpy(scan->direct_scan[p].ssid,
2941 priv->scan_request->ssids[i].ssid,
2942 priv->scan_request->ssids[i].ssid_len);
2943 n_probes++;
2944 p++;
2945 }
2946 is_active = true;
f9340520 2947 } else
1ecf9fc1 2948 IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
b481de9c
ZY
2949
2950 /* We don't build a direct scan probe request; the uCode will do
2951 * that based on the direct_mask added to each channel entry */
b481de9c 2952 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
3832ec9d 2953 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY
2954 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2955
2956 /* flags + rate selection */
2957
66b5004d 2958 if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
b481de9c
ZY
2959 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2960 scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
2961 scan->good_CRC_th = 0;
8318d78a 2962 band = IEEE80211_BAND_2GHZ;
66b5004d 2963 } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
b481de9c 2964 scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
b097ad29
JB
2965 /*
2966 * If active scaning is requested but a certain channel
2967 * is marked passive, we can do active scanning if we
2968 * detect transmissions.
2969 */
2970 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH : 0;
8318d78a 2971 band = IEEE80211_BAND_5GHZ;
66b5004d 2972 } else {
39aadf8c 2973 IWL_WARN(priv, "Invalid scan band count\n");
b481de9c
ZY
2974 goto done;
2975 }
2976
77fecfb8 2977 scan->tx_cmd.len = cpu_to_le16(
1ecf9fc1
JB
2978 iwl_fill_probe_req(priv,
2979 (struct ieee80211_mgmt *)scan->data,
2980 priv->scan_request->ie,
2981 priv->scan_request->ie_len,
2982 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
77fecfb8 2983
b481de9c
ZY
2984 /* select Rx antennas */
2985 scan->flags |= iwl3945_get_antenna_flags(priv);
2986
279b05d4 2987 if (iwl_is_monitor_mode(priv))
b481de9c
ZY
2988 scan->filter_flags = RXON_FILTER_PROMISC_MSK;
2989
f9340520 2990 scan->channel_count =
1ecf9fc1 2991 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
f9340520 2992 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
b481de9c 2993
14b54336 2994 if (scan->channel_count == 0) {
e1623446 2995 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
14b54336
RC
2996 goto done;
2997 }
2998
b481de9c 2999 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
bb8c093b 3000 scan->channel_count * sizeof(struct iwl3945_scan_channel);
b481de9c
ZY
3001 cmd.data = scan;
3002 scan->len = cpu_to_le16(cmd.len);
3003
3004 set_bit(STATUS_SCAN_HW, &priv->status);
518099a8 3005 rc = iwl_send_cmd_sync(priv, &cmd);
b481de9c
ZY
3006 if (rc)
3007 goto done;
3008
3009 queue_delayed_work(priv->workqueue, &priv->scan_check,
3010 IWL_SCAN_CHECK_WATCHDOG);
3011
3012 mutex_unlock(&priv->mutex);
3013 return;
3014
3015 done:
2420ebc1
MA
3016 /* can not perform scan make sure we clear scanning
3017 * bits from status so next scan request can be performed.
3018 * if we dont clear scanning status bit here all next scan
3019 * will fail
3020 */
3021 clear_bit(STATUS_SCAN_HW, &priv->status);
3022 clear_bit(STATUS_SCANNING, &priv->status);
3023
01ebd063 3024 /* inform mac80211 scan aborted */
b481de9c
ZY
3025 queue_work(priv->workqueue, &priv->scan_completed);
3026 mutex_unlock(&priv->mutex);
3027}
3028
bb8c093b 3029static void iwl3945_bg_restart(struct work_struct *data)
b481de9c 3030{
4a8a4322 3031 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
3032
3033 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3034 return;
3035
19cc1087
JB
3036 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3037 mutex_lock(&priv->mutex);
3038 priv->vif = NULL;
3039 priv->is_open = 0;
3040 mutex_unlock(&priv->mutex);
3041 iwl3945_down(priv);
3042 ieee80211_restart_hw(priv->hw);
3043 } else {
3044 iwl3945_down(priv);
80676518
JB
3045
3046 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3047 return;
3048
3049 mutex_lock(&priv->mutex);
3050 __iwl3945_up(priv);
3051 mutex_unlock(&priv->mutex);
19cc1087 3052 }
b481de9c
ZY
3053}
3054
bb8c093b 3055static void iwl3945_bg_rx_replenish(struct work_struct *data)
b481de9c 3056{
4a8a4322
AK
3057 struct iwl_priv *priv =
3058 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
3059
3060 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3061 return;
3062
3063 mutex_lock(&priv->mutex);
bb8c093b 3064 iwl3945_rx_replenish(priv);
b481de9c
ZY
3065 mutex_unlock(&priv->mutex);
3066}
3067
7878a5a4
MA
3068#define IWL_DELAY_NEXT_SCAN (HZ*2)
3069
5bbe233b 3070void iwl3945_post_associate(struct iwl_priv *priv)
b481de9c 3071{
b481de9c
ZY
3072 int rc = 0;
3073 struct ieee80211_conf *conf = NULL;
3074
05c914fe 3075 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 3076 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
3077 return;
3078 }
3079
3080
e1623446 3081 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
8ccde88a 3082 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
3083
3084 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3085 return;
3086
322a9811 3087 if (!priv->vif || !priv->is_open)
6ef89d0a 3088 return;
322a9811 3089
af0053d6 3090 iwl_scan_cancel_timeout(priv, 200);
15e869d8 3091
b481de9c
ZY
3092 conf = ieee80211_get_hw_conf(priv->hw);
3093
8ccde88a 3094 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3095 iwlcore_commit_rxon(priv);
b481de9c 3096
28afaf91 3097 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3098 iwl_setup_rxon_timing(priv);
518099a8 3099 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c
ZY
3100 sizeof(priv->rxon_timing), &priv->rxon_timing);
3101 if (rc)
39aadf8c 3102 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3103 "Attempting to continue.\n");
3104
8ccde88a 3105 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3106
8ccde88a 3107 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3108
e1623446 3109 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
3110 priv->assoc_id, priv->beacon_int);
3111
3112 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3113 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3114 else
8ccde88a 3115 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3116
8ccde88a 3117 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c 3118 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3119 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3120 else
8ccde88a 3121 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3122
05c914fe 3123 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3124 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY
3125
3126 }
3127
e0158e61 3128 iwlcore_commit_rxon(priv);
b481de9c
ZY
3129
3130 switch (priv->iw_mode) {
05c914fe 3131 case NL80211_IFTYPE_STATION:
bb8c093b 3132 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
b481de9c
ZY
3133 break;
3134
05c914fe 3135 case NL80211_IFTYPE_ADHOC:
b481de9c 3136
ce546fd2 3137 priv->assoc_id = 1;
c587de0b 3138 iwl_add_station(priv, priv->bssid, 0, CMD_SYNC, NULL);
b481de9c 3139 iwl3945_sync_sta(priv, IWL_STA_ID,
8318d78a 3140 (priv->band == IEEE80211_BAND_5GHZ) ?
b481de9c
ZY
3141 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
3142 CMD_ASYNC);
bb8c093b
CH
3143 iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
3144 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3145
3146 break;
3147
3148 default:
15b1687c 3149 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 3150 __func__, priv->iw_mode);
b481de9c
ZY
3151 break;
3152 }
3153
14d2aac5 3154 iwl_activate_qos(priv, 0);
292ae174 3155
7878a5a4
MA
3156 /* we have just associated, don't start scan too early */
3157 priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
cd56d331
AK
3158}
3159
b481de9c
ZY
3160/*****************************************************************************
3161 *
3162 * mac80211 entry point functions
3163 *
3164 *****************************************************************************/
3165
5a66926a
ZY
3166#define UCODE_READY_TIMEOUT (2 * HZ)
3167
bb8c093b 3168static int iwl3945_mac_start(struct ieee80211_hw *hw)
b481de9c 3169{
4a8a4322 3170 struct iwl_priv *priv = hw->priv;
5a66926a 3171 int ret;
b481de9c 3172
e1623446 3173 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
3174
3175 /* we should be verifying the device is ready to be opened */
3176 mutex_lock(&priv->mutex);
3177
5a66926a
ZY
3178 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
3179 * ucode filename and max sizes are card-specific. */
3180
3181 if (!priv->ucode_code.len) {
3182 ret = iwl3945_read_ucode(priv);
3183 if (ret) {
15b1687c 3184 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a
ZY
3185 mutex_unlock(&priv->mutex);
3186 goto out_release_irq;
3187 }
3188 }
b481de9c 3189
e655b9f0 3190 ret = __iwl3945_up(priv);
b481de9c
ZY
3191
3192 mutex_unlock(&priv->mutex);
5a66926a 3193
e655b9f0
ZY
3194 if (ret)
3195 goto out_release_irq;
3196
e1623446 3197 IWL_DEBUG_INFO(priv, "Start UP work.\n");
e655b9f0 3198
5a66926a
ZY
3199 /* Wait for START_ALIVE from ucode. Otherwise callbacks from
3200 * mac80211 will not be run successfully. */
3201 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3202 test_bit(STATUS_READY, &priv->status),
3203 UCODE_READY_TIMEOUT);
3204 if (!ret) {
3205 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c
WT
3206 IWL_ERR(priv,
3207 "Wait for START_ALIVE timeout after %dms.\n",
3208 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5a66926a
ZY
3209 ret = -ETIMEDOUT;
3210 goto out_release_irq;
3211 }
3212 }
3213
2663516d
HS
3214 /* ucode is running and will send rfkill notifications,
3215 * no need to poll the killswitch state anymore */
3216 cancel_delayed_work(&priv->rfkill_poll);
3217
e932a609
JB
3218 iwl_led_start(priv);
3219
e655b9f0 3220 priv->is_open = 1;
e1623446 3221 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3222 return 0;
5a66926a
ZY
3223
3224out_release_irq:
e655b9f0 3225 priv->is_open = 0;
e1623446 3226 IWL_DEBUG_MAC80211(priv, "leave - failed\n");
5a66926a 3227 return ret;
b481de9c
ZY
3228}
3229
bb8c093b 3230static void iwl3945_mac_stop(struct ieee80211_hw *hw)
b481de9c 3231{
4a8a4322 3232 struct iwl_priv *priv = hw->priv;
b481de9c 3233
e1623446 3234 IWL_DEBUG_MAC80211(priv, "enter\n");
6ef89d0a 3235
e655b9f0 3236 if (!priv->is_open) {
e1623446 3237 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY
3238 return;
3239 }
3240
b481de9c 3241 priv->is_open = 0;
5a66926a 3242
775a6e27 3243 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
3244 /* stop mac, cancel any scan request and clear
3245 * RXON_FILTER_ASSOC_MSK BIT
3246 */
5a66926a 3247 mutex_lock(&priv->mutex);
af0053d6 3248 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3249 mutex_unlock(&priv->mutex);
fde3571f
MA
3250 }
3251
5a66926a
ZY
3252 iwl3945_down(priv);
3253
3254 flush_workqueue(priv->workqueue);
2663516d
HS
3255
3256 /* start polling the killswitch state again */
3257 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
3258 round_jiffies_relative(2 * HZ));
6ef89d0a 3259
e1623446 3260 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
3261}
3262
e039fa4a 3263static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3264{
4a8a4322 3265 struct iwl_priv *priv = hw->priv;
b481de9c 3266
e1623446 3267 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3268
e1623446 3269 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3270 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3271
e039fa4a 3272 if (iwl3945_tx_skb(priv, skb))
b481de9c
ZY
3273 dev_kfree_skb_any(skb);
3274
e1623446 3275 IWL_DEBUG_MAC80211(priv, "leave\n");
637f8837 3276 return NETDEV_TX_OK;
b481de9c
ZY
3277}
3278
60690a6a 3279void iwl3945_config_ap(struct iwl_priv *priv)
b481de9c
ZY
3280{
3281 int rc = 0;
3282
d986bcd1 3283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
3284 return;
3285
3286 /* The following should be done only at AP bring up */
8ccde88a 3287 if (!(iwl_is_associated(priv))) {
b481de9c
ZY
3288
3289 /* RXON - unassoc (to set timing command) */
8ccde88a 3290 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3291 iwlcore_commit_rxon(priv);
b481de9c
ZY
3292
3293 /* RXON Timing */
28afaf91 3294 memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
2c2f3b33 3295 iwl_setup_rxon_timing(priv);
518099a8
SO
3296 rc = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3297 sizeof(priv->rxon_timing),
3298 &priv->rxon_timing);
b481de9c 3299 if (rc)
39aadf8c 3300 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
3301 "Attempting to continue.\n");
3302
3303 /* FIXME: what should be the assoc_id for AP? */
8ccde88a 3304 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
b481de9c 3305 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
8ccde88a 3306 priv->staging_rxon.flags |=
b481de9c
ZY
3307 RXON_FLG_SHORT_PREAMBLE_MSK;
3308 else
8ccde88a 3309 priv->staging_rxon.flags &=
b481de9c
ZY
3310 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3311
8ccde88a 3312 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
b481de9c
ZY
3313 if (priv->assoc_capability &
3314 WLAN_CAPABILITY_SHORT_SLOT_TIME)
8ccde88a 3315 priv->staging_rxon.flags |=
b481de9c
ZY
3316 RXON_FLG_SHORT_SLOT_MSK;
3317 else
8ccde88a 3318 priv->staging_rxon.flags &=
b481de9c
ZY
3319 ~RXON_FLG_SHORT_SLOT_MSK;
3320
05c914fe 3321 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
8ccde88a 3322 priv->staging_rxon.flags &=
b481de9c
ZY
3323 ~RXON_FLG_SHORT_SLOT_MSK;
3324 }
3325 /* restore RXON assoc */
8ccde88a 3326 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3327 iwlcore_commit_rxon(priv);
c587de0b 3328 iwl_add_station(priv, iwl_bcast_addr, 0, CMD_SYNC, NULL);
556f8db7 3329 }
bb8c093b 3330 iwl3945_send_beacon_cmd(priv);
b481de9c
ZY
3331
3332 /* FIXME - we need to add code here to detect a totally new
3333 * configuration, reset the AP, unassoc, rxon timing, assoc,
3334 * clear sta table, add BCAST sta... */
3335}
3336
bb8c093b 3337static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
3338 struct ieee80211_vif *vif,
3339 struct ieee80211_sta *sta,
3340 struct ieee80211_key_conf *key)
b481de9c 3341{
4a8a4322 3342 struct iwl_priv *priv = hw->priv;
dc822b5d 3343 const u8 *addr;
6e21f15c
AK
3344 int ret = 0;
3345 u8 sta_id = IWL_INVALID_STATION;
3346 u8 static_key;
b481de9c 3347
e1623446 3348 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3349
df878d8f 3350 if (iwl3945_mod_params.sw_crypto) {
e1623446 3351 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
3352 return -EOPNOTSUPP;
3353 }
3354
42986796 3355 addr = sta ? sta->addr : iwl_bcast_addr;
6e21f15c
AK
3356 static_key = !iwl_is_associated(priv);
3357
3358 if (!static_key) {
c587de0b 3359 sta_id = iwl_find_station(priv, addr);
6e21f15c 3360 if (sta_id == IWL_INVALID_STATION) {
12514396 3361 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
6e21f15c
AK
3362 addr);
3363 return -EINVAL;
3364 }
b481de9c
ZY
3365 }
3366
3367 mutex_lock(&priv->mutex);
af0053d6 3368 iwl_scan_cancel_timeout(priv, 100);
6e21f15c 3369 mutex_unlock(&priv->mutex);
15e869d8 3370
b481de9c 3371 switch (cmd) {
6e21f15c
AK
3372 case SET_KEY:
3373 if (static_key)
3374 ret = iwl3945_set_static_key(priv, key);
3375 else
3376 ret = iwl3945_set_dynamic_key(priv, key, sta_id);
3377 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
3378 break;
3379 case DISABLE_KEY:
6e21f15c
AK
3380 if (static_key)
3381 ret = iwl3945_remove_static_key(priv);
3382 else
3383 ret = iwl3945_clear_sta_key_info(priv, sta_id);
3384 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
3385 break;
3386 default:
42986796 3387 ret = -EINVAL;
b481de9c
ZY
3388 }
3389
e1623446 3390 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3391
42986796 3392 return ret;
b481de9c
ZY
3393}
3394
b481de9c
ZY
3395/*****************************************************************************
3396 *
3397 * sysfs attributes
3398 *
3399 *****************************************************************************/
3400
d08853a3 3401#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3402
3403/*
3404 * The following adds a new attribute to the sysfs representation
3405 * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
3406 * used for controlling the debug level.
3407 *
3408 * See the level definitions in iwl for details.
a562a9dd 3409 *
3d816c77
RC
3410 * The debug_level being managed using sysfs below is a per device debug
3411 * level that is used instead of the global debug level if it (the per
3412 * device debug level) is set.
b481de9c 3413 */
40b8ec0b
SO
3414static ssize_t show_debug_level(struct device *d,
3415 struct device_attribute *attr, char *buf)
b481de9c 3416{
3d816c77
RC
3417 struct iwl_priv *priv = dev_get_drvdata(d);
3418 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 3419}
40b8ec0b
SO
3420static ssize_t store_debug_level(struct device *d,
3421 struct device_attribute *attr,
b481de9c
ZY
3422 const char *buf, size_t count)
3423{
928841b1 3424 struct iwl_priv *priv = dev_get_drvdata(d);
40b8ec0b
SO
3425 unsigned long val;
3426 int ret;
b481de9c 3427
40b8ec0b
SO
3428 ret = strict_strtoul(buf, 0, &val);
3429 if (ret)
978785a3 3430 IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 3431 else {
3d816c77 3432 priv->debug_level = val;
20594eb0
WYG
3433 if (iwl_alloc_traffic_mem(priv))
3434 IWL_ERR(priv,
3435 "Not enough memory to generate traffic log\n");
3436 }
b481de9c
ZY
3437 return strnlen(buf, count);
3438}
3439
40b8ec0b
SO
3440static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3441 show_debug_level, store_debug_level);
b481de9c 3442
d08853a3 3443#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3444
b481de9c
ZY
3445static ssize_t show_temperature(struct device *d,
3446 struct device_attribute *attr, char *buf)
3447{
928841b1 3448 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3449
775a6e27 3450 if (!iwl_is_alive(priv))
b481de9c
ZY
3451 return -EAGAIN;
3452
bb8c093b 3453 return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
b481de9c
ZY
3454}
3455
3456static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3457
b481de9c
ZY
3458static ssize_t show_tx_power(struct device *d,
3459 struct device_attribute *attr, char *buf)
3460{
928841b1 3461 struct iwl_priv *priv = dev_get_drvdata(d);
62ea9c5b 3462 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
3463}
3464
3465static ssize_t store_tx_power(struct device *d,
3466 struct device_attribute *attr,
3467 const char *buf, size_t count)
3468{
928841b1 3469 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3470 char *p = (char *)buf;
3471 u32 val;
3472
3473 val = simple_strtoul(p, &p, 10);
3474 if (p == buf)
978785a3 3475 IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
b481de9c 3476 else
bb8c093b 3477 iwl3945_hw_reg_set_txpower(priv, val);
b481de9c
ZY
3478
3479 return count;
3480}
3481
3482static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3483
3484static ssize_t show_flags(struct device *d,
3485 struct device_attribute *attr, char *buf)
3486{
928841b1 3487 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3488
8ccde88a 3489 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
b481de9c
ZY
3490}
3491
3492static ssize_t store_flags(struct device *d,
3493 struct device_attribute *attr,
3494 const char *buf, size_t count)
3495{
928841b1 3496 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3497 u32 flags = simple_strtoul(buf, NULL, 0);
3498
3499 mutex_lock(&priv->mutex);
8ccde88a 3500 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
b481de9c 3501 /* Cancel any currently running scans... */
af0053d6 3502 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3503 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3504 else {
e1623446 3505 IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
b481de9c 3506 flags);
8ccde88a 3507 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 3508 iwlcore_commit_rxon(priv);
b481de9c
ZY
3509 }
3510 }
3511 mutex_unlock(&priv->mutex);
3512
3513 return count;
3514}
3515
3516static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3517
3518static ssize_t show_filter_flags(struct device *d,
3519 struct device_attribute *attr, char *buf)
3520{
928841b1 3521 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3522
3523 return sprintf(buf, "0x%04X\n",
8ccde88a 3524 le32_to_cpu(priv->active_rxon.filter_flags));
b481de9c
ZY
3525}
3526
3527static ssize_t store_filter_flags(struct device *d,
3528 struct device_attribute *attr,
3529 const char *buf, size_t count)
3530{
928841b1 3531 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3532 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3533
3534 mutex_lock(&priv->mutex);
8ccde88a 3535 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
b481de9c 3536 /* Cancel any currently running scans... */
af0053d6 3537 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3538 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3539 else {
e1623446 3540 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c 3541 "0x%04X\n", filter_flags);
8ccde88a 3542 priv->staging_rxon.filter_flags =
b481de9c 3543 cpu_to_le32(filter_flags);
e0158e61 3544 iwlcore_commit_rxon(priv);
b481de9c
ZY
3545 }
3546 }
3547 mutex_unlock(&priv->mutex);
3548
3549 return count;
3550}
3551
3552static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3553 store_filter_flags);
3554
b481de9c
ZY
3555static ssize_t show_measurement(struct device *d,
3556 struct device_attribute *attr, char *buf)
3557{
4a8a4322 3558 struct iwl_priv *priv = dev_get_drvdata(d);
600c0e11 3559 struct iwl_spectrum_notification measure_report;
b481de9c 3560 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3ac7f146 3561 u8 *data = (u8 *)&measure_report;
b481de9c
ZY
3562 unsigned long flags;
3563
3564 spin_lock_irqsave(&priv->lock, flags);
3565 if (!(priv->measurement_status & MEASUREMENT_READY)) {
3566 spin_unlock_irqrestore(&priv->lock, flags);
3567 return 0;
3568 }
3569 memcpy(&measure_report, &priv->measure_report, size);
3570 priv->measurement_status = 0;
3571 spin_unlock_irqrestore(&priv->lock, flags);
3572
3573 while (size && (PAGE_SIZE - len)) {
3574 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3575 PAGE_SIZE - len, 1);
3576 len = strlen(buf);
3577 if (PAGE_SIZE - len)
3578 buf[len++] = '\n';
3579
3580 ofs += 16;
3581 size -= min(size, 16U);
3582 }
3583
3584 return len;
3585}
3586
3587static ssize_t store_measurement(struct device *d,
3588 struct device_attribute *attr,
3589 const char *buf, size_t count)
3590{
4a8a4322 3591 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3592 struct ieee80211_measurement_params params = {
8ccde88a 3593 .channel = le16_to_cpu(priv->active_rxon.channel),
b481de9c
ZY
3594 .start_time = cpu_to_le64(priv->last_tsf),
3595 .duration = cpu_to_le16(1),
3596 };
3597 u8 type = IWL_MEASURE_BASIC;
3598 u8 buffer[32];
3599 u8 channel;
3600
3601 if (count) {
3602 char *p = buffer;
3603 strncpy(buffer, buf, min(sizeof(buffer), count));
3604 channel = simple_strtoul(p, NULL, 0);
3605 if (channel)
3606 params.channel = channel;
3607
3608 p = buffer;
3609 while (*p && *p != ' ')
3610 p++;
3611 if (*p)
3612 type = simple_strtoul(p + 1, NULL, 0);
3613 }
3614
e1623446 3615 IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
b481de9c 3616 "channel %d (for '%s')\n", type, params.channel, buf);
bb8c093b 3617 iwl3945_get_measurement(priv, &params, type);
b481de9c
ZY
3618
3619 return count;
3620}
3621
3622static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
3623 show_measurement, store_measurement);
b481de9c 3624
b481de9c
ZY
3625static ssize_t store_retry_rate(struct device *d,
3626 struct device_attribute *attr,
3627 const char *buf, size_t count)
3628{
4a8a4322 3629 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3630
3631 priv->retry_rate = simple_strtoul(buf, NULL, 0);
3632 if (priv->retry_rate <= 0)
3633 priv->retry_rate = 1;
3634
3635 return count;
3636}
3637
3638static ssize_t show_retry_rate(struct device *d,
3639 struct device_attribute *attr, char *buf)
3640{
4a8a4322 3641 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3642 return sprintf(buf, "%d", priv->retry_rate);
3643}
3644
3645static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
3646 store_retry_rate);
3647
d25aabb0 3648
b481de9c
ZY
3649static ssize_t show_channels(struct device *d,
3650 struct device_attribute *attr, char *buf)
3651{
8318d78a
JB
3652 /* all this shit doesn't belong into sysfs anyway */
3653 return 0;
b481de9c
ZY
3654}
3655
3656static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
3657
3658static ssize_t show_statistics(struct device *d,
3659 struct device_attribute *attr, char *buf)
3660{
4a8a4322 3661 struct iwl_priv *priv = dev_get_drvdata(d);
bb8c093b 3662 u32 size = sizeof(struct iwl3945_notif_statistics);
b481de9c 3663 u32 len = 0, ofs = 0;
f2c7e521 3664 u8 *data = (u8 *)&priv->statistics_39;
b481de9c
ZY
3665 int rc = 0;
3666
775a6e27 3667 if (!iwl_is_alive(priv))
b481de9c
ZY
3668 return -EAGAIN;
3669
3670 mutex_lock(&priv->mutex);
ef8d5529 3671 rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
b481de9c
ZY
3672 mutex_unlock(&priv->mutex);
3673
3674 if (rc) {
3675 len = sprintf(buf,
3676 "Error sending statistics request: 0x%08X\n", rc);
3677 return len;
3678 }
3679
3680 while (size && (PAGE_SIZE - len)) {
3681 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3682 PAGE_SIZE - len, 1);
3683 len = strlen(buf);
3684 if (PAGE_SIZE - len)
3685 buf[len++] = '\n';
3686
3687 ofs += 16;
3688 size -= min(size, 16U);
3689 }
3690
3691 return len;
3692}
3693
3694static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3695
3696static ssize_t show_antenna(struct device *d,
3697 struct device_attribute *attr, char *buf)
3698{
4a8a4322 3699 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 3700
775a6e27 3701 if (!iwl_is_alive(priv))
b481de9c
ZY
3702 return -EAGAIN;
3703
7e4bca5e 3704 return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
b481de9c
ZY
3705}
3706
3707static ssize_t store_antenna(struct device *d,
3708 struct device_attribute *attr,
3709 const char *buf, size_t count)
3710{
7530f85f 3711 struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
b481de9c 3712 int ant;
b481de9c
ZY
3713
3714 if (count == 0)
3715 return 0;
3716
3717 if (sscanf(buf, "%1i", &ant) != 1) {
e1623446 3718 IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
b481de9c
ZY
3719 return count;
3720 }
3721
3722 if ((ant >= 0) && (ant <= 2)) {
e1623446 3723 IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
7e4bca5e 3724 iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
b481de9c 3725 } else
e1623446 3726 IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
b481de9c
ZY
3727
3728
3729 return count;
3730}
3731
3732static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
3733
3734static ssize_t show_status(struct device *d,
3735 struct device_attribute *attr, char *buf)
3736{
928841b1 3737 struct iwl_priv *priv = dev_get_drvdata(d);
775a6e27 3738 if (!iwl_is_alive(priv))
b481de9c
ZY
3739 return -EAGAIN;
3740 return sprintf(buf, "0x%08x\n", (int)priv->status);
3741}
3742
3743static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
3744
3745static ssize_t dump_error_log(struct device *d,
3746 struct device_attribute *attr,
3747 const char *buf, size_t count)
3748{
928841b1 3749 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
3750 char *p = (char *)buf;
3751
3752 if (p[0] == '1')
928841b1 3753 iwl3945_dump_nic_error_log(priv);
b481de9c
ZY
3754
3755 return strnlen(buf, count);
3756}
3757
3758static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
3759
b481de9c
ZY
3760/*****************************************************************************
3761 *
a96a27f9 3762 * driver setup and tear down
b481de9c
ZY
3763 *
3764 *****************************************************************************/
3765
4a8a4322 3766static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3767{
d21050c7 3768 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3769
3770 init_waitqueue_head(&priv->wait_command_queue);
3771
bb8c093b
CH
3772 INIT_WORK(&priv->restart, iwl3945_bg_restart);
3773 INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
bb8c093b 3774 INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
bb8c093b
CH
3775 INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
3776 INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
2663516d 3777 INIT_DELAYED_WORK(&priv->rfkill_poll, iwl3945_rfkill_poll);
77fecfb8
SO
3778 INIT_WORK(&priv->scan_completed, iwl_bg_scan_completed);
3779 INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
3780 INIT_WORK(&priv->abort_scan, iwl_bg_abort_scan);
3781 INIT_DELAYED_WORK(&priv->scan_check, iwl_bg_scan_check);
bb8c093b
CH
3782
3783 iwl3945_hw_setup_deferred_work(priv);
b481de9c
ZY
3784
3785 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
bb8c093b 3786 iwl3945_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3787}
3788
4a8a4322 3789static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3790{
bb8c093b 3791 iwl3945_hw_cancel_deferred_work(priv);
b481de9c 3792
e47eb6ad 3793 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3794 cancel_delayed_work(&priv->scan_check);
3795 cancel_delayed_work(&priv->alive_start);
b481de9c
ZY
3796 cancel_work_sync(&priv->beacon_update);
3797}
3798
bb8c093b 3799static struct attribute *iwl3945_sysfs_entries[] = {
b481de9c
ZY
3800 &dev_attr_antenna.attr,
3801 &dev_attr_channels.attr,
3802 &dev_attr_dump_errors.attr,
b481de9c
ZY
3803 &dev_attr_flags.attr,
3804 &dev_attr_filter_flags.attr,
b481de9c 3805 &dev_attr_measurement.attr,
b481de9c 3806 &dev_attr_retry_rate.attr,
b481de9c
ZY
3807 &dev_attr_statistics.attr,
3808 &dev_attr_status.attr,
3809 &dev_attr_temperature.attr,
b481de9c 3810 &dev_attr_tx_power.attr,
d08853a3 3811#ifdef CONFIG_IWLWIFI_DEBUG
40b8ec0b
SO
3812 &dev_attr_debug_level.attr,
3813#endif
b481de9c
ZY
3814 NULL
3815};
3816
bb8c093b 3817static struct attribute_group iwl3945_attribute_group = {
b481de9c 3818 .name = NULL, /* put in device directory */
bb8c093b 3819 .attrs = iwl3945_sysfs_entries,
b481de9c
ZY
3820};
3821
bb8c093b
CH
3822static struct ieee80211_ops iwl3945_hw_ops = {
3823 .tx = iwl3945_mac_tx,
3824 .start = iwl3945_mac_start,
3825 .stop = iwl3945_mac_stop,
cbb6ab94 3826 .add_interface = iwl_mac_add_interface,
d8052319 3827 .remove_interface = iwl_mac_remove_interface,
4808368d 3828 .config = iwl_mac_config,
8ccde88a 3829 .configure_filter = iwl_configure_filter,
bb8c093b 3830 .set_key = iwl3945_mac_set_key,
488829f1 3831 .conf_tx = iwl_mac_conf_tx,
bd564261 3832 .reset_tsf = iwl_mac_reset_tsf,
5bbe233b 3833 .bss_info_changed = iwl_bss_info_changed,
e9dde6f6 3834 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3835};
3836
e52119c5 3837static int iwl3945_init_drv(struct iwl_priv *priv)
90a30a02
KA
3838{
3839 int ret;
e6148917 3840 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
90a30a02
KA
3841
3842 priv->retry_rate = 1;
3843 priv->ibss_beacon = NULL;
3844
90a30a02
KA
3845 spin_lock_init(&priv->sta_lock);
3846 spin_lock_init(&priv->hcmd_lock);
3847
3848 INIT_LIST_HEAD(&priv->free_frames);
3849
3850 mutex_init(&priv->mutex);
d2dfe6df 3851 mutex_init(&priv->sync_cmd_mutex);
90a30a02
KA
3852
3853 /* Clear the driver's (not device's) station table */
c587de0b 3854 iwl_clear_stations_table(priv);
90a30a02 3855
90a30a02
KA
3856 priv->ieee_channels = NULL;
3857 priv->ieee_rates = NULL;
3858 priv->band = IEEE80211_BAND_2GHZ;
3859
3860 priv->iw_mode = NL80211_IFTYPE_STATION;
a13d276f 3861 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
90a30a02
KA
3862
3863 iwl_reset_qos(priv);
3864
3865 priv->qos_data.qos_active = 0;
3866 priv->qos_data.qos_cap.val = 0;
3867
3868 priv->rates_mask = IWL_RATES_MASK;
62ea9c5b 3869 priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
90a30a02 3870
e6148917
SO
3871 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3872 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
3873 eeprom->version);
3874 ret = -EINVAL;
3875 goto err;
3876 }
3877 ret = iwl_init_channel_map(priv);
90a30a02
KA
3878 if (ret) {
3879 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3880 goto err;
3881 }
3882
e6148917
SO
3883 /* Set up txpower settings in driver for all channels */
3884 if (iwl3945_txpower_set_from_eeprom(priv)) {
3885 ret = -EIO;
3886 goto err_free_channel_map;
3887 }
3888
534166de 3889 ret = iwlcore_init_geos(priv);
90a30a02
KA
3890 if (ret) {
3891 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3892 goto err_free_channel_map;
3893 }
534166de
SO
3894 iwl3945_init_hw_rates(priv, priv->ieee_rates);
3895
2a4ddaab
AK
3896 return 0;
3897
3898err_free_channel_map:
3899 iwl_free_channel_map(priv);
3900err:
3901 return ret;
3902}
3903
3904static int iwl3945_setup_mac(struct iwl_priv *priv)
3905{
3906 int ret;
3907 struct ieee80211_hw *hw = priv->hw;
3908
3909 hw->rate_control_algorithm = "iwl-3945-rs";
3910 hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
3911
3912 /* Tell mac80211 our characteristics */
3913 hw->flags = IEEE80211_HW_SIGNAL_DBM |
b1c6019b 3914 IEEE80211_HW_NOISE_DBM |
bc45a670
RC
3915 IEEE80211_HW_SPECTRUM_MGMT;
3916
3917 if (!priv->cfg->broken_powersave)
3918 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3919 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2a4ddaab
AK
3920
3921 hw->wiphy->interface_modes =
3922 BIT(NL80211_IFTYPE_STATION) |
3923 BIT(NL80211_IFTYPE_ADHOC);
3924
5be83de5
JB
3925 hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
3926 WIPHY_FLAG_DISABLE_BEACON_HINTS;
37184244 3927
1ecf9fc1
JB
3928 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3929 /* we create the 802.11 header and a zero-length SSID element */
3930 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
d60cc91a 3931
2a4ddaab
AK
3932 /* Default value; 4 EDCA QOS priorities */
3933 hw->queues = 4;
3934
534166de
SO
3935 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3936 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3937 &priv->bands[IEEE80211_BAND_2GHZ];
2a4ddaab 3938
534166de
SO
3939 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3940 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3941 &priv->bands[IEEE80211_BAND_5GHZ];
90a30a02 3942
2a4ddaab
AK
3943 ret = ieee80211_register_hw(priv->hw);
3944 if (ret) {
3945 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3946 return ret;
3947 }
3948 priv->mac80211_registered = 1;
90a30a02 3949
2a4ddaab 3950 return 0;
90a30a02
KA
3951}
3952
bb8c093b 3953static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3954{
3955 int err = 0;
4a8a4322 3956 struct iwl_priv *priv;
b481de9c 3957 struct ieee80211_hw *hw;
c0f20d91 3958 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
e6148917 3959 struct iwl3945_eeprom *eeprom;
0359facc 3960 unsigned long flags;
b481de9c 3961
cee53ddb
KA
3962 /***********************
3963 * 1. Allocating HW data
3964 * ********************/
3965
b481de9c
ZY
3966 /* mac80211 allocates memory for this device instance, including
3967 * space for this driver's private structure */
90a30a02 3968 hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
b481de9c 3969 if (hw == NULL) {
a3139c59 3970 printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
b481de9c
ZY
3971 err = -ENOMEM;
3972 goto out;
3973 }
b481de9c 3974 priv = hw->priv;
90a30a02 3975 SET_IEEE80211_DEV(hw, &pdev->dev);
6440adb5 3976
90a30a02
KA
3977 /*
3978 * Disabling hardware scan means that mac80211 will perform scans
3979 * "the hard way", rather than using device's scan.
3980 */
df878d8f 3981 if (iwl3945_mod_params.disable_hw_scan) {
e1623446 3982 IWL_DEBUG_INFO(priv, "Disabling hw_scan\n");
40b8ec0b
SO
3983 iwl3945_hw_ops.hw_scan = NULL;
3984 }
3985
90a30a02 3986
e1623446 3987 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
90a30a02
KA
3988 priv->cfg = cfg;
3989 priv->pci_dev = pdev;
40cefda9 3990 priv->inta_mask = CSR_INI_SET_MASK;
cee53ddb 3991
d08853a3 3992#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3993 atomic_set(&priv->restrict_refcnt, 0);
3994#endif
20594eb0
WYG
3995 if (iwl_alloc_traffic_mem(priv))
3996 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3997
cee53ddb
KA
3998 /***************************
3999 * 2. Initializing PCI bus
4000 * *************************/
b481de9c
ZY
4001 if (pci_enable_device(pdev)) {
4002 err = -ENODEV;
4003 goto out_ieee80211_free_hw;
4004 }
4005
4006 pci_set_master(pdev);
4007
284901a9 4008 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4009 if (!err)
284901a9 4010 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b481de9c 4011 if (err) {
978785a3 4012 IWL_WARN(priv, "No suitable DMA available.\n");
b481de9c
ZY
4013 goto out_pci_disable_device;
4014 }
4015
4016 pci_set_drvdata(pdev, priv);
4017 err = pci_request_regions(pdev, DRV_NAME);
4018 if (err)
4019 goto out_pci_disable_device;
6440adb5 4020
cee53ddb
KA
4021 /***********************
4022 * 3. Read REV Register
4023 * ********************/
b481de9c
ZY
4024 priv->hw_base = pci_iomap(pdev, 0, 0);
4025 if (!priv->hw_base) {
4026 err = -ENODEV;
4027 goto out_pci_release_regions;
4028 }
4029
e1623446 4030 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
b481de9c 4031 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4032 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
b481de9c 4033
cee53ddb
KA
4034 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4035 * PCI Tx retries from interfering with C3 CPU state */
4036 pci_write_config_byte(pdev, 0x41, 0x00);
b481de9c 4037
731a29b7 4038 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
4039 * we should init now
4040 */
4041 spin_lock_init(&priv->reg_lock);
731a29b7 4042 spin_lock_init(&priv->lock);
a8b50a0a 4043
4843b5a7
RC
4044 /*
4045 * stop and reset the on-board processor just in case it is in a
4046 * strange state ... like being left stranded by a primary kernel
4047 * and this is now the kdump kernel trying to start up
4048 */
4049 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4050
cee53ddb
KA
4051 /***********************
4052 * 4. Read EEPROM
4053 * ********************/
90a30a02 4054
cee53ddb 4055 /* Read the EEPROM */
e6148917 4056 err = iwl_eeprom_init(priv);
cee53ddb 4057 if (err) {
15b1687c 4058 IWL_ERR(priv, "Unable to init EEPROM\n");
c8f16138 4059 goto out_iounmap;
cee53ddb
KA
4060 }
4061 /* MAC Address location in EEPROM same for 3945/4965 */
e6148917
SO
4062 eeprom = (struct iwl3945_eeprom *)priv->eeprom;
4063 memcpy(priv->mac_addr, eeprom->mac_address, ETH_ALEN);
e1623446 4064 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
cee53ddb 4065 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
b481de9c 4066
cee53ddb
KA
4067 /***********************
4068 * 5. Setup HW Constants
4069 * ********************/
b481de9c 4070 /* Device-specific setup */
3832ec9d 4071 if (iwl3945_hw_set_hw_params(priv)) {
15b1687c 4072 IWL_ERR(priv, "failed to set hw settings\n");
c8f16138 4073 goto out_eeprom_free;
b481de9c
ZY
4074 }
4075
cee53ddb
KA
4076 /***********************
4077 * 6. Setup priv
4078 * ********************/
cee53ddb 4079
90a30a02 4080 err = iwl3945_init_drv(priv);
b481de9c 4081 if (err) {
90a30a02 4082 IWL_ERR(priv, "initializing driver failed\n");
c8f16138 4083 goto out_unset_hw_params;
b481de9c
ZY
4084 }
4085
978785a3
TW
4086 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
4087 priv->cfg->name);
cee53ddb 4088
cee53ddb 4089 /***********************
09f9bf79 4090 * 7. Setup Services
cee53ddb
KA
4091 * ********************/
4092
4093 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4094 iwl_disable_interrupts(priv);
cee53ddb
KA
4095 spin_unlock_irqrestore(&priv->lock, flags);
4096
2663516d
HS
4097 pci_enable_msi(priv->pci_dev);
4098
ef850d7c
MA
4099 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4100 IRQF_SHARED, DRV_NAME, priv);
2663516d
HS
4101 if (err) {
4102 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4103 goto out_disable_msi;
4104 }
4105
cee53ddb 4106 err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
849e0dce 4107 if (err) {
15b1687c 4108 IWL_ERR(priv, "failed to create sysfs device attributes\n");
90a30a02 4109 goto out_release_irq;
849e0dce 4110 }
849e0dce 4111
8ccde88a
SO
4112 iwl_set_rxon_channel(priv,
4113 &priv->bands[IEEE80211_BAND_2GHZ].channels[5]);
cee53ddb
KA
4114 iwl3945_setup_deferred_work(priv);
4115 iwl3945_setup_rx_handlers(priv);
008a9e3e 4116 iwl_power_initialize(priv);
cee53ddb 4117
cee53ddb 4118 /*********************************
09f9bf79 4119 * 8. Setup and Register mac80211
cee53ddb
KA
4120 * *******************************/
4121
2a4ddaab 4122 iwl_enable_interrupts(priv);
b481de9c 4123
2a4ddaab
AK
4124 err = iwl3945_setup_mac(priv);
4125 if (err)
4126 goto out_remove_sysfs;
cee53ddb 4127
a75fbe8d
AK
4128 err = iwl_dbgfs_register(priv, DRV_NAME);
4129 if (err)
4130 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
4131
2663516d
HS
4132 /* Start monitoring the killswitch */
4133 queue_delayed_work(priv->workqueue, &priv->rfkill_poll,
4134 2 * HZ);
4135
b481de9c
ZY
4136 return 0;
4137
cee53ddb 4138 out_remove_sysfs:
c8f16138
RC
4139 destroy_workqueue(priv->workqueue);
4140 priv->workqueue = NULL;
cee53ddb 4141 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4142 out_release_irq:
2663516d 4143 free_irq(priv->pci_dev->irq, priv);
2663516d
HS
4144 out_disable_msi:
4145 pci_disable_msi(priv->pci_dev);
c8f16138
RC
4146 iwlcore_free_geos(priv);
4147 iwl_free_channel_map(priv);
4148 out_unset_hw_params:
4149 iwl3945_unset_hw_params(priv);
4150 out_eeprom_free:
4151 iwl_eeprom_free(priv);
b481de9c
ZY
4152 out_iounmap:
4153 pci_iounmap(pdev, priv->hw_base);
4154 out_pci_release_regions:
4155 pci_release_regions(pdev);
4156 out_pci_disable_device:
b481de9c 4157 pci_set_drvdata(pdev, NULL);
623d563e 4158 pci_disable_device(pdev);
b481de9c 4159 out_ieee80211_free_hw:
20594eb0 4160 iwl_free_traffic_mem(priv);
d7c76f4c 4161 ieee80211_free_hw(priv->hw);
b481de9c
ZY
4162 out:
4163 return err;
4164}
4165
c83dbf68 4166static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
b481de9c 4167{
4a8a4322 4168 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4169 unsigned long flags;
b481de9c
ZY
4170
4171 if (!priv)
4172 return;
4173
e1623446 4174 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4175
a75fbe8d
AK
4176 iwl_dbgfs_unregister(priv);
4177
b481de9c 4178 set_bit(STATUS_EXIT_PENDING, &priv->status);
b24d22b1 4179
d552bfb6
KA
4180 if (priv->mac80211_registered) {
4181 ieee80211_unregister_hw(priv->hw);
4182 priv->mac80211_registered = 0;
4183 } else {
4184 iwl3945_down(priv);
4185 }
b481de9c 4186
c166b25a
BC
4187 /*
4188 * Make sure device is reset to low power before unloading driver.
4189 * This may be redundant with iwl_down(), but there are paths to
4190 * run iwl_down() without calling apm_ops.stop(), and there are
4191 * paths to avoid running iwl_down() at all before leaving driver.
4192 * This (inexpensive) call *makes sure* device is reset.
4193 */
4194 priv->cfg->ops->lib->apm_ops.stop(priv);
4195
0359facc
MA
4196 /* make sure we flush any pending irq or
4197 * tasklet for the driver
4198 */
4199 spin_lock_irqsave(&priv->lock, flags);
ed3b932e 4200 iwl_disable_interrupts(priv);
0359facc
MA
4201 spin_unlock_irqrestore(&priv->lock, flags);
4202
4203 iwl_synchronize_irq(priv);
4204
bb8c093b 4205 sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
b481de9c 4206
71d449b5 4207 cancel_delayed_work_sync(&priv->rfkill_poll);
2663516d 4208
bb8c093b 4209 iwl3945_dealloc_ucode_pci(priv);
b481de9c
ZY
4210
4211 if (priv->rxq.bd)
df833b1d 4212 iwl3945_rx_queue_free(priv, &priv->rxq);
bb8c093b 4213 iwl3945_hw_txq_ctx_free(priv);
b481de9c 4214
3832ec9d 4215 iwl3945_unset_hw_params(priv);
c587de0b 4216 iwl_clear_stations_table(priv);
b481de9c 4217
6ef89d0a
MA
4218 /*netif_stop_queue(dev); */
4219 flush_workqueue(priv->workqueue);
4220
bb8c093b 4221 /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
b481de9c
ZY
4222 * priv->workqueue... so we can't take down the workqueue
4223 * until now... */
4224 destroy_workqueue(priv->workqueue);
4225 priv->workqueue = NULL;
20594eb0 4226 iwl_free_traffic_mem(priv);
b481de9c 4227
2663516d
HS
4228 free_irq(pdev->irq, priv);
4229 pci_disable_msi(pdev);
4230
b481de9c
ZY
4231 pci_iounmap(pdev, priv->hw_base);
4232 pci_release_regions(pdev);
4233 pci_disable_device(pdev);
4234 pci_set_drvdata(pdev, NULL);
4235
e6148917 4236 iwl_free_channel_map(priv);
534166de 4237 iwlcore_free_geos(priv);
805cee5b 4238 kfree(priv->scan);
b481de9c
ZY
4239 if (priv->ibss_beacon)
4240 dev_kfree_skb(priv->ibss_beacon);
4241
4242 ieee80211_free_hw(priv->hw);
4243}
4244
b481de9c
ZY
4245
4246/*****************************************************************************
4247 *
4248 * driver and module entry point
4249 *
4250 *****************************************************************************/
4251
bb8c093b 4252static struct pci_driver iwl3945_driver = {
b481de9c 4253 .name = DRV_NAME,
bb8c093b
CH
4254 .id_table = iwl3945_hw_card_ids,
4255 .probe = iwl3945_pci_probe,
4256 .remove = __devexit_p(iwl3945_pci_remove),
b481de9c 4257#ifdef CONFIG_PM
6da3a13e
WYG
4258 .suspend = iwl_pci_suspend,
4259 .resume = iwl_pci_resume,
b481de9c
ZY
4260#endif
4261};
4262
bb8c093b 4263static int __init iwl3945_init(void)
b481de9c
ZY
4264{
4265
4266 int ret;
4267 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4268 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2
RC
4269
4270 ret = iwl3945_rate_control_register();
4271 if (ret) {
a3139c59
SO
4272 printk(KERN_ERR DRV_NAME
4273 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4274 return ret;
4275 }
4276
bb8c093b 4277 ret = pci_register_driver(&iwl3945_driver);
b481de9c 4278 if (ret) {
a3139c59 4279 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4280 goto error_register;
b481de9c 4281 }
b481de9c
ZY
4282
4283 return ret;
897e1cf2 4284
897e1cf2
RC
4285error_register:
4286 iwl3945_rate_control_unregister();
4287 return ret;
b481de9c
ZY
4288}
4289
bb8c093b 4290static void __exit iwl3945_exit(void)
b481de9c 4291{
bb8c093b 4292 pci_unregister_driver(&iwl3945_driver);
897e1cf2 4293 iwl3945_rate_control_unregister();
b481de9c
ZY
4294}
4295
a0987a8d 4296MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
25cb6cad 4297
4e30cb69 4298module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
b481de9c 4299MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4e30cb69 4300module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
9c74d9fb
SO
4301MODULE_PARM_DESC(swcrypto,
4302 "using software crypto (default 1 [software])\n");
a562a9dd 4303#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4304module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
b481de9c 4305MODULE_PARM_DESC(debug, "debug output mask");
a562a9dd 4306#endif
4e30cb69
WYG
4307module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
4308 int, S_IRUGO);
b481de9c 4309MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4e30cb69 4310module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
af48d048
SO
4311MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
4312
bb8c093b
CH
4313module_exit(iwl3945_exit);
4314module_init(iwl3945_init);