[thirdparty/kernel/stable.git] / drivers / net / wireless / mediatek / mt76 / mt76x2 / eeprom.c

// SPDX-License-Identifier: ISC
/*
 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
 */

#include <linux/module.h>
#include <linux/of.h>
#include <asm/unaligned.h>
#include "mt76x2.h"
#include "eeprom.h"

#define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1

static int
mt76x2_eeprom_get_macaddr(struct mt76x02_dev *dev)
{
	void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;

	memcpy(dev->mphy.macaddr, src, ETH_ALEN);
	return 0;
}

static bool
mt76x2_has_cal_free_data(struct mt76x02_dev *dev, u8 *efuse)
{
	u16 *efuse_w = (u16 *)efuse;

	if (efuse_w[MT_EE_NIC_CONF_0] != 0)
		return false;

	if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
		return false;

	if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
		return false;

	if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
		return false;

	if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
		return false;

	if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
		return false;

	return true;
}

static void
mt76x2_apply_cal_free_data(struct mt76x02_dev *dev, u8 *efuse)
{
#define GROUP_5G(_id)							   \
	MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id),	   \
	MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
	MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id),	   \
	MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1

	static const u8 cal_free_bytes[] = {
		MT_EE_XTAL_TRIM_1,
		MT_EE_TX_POWER_EXT_PA_5G + 1,
		MT_EE_TX_POWER_0_START_2G,
		MT_EE_TX_POWER_0_START_2G + 1,
		MT_EE_TX_POWER_1_START_2G,
		MT_EE_TX_POWER_1_START_2G + 1,
		GROUP_5G(0),
		GROUP_5G(1),
		GROUP_5G(2),
		GROUP_5G(3),
		GROUP_5G(4),
		GROUP_5G(5),
		MT_EE_RF_2G_TSSI_OFF_TXPOWER,
		MT_EE_RF_2G_RX_HIGH_GAIN + 1,
		MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
		MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
		MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
		MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
		MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
		MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
	};
	struct device_node *np = dev->mt76.dev->of_node;
	u8 *eeprom = dev->mt76.eeprom.data;
	u8 prev_grp0[4] = {
		eeprom[MT_EE_TX_POWER_0_START_5G],
		eeprom[MT_EE_TX_POWER_0_START_5G + 1],
		eeprom[MT_EE_TX_POWER_1_START_5G],
		eeprom[MT_EE_TX_POWER_1_START_5G + 1]
	};
	u16 val;
	int i;

	if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp"))
		return;

	if (!mt76x2_has_cal_free_data(dev, efuse))
		return;

	for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
		int offset = cal_free_bytes[i];

		eeprom[offset] = efuse[offset];
	}

	if (!(efuse[MT_EE_TX_POWER_0_START_5G] |
	      efuse[MT_EE_TX_POWER_0_START_5G + 1]))
		memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
	if (!(efuse[MT_EE_TX_POWER_1_START_5G] |
	      efuse[MT_EE_TX_POWER_1_START_5G + 1]))
		memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);

	val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
	if (val != 0xffff)
		eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;

	val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
	if (val != 0xffff)
		eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;

	val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
	if (val != 0xffff)
		eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
}

static int mt76x2_check_eeprom(struct mt76x02_dev *dev)
{
	u16 val = get_unaligned_le16(dev->mt76.eeprom.data);

	if (!val)
		val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);

	switch (val) {
	case 0x7662:
	case 0x7612:
		return 0;
	default:
		dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
		return -EINVAL;
	}
}

static int
mt76x2_eeprom_load(struct mt76x02_dev *dev)
{
	void *efuse;
	bool found;
	int ret;

	ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
	if (ret < 0)
		return ret;

	found = ret;
	if (found)
		found = !mt76x2_check_eeprom(dev);

	dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
					  GFP_KERNEL);
	dev->mt76.otp.size = MT7662_EEPROM_SIZE;
	if (!dev->mt76.otp.data)
		return -ENOMEM;

	efuse = dev->mt76.otp.data;

	if (mt76x02_get_efuse_data(dev, 0, efuse, MT7662_EEPROM_SIZE,
				   MT_EE_READ))
		goto out;

	if (found) {
		mt76x2_apply_cal_free_data(dev, efuse);
	} else {
		/* FIXME: check if efuse data is complete */
		found = true;
		memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
	}

out:
	if (!found)
		return -ENOENT;

	return 0;
}

static void
mt76x2_set_rx_gain_group(struct mt76x02_dev *dev, u8 val)
{
	s8 *dest = dev->cal.rx.high_gain;

	if (!mt76x02_field_valid(val)) {
		dest[0] = 0;
		dest[1] = 0;
		return;
	}

	dest[0] = mt76x02_sign_extend(val, 4);
	dest[1] = mt76x02_sign_extend(val >> 4, 4);
}

static void
mt76x2_set_rssi_offset(struct mt76x02_dev *dev, int chain, u8 val)
{
	s8 *dest = dev->cal.rx.rssi_offset;

	if (!mt76x02_field_valid(val)) {
		dest[chain] = 0;
		return;
	}

	dest[chain] = mt76x02_sign_extend_optional(val, 7);
}

static enum mt76x2_cal_channel_group
mt76x2_get_cal_channel_group(int channel)
{
	if (channel >= 184 && channel <= 196)
		return MT_CH_5G_JAPAN;
	if (channel <= 48)
		return MT_CH_5G_UNII_1;
	if (channel <= 64)
		return MT_CH_5G_UNII_2;
	if (channel <= 114)
		return MT_CH_5G_UNII_2E_1;
	if (channel <= 144)
		return MT_CH_5G_UNII_2E_2;
	return MT_CH_5G_UNII_3;
}

static u8
mt76x2_get_5g_rx_gain(struct mt76x02_dev *dev, u8 channel)
{
	enum mt76x2_cal_channel_group group;

	group = mt76x2_get_cal_channel_group(channel);
	switch (group) {
	case MT_CH_5G_JAPAN:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
	case MT_CH_5G_UNII_1:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
	case MT_CH_5G_UNII_2:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
	case MT_CH_5G_UNII_2E_1:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
	case MT_CH_5G_UNII_2E_2:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
	default:
		return mt76x02_eeprom_get(dev,
					  MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
	}
}

void mt76x2_read_rx_gain(struct mt76x02_dev *dev)
{
	struct ieee80211_channel *chan = dev->mphy.chandef.chan;
	int channel = chan->hw_value;
	s8 lna_5g[3], lna_2g;
	bool use_lna;
	u8 lna = 0;
	u16 val;

	if (chan->band == NL80211_BAND_2GHZ)
		val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
	else
		val = mt76x2_get_5g_rx_gain(dev, channel);

	mt76x2_set_rx_gain_group(dev, val);

	mt76x02_get_rx_gain(dev, chan->band, &val, &lna_2g, lna_5g);
	mt76x2_set_rssi_offset(dev, 0, val);
	mt76x2_set_rssi_offset(dev, 1, val >> 8);

	dev->cal.rx.mcu_gain =  (lna_2g & 0xff);
	dev->cal.rx.mcu_gain |= (lna_5g[0] & 0xff) << 8;
	dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
	dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;

	val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
	if (chan->band == NL80211_BAND_2GHZ)
		use_lna = !(val & MT_EE_NIC_CONF_1_LNA_EXT_2G);
	else
		use_lna = !(val & MT_EE_NIC_CONF_1_LNA_EXT_5G);

	if (use_lna)
		lna = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);

	dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8);
}
EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);

void mt76x2_get_rate_power(struct mt76x02_dev *dev, struct mt76x02_rate_power *t,
			   struct ieee80211_channel *chan)
{
	bool is_5ghz;
	u16 val;

	is_5ghz = chan->band == NL80211_BAND_5GHZ;

	memset(t, 0, sizeof(*t));

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_CCK);
	t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val);
	t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8);

	if (is_5ghz)
		val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
	else
		val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
	t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val);
	t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8);

	if (is_5ghz)
		val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
	else
		val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
	t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val);
	t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8);

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
	t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val);
	t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8);

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
	t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val);
	t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8);

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
	t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val);
	t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8);

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
	t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val);
	t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8);

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
	if (!is_5ghz)
		val >>= 8;
	t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val >> 8);
}
EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);

static void
mt76x2_get_power_info_2g(struct mt76x02_dev *dev,
			 struct mt76x2_tx_power_info *t,
			 struct ieee80211_channel *chan,
			 int chain, int offset)
{
	int channel = chan->hw_value;
	int delta_idx;
	u8 data[6];
	u16 val;

	if (channel < 6)
		delta_idx = 3;
	else if (channel < 11)
		delta_idx = 4;
	else
		delta_idx = 5;

	mt76x02_eeprom_copy(dev, offset, data, sizeof(data));

	t->chain[chain].tssi_slope = data[0];
	t->chain[chain].tssi_offset = data[1];
	t->chain[chain].target_power = data[2];
	t->chain[chain].delta =
		mt76x02_sign_extend_optional(data[delta_idx], 7);

	val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
	t->target_power = val >> 8;
}

static void
mt76x2_get_power_info_5g(struct mt76x02_dev *dev,
			 struct mt76x2_tx_power_info *t,
			 struct ieee80211_channel *chan,
			 int chain, int offset)
{
	int channel = chan->hw_value;
	enum mt76x2_cal_channel_group group;
	int delta_idx;
	u16 val;
	u8 data[5];

	group = mt76x2_get_cal_channel_group(channel);
	offset += group * MT_TX_POWER_GROUP_SIZE_5G;

	if (channel >= 192)
		delta_idx = 4;
	else if (channel >= 184)
		delta_idx = 3;
	else if (channel < 44)
		delta_idx = 3;
	else if (channel < 52)
		delta_idx = 4;
	else if (channel < 58)
		delta_idx = 3;
	else if (channel < 98)
		delta_idx = 4;
	else if (channel < 106)
		delta_idx = 3;
	else if (channel < 116)
		delta_idx = 4;
	else if (channel < 130)
		delta_idx = 3;
	else if (channel < 149)
		delta_idx = 4;
	else if (channel < 157)
		delta_idx = 3;
	else
		delta_idx = 4;

	mt76x02_eeprom_copy(dev, offset, data, sizeof(data));

	t->chain[chain].tssi_slope = data[0];
	t->chain[chain].tssi_offset = data[1];
	t->chain[chain].target_power = data[2];
	t->chain[chain].delta =
		mt76x02_sign_extend_optional(data[delta_idx], 7);

	val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
	t->target_power = val & 0xff;
}

void mt76x2_get_power_info(struct mt76x02_dev *dev,
			   struct mt76x2_tx_power_info *t,
			   struct ieee80211_channel *chan)
{
	u16 bw40, bw80;

	memset(t, 0, sizeof(*t));

	bw40 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
	bw80 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);

	if (chan->band == NL80211_BAND_5GHZ) {
		bw40 >>= 8;
		mt76x2_get_power_info_5g(dev, t, chan, 0,
					 MT_EE_TX_POWER_0_START_5G);
		mt76x2_get_power_info_5g(dev, t, chan, 1,
					 MT_EE_TX_POWER_1_START_5G);
	} else {
		mt76x2_get_power_info_2g(dev, t, chan, 0,
					 MT_EE_TX_POWER_0_START_2G);
		mt76x2_get_power_info_2g(dev, t, chan, 1,
					 MT_EE_TX_POWER_1_START_2G);
	}

	if (mt76x2_tssi_enabled(dev) ||
	    !mt76x02_field_valid(t->target_power))
		t->target_power = t->chain[0].target_power;

	t->delta_bw40 = mt76x02_rate_power_val(bw40);
	t->delta_bw80 = mt76x02_rate_power_val(bw80);
}
EXPORT_SYMBOL_GPL(mt76x2_get_power_info);

int mt76x2_get_temp_comp(struct mt76x02_dev *dev, struct mt76x2_temp_comp *t)
{
	enum nl80211_band band = dev->mphy.chandef.chan->band;
	u16 val, slope;
	u8 bounds;

	memset(t, 0, sizeof(*t));

	if (!mt76x2_temp_tx_alc_enabled(dev))
		return -EINVAL;

	if (!mt76x02_ext_pa_enabled(dev, band))
		return -EINVAL;

	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
	t->temp_25_ref = val & 0x7f;
	if (band == NL80211_BAND_5GHZ) {
		slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
		bounds = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
	} else {
		slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
		bounds = mt76x02_eeprom_get(dev,
					    MT_EE_TX_POWER_DELTA_BW80) >> 8;
	}

	t->high_slope = slope & 0xff;
	t->low_slope = slope >> 8;
	t->lower_bound = 0 - (bounds & 0xf);
	t->upper_bound = (bounds >> 4) & 0xf;

	return 0;
}
EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);

int mt76x2_eeprom_init(struct mt76x02_dev *dev)
{
	int ret;

	ret = mt76x2_eeprom_load(dev);
	if (ret)
		return ret;

	mt76x02_eeprom_parse_hw_cap(dev);
	mt76x2_eeprom_get_macaddr(dev);
	mt76_eeprom_override(&dev->mphy);
	dev->mphy.macaddr[0] &= ~BIT(1);

	return 0;
}
EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);

MODULE_LICENSE("Dual BSD/GPL");
Commit	Line	Data
0e3d6777	1	// SPDX-License-Identifier: ISC
7bc04215 FF	2	/*
7bc04215 FF	3	* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
7bc04215 FF	4	*/
7bc04215 FF	5
db6bb5c6	6	#include <linux/module.h>
9a865741	7	#include <linux/of.h>
7bc04215 FF	8	#include <asm/unaligned.h>
7bc04215 FF	9	#include "mt76x2.h"
1613c621	10	#include "eeprom.h"
7bc04215 FF	11
	12	#define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) \| 1
	13
7bc04215	14	static int
e40803f2	15	mt76x2_eeprom_get_macaddr(struct mt76x02_dev *dev)
7bc04215 FF	16	{
	17	void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;
	18
98df2bae	19	memcpy(dev->mphy.macaddr, src, ETH_ALEN);
7bc04215 FF	20	return 0;
	21	}
	22
7bc04215	23	static bool
e40803f2	24	mt76x2_has_cal_free_data(struct mt76x02_dev dev, u8 efuse)
7bc04215	25	{
ff97c52a	26	u16 efuse_w = (u16 )efuse;
7bc04215 FF	27
	28	if (efuse_w[MT_EE_NIC_CONF_0] != 0)
	29	return false;
	30
	31	if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
	32	return false;
	33
	34	if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
	35	return false;
	36
	37	if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
	38	return false;
	39
	40	if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
	41	return false;
	42
	43	if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
	44	return false;
	45
	46	return true;
	47	}
	48
	49	static void
e40803f2	50	mt76x2_apply_cal_free_data(struct mt76x02_dev dev, u8 efuse)
7bc04215 FF	51	{
	52	#define GROUP_5G(_id) \
	53	MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
	54	MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
	55	MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
	56	MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
	57
	58	static const u8 cal_free_bytes[] = {
	59	MT_EE_XTAL_TRIM_1,
	60	MT_EE_TX_POWER_EXT_PA_5G + 1,
	61	MT_EE_TX_POWER_0_START_2G,
	62	MT_EE_TX_POWER_0_START_2G + 1,
	63	MT_EE_TX_POWER_1_START_2G,
	64	MT_EE_TX_POWER_1_START_2G + 1,
	65	GROUP_5G(0),
	66	GROUP_5G(1),
	67	GROUP_5G(2),
	68	GROUP_5G(3),
	69	GROUP_5G(4),
	70	GROUP_5G(5),
	71	MT_EE_RF_2G_TSSI_OFF_TXPOWER,
	72	MT_EE_RF_2G_RX_HIGH_GAIN + 1,
	73	MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
	74	MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
	75	MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
	76	MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
	77	MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
	78	MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
	79	};
9a865741	80	struct device_node *np = dev->mt76.dev->of_node;
7bc04215 FF	81	u8 *eeprom = dev->mt76.eeprom.data;
	82	u8 prev_grp0[4] = {
	83	eeprom[MT_EE_TX_POWER_0_START_5G],
	84	eeprom[MT_EE_TX_POWER_0_START_5G + 1],
	85	eeprom[MT_EE_TX_POWER_1_START_5G],
	86	eeprom[MT_EE_TX_POWER_1_START_5G + 1]
	87	};
	88	u16 val;
	89	int i;
	90
9a865741 FF	91	if (!np \|\| !of_property_read_bool(np, "mediatek,eeprom-merge-otp"))
	92	return;
	93
7bc04215 FF	94	if (!mt76x2_has_cal_free_data(dev, efuse))
	95	return;
	96
	97	for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
	98	int offset = cal_free_bytes[i];
	99
	100	eeprom[offset] = efuse[offset];
	101	}
	102
	103	if (!(efuse[MT_EE_TX_POWER_0_START_5G] \|
	104	efuse[MT_EE_TX_POWER_0_START_5G + 1]))
	105	memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
	106	if (!(efuse[MT_EE_TX_POWER_1_START_5G] \|
	107	efuse[MT_EE_TX_POWER_1_START_5G + 1]))
	108	memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);
	109
	110	val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
	111	if (val != 0xffff)
	112	eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;
	113
	114	val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
	115	if (val != 0xffff)
	116	eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;
	117
	118	val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
	119	if (val != 0xffff)
	120	eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
	121	}
	122
e40803f2	123	static int mt76x2_check_eeprom(struct mt76x02_dev *dev)
7bc04215 FF	124	{
	125	u16 val = get_unaligned_le16(dev->mt76.eeprom.data);
	126
	127	if (!val)
	128	val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);
	129
	130	switch (val) {
	131	case 0x7662:
	132	case 0x7612:
	133	return 0;
	134	default:
	135	dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
	136	return -EINVAL;
	137	}
	138	}
	139
	140	static int
e40803f2	141	mt76x2_eeprom_load(struct mt76x02_dev *dev)
7bc04215 FF	142	{
7bc04215 FF	143	void *efuse;
7bc04215 FF	144	bool found;
	145	int ret;
	146
fbae9c74	147	ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
7bc04215 FF	148	if (ret < 0)
	149	return ret;
	150
	151	found = ret;
	152	if (found)
	153	found = !mt76x2_check_eeprom(dev);
	154
fbae9c74 LB	155	dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
	156	GFP_KERNEL);
	157	dev->mt76.otp.size = MT7662_EEPROM_SIZE;
7bc04215 FF	158	if (!dev->mt76.otp.data)
	159	return -ENOMEM;
	160
	161	efuse = dev->mt76.otp.data;
	162
26a9daa6 LB	163	if (mt76x02_get_efuse_data(dev, 0, efuse, MT7662_EEPROM_SIZE,
26a9daa6 LB	164	MT_EE_READ))
7bc04215 FF	165	goto out;
	166
	167	if (found) {
	168	mt76x2_apply_cal_free_data(dev, efuse);
	169	} else {
	170	/* FIXME: check if efuse data is complete */
	171	found = true;
fbae9c74	172	memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
7bc04215 FF	173	}
	174
	175	out:
	176	if (!found)
	177	return -ENOENT;
	178
	179	return 0;
	180	}
	181
7bc04215	182	static void
e40803f2	183	mt76x2_set_rx_gain_group(struct mt76x02_dev *dev, u8 val)
7bc04215 FF	184	{
	185	s8 *dest = dev->cal.rx.high_gain;
	186
86c71d3d	187	if (!mt76x02_field_valid(val)) {
7bc04215 FF	188	dest[0] = 0;
	189	dest[1] = 0;
	190	return;
	191	}
	192
86c71d3d LB	193	dest[0] = mt76x02_sign_extend(val, 4);
86c71d3d LB	194	dest[1] = mt76x02_sign_extend(val >> 4, 4);
7bc04215 FF	195	}
	196
	197	static void
e40803f2	198	mt76x2_set_rssi_offset(struct mt76x02_dev *dev, int chain, u8 val)
7bc04215 FF	199	{
	200	s8 *dest = dev->cal.rx.rssi_offset;
	201
86c71d3d	202	if (!mt76x02_field_valid(val)) {
7bc04215 FF	203	dest[chain] = 0;
	204	return;
	205	}
	206
02a4251d	207	dest[chain] = mt76x02_sign_extend_optional(val, 7);
7bc04215 FF	208	}
	209
	210	static enum mt76x2_cal_channel_group
	211	mt76x2_get_cal_channel_group(int channel)
	212	{
	213	if (channel >= 184 && channel <= 196)
	214	return MT_CH_5G_JAPAN;
	215	if (channel <= 48)
	216	return MT_CH_5G_UNII_1;
	217	if (channel <= 64)
	218	return MT_CH_5G_UNII_2;
	219	if (channel <= 114)
	220	return MT_CH_5G_UNII_2E_1;
	221	if (channel <= 144)
	222	return MT_CH_5G_UNII_2E_2;
	223	return MT_CH_5G_UNII_3;
	224	}
	225
	226	static u8
e40803f2	227	mt76x2_get_5g_rx_gain(struct mt76x02_dev *dev, u8 channel)
7bc04215 FF	228	{
	229	enum mt76x2_cal_channel_group group;
	230
	231	group = mt76x2_get_cal_channel_group(channel);
	232	switch (group) {
	233	case MT_CH_5G_JAPAN:
26a9daa6	234	return mt76x02_eeprom_get(dev,
b27823a7	235	MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
7bc04215	236	case MT_CH_5G_UNII_1:
26a9daa6	237	return mt76x02_eeprom_get(dev,
b27823a7	238	MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
7bc04215	239	case MT_CH_5G_UNII_2:
26a9daa6	240	return mt76x02_eeprom_get(dev,
b27823a7	241	MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
7bc04215	242	case MT_CH_5G_UNII_2E_1:
26a9daa6	243	return mt76x02_eeprom_get(dev,
b27823a7	244	MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
7bc04215	245	case MT_CH_5G_UNII_2E_2:
26a9daa6	246	return mt76x02_eeprom_get(dev,
b27823a7	247	MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
7bc04215	248	default:
26a9daa6	249	return mt76x02_eeprom_get(dev,
b27823a7	250	MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
7bc04215 FF	251	}
	252	}
	253
e40803f2	254	void mt76x2_read_rx_gain(struct mt76x02_dev *dev)
7bc04215	255	{
96747a51	256	struct ieee80211_channel *chan = dev->mphy.chandef.chan;
7bc04215 FF	257	int channel = chan->hw_value;
7bc04215 FF	258	s8 lna_5g[3], lna_2g;
684e45e1 FF	259	bool use_lna;
684e45e1 FF	260	u8 lna = 0;
7bc04215 FF	261	u16 val;
	262
	263	if (chan->band == NL80211_BAND_2GHZ)
26a9daa6	264	val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
7bc04215 FF	265	else
	266	val = mt76x2_get_5g_rx_gain(dev, channel);
	267
	268	mt76x2_set_rx_gain_group(dev, val);
	269
26a9daa6	270	mt76x02_get_rx_gain(dev, chan->band, &val, &lna_2g, lna_5g);
e59ad99b LB	271	mt76x2_set_rssi_offset(dev, 0, val);
e59ad99b LB	272	mt76x2_set_rssi_offset(dev, 1, val >> 8);
7bc04215 FF	273
	274	dev->cal.rx.mcu_gain = (lna_2g & 0xff);
	275	dev->cal.rx.mcu_gain \|= (lna_5g[0] & 0xff) << 8;
	276	dev->cal.rx.mcu_gain \|= (lna_5g[1] & 0xff) << 16;
	277	dev->cal.rx.mcu_gain \|= (lna_5g[2] & 0xff) << 24;
	278
684e45e1 FF	279	val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
	280	if (chan->band == NL80211_BAND_2GHZ)
	281	use_lna = !(val & MT_EE_NIC_CONF_1_LNA_EXT_2G);
	282	else
	283	use_lna = !(val & MT_EE_NIC_CONF_1_LNA_EXT_5G);
	284
	285	if (use_lna)
	286	lna = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
	287
86c71d3d	288	dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8);
7bc04215	289	}
d20ad581	290	EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
7bc04215	291
b376d963	292	void mt76x2_get_rate_power(struct mt76x02_dev dev, struct mt76x02_rate_power t,
60e2434c	293	struct ieee80211_channel *chan)
7bc04215 FF	294	{
	295	bool is_5ghz;
	296	u16 val;
	297
60e2434c	298	is_5ghz = chan->band == NL80211_BAND_5GHZ;
7bc04215 FF	299
	300	memset(t, 0, sizeof(*t));
	301
26a9daa6	302	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_CCK);
02a4251d LB	303	t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val);
02a4251d LB	304	t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8);
7bc04215 FF	305
7bc04215 FF	306	if (is_5ghz)
26a9daa6	307	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
7bc04215	308	else
26a9daa6	309	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
02a4251d LB	310	t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val);
02a4251d LB	311	t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8);
7bc04215 FF	312
7bc04215 FF	313	if (is_5ghz)
26a9daa6	314	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
7bc04215	315	else
26a9daa6	316	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
02a4251d LB	317	t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val);
02a4251d LB	318	t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8);
7bc04215	319
26a9daa6	320	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
02a4251d LB	321	t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val);
02a4251d LB	322	t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8);
7bc04215	323
26a9daa6	324	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
02a4251d LB	325	t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val);
02a4251d LB	326	t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8);
7bc04215	327
26a9daa6	328	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
02a4251d LB	329	t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val);
02a4251d LB	330	t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8);
7bc04215	331
26a9daa6	332	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
02a4251d LB	333	t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val);
02a4251d LB	334	t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8);
7bc04215	335
26a9daa6	336	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
7bc04215 FF	337	if (!is_5ghz)
7bc04215 FF	338	val >>= 8;
ba45841c	339	t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val >> 8);
7bc04215	340	}
d20ad581	341	EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);
7bc04215 FF	342
7bc04215 FF	343	static void
e40803f2 LB	344	mt76x2_get_power_info_2g(struct mt76x02_dev *dev,
	345	struct mt76x2_tx_power_info *t,
	346	struct ieee80211_channel *chan,
	347	int chain, int offset)
7bc04215	348	{
60e2434c	349	int channel = chan->hw_value;
7bc04215 FF	350	int delta_idx;
	351	u8 data[6];
	352	u16 val;
	353
	354	if (channel < 6)
	355	delta_idx = 3;
	356	else if (channel < 11)
	357	delta_idx = 4;
	358	else
	359	delta_idx = 5;
	360
693792ec	361	mt76x02_eeprom_copy(dev, offset, data, sizeof(data));
7bc04215 FF	362
	363	t->chain[chain].tssi_slope = data[0];
	364	t->chain[chain].tssi_offset = data[1];
	365	t->chain[chain].target_power = data[2];
ff97c52a RL	366	t->chain[chain].delta =
ff97c52a RL	367	mt76x02_sign_extend_optional(data[delta_idx], 7);
7bc04215	368
26a9daa6	369	val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
7bc04215 FF	370	t->target_power = val >> 8;
	371	}
	372
	373	static void
e40803f2 LB	374	mt76x2_get_power_info_5g(struct mt76x02_dev *dev,
e40803f2 LB	375	struct mt76x2_tx_power_info *t,
ff97c52a	376	struct ieee80211_channel *chan,
e40803f2	377	int chain, int offset)
7bc04215	378	{
60e2434c	379	int channel = chan->hw_value;
7bc04215 FF	380	enum mt76x2_cal_channel_group group;
	381	int delta_idx;
	382	u16 val;
	383	u8 data[5];
	384
	385	group = mt76x2_get_cal_channel_group(channel);
	386	offset += group * MT_TX_POWER_GROUP_SIZE_5G;
	387
	388	if (channel >= 192)
	389	delta_idx = 4;
c3929a98	390	else if (channel >= 184)
7bc04215 FF	391	delta_idx = 3;
	392	else if (channel < 44)
	393	delta_idx = 3;
	394	else if (channel < 52)
	395	delta_idx = 4;
	396	else if (channel < 58)
	397	delta_idx = 3;
	398	else if (channel < 98)
	399	delta_idx = 4;
	400	else if (channel < 106)
	401	delta_idx = 3;
	402	else if (channel < 116)
	403	delta_idx = 4;
	404	else if (channel < 130)
	405	delta_idx = 3;
	406	else if (channel < 149)
	407	delta_idx = 4;
	408	else if (channel < 157)
	409	delta_idx = 3;
	410	else
	411	delta_idx = 4;
	412
693792ec	413	mt76x02_eeprom_copy(dev, offset, data, sizeof(data));
7bc04215 FF	414
	415	t->chain[chain].tssi_slope = data[0];
	416	t->chain[chain].tssi_offset = data[1];
	417	t->chain[chain].target_power = data[2];
ff97c52a RL	418	t->chain[chain].delta =
ff97c52a RL	419	mt76x02_sign_extend_optional(data[delta_idx], 7);
7bc04215	420
26a9daa6	421	val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
7bc04215 FF	422	t->target_power = val & 0xff;
	423	}
	424
e40803f2	425	void mt76x2_get_power_info(struct mt76x02_dev *dev,
60e2434c FF	426	struct mt76x2_tx_power_info *t,
60e2434c FF	427	struct ieee80211_channel *chan)
7bc04215 FF	428	{
	429	u16 bw40, bw80;
	430
	431	memset(t, 0, sizeof(*t));
	432
26a9daa6 LB	433	bw40 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
26a9daa6 LB	434	bw80 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
7bc04215	435
60e2434c	436	if (chan->band == NL80211_BAND_5GHZ) {
7bc04215	437	bw40 >>= 8;
60e2434c FF	438	mt76x2_get_power_info_5g(dev, t, chan, 0,
	439	MT_EE_TX_POWER_0_START_5G);
	440	mt76x2_get_power_info_5g(dev, t, chan, 1,
	441	MT_EE_TX_POWER_1_START_5G);
7bc04215	442	} else {
60e2434c FF	443	mt76x2_get_power_info_2g(dev, t, chan, 0,
	444	MT_EE_TX_POWER_0_START_2G);
	445	mt76x2_get_power_info_2g(dev, t, chan, 1,
	446	MT_EE_TX_POWER_1_START_2G);
7bc04215 FF	447	}
7bc04215 FF	448
4afeb396	449	if (mt76x2_tssi_enabled(dev) \|\|
86c71d3d	450	!mt76x02_field_valid(t->target_power))
7bc04215 FF	451	t->target_power = t->chain[0].target_power;
7bc04215 FF	452
02a4251d LB	453	t->delta_bw40 = mt76x02_rate_power_val(bw40);
02a4251d LB	454	t->delta_bw80 = mt76x02_rate_power_val(bw80);
7bc04215	455	}
d20ad581	456	EXPORT_SYMBOL_GPL(mt76x2_get_power_info);
7bc04215	457
e40803f2	458	int mt76x2_get_temp_comp(struct mt76x02_dev dev, struct mt76x2_temp_comp t)
7bc04215	459	{
96747a51	460	enum nl80211_band band = dev->mphy.chandef.chan->band;
7bc04215 FF	461	u16 val, slope;
	462	u8 bounds;
	463
	464	memset(t, 0, sizeof(*t));
	465
4afeb396	466	if (!mt76x2_temp_tx_alc_enabled(dev))
7bc04215 FF	467	return -EINVAL;
7bc04215 FF	468
26a9daa6	469	if (!mt76x02_ext_pa_enabled(dev, band))
7bc04215 FF	470	return -EINVAL;
7bc04215 FF	471
26a9daa6	472	val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
7bc04215 FF	473	t->temp_25_ref = val & 0x7f;
7bc04215 FF	474	if (band == NL80211_BAND_5GHZ) {
26a9daa6 LB	475	slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
26a9daa6 LB	476	bounds = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
7bc04215	477	} else {
26a9daa6 LB	478	slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
26a9daa6 LB	479	bounds = mt76x02_eeprom_get(dev,
b27823a7	480	MT_EE_TX_POWER_DELTA_BW80) >> 8;
7bc04215 FF	481	}
	482
	483	t->high_slope = slope & 0xff;
	484	t->low_slope = slope >> 8;
	485	t->lower_bound = 0 - (bounds & 0xf);
	486	t->upper_bound = (bounds >> 4) & 0xf;
	487
	488	return 0;
	489	}
d20ad581	490	EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);
7bc04215	491
e40803f2	492	int mt76x2_eeprom_init(struct mt76x02_dev *dev)
7bc04215 FF	493	{
	494	int ret;
	495
	496	ret = mt76x2_eeprom_load(dev);
	497	if (ret)
	498	return ret;
	499
26a9daa6	500	mt76x02_eeprom_parse_hw_cap(dev);
7bc04215	501	mt76x2_eeprom_get_macaddr(dev);
98df2bae LB	502	mt76_eeprom_override(&dev->mphy);
98df2bae LB	503	dev->mphy.macaddr[0] &= ~BIT(1);
7bc04215 FF	504
	505	return 0;
	506	}
d20ad581 LB	507	EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);
	508
	509	MODULE_LICENSE("Dual BSD/GPL");