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Commit | Line | Data |
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181d6902 | 1 | /* |
7e613e16 ID |
2 | Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> |
3 | Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> | |
9c9a0d14 | 4 | Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> |
181d6902 ID |
5 | <http://rt2x00.serialmonkey.com> |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a05b8c58 | 18 | along with this program; if not, see <http://www.gnu.org/licenses/>. |
181d6902 ID |
19 | */ |
20 | ||
21 | /* | |
22 | Module: rt2x00lib | |
23 | Abstract: rt2x00 queue specific routines. | |
24 | */ | |
25 | ||
5a0e3ad6 | 26 | #include <linux/slab.h> |
181d6902 ID |
27 | #include <linux/kernel.h> |
28 | #include <linux/module.h> | |
c4da0048 | 29 | #include <linux/dma-mapping.h> |
181d6902 ID |
30 | |
31 | #include "rt2x00.h" | |
32 | #include "rt2x00lib.h" | |
33 | ||
88211021 | 34 | struct sk_buff *rt2x00queue_alloc_rxskb(struct queue_entry *entry, gfp_t gfp) |
239c249d | 35 | { |
f0bda571 SG |
36 | struct data_queue *queue = entry->queue; |
37 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
c4da0048 GW |
38 | struct sk_buff *skb; |
39 | struct skb_frame_desc *skbdesc; | |
2bb057d0 ID |
40 | unsigned int frame_size; |
41 | unsigned int head_size = 0; | |
42 | unsigned int tail_size = 0; | |
239c249d GW |
43 | |
44 | /* | |
45 | * The frame size includes descriptor size, because the | |
46 | * hardware directly receive the frame into the skbuffer. | |
47 | */ | |
f0bda571 | 48 | frame_size = queue->data_size + queue->desc_size + queue->winfo_size; |
239c249d GW |
49 | |
50 | /* | |
ff352391 ID |
51 | * The payload should be aligned to a 4-byte boundary, |
52 | * this means we need at least 3 bytes for moving the frame | |
53 | * into the correct offset. | |
239c249d | 54 | */ |
2bb057d0 ID |
55 | head_size = 4; |
56 | ||
57 | /* | |
58 | * For IV/EIV/ICV assembly we must make sure there is | |
59 | * at least 8 bytes bytes available in headroom for IV/EIV | |
9c3444d3 | 60 | * and 8 bytes for ICV data as tailroon. |
2bb057d0 | 61 | */ |
7b8a00dc | 62 | if (rt2x00_has_cap_hw_crypto(rt2x00dev)) { |
2bb057d0 | 63 | head_size += 8; |
9c3444d3 | 64 | tail_size += 8; |
2bb057d0 | 65 | } |
239c249d GW |
66 | |
67 | /* | |
68 | * Allocate skbuffer. | |
69 | */ | |
88211021 | 70 | skb = __dev_alloc_skb(frame_size + head_size + tail_size, gfp); |
239c249d GW |
71 | if (!skb) |
72 | return NULL; | |
73 | ||
2bb057d0 ID |
74 | /* |
75 | * Make sure we not have a frame with the requested bytes | |
76 | * available in the head and tail. | |
77 | */ | |
78 | skb_reserve(skb, head_size); | |
239c249d GW |
79 | skb_put(skb, frame_size); |
80 | ||
c4da0048 GW |
81 | /* |
82 | * Populate skbdesc. | |
83 | */ | |
84 | skbdesc = get_skb_frame_desc(skb); | |
85 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
86 | skbdesc->entry = entry; | |
87 | ||
7dab73b3 | 88 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags)) { |
4ea545d4 SG |
89 | dma_addr_t skb_dma; |
90 | ||
91 | skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len, | |
92 | DMA_FROM_DEVICE); | |
93 | if (unlikely(dma_mapping_error(rt2x00dev->dev, skb_dma))) { | |
94 | dev_kfree_skb_any(skb); | |
95 | return NULL; | |
96 | } | |
97 | ||
98 | skbdesc->skb_dma = skb_dma; | |
c4da0048 GW |
99 | skbdesc->flags |= SKBDESC_DMA_MAPPED_RX; |
100 | } | |
101 | ||
239c249d GW |
102 | return skb; |
103 | } | |
30caa6e3 | 104 | |
4ea545d4 | 105 | int rt2x00queue_map_txskb(struct queue_entry *entry) |
30caa6e3 | 106 | { |
fa69560f ID |
107 | struct device *dev = entry->queue->rt2x00dev->dev; |
108 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 | 109 | |
3ee54a07 | 110 | skbdesc->skb_dma = |
fa69560f | 111 | dma_map_single(dev, entry->skb->data, entry->skb->len, DMA_TO_DEVICE); |
4ea545d4 SG |
112 | |
113 | if (unlikely(dma_mapping_error(dev, skbdesc->skb_dma))) | |
114 | return -ENOMEM; | |
115 | ||
c4da0048 | 116 | skbdesc->flags |= SKBDESC_DMA_MAPPED_TX; |
4ea545d4 | 117 | return 0; |
c4da0048 GW |
118 | } |
119 | EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb); | |
120 | ||
fa69560f | 121 | void rt2x00queue_unmap_skb(struct queue_entry *entry) |
c4da0048 | 122 | { |
fa69560f ID |
123 | struct device *dev = entry->queue->rt2x00dev->dev; |
124 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
c4da0048 GW |
125 | |
126 | if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) { | |
fa69560f | 127 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
128 | DMA_FROM_DEVICE); |
129 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX; | |
546adf29 | 130 | } else if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) { |
fa69560f | 131 | dma_unmap_single(dev, skbdesc->skb_dma, entry->skb->len, |
c4da0048 GW |
132 | DMA_TO_DEVICE); |
133 | skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX; | |
134 | } | |
135 | } | |
0b8004aa | 136 | EXPORT_SYMBOL_GPL(rt2x00queue_unmap_skb); |
c4da0048 | 137 | |
fa69560f | 138 | void rt2x00queue_free_skb(struct queue_entry *entry) |
c4da0048 | 139 | { |
fa69560f | 140 | if (!entry->skb) |
9a613195 ID |
141 | return; |
142 | ||
fa69560f ID |
143 | rt2x00queue_unmap_skb(entry); |
144 | dev_kfree_skb_any(entry->skb); | |
145 | entry->skb = NULL; | |
30caa6e3 | 146 | } |
239c249d | 147 | |
daee6c09 | 148 | void rt2x00queue_align_frame(struct sk_buff *skb) |
9f166171 | 149 | { |
9f166171 | 150 | unsigned int frame_length = skb->len; |
daee6c09 | 151 | unsigned int align = ALIGN_SIZE(skb, 0); |
9f166171 ID |
152 | |
153 | if (!align) | |
154 | return; | |
155 | ||
daee6c09 ID |
156 | skb_push(skb, align); |
157 | memmove(skb->data, skb->data + align, frame_length); | |
158 | skb_trim(skb, frame_length); | |
159 | } | |
160 | ||
daee6c09 ID |
161 | void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length) |
162 | { | |
2e331462 | 163 | unsigned int payload_length = skb->len - header_length; |
daee6c09 ID |
164 | unsigned int header_align = ALIGN_SIZE(skb, 0); |
165 | unsigned int payload_align = ALIGN_SIZE(skb, header_length); | |
e54be4e7 | 166 | unsigned int l2pad = payload_length ? L2PAD_SIZE(header_length) : 0; |
daee6c09 | 167 | |
2e331462 GW |
168 | /* |
169 | * Adjust the header alignment if the payload needs to be moved more | |
170 | * than the header. | |
171 | */ | |
172 | if (payload_align > header_align) | |
173 | header_align += 4; | |
174 | ||
175 | /* There is nothing to do if no alignment is needed */ | |
176 | if (!header_align) | |
177 | return; | |
daee6c09 | 178 | |
2e331462 GW |
179 | /* Reserve the amount of space needed in front of the frame */ |
180 | skb_push(skb, header_align); | |
181 | ||
182 | /* | |
183 | * Move the header. | |
184 | */ | |
185 | memmove(skb->data, skb->data + header_align, header_length); | |
186 | ||
187 | /* Move the payload, if present and if required */ | |
188 | if (payload_length && payload_align) | |
daee6c09 | 189 | memmove(skb->data + header_length + l2pad, |
a5186e99 | 190 | skb->data + header_length + l2pad + payload_align, |
2e331462 GW |
191 | payload_length); |
192 | ||
193 | /* Trim the skb to the correct size */ | |
194 | skb_trim(skb, header_length + l2pad + payload_length); | |
9f166171 ID |
195 | } |
196 | ||
daee6c09 ID |
197 | void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length) |
198 | { | |
a061a93b GW |
199 | /* |
200 | * L2 padding is only present if the skb contains more than just the | |
201 | * IEEE 802.11 header. | |
202 | */ | |
203 | unsigned int l2pad = (skb->len > header_length) ? | |
204 | L2PAD_SIZE(header_length) : 0; | |
daee6c09 | 205 | |
354e39db | 206 | if (!l2pad) |
daee6c09 ID |
207 | return; |
208 | ||
a061a93b GW |
209 | memmove(skb->data + l2pad, skb->data, header_length); |
210 | skb_pull(skb, l2pad); | |
daee6c09 ID |
211 | } |
212 | ||
77b5621b GW |
213 | static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev, |
214 | struct sk_buff *skb, | |
7b40982e ID |
215 | struct txentry_desc *txdesc) |
216 | { | |
77b5621b GW |
217 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
218 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
7b40982e | 219 | struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); |
e5851dac | 220 | u16 seqno; |
7b40982e | 221 | |
c262e08b | 222 | if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) |
7b40982e ID |
223 | return; |
224 | ||
7fe7ee77 HS |
225 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); |
226 | ||
e66a8ddf SG |
227 | if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags)) { |
228 | /* | |
229 | * rt2800 has a H/W (or F/W) bug, device incorrectly increase | |
230 | * seqno on retransmited data (non-QOS) frames. To workaround | |
231 | * the problem let's generate seqno in software if QOS is | |
232 | * disabled. | |
233 | */ | |
234 | if (test_bit(CONFIG_QOS_DISABLED, &rt2x00dev->flags)) | |
235 | __clear_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); | |
236 | else | |
237 | /* H/W will generate sequence number */ | |
238 | return; | |
239 | } | |
7fe7ee77 | 240 | |
7b40982e | 241 | /* |
7fe7ee77 HS |
242 | * The hardware is not able to insert a sequence number. Assign a |
243 | * software generated one here. | |
7b40982e ID |
244 | * |
245 | * This is wrong because beacons are not getting sequence | |
246 | * numbers assigned properly. | |
247 | * | |
248 | * A secondary problem exists for drivers that cannot toggle | |
249 | * sequence counting per-frame, since those will override the | |
250 | * sequence counter given by mac80211. | |
251 | */ | |
7b40982e | 252 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) |
e5851dac SG |
253 | seqno = atomic_add_return(0x10, &intf->seqno); |
254 | else | |
255 | seqno = atomic_read(&intf->seqno); | |
7b40982e | 256 | |
e5851dac SG |
257 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
258 | hdr->seq_ctrl |= cpu_to_le16(seqno); | |
7b40982e ID |
259 | } |
260 | ||
77b5621b GW |
261 | static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev, |
262 | struct sk_buff *skb, | |
7b40982e ID |
263 | struct txentry_desc *txdesc, |
264 | const struct rt2x00_rate *hwrate) | |
265 | { | |
77b5621b | 266 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
7b40982e ID |
267 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
268 | unsigned int data_length; | |
269 | unsigned int duration; | |
270 | unsigned int residual; | |
271 | ||
2517794b HS |
272 | /* |
273 | * Determine with what IFS priority this frame should be send. | |
274 | * Set ifs to IFS_SIFS when the this is not the first fragment, | |
275 | * or this fragment came after RTS/CTS. | |
276 | */ | |
277 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | |
278 | txdesc->u.plcp.ifs = IFS_BACKOFF; | |
279 | else | |
280 | txdesc->u.plcp.ifs = IFS_SIFS; | |
281 | ||
7b40982e | 282 | /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ |
77b5621b GW |
283 | data_length = skb->len + 4; |
284 | data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb); | |
7b40982e ID |
285 | |
286 | /* | |
287 | * PLCP setup | |
288 | * Length calculation depends on OFDM/CCK rate. | |
289 | */ | |
26a1d07f HS |
290 | txdesc->u.plcp.signal = hwrate->plcp; |
291 | txdesc->u.plcp.service = 0x04; | |
7b40982e ID |
292 | |
293 | if (hwrate->flags & DEV_RATE_OFDM) { | |
26a1d07f HS |
294 | txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f; |
295 | txdesc->u.plcp.length_low = data_length & 0x3f; | |
7b40982e ID |
296 | } else { |
297 | /* | |
298 | * Convert length to microseconds. | |
299 | */ | |
300 | residual = GET_DURATION_RES(data_length, hwrate->bitrate); | |
301 | duration = GET_DURATION(data_length, hwrate->bitrate); | |
302 | ||
303 | if (residual != 0) { | |
304 | duration++; | |
305 | ||
306 | /* | |
307 | * Check if we need to set the Length Extension | |
308 | */ | |
309 | if (hwrate->bitrate == 110 && residual <= 30) | |
26a1d07f | 310 | txdesc->u.plcp.service |= 0x80; |
7b40982e ID |
311 | } |
312 | ||
26a1d07f HS |
313 | txdesc->u.plcp.length_high = (duration >> 8) & 0xff; |
314 | txdesc->u.plcp.length_low = duration & 0xff; | |
7b40982e ID |
315 | |
316 | /* | |
317 | * When preamble is enabled we should set the | |
318 | * preamble bit for the signal. | |
319 | */ | |
320 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
26a1d07f | 321 | txdesc->u.plcp.signal |= 0x08; |
7b40982e ID |
322 | } |
323 | } | |
324 | ||
77b5621b GW |
325 | static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev, |
326 | struct sk_buff *skb, | |
46a01ec0 | 327 | struct txentry_desc *txdesc, |
36323f81 | 328 | struct ieee80211_sta *sta, |
46a01ec0 GW |
329 | const struct rt2x00_rate *hwrate) |
330 | { | |
77b5621b | 331 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
46a01ec0 | 332 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
77b5621b | 333 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
ead2bb64 | 334 | struct rt2x00_sta *sta_priv = NULL; |
46a01ec0 | 335 | |
36323f81 | 336 | if (sta) { |
46a01ec0 | 337 | txdesc->u.ht.mpdu_density = |
36323f81 | 338 | sta->ht_cap.ampdu_density; |
46a01ec0 | 339 | |
36323f81 | 340 | sta_priv = sta_to_rt2x00_sta(sta); |
ead2bb64 HS |
341 | txdesc->u.ht.wcid = sta_priv->wcid; |
342 | } | |
343 | ||
46a01ec0 GW |
344 | /* |
345 | * If IEEE80211_TX_RC_MCS is set txrate->idx just contains the | |
346 | * mcs rate to be used | |
347 | */ | |
348 | if (txrate->flags & IEEE80211_TX_RC_MCS) { | |
349 | txdesc->u.ht.mcs = txrate->idx; | |
350 | ||
351 | /* | |
352 | * MIMO PS should be set to 1 for STA's using dynamic SM PS | |
353 | * when using more then one tx stream (>MCS7). | |
354 | */ | |
36323f81 | 355 | if (sta && txdesc->u.ht.mcs > 7 && |
af0ed69b | 356 | sta->smps_mode == IEEE80211_SMPS_DYNAMIC) |
46a01ec0 GW |
357 | __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags); |
358 | } else { | |
359 | txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs); | |
360 | if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
361 | txdesc->u.ht.mcs |= 0x08; | |
362 | } | |
363 | ||
da40f407 SG |
364 | if (test_bit(CONFIG_HT_DISABLED, &rt2x00dev->flags)) { |
365 | if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
366 | txdesc->u.ht.txop = TXOP_SIFS; | |
367 | else | |
368 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
369 | ||
370 | /* Left zero on all other settings. */ | |
371 | return; | |
372 | } | |
373 | ||
374 | txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */ | |
375 | ||
376 | /* | |
377 | * Only one STBC stream is supported for now. | |
378 | */ | |
379 | if (tx_info->flags & IEEE80211_TX_CTL_STBC) | |
380 | txdesc->u.ht.stbc = 1; | |
381 | ||
46a01ec0 GW |
382 | /* |
383 | * This frame is eligible for an AMPDU, however, don't aggregate | |
384 | * frames that are intended to probe a specific tx rate. | |
385 | */ | |
386 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU && | |
387 | !(tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) | |
388 | __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags); | |
389 | ||
390 | /* | |
391 | * Set 40Mhz mode if necessary (for legacy rates this will | |
392 | * duplicate the frame to both channels). | |
393 | */ | |
394 | if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH || | |
395 | txrate->flags & IEEE80211_TX_RC_DUP_DATA) | |
396 | __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags); | |
397 | if (txrate->flags & IEEE80211_TX_RC_SHORT_GI) | |
398 | __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags); | |
399 | ||
400 | /* | |
401 | * Determine IFS values | |
402 | * - Use TXOP_BACKOFF for management frames except beacons | |
403 | * - Use TXOP_SIFS for fragment bursts | |
404 | * - Use TXOP_HTTXOP for everything else | |
405 | * | |
406 | * Note: rt2800 devices won't use CTS protection (if used) | |
407 | * for frames not transmitted with TXOP_HTTXOP | |
408 | */ | |
409 | if (ieee80211_is_mgmt(hdr->frame_control) && | |
410 | !ieee80211_is_beacon(hdr->frame_control)) | |
411 | txdesc->u.ht.txop = TXOP_BACKOFF; | |
412 | else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) | |
413 | txdesc->u.ht.txop = TXOP_SIFS; | |
414 | else | |
415 | txdesc->u.ht.txop = TXOP_HTTXOP; | |
416 | } | |
417 | ||
77b5621b GW |
418 | static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev, |
419 | struct sk_buff *skb, | |
36323f81 TH |
420 | struct txentry_desc *txdesc, |
421 | struct ieee80211_sta *sta) | |
7050ec82 | 422 | { |
77b5621b GW |
423 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
424 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
55b585e2 HS |
425 | struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; |
426 | struct ieee80211_rate *rate; | |
427 | const struct rt2x00_rate *hwrate = NULL; | |
7050ec82 ID |
428 | |
429 | memset(txdesc, 0, sizeof(*txdesc)); | |
430 | ||
9f166171 | 431 | /* |
df624ca5 | 432 | * Header and frame information. |
9f166171 | 433 | */ |
77b5621b GW |
434 | txdesc->length = skb->len; |
435 | txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb); | |
9f166171 | 436 | |
7050ec82 ID |
437 | /* |
438 | * Check whether this frame is to be acked. | |
439 | */ | |
e039fa4a | 440 | if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) |
7050ec82 ID |
441 | __set_bit(ENTRY_TXD_ACK, &txdesc->flags); |
442 | ||
443 | /* | |
444 | * Check if this is a RTS/CTS frame | |
445 | */ | |
ac104462 ID |
446 | if (ieee80211_is_rts(hdr->frame_control) || |
447 | ieee80211_is_cts(hdr->frame_control)) { | |
7050ec82 | 448 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
ac104462 | 449 | if (ieee80211_is_rts(hdr->frame_control)) |
7050ec82 | 450 | __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags); |
e039fa4a | 451 | else |
7050ec82 | 452 | __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags); |
e039fa4a | 453 | if (tx_info->control.rts_cts_rate_idx >= 0) |
2e92e6f2 | 454 | rate = |
e039fa4a | 455 | ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info); |
7050ec82 ID |
456 | } |
457 | ||
458 | /* | |
459 | * Determine retry information. | |
460 | */ | |
e6a9854b | 461 | txdesc->retry_limit = tx_info->control.rates[0].count - 1; |
42c82857 | 462 | if (txdesc->retry_limit >= rt2x00dev->long_retry) |
7050ec82 ID |
463 | __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags); |
464 | ||
465 | /* | |
466 | * Check if more fragments are pending | |
467 | */ | |
2606e422 | 468 | if (ieee80211_has_morefrags(hdr->frame_control)) { |
7050ec82 ID |
469 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); |
470 | __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags); | |
471 | } | |
472 | ||
2606e422 HS |
473 | /* |
474 | * Check if more frames (!= fragments) are pending | |
475 | */ | |
476 | if (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES) | |
477 | __set_bit(ENTRY_TXD_BURST, &txdesc->flags); | |
478 | ||
7050ec82 ID |
479 | /* |
480 | * Beacons and probe responses require the tsf timestamp | |
1bce85cf | 481 | * to be inserted into the frame. |
7050ec82 | 482 | */ |
1bce85cf HS |
483 | if (ieee80211_is_beacon(hdr->frame_control) || |
484 | ieee80211_is_probe_resp(hdr->frame_control)) | |
7050ec82 ID |
485 | __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); |
486 | ||
7b40982e | 487 | if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && |
2517794b | 488 | !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) |
7050ec82 | 489 | __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); |
7050ec82 | 490 | |
076f9582 ID |
491 | /* |
492 | * Determine rate modulation. | |
493 | */ | |
55b585e2 HS |
494 | if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD) |
495 | txdesc->rate_mode = RATE_MODE_HT_GREENFIELD; | |
496 | else if (txrate->flags & IEEE80211_TX_RC_MCS) | |
497 | txdesc->rate_mode = RATE_MODE_HT_MIX; | |
498 | else { | |
499 | rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); | |
500 | hwrate = rt2x00_get_rate(rate->hw_value); | |
501 | if (hwrate->flags & DEV_RATE_OFDM) | |
502 | txdesc->rate_mode = RATE_MODE_OFDM; | |
503 | else | |
504 | txdesc->rate_mode = RATE_MODE_CCK; | |
505 | } | |
7050ec82 | 506 | |
7b40982e ID |
507 | /* |
508 | * Apply TX descriptor handling by components | |
509 | */ | |
77b5621b GW |
510 | rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc); |
511 | rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc); | |
26a1d07f | 512 | |
7dab73b3 | 513 | if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags)) |
77b5621b | 514 | rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc, |
36323f81 | 515 | sta, hwrate); |
26a1d07f | 516 | else |
77b5621b GW |
517 | rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc, |
518 | hwrate); | |
7050ec82 | 519 | } |
7050ec82 | 520 | |
78eea11b GW |
521 | static int rt2x00queue_write_tx_data(struct queue_entry *entry, |
522 | struct txentry_desc *txdesc) | |
523 | { | |
524 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
525 | ||
526 | /* | |
527 | * This should not happen, we already checked the entry | |
528 | * was ours. When the hardware disagrees there has been | |
529 | * a queue corruption! | |
530 | */ | |
531 | if (unlikely(rt2x00dev->ops->lib->get_entry_state && | |
532 | rt2x00dev->ops->lib->get_entry_state(entry))) { | |
ec9c4989 JP |
533 | rt2x00_err(rt2x00dev, |
534 | "Corrupt queue %d, accessing entry which is not ours\n" | |
535 | "Please file bug report to %s\n", | |
536 | entry->queue->qid, DRV_PROJECT); | |
78eea11b GW |
537 | return -EINVAL; |
538 | } | |
539 | ||
540 | /* | |
541 | * Add the requested extra tx headroom in front of the skb. | |
542 | */ | |
5616a6ef GJ |
543 | skb_push(entry->skb, rt2x00dev->extra_tx_headroom); |
544 | memset(entry->skb->data, 0, rt2x00dev->extra_tx_headroom); | |
78eea11b GW |
545 | |
546 | /* | |
76dd5ddf | 547 | * Call the driver's write_tx_data function, if it exists. |
78eea11b | 548 | */ |
76dd5ddf GW |
549 | if (rt2x00dev->ops->lib->write_tx_data) |
550 | rt2x00dev->ops->lib->write_tx_data(entry, txdesc); | |
78eea11b GW |
551 | |
552 | /* | |
553 | * Map the skb to DMA. | |
554 | */ | |
4ea545d4 SG |
555 | if (test_bit(REQUIRE_DMA, &rt2x00dev->cap_flags) && |
556 | rt2x00queue_map_txskb(entry)) | |
557 | return -ENOMEM; | |
78eea11b GW |
558 | |
559 | return 0; | |
560 | } | |
561 | ||
bd88a781 ID |
562 | static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry, |
563 | struct txentry_desc *txdesc) | |
7050ec82 | 564 | { |
b869767b | 565 | struct data_queue *queue = entry->queue; |
7050ec82 | 566 | |
93331458 | 567 | queue->rt2x00dev->ops->lib->write_tx_desc(entry, txdesc); |
7050ec82 ID |
568 | |
569 | /* | |
570 | * All processing on the frame has been completed, this means | |
571 | * it is now ready to be dumped to userspace through debugfs. | |
572 | */ | |
93331458 | 573 | rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb); |
6295d815 GW |
574 | } |
575 | ||
8be4eed0 | 576 | static void rt2x00queue_kick_tx_queue(struct data_queue *queue, |
6295d815 GW |
577 | struct txentry_desc *txdesc) |
578 | { | |
7050ec82 | 579 | /* |
b869767b | 580 | * Check if we need to kick the queue, there are however a few rules |
6295d815 | 581 | * 1) Don't kick unless this is the last in frame in a burst. |
b869767b ID |
582 | * When the burst flag is set, this frame is always followed |
583 | * by another frame which in some way are related to eachother. | |
584 | * This is true for fragments, RTS or CTS-to-self frames. | |
6295d815 | 585 | * 2) Rule 1 can be broken when the available entries |
b869767b | 586 | * in the queue are less then a certain threshold. |
7050ec82 | 587 | */ |
b869767b ID |
588 | if (rt2x00queue_threshold(queue) || |
589 | !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) | |
dbba306f | 590 | queue->rt2x00dev->ops->lib->kick_queue(queue); |
7050ec82 | 591 | } |
7050ec82 | 592 | |
84e9e8eb HS |
593 | static void rt2x00queue_bar_check(struct queue_entry *entry) |
594 | { | |
595 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
596 | struct ieee80211_bar *bar = (void *) (entry->skb->data + | |
5616a6ef | 597 | rt2x00dev->extra_tx_headroom); |
84e9e8eb HS |
598 | struct rt2x00_bar_list_entry *bar_entry; |
599 | ||
600 | if (likely(!ieee80211_is_back_req(bar->frame_control))) | |
601 | return; | |
602 | ||
603 | bar_entry = kmalloc(sizeof(*bar_entry), GFP_ATOMIC); | |
604 | ||
605 | /* | |
606 | * If the alloc fails we still send the BAR out but just don't track | |
607 | * it in our bar list. And as a result we will report it to mac80211 | |
608 | * back as failed. | |
609 | */ | |
610 | if (!bar_entry) | |
611 | return; | |
612 | ||
613 | bar_entry->entry = entry; | |
614 | bar_entry->block_acked = 0; | |
615 | ||
616 | /* | |
617 | * Copy the relevant parts of the 802.11 BAR into out check list | |
618 | * such that we can use RCU for less-overhead in the RX path since | |
619 | * sending BARs and processing the according BlockAck should be | |
620 | * the exception. | |
621 | */ | |
622 | memcpy(bar_entry->ra, bar->ra, sizeof(bar->ra)); | |
623 | memcpy(bar_entry->ta, bar->ta, sizeof(bar->ta)); | |
624 | bar_entry->control = bar->control; | |
625 | bar_entry->start_seq_num = bar->start_seq_num; | |
626 | ||
627 | /* | |
628 | * Insert BAR into our BAR check list. | |
629 | */ | |
630 | spin_lock_bh(&rt2x00dev->bar_list_lock); | |
631 | list_add_tail_rcu(&bar_entry->list, &rt2x00dev->bar_list); | |
632 | spin_unlock_bh(&rt2x00dev->bar_list_lock); | |
633 | } | |
634 | ||
7351c6bd | 635 | int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb, |
3d8bfe14 | 636 | struct ieee80211_sta *sta, bool local) |
6db3786a | 637 | { |
e6a9854b | 638 | struct ieee80211_tx_info *tx_info; |
77a861c4 | 639 | struct queue_entry *entry; |
6db3786a | 640 | struct txentry_desc txdesc; |
d74f5ba4 | 641 | struct skb_frame_desc *skbdesc; |
e6a9854b | 642 | u8 rate_idx, rate_flags; |
77a861c4 GW |
643 | int ret = 0; |
644 | ||
6db3786a ID |
645 | /* |
646 | * Copy all TX descriptor information into txdesc, | |
647 | * after that we are free to use the skb->cb array | |
648 | * for our information. | |
649 | */ | |
3d8bfe14 | 650 | rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta); |
6db3786a | 651 | |
d74f5ba4 | 652 | /* |
e6a9854b | 653 | * All information is retrieved from the skb->cb array, |
2bb057d0 | 654 | * now we should claim ownership of the driver part of that |
e6a9854b | 655 | * array, preserving the bitrate index and flags. |
d74f5ba4 | 656 | */ |
e6a9854b JB |
657 | tx_info = IEEE80211_SKB_CB(skb); |
658 | rate_idx = tx_info->control.rates[0].idx; | |
659 | rate_flags = tx_info->control.rates[0].flags; | |
0e3de998 | 660 | skbdesc = get_skb_frame_desc(skb); |
d74f5ba4 | 661 | memset(skbdesc, 0, sizeof(*skbdesc)); |
e6a9854b JB |
662 | skbdesc->tx_rate_idx = rate_idx; |
663 | skbdesc->tx_rate_flags = rate_flags; | |
d74f5ba4 | 664 | |
7351c6bd JB |
665 | if (local) |
666 | skbdesc->flags |= SKBDESC_NOT_MAC80211; | |
667 | ||
2bb057d0 ID |
668 | /* |
669 | * When hardware encryption is supported, and this frame | |
670 | * is to be encrypted, we should strip the IV/EIV data from | |
3ad2f3fb | 671 | * the frame so we can provide it to the driver separately. |
2bb057d0 ID |
672 | */ |
673 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && | |
dddfb478 | 674 | !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { |
7dab73b3 | 675 | if (test_bit(REQUIRE_COPY_IV, &queue->rt2x00dev->cap_flags)) |
9eb4e21e | 676 | rt2x00crypto_tx_copy_iv(skb, &txdesc); |
dddfb478 | 677 | else |
9eb4e21e | 678 | rt2x00crypto_tx_remove_iv(skb, &txdesc); |
dddfb478 | 679 | } |
2bb057d0 | 680 | |
93354cbb | 681 | /* |
25985edc | 682 | * When DMA allocation is required we should guarantee to the |
93354cbb | 683 | * driver that the DMA is aligned to a 4-byte boundary. |
93354cbb ID |
684 | * However some drivers require L2 padding to pad the payload |
685 | * rather then the header. This could be a requirement for | |
686 | * PCI and USB devices, while header alignment only is valid | |
687 | * for PCI devices. | |
688 | */ | |
7dab73b3 | 689 | if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags)) |
128f8f77 | 690 | rt2x00queue_insert_l2pad(skb, txdesc.header_length); |
7dab73b3 | 691 | else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags)) |
128f8f77 GW |
692 | rt2x00queue_align_frame(skb); |
693 | ||
3780d038 SG |
694 | /* |
695 | * That function must be called with bh disabled. | |
696 | */ | |
128f8f77 GW |
697 | spin_lock(&queue->tx_lock); |
698 | ||
699 | if (unlikely(rt2x00queue_full(queue))) { | |
ec9c4989 JP |
700 | rt2x00_err(queue->rt2x00dev, "Dropping frame due to full tx queue %d\n", |
701 | queue->qid); | |
128f8f77 GW |
702 | ret = -ENOBUFS; |
703 | goto out; | |
704 | } | |
705 | ||
706 | entry = rt2x00queue_get_entry(queue, Q_INDEX); | |
707 | ||
708 | if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, | |
709 | &entry->flags))) { | |
ec9c4989 JP |
710 | rt2x00_err(queue->rt2x00dev, |
711 | "Arrived at non-free entry in the non-full queue %d\n" | |
712 | "Please file bug report to %s\n", | |
713 | queue->qid, DRV_PROJECT); | |
128f8f77 GW |
714 | ret = -EINVAL; |
715 | goto out; | |
716 | } | |
717 | ||
718 | skbdesc->entry = entry; | |
719 | entry->skb = skb; | |
9f166171 | 720 | |
2bb057d0 ID |
721 | /* |
722 | * It could be possible that the queue was corrupted and this | |
0e3de998 ID |
723 | * call failed. Since we always return NETDEV_TX_OK to mac80211, |
724 | * this frame will simply be dropped. | |
2bb057d0 | 725 | */ |
78eea11b | 726 | if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) { |
0262ab0d | 727 | clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); |
2bb057d0 | 728 | entry->skb = NULL; |
77a861c4 GW |
729 | ret = -EIO; |
730 | goto out; | |
6db3786a ID |
731 | } |
732 | ||
84e9e8eb HS |
733 | /* |
734 | * Put BlockAckReqs into our check list for driver BA processing. | |
735 | */ | |
736 | rt2x00queue_bar_check(entry); | |
737 | ||
0262ab0d | 738 | set_bit(ENTRY_DATA_PENDING, &entry->flags); |
6db3786a | 739 | |
75256f03 | 740 | rt2x00queue_index_inc(entry, Q_INDEX); |
6db3786a | 741 | rt2x00queue_write_tx_descriptor(entry, &txdesc); |
8be4eed0 | 742 | rt2x00queue_kick_tx_queue(queue, &txdesc); |
6db3786a | 743 | |
77a861c4 GW |
744 | out: |
745 | spin_unlock(&queue->tx_lock); | |
746 | return ret; | |
6db3786a ID |
747 | } |
748 | ||
69cf36a4 HS |
749 | int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev, |
750 | struct ieee80211_vif *vif) | |
751 | { | |
752 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
753 | ||
754 | if (unlikely(!intf->beacon)) | |
755 | return -ENOBUFS; | |
756 | ||
69cf36a4 HS |
757 | /* |
758 | * Clean up the beacon skb. | |
759 | */ | |
760 | rt2x00queue_free_skb(intf->beacon); | |
761 | ||
762 | /* | |
763 | * Clear beacon (single bssid devices don't need to clear the beacon | |
764 | * since the beacon queue will get stopped anyway). | |
765 | */ | |
766 | if (rt2x00dev->ops->lib->clear_beacon) | |
767 | rt2x00dev->ops->lib->clear_beacon(intf->beacon); | |
768 | ||
69cf36a4 HS |
769 | return 0; |
770 | } | |
771 | ||
283dafa1 SG |
772 | int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, |
773 | struct ieee80211_vif *vif) | |
bd88a781 ID |
774 | { |
775 | struct rt2x00_intf *intf = vif_to_intf(vif); | |
776 | struct skb_frame_desc *skbdesc; | |
777 | struct txentry_desc txdesc; | |
bd88a781 ID |
778 | |
779 | if (unlikely(!intf->beacon)) | |
780 | return -ENOBUFS; | |
781 | ||
17512dc3 IP |
782 | /* |
783 | * Clean up the beacon skb. | |
784 | */ | |
fa69560f | 785 | rt2x00queue_free_skb(intf->beacon); |
17512dc3 | 786 | |
bd88a781 | 787 | intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); |
8414ff07 | 788 | if (!intf->beacon->skb) |
bd88a781 ID |
789 | return -ENOMEM; |
790 | ||
791 | /* | |
792 | * Copy all TX descriptor information into txdesc, | |
793 | * after that we are free to use the skb->cb array | |
794 | * for our information. | |
795 | */ | |
36323f81 | 796 | rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc, NULL); |
bd88a781 | 797 | |
bd88a781 ID |
798 | /* |
799 | * Fill in skb descriptor | |
800 | */ | |
801 | skbdesc = get_skb_frame_desc(intf->beacon->skb); | |
802 | memset(skbdesc, 0, sizeof(*skbdesc)); | |
bd88a781 ID |
803 | skbdesc->entry = intf->beacon; |
804 | ||
bd88a781 | 805 | /* |
69cf36a4 | 806 | * Send beacon to hardware. |
bd88a781 | 807 | */ |
f224f4ef | 808 | rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); |
bd88a781 | 809 | |
8414ff07 HS |
810 | return 0; |
811 | ||
812 | } | |
813 | ||
10e11568 | 814 | bool rt2x00queue_for_each_entry(struct data_queue *queue, |
5eb7efe8 ID |
815 | enum queue_index start, |
816 | enum queue_index end, | |
1dd0dbb3 HS |
817 | void *data, |
818 | bool (*fn)(struct queue_entry *entry, | |
819 | void *data)) | |
5eb7efe8 ID |
820 | { |
821 | unsigned long irqflags; | |
822 | unsigned int index_start; | |
823 | unsigned int index_end; | |
824 | unsigned int i; | |
825 | ||
826 | if (unlikely(start >= Q_INDEX_MAX || end >= Q_INDEX_MAX)) { | |
ec9c4989 JP |
827 | rt2x00_err(queue->rt2x00dev, |
828 | "Entry requested from invalid index range (%d - %d)\n", | |
829 | start, end); | |
10e11568 | 830 | return true; |
5eb7efe8 ID |
831 | } |
832 | ||
833 | /* | |
834 | * Only protect the range we are going to loop over, | |
835 | * if during our loop a extra entry is set to pending | |
836 | * it should not be kicked during this run, since it | |
837 | * is part of another TX operation. | |
838 | */ | |
813f0339 | 839 | spin_lock_irqsave(&queue->index_lock, irqflags); |
5eb7efe8 ID |
840 | index_start = queue->index[start]; |
841 | index_end = queue->index[end]; | |
813f0339 | 842 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
5eb7efe8 ID |
843 | |
844 | /* | |
25985edc | 845 | * Start from the TX done pointer, this guarantees that we will |
5eb7efe8 ID |
846 | * send out all frames in the correct order. |
847 | */ | |
848 | if (index_start < index_end) { | |
10e11568 | 849 | for (i = index_start; i < index_end; i++) { |
1dd0dbb3 | 850 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
851 | return true; |
852 | } | |
5eb7efe8 | 853 | } else { |
10e11568 | 854 | for (i = index_start; i < queue->limit; i++) { |
1dd0dbb3 | 855 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
856 | return true; |
857 | } | |
5eb7efe8 | 858 | |
10e11568 | 859 | for (i = 0; i < index_end; i++) { |
1dd0dbb3 | 860 | if (fn(&queue->entries[i], data)) |
10e11568 HS |
861 | return true; |
862 | } | |
5eb7efe8 | 863 | } |
10e11568 HS |
864 | |
865 | return false; | |
5eb7efe8 ID |
866 | } |
867 | EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry); | |
868 | ||
181d6902 ID |
869 | struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, |
870 | enum queue_index index) | |
871 | { | |
872 | struct queue_entry *entry; | |
5f46c4d0 | 873 | unsigned long irqflags; |
181d6902 ID |
874 | |
875 | if (unlikely(index >= Q_INDEX_MAX)) { | |
ec9c4989 JP |
876 | rt2x00_err(queue->rt2x00dev, "Entry requested from invalid index type (%d)\n", |
877 | index); | |
181d6902 ID |
878 | return NULL; |
879 | } | |
880 | ||
813f0339 | 881 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
882 | |
883 | entry = &queue->entries[queue->index[index]]; | |
884 | ||
813f0339 | 885 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
886 | |
887 | return entry; | |
888 | } | |
889 | EXPORT_SYMBOL_GPL(rt2x00queue_get_entry); | |
890 | ||
75256f03 | 891 | void rt2x00queue_index_inc(struct queue_entry *entry, enum queue_index index) |
181d6902 | 892 | { |
75256f03 | 893 | struct data_queue *queue = entry->queue; |
5f46c4d0 ID |
894 | unsigned long irqflags; |
895 | ||
181d6902 | 896 | if (unlikely(index >= Q_INDEX_MAX)) { |
ec9c4989 JP |
897 | rt2x00_err(queue->rt2x00dev, |
898 | "Index change on invalid index type (%d)\n", index); | |
181d6902 ID |
899 | return; |
900 | } | |
901 | ||
813f0339 | 902 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
903 | |
904 | queue->index[index]++; | |
905 | if (queue->index[index] >= queue->limit) | |
906 | queue->index[index] = 0; | |
907 | ||
75256f03 | 908 | entry->last_action = jiffies; |
652a9dd2 | 909 | |
10b6b801 ID |
910 | if (index == Q_INDEX) { |
911 | queue->length++; | |
912 | } else if (index == Q_INDEX_DONE) { | |
913 | queue->length--; | |
55887511 | 914 | queue->count++; |
10b6b801 | 915 | } |
181d6902 | 916 | |
813f0339 | 917 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 | 918 | } |
181d6902 | 919 | |
6cdfc1de | 920 | static void rt2x00queue_pause_queue_nocheck(struct data_queue *queue) |
0b7fde54 | 921 | { |
0b7fde54 | 922 | switch (queue->qid) { |
f615e9a3 ID |
923 | case QID_AC_VO: |
924 | case QID_AC_VI: | |
0b7fde54 ID |
925 | case QID_AC_BE: |
926 | case QID_AC_BK: | |
0b7fde54 ID |
927 | /* |
928 | * For TX queues, we have to disable the queue | |
929 | * inside mac80211. | |
930 | */ | |
931 | ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid); | |
932 | break; | |
933 | default: | |
934 | break; | |
935 | } | |
936 | } | |
e2288b66 SG |
937 | void rt2x00queue_pause_queue(struct data_queue *queue) |
938 | { | |
939 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
940 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
941 | test_and_set_bit(QUEUE_PAUSED, &queue->flags)) | |
942 | return; | |
943 | ||
944 | rt2x00queue_pause_queue_nocheck(queue); | |
945 | } | |
0b7fde54 ID |
946 | EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue); |
947 | ||
948 | void rt2x00queue_unpause_queue(struct data_queue *queue) | |
949 | { | |
950 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
951 | !test_bit(QUEUE_STARTED, &queue->flags) || | |
952 | !test_and_clear_bit(QUEUE_PAUSED, &queue->flags)) | |
953 | return; | |
954 | ||
955 | switch (queue->qid) { | |
f615e9a3 ID |
956 | case QID_AC_VO: |
957 | case QID_AC_VI: | |
0b7fde54 ID |
958 | case QID_AC_BE: |
959 | case QID_AC_BK: | |
0b7fde54 ID |
960 | /* |
961 | * For TX queues, we have to enable the queue | |
962 | * inside mac80211. | |
963 | */ | |
964 | ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid); | |
965 | break; | |
5be65609 ID |
966 | case QID_RX: |
967 | /* | |
968 | * For RX we need to kick the queue now in order to | |
969 | * receive frames. | |
970 | */ | |
971 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
0b7fde54 ID |
972 | default: |
973 | break; | |
974 | } | |
975 | } | |
976 | EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue); | |
977 | ||
978 | void rt2x00queue_start_queue(struct data_queue *queue) | |
979 | { | |
980 | mutex_lock(&queue->status_lock); | |
981 | ||
982 | if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) || | |
983 | test_and_set_bit(QUEUE_STARTED, &queue->flags)) { | |
984 | mutex_unlock(&queue->status_lock); | |
985 | return; | |
986 | } | |
987 | ||
988 | set_bit(QUEUE_PAUSED, &queue->flags); | |
989 | ||
990 | queue->rt2x00dev->ops->lib->start_queue(queue); | |
991 | ||
992 | rt2x00queue_unpause_queue(queue); | |
993 | ||
994 | mutex_unlock(&queue->status_lock); | |
995 | } | |
996 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queue); | |
997 | ||
998 | void rt2x00queue_stop_queue(struct data_queue *queue) | |
999 | { | |
1000 | mutex_lock(&queue->status_lock); | |
1001 | ||
1002 | if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) { | |
1003 | mutex_unlock(&queue->status_lock); | |
1004 | return; | |
1005 | } | |
1006 | ||
e2288b66 | 1007 | rt2x00queue_pause_queue_nocheck(queue); |
0b7fde54 ID |
1008 | |
1009 | queue->rt2x00dev->ops->lib->stop_queue(queue); | |
1010 | ||
1011 | mutex_unlock(&queue->status_lock); | |
1012 | } | |
1013 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue); | |
1014 | ||
5be65609 ID |
1015 | void rt2x00queue_flush_queue(struct data_queue *queue, bool drop) |
1016 | { | |
5be65609 | 1017 | bool tx_queue = |
f615e9a3 | 1018 | (queue->qid == QID_AC_VO) || |
5be65609 | 1019 | (queue->qid == QID_AC_VI) || |
f615e9a3 ID |
1020 | (queue->qid == QID_AC_BE) || |
1021 | (queue->qid == QID_AC_BK); | |
5be65609 | 1022 | |
5be65609 ID |
1023 | |
1024 | /* | |
fdbdd25c SG |
1025 | * If we are not supposed to drop any pending |
1026 | * frames, this means we must force a start (=kick) | |
1027 | * to the queue to make sure the hardware will | |
1028 | * start transmitting. | |
5be65609 | 1029 | */ |
fdbdd25c SG |
1030 | if (!drop && tx_queue) |
1031 | queue->rt2x00dev->ops->lib->kick_queue(queue); | |
5be65609 ID |
1032 | |
1033 | /* | |
152a5992 ID |
1034 | * Check if driver supports flushing, if that is the case we can |
1035 | * defer the flushing to the driver. Otherwise we must use the | |
1036 | * alternative which just waits for the queue to become empty. | |
5be65609 | 1037 | */ |
152a5992 ID |
1038 | if (likely(queue->rt2x00dev->ops->lib->flush_queue)) |
1039 | queue->rt2x00dev->ops->lib->flush_queue(queue, drop); | |
5be65609 ID |
1040 | |
1041 | /* | |
1042 | * The queue flush has failed... | |
1043 | */ | |
1044 | if (unlikely(!rt2x00queue_empty(queue))) | |
ec9c4989 JP |
1045 | rt2x00_warn(queue->rt2x00dev, "Queue %d failed to flush\n", |
1046 | queue->qid); | |
5be65609 ID |
1047 | } |
1048 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue); | |
1049 | ||
0b7fde54 ID |
1050 | void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev) |
1051 | { | |
1052 | struct data_queue *queue; | |
1053 | ||
1054 | /* | |
1055 | * rt2x00queue_start_queue will call ieee80211_wake_queue | |
1056 | * for each queue after is has been properly initialized. | |
1057 | */ | |
1058 | tx_queue_for_each(rt2x00dev, queue) | |
1059 | rt2x00queue_start_queue(queue); | |
1060 | ||
1061 | rt2x00queue_start_queue(rt2x00dev->rx); | |
1062 | } | |
1063 | EXPORT_SYMBOL_GPL(rt2x00queue_start_queues); | |
1064 | ||
1065 | void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev) | |
1066 | { | |
1067 | struct data_queue *queue; | |
1068 | ||
1069 | /* | |
1070 | * rt2x00queue_stop_queue will call ieee80211_stop_queue | |
1071 | * as well, but we are completely shutting doing everything | |
1072 | * now, so it is much safer to stop all TX queues at once, | |
1073 | * and use rt2x00queue_stop_queue for cleaning up. | |
1074 | */ | |
1075 | ieee80211_stop_queues(rt2x00dev->hw); | |
1076 | ||
1077 | tx_queue_for_each(rt2x00dev, queue) | |
1078 | rt2x00queue_stop_queue(queue); | |
1079 | ||
1080 | rt2x00queue_stop_queue(rt2x00dev->rx); | |
1081 | } | |
1082 | EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues); | |
1083 | ||
5be65609 ID |
1084 | void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop) |
1085 | { | |
1086 | struct data_queue *queue; | |
1087 | ||
1088 | tx_queue_for_each(rt2x00dev, queue) | |
1089 | rt2x00queue_flush_queue(queue, drop); | |
1090 | ||
1091 | rt2x00queue_flush_queue(rt2x00dev->rx, drop); | |
1092 | } | |
1093 | EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues); | |
1094 | ||
181d6902 ID |
1095 | static void rt2x00queue_reset(struct data_queue *queue) |
1096 | { | |
5f46c4d0 | 1097 | unsigned long irqflags; |
652a9dd2 | 1098 | unsigned int i; |
5f46c4d0 | 1099 | |
813f0339 | 1100 | spin_lock_irqsave(&queue->index_lock, irqflags); |
181d6902 ID |
1101 | |
1102 | queue->count = 0; | |
1103 | queue->length = 0; | |
652a9dd2 | 1104 | |
75256f03 | 1105 | for (i = 0; i < Q_INDEX_MAX; i++) |
652a9dd2 | 1106 | queue->index[i] = 0; |
181d6902 | 1107 | |
813f0339 | 1108 | spin_unlock_irqrestore(&queue->index_lock, irqflags); |
181d6902 ID |
1109 | } |
1110 | ||
798b7adb | 1111 | void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev) |
181d6902 ID |
1112 | { |
1113 | struct data_queue *queue; | |
1114 | unsigned int i; | |
1115 | ||
798b7adb | 1116 | queue_for_each(rt2x00dev, queue) { |
181d6902 ID |
1117 | rt2x00queue_reset(queue); |
1118 | ||
64e7d723 | 1119 | for (i = 0; i < queue->limit; i++) |
798b7adb | 1120 | rt2x00dev->ops->lib->clear_entry(&queue->entries[i]); |
181d6902 ID |
1121 | } |
1122 | } | |
1123 | ||
15d6c079 | 1124 | static int rt2x00queue_alloc_entries(struct data_queue *queue) |
181d6902 ID |
1125 | { |
1126 | struct queue_entry *entries; | |
1127 | unsigned int entry_size; | |
1128 | unsigned int i; | |
1129 | ||
1130 | rt2x00queue_reset(queue); | |
1131 | ||
181d6902 ID |
1132 | /* |
1133 | * Allocate all queue entries. | |
1134 | */ | |
568f7a43 | 1135 | entry_size = sizeof(*entries) + queue->priv_size; |
baeb2ffa | 1136 | entries = kcalloc(queue->limit, entry_size, GFP_KERNEL); |
181d6902 ID |
1137 | if (!entries) |
1138 | return -ENOMEM; | |
1139 | ||
1140 | #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \ | |
f8bfbc31 ME |
1141 | (((char *)(__base)) + ((__limit) * (__esize)) + \ |
1142 | ((__index) * (__psize))) | |
181d6902 ID |
1143 | |
1144 | for (i = 0; i < queue->limit; i++) { | |
1145 | entries[i].flags = 0; | |
1146 | entries[i].queue = queue; | |
1147 | entries[i].skb = NULL; | |
1148 | entries[i].entry_idx = i; | |
1149 | entries[i].priv_data = | |
1150 | QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit, | |
568f7a43 | 1151 | sizeof(*entries), queue->priv_size); |
181d6902 ID |
1152 | } |
1153 | ||
1154 | #undef QUEUE_ENTRY_PRIV_OFFSET | |
1155 | ||
1156 | queue->entries = entries; | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
fa69560f | 1161 | static void rt2x00queue_free_skbs(struct data_queue *queue) |
30caa6e3 GW |
1162 | { |
1163 | unsigned int i; | |
1164 | ||
1165 | if (!queue->entries) | |
1166 | return; | |
1167 | ||
1168 | for (i = 0; i < queue->limit; i++) { | |
fa69560f | 1169 | rt2x00queue_free_skb(&queue->entries[i]); |
30caa6e3 GW |
1170 | } |
1171 | } | |
1172 | ||
fa69560f | 1173 | static int rt2x00queue_alloc_rxskbs(struct data_queue *queue) |
30caa6e3 GW |
1174 | { |
1175 | unsigned int i; | |
1176 | struct sk_buff *skb; | |
1177 | ||
1178 | for (i = 0; i < queue->limit; i++) { | |
88211021 | 1179 | skb = rt2x00queue_alloc_rxskb(&queue->entries[i], GFP_KERNEL); |
30caa6e3 | 1180 | if (!skb) |
61243d8e | 1181 | return -ENOMEM; |
30caa6e3 GW |
1182 | queue->entries[i].skb = skb; |
1183 | } | |
1184 | ||
1185 | return 0; | |
30caa6e3 GW |
1186 | } |
1187 | ||
181d6902 ID |
1188 | int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev) |
1189 | { | |
1190 | struct data_queue *queue; | |
1191 | int status; | |
1192 | ||
15d6c079 | 1193 | status = rt2x00queue_alloc_entries(rt2x00dev->rx); |
181d6902 ID |
1194 | if (status) |
1195 | goto exit; | |
1196 | ||
1197 | tx_queue_for_each(rt2x00dev, queue) { | |
15d6c079 | 1198 | status = rt2x00queue_alloc_entries(queue); |
181d6902 ID |
1199 | if (status) |
1200 | goto exit; | |
1201 | } | |
1202 | ||
15d6c079 | 1203 | status = rt2x00queue_alloc_entries(rt2x00dev->bcn); |
181d6902 ID |
1204 | if (status) |
1205 | goto exit; | |
1206 | ||
7dab73b3 | 1207 | if (test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags)) { |
15d6c079 | 1208 | status = rt2x00queue_alloc_entries(rt2x00dev->atim); |
30caa6e3 GW |
1209 | if (status) |
1210 | goto exit; | |
1211 | } | |
181d6902 | 1212 | |
fa69560f | 1213 | status = rt2x00queue_alloc_rxskbs(rt2x00dev->rx); |
181d6902 ID |
1214 | if (status) |
1215 | goto exit; | |
1216 | ||
1217 | return 0; | |
1218 | ||
1219 | exit: | |
ec9c4989 | 1220 | rt2x00_err(rt2x00dev, "Queue entries allocation failed\n"); |
181d6902 ID |
1221 | |
1222 | rt2x00queue_uninitialize(rt2x00dev); | |
1223 | ||
1224 | return status; | |
1225 | } | |
1226 | ||
1227 | void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev) | |
1228 | { | |
1229 | struct data_queue *queue; | |
1230 | ||
fa69560f | 1231 | rt2x00queue_free_skbs(rt2x00dev->rx); |
30caa6e3 | 1232 | |
181d6902 ID |
1233 | queue_for_each(rt2x00dev, queue) { |
1234 | kfree(queue->entries); | |
1235 | queue->entries = NULL; | |
1236 | } | |
1237 | } | |
1238 | ||
8f539276 ID |
1239 | static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev, |
1240 | struct data_queue *queue, enum data_queue_qid qid) | |
1241 | { | |
0b7fde54 | 1242 | mutex_init(&queue->status_lock); |
77a861c4 | 1243 | spin_lock_init(&queue->tx_lock); |
813f0339 | 1244 | spin_lock_init(&queue->index_lock); |
8f539276 ID |
1245 | |
1246 | queue->rt2x00dev = rt2x00dev; | |
1247 | queue->qid = qid; | |
2af0a570 | 1248 | queue->txop = 0; |
8f539276 ID |
1249 | queue->aifs = 2; |
1250 | queue->cw_min = 5; | |
1251 | queue->cw_max = 10; | |
10af87c3 | 1252 | |
705802bf | 1253 | rt2x00dev->ops->queue_init(queue); |
04453e9b GJ |
1254 | |
1255 | queue->threshold = DIV_ROUND_UP(queue->limit, 10); | |
8f539276 ID |
1256 | } |
1257 | ||
181d6902 ID |
1258 | int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev) |
1259 | { | |
1260 | struct data_queue *queue; | |
1261 | enum data_queue_qid qid; | |
1262 | unsigned int req_atim = | |
7dab73b3 | 1263 | !!test_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags); |
181d6902 ID |
1264 | |
1265 | /* | |
1266 | * We need the following queues: | |
1267 | * RX: 1 | |
61448f88 | 1268 | * TX: ops->tx_queues |
181d6902 ID |
1269 | * Beacon: 1 |
1270 | * Atim: 1 (if required) | |
1271 | */ | |
61448f88 | 1272 | rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim; |
181d6902 | 1273 | |
baeb2ffa | 1274 | queue = kcalloc(rt2x00dev->data_queues, sizeof(*queue), GFP_KERNEL); |
181d6902 | 1275 | if (!queue) { |
ec9c4989 | 1276 | rt2x00_err(rt2x00dev, "Queue allocation failed\n"); |
181d6902 ID |
1277 | return -ENOMEM; |
1278 | } | |
1279 | ||
1280 | /* | |
1281 | * Initialize pointers | |
1282 | */ | |
1283 | rt2x00dev->rx = queue; | |
1284 | rt2x00dev->tx = &queue[1]; | |
61448f88 | 1285 | rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; |
e74df4a7 | 1286 | rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL; |
181d6902 ID |
1287 | |
1288 | /* | |
1289 | * Initialize queue parameters. | |
1290 | * RX: qid = QID_RX | |
f615e9a3 | 1291 | * TX: qid = QID_AC_VO + index |
181d6902 ID |
1292 | * TX: cw_min: 2^5 = 32. |
1293 | * TX: cw_max: 2^10 = 1024. | |
565a019a ID |
1294 | * BCN: qid = QID_BEACON |
1295 | * ATIM: qid = QID_ATIM | |
181d6902 | 1296 | */ |
8f539276 | 1297 | rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX); |
181d6902 | 1298 | |
f615e9a3 | 1299 | qid = QID_AC_VO; |
8f539276 ID |
1300 | tx_queue_for_each(rt2x00dev, queue) |
1301 | rt2x00queue_init(rt2x00dev, queue, qid++); | |
181d6902 | 1302 | |
e74df4a7 | 1303 | rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON); |
181d6902 | 1304 | if (req_atim) |
e74df4a7 | 1305 | rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM); |
181d6902 ID |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | void rt2x00queue_free(struct rt2x00_dev *rt2x00dev) | |
1311 | { | |
1312 | kfree(rt2x00dev->rx); | |
1313 | rt2x00dev->rx = NULL; | |
1314 | rt2x00dev->tx = NULL; | |
1315 | rt2x00dev->bcn = NULL; | |
1316 | } |