[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
#include <fdtdec.h>

#undef DEBUG

#define ENET_ADDR_LENGTH	6

/* EmacLite constants */
#define XEL_BUFFER_OFFSET	0x0800	/* Next buffer's offset */
#define XEL_TPLR_OFFSET		0x07F4	/* Tx packet length */
#define XEL_TSR_OFFSET		0x07FC	/* Tx status */
#define XEL_RSR_OFFSET		0x17FC	/* Rx status */
#define XEL_RXBUFF_OFFSET	0x1000	/* Receive Buffer */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK	0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

struct xemaclite {
	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
};

static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

static void emaclite_halt(struct eth_device *dev)
{
	debug("eth_halt\n");
}

static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
	struct xemaclite *emaclite = dev->priv;
	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
	/* Copy MAC address */
	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
	/* Set the length */
	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	/* Update the MAC address in the EMAC Lite */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
		xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
			XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_TSR_PROG_MAC_ADDR);
		while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
			XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);

	if (emaclite->rxpp)
		out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_RSR_RECV_IE_MASK);

	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct eth_device *dev)
{
	u32 reg;
	u32 txpingbusy;
	u32 txpongbusy;
	struct xemaclite *emaclite = dev->priv;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	reg = in_be32 (dev->iobase +
			emaclite->nexttxbuffertouse + 0);
	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	reg = in_be32 (dev->iobase +
			(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	return !(txpingbusy && txpongbusy);
}

static int emaclite_send(struct eth_device *dev, void *ptr, int len)
{
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (!xemaclite_txbufferavailable(dev) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
		if (emaclite->txpp) {
			out_be32 (dev->iobase + XEL_TSR_OFFSET +
				XEL_BUFFER_OFFSET, 0);
		}
		return -1;
	}

	/* Determine the expected TX buffer address */
	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);

	/* Determine if the expected buffer address is empty */
	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {

		if (emaclite->txpp)
			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;

		debug("Send packet from 0x%x\n", baseaddress);
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, baseaddress, len);
		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
		return 0;
	}

	if (emaclite->txpp) {
		/* Switch to second buffer */
		baseaddress ^= XEL_BUFFER_OFFSET;
		/* Determine if the expected buffer address is empty */
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
			&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
			debug("Send packet from 0x%x\n", baseaddress);
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, baseaddress, len);
			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
				(XEL_TPLR_LENGTH_MASK_HI |
					XEL_TPLR_LENGTH_MASK_LO)));
			reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
				reg |= XEL_TSR_XMIT_ACTIVE_MASK;
			out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct eth_device *dev)
{
	u32 length;
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	debug("Testing data at address 0x%x\n", baseaddress);
	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
		if (emaclite->rxpp)
			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
	} else {

		if (!emaclite->rxpp) {
			debug("No data was available - address 0x%x\n",
								baseaddress);
			return 0;
		} else {
			baseaddress ^= XEL_BUFFER_OFFSET;
			reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
			if ((reg & XEL_RSR_RECV_DONE_MASK) !=
						XEL_RSR_RECV_DONE_MASK) {
				debug("No data was available - address 0x%x\n",
						baseaddress);
				return 0;
			}
		}
	}
	/* Get the length of the frame that arrived */
	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
			0xFFFF0000 ) >> 16) {
		case 0x806:
			length = 42 + 20; /* FIXME size of ARP */
			debug("ARP Packet\n");
			break;
		case 0x800:
			length = 14 + 14 +
			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
						0x10))) & 0xFFFF0000) >> 16);
			/* FIXME size of IP packet */
			debug ("IP Packet\n");
			break;
		default:
			debug("Other Packet\n");
			length = PKTSIZE;
			break;
	}

	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
			etherrxbuff, length);

	/* Acknowledge the frame */
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);

	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
	NetReceive((uchar *) etherrxbuff, length);
	return length;

}

int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
							int txpp, int rxpp)
{
	struct eth_device *dev;
	struct xemaclite *emaclite;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	emaclite = calloc(1, sizeof(struct xemaclite));
	if (emaclite == NULL) {
		free(dev);
		return -1;
	}

	dev->priv = emaclite;

	emaclite->txpp = txpp;
	emaclite->rxpp = rxpp;

	sprintf(dev->name, "Xelite.%lx", base_addr);

	dev->iobase = base_addr;
	dev->init = emaclite_init;
	dev->halt = emaclite_halt;
	dev->send = emaclite_send;
	dev->recv = emaclite_recv;

	eth_register(dev);

	return 1;
}

#ifdef CONFIG_OF_CONTROL
int xilinx_emaclite_of_init(const void *blob)
{
	int offset = 0;
	u32 ret = 0;
	u32 reg;

	do {
		offset = fdt_node_offset_by_compatible(blob, offset,
					"xlnx,xps-ethernetlite-1.00.a");
		if (offset != -1) {
			reg = fdtdec_get_addr(blob, offset, "reg");
			if (reg != FDT_ADDR_T_NONE) {
				u32 rxpp = fdtdec_get_int(blob, offset,
							"xlnx,rx-ping-pong", 0);
				u32 txpp = fdtdec_get_int(blob, offset,
							"xlnx,tx-ping-pong", 0);
				ret |= xilinx_emaclite_initialize(NULL, reg,
								txpp, rxpp);
			} else {
				debug("EMACLITE: Can't get base address\n");
				return -1;
			}
		}
	} while (offset != -1);

	return ret;
}
#endif
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
78d19a39	8	*/
89c53891 MS	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <config.h>
042272a6	13	#include <malloc.h>
89c53891	14	#include <asm/io.h>
7fd70820 MS	15	#include <fdtdec.h>
7fd70820 MS	16
89c53891 MS	17	#undef DEBUG
89c53891 MS	18
89c53891 MS	19	#define ENET_ADDR_LENGTH 6
	20
	21	/* EmacLite constants */
	22	#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
	23	#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
	24	#define XEL_TSR_OFFSET 0x07FC /* Tx status */
	25	#define XEL_RSR_OFFSET 0x17FC /* Rx status */
	26	#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
	27
	28	/* Xmit complete */
	29	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	30	/* Xmit interrupt enable bit */
	31	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
	32	/* Buffer is active, SW bit only */
	33	#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
	34	/* Program the MAC address */
	35	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	36	/* define for programming the MAC address into the EMAC Lite */
	37	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	38
	39	/* Transmit packet length upper byte */
	40	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	41	/* Transmit packet length lower byte */
	42	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	43
	44	/* Recv complete */
	45	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	46	/* Recv interrupt enable bit */
	47	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	48
773cfa8d	49	struct xemaclite {
042272a6 MS	50	u32 nexttxbuffertouse; /* Next TX buffer to write to */
042272a6 MS	51	u32 nextrxbuffertouse; /* Next RX buffer to read from */
947324b9 MS	52	u32 txpp; /* TX ping pong buffer */
947324b9 MS	53	u32 rxpp; /* RX ping pong buffer */
773cfa8d	54	};
89c53891	55
f2a7806f	56	static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
89c53891	57
5ac83801	58	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	59	{
042272a6	60	u32 i;
89c53891 MS	61	u32 alignbuffer;
	62	u32 *to32ptr;
	63	u32 *from32ptr;
	64	u8 *to8ptr;
	65	u8 *from8ptr;
	66
	67	from32ptr = (u32 *) srcptr;
	68
	69	/* Word aligned buffer, no correction needed. */
	70	to32ptr = (u32 *) destptr;
	71	while (bytecount > 3) {
	72	to32ptr++ = from32ptr++;
	73	bytecount -= 4;
	74	}
	75	to8ptr = (u8 *) to32ptr;
	76
	77	alignbuffer = *from32ptr++;
5ac83801	78	from8ptr = (u8 *) &alignbuffer;
89c53891	79
5ac83801	80	for (i = 0; i < bytecount; i++)
89c53891	81	to8ptr++ = from8ptr++;
89c53891 MS	82	}
89c53891 MS	83
5ac83801	84	static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
89c53891	85	{
042272a6	86	u32 i;
89c53891 MS	87	u32 alignbuffer;
	88	u32 to32ptr = (u32 ) destptr;
	89	u32 *from32ptr;
	90	u8 *to8ptr;
	91	u8 *from8ptr;
	92
	93	from32ptr = (u32 *) srcptr;
	94	while (bytecount > 3) {
	95
	96	to32ptr++ = from32ptr++;
	97	bytecount -= 4;
	98	}
	99
	100	alignbuffer = 0;
5ac83801	101	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	102	from8ptr = (u8 *) from32ptr;
89c53891 MS	103
5ac83801	104	for (i = 0; i < bytecount; i++)
89c53891	105	to8ptr++ = from8ptr++;
89c53891 MS	106
	107	*to32ptr++ = alignbuffer;
	108	}
	109
042272a6	110	static void emaclite_halt(struct eth_device *dev)
89c53891	111	{
5ac83801	112	debug("eth_halt\n");
89c53891 MS	113	}
89c53891 MS	114
042272a6	115	static int emaclite_init(struct eth_device dev, bd_t bis)
89c53891	116	{
947324b9	117	struct xemaclite *emaclite = dev->priv;
5ac83801	118	debug("EmacLite Initialization Started\n");
89c53891 MS	119
	120	/*
	121	* TX - TX_PING & TX_PONG initialization
	122	*/
	123	/* Restart PING TX */
8d95ddbb	124	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
89c53891	125	/* Copy MAC address */
5ac83801	126	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
89c53891	127	/* Set the length */
8d95ddbb	128	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
89c53891	129	/* Update the MAC address in the EMAC Lite */
8d95ddbb	130	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
89c53891	131	/* Wait for EMAC Lite to finish with the MAC address update */
8d95ddbb MS	132	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
	133	XEL_TSR_PROG_MAC_ADDR) != 0)
	134	;
89c53891	135
947324b9 MS	136	if (emaclite->txpp) {
	137	/* The same operation with PONG TX */
	138	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
	139	xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
	140	XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
	141	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	142	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
	143	XEL_TSR_PROG_MAC_ADDR);
	144	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
	145	XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
	146	;
	147	}
89c53891 MS	148
	149	/*
	150	* RX - RX_PING & RX_PONG initialization
	151	*/
	152	/* Write out the value to flush the RX buffer */
8d95ddbb	153	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
947324b9 MS	154
	155	if (emaclite->rxpp)
	156	out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
	157	XEL_RSR_RECV_IE_MASK);
89c53891	158
5ac83801	159	debug("EmacLite Initialization complete\n");
89c53891 MS	160	return 0;
	161	}
	162
773cfa8d	163	static int xemaclite_txbufferavailable(struct eth_device *dev)
89c53891 MS	164	{
	165	u32 reg;
	166	u32 txpingbusy;
	167	u32 txpongbusy;
773cfa8d MS	168	struct xemaclite *emaclite = dev->priv;
773cfa8d MS	169
89c53891 MS	170	/*
	171	* Read the other buffer register
	172	* and determine if the other buffer is available
	173	*/
773cfa8d MS	174	reg = in_be32 (dev->iobase +
773cfa8d MS	175	emaclite->nexttxbuffertouse + 0);
89c53891 MS	176	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	177	XEL_TSR_XMIT_BUSY_MASK);
	178
773cfa8d MS	179	reg = in_be32 (dev->iobase +
773cfa8d MS	180	(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
89c53891 MS	181	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	182	XEL_TSR_XMIT_BUSY_MASK);
	183
5ac83801	184	return !(txpingbusy && txpongbusy);
89c53891 MS	185	}
89c53891 MS	186
1ae6b9c4	187	static int emaclite_send(struct eth_device dev, void ptr, int len)
042272a6 MS	188	{
	189	u32 reg;
	190	u32 baseaddress;
773cfa8d	191	struct xemaclite *emaclite = dev->priv;
89c53891	192
042272a6	193	u32 maxtry = 1000;
89c53891	194
80439252 MS	195	if (len > PKTSIZE)
80439252 MS	196	len = PKTSIZE;
89c53891	197
773cfa8d	198	while (!xemaclite_txbufferavailable(dev) && maxtry) {
5ac83801	199	udelay(10);
89c53891 MS	200	maxtry--;
	201	}
	202
	203	if (!maxtry) {
5ac83801	204	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	205	/* Restart PING TX */
8d95ddbb	206	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
947324b9 MS	207	if (emaclite->txpp) {
	208	out_be32 (dev->iobase + XEL_TSR_OFFSET +
	209	XEL_BUFFER_OFFSET, 0);
	210	}
95efa79d	211	return -1;
89c53891 MS	212	}
	213
	214	/* Determine the expected TX buffer address */
773cfa8d	215	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
89c53891 MS	216
	217	/* Determine if the expected buffer address is empty */
	218	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	219	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	220	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	221	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	222
947324b9 MS	223	if (emaclite->txpp)
	224	emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
	225
5ac83801	226	debug("Send packet from 0x%x\n", baseaddress);
89c53891	227	/* Write the frame to the buffer */
1ae6b9c4	228	xemaclite_alignedwrite(ptr, baseaddress, len);
89c53891 MS	229	out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
	230	(XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO)));
	231	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	232	reg \|= XEL_TSR_XMIT_BUSY_MASK;
5ac83801	233	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
89c53891	234	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
89c53891	235	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
95efa79d	236	return 0;
89c53891	237	}
947324b9 MS	238
	239	if (emaclite->txpp) {
	240	/* Switch to second buffer */
	241	baseaddress ^= XEL_BUFFER_OFFSET;
	242	/* Determine if the expected buffer address is empty */
89c53891	243	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
947324b9 MS	244	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	245	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	246	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	247	debug("Send packet from 0x%x\n", baseaddress);
	248	/* Write the frame to the buffer */
1ae6b9c4	249	xemaclite_alignedwrite(ptr, baseaddress, len);
947324b9 MS	250	out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
	251	(XEL_TPLR_LENGTH_MASK_HI \|
	252	XEL_TPLR_LENGTH_MASK_LO)));
	253	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	254	reg \|= XEL_TSR_XMIT_BUSY_MASK;
	255	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
	256	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
	257	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
	258	return 0;
89c53891	259	}
89c53891	260	}
947324b9	261
5ac83801	262	puts("Error while sending frame\n");
95efa79d	263	return -1;
89c53891 MS	264	}
89c53891 MS	265
042272a6	266	static int emaclite_recv(struct eth_device *dev)
89c53891	267	{
042272a6 MS	268	u32 length;
	269	u32 reg;
	270	u32 baseaddress;
773cfa8d	271	struct xemaclite *emaclite = dev->priv;
89c53891	272
773cfa8d	273	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
89c53891	274	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
5ac83801	275	debug("Testing data at address 0x%x\n", baseaddress);
89c53891	276	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
947324b9 MS	277	if (emaclite->rxpp)
947324b9 MS	278	emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
89c53891	279	} else {
947324b9 MS	280
947324b9 MS	281	if (!emaclite->rxpp) {
5ac83801	282	debug("No data was available - address 0x%x\n",
947324b9	283	baseaddress);
89c53891	284	return 0;
947324b9 MS	285	} else {
	286	baseaddress ^= XEL_BUFFER_OFFSET;
	287	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	288	if ((reg & XEL_RSR_RECV_DONE_MASK) !=
	289	XEL_RSR_RECV_DONE_MASK) {
	290	debug("No data was available - address 0x%x\n",
	291	baseaddress);
	292	return 0;
	293	}
89c53891	294	}
89c53891 MS	295	}
89c53891 MS	296	/* Get the length of the frame that arrived */
3f91ec0f	297	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
89c53891 MS	298	0xFFFF0000 ) >> 16) {
	299	case 0x806:
	300	length = 42 + 20; /* FIXME size of ARP */
5ac83801	301	debug("ARP Packet\n");
89c53891 MS	302	break;
	303	case 0x800:
	304	length = 14 + 14 +
5ac83801 MS	305	(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
	306	0x10))) & 0xFFFF0000) >> 16);
	307	/* FIXME size of IP packet */
89c53891 MS	308	debug ("IP Packet\n");
	309	break;
	310	default:
80439252 MS	311	debug("Other Packet\n");
80439252 MS	312	length = PKTSIZE;
89c53891 MS	313	break;
	314	}
	315
5ac83801	316	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
89c53891 MS	317	etherrxbuff, length);
	318
	319	/* Acknowledge the frame */
	320	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	321	reg &= ~XEL_RSR_RECV_DONE_MASK;
	322	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
	323
5ac83801 MS	324	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
5ac83801 MS	325	NetReceive((uchar *) etherrxbuff, length);
95efa79d	326	return length;
89c53891 MS	327
89c53891 MS	328	}
042272a6	329
c1044a1e MS	330	int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
c1044a1e MS	331	int txpp, int rxpp)
042272a6 MS	332	{
042272a6 MS	333	struct eth_device *dev;
773cfa8d	334	struct xemaclite *emaclite;
042272a6	335
28ae02e5	336	dev = calloc(1, sizeof(*dev));
042272a6	337	if (dev == NULL)
95efa79d	338	return -1;
042272a6	339
773cfa8d MS	340	emaclite = calloc(1, sizeof(struct xemaclite));
	341	if (emaclite == NULL) {
	342	free(dev);
	343	return -1;
	344	}
	345
	346	dev->priv = emaclite;
	347
c1044a1e MS	348	emaclite->txpp = txpp;
c1044a1e MS	349	emaclite->rxpp = rxpp;
947324b9	350
9b94755a	351	sprintf(dev->name, "Xelite.%lx", base_addr);
042272a6 MS	352
042272a6 MS	353	dev->iobase = base_addr;
042272a6 MS	354	dev->init = emaclite_init;
	355	dev->halt = emaclite_halt;
	356	dev->send = emaclite_send;
	357	dev->recv = emaclite_recv;
	358
	359	eth_register(dev);
	360
95efa79d	361	return 1;
042272a6	362	}
7fd70820 MS	363
7fd70820 MS	364	#ifdef CONFIG_OF_CONTROL
0c9c99a2	365	int xilinx_emaclite_of_init(const void *blob)
7fd70820 MS	366	{
	367	int offset = 0;
	368	u32 ret = 0;
	369	u32 reg;
	370
	371	do {
0c9c99a2	372	offset = fdt_node_offset_by_compatible(blob, offset,
7fd70820 MS	373	"xlnx,xps-ethernetlite-1.00.a");
7fd70820 MS	374	if (offset != -1) {
0c9c99a2	375	reg = fdtdec_get_addr(blob, offset, "reg");
7fd70820	376	if (reg != FDT_ADDR_T_NONE) {
0c9c99a2	377	u32 rxpp = fdtdec_get_int(blob, offset,
7fd70820	378	"xlnx,rx-ping-pong", 0);
0c9c99a2	379	u32 txpp = fdtdec_get_int(blob, offset,
7fd70820	380	"xlnx,tx-ping-pong", 0);
0c9c99a2	381	ret \|= xilinx_emaclite_initialize(NULL, reg,
7fd70820	382	txpp, rxpp);
0c9c99a2 MS	383	} else {
	384	debug("EMACLITE: Can't get base address\n");
	385	return -1;
7fd70820 MS	386	}
	387	}
	388	} while (offset != -1);
	389
	390	return ret;
	391	}
	392	#endif