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Commit | Line | Data |
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78d19a39 MS |
1 | /* |
2 | * (C) Copyright 2007-2009 Michal Simek | |
3 | * (C) Copyright 2003 Xilinx Inc. | |
89c53891 | 4 | * |
89c53891 MS |
5 | * Michal SIMEK <monstr@monstr.eu> |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
78d19a39 | 8 | */ |
89c53891 MS |
9 | |
10 | #include <common.h> | |
11 | #include <net.h> | |
12 | #include <config.h> | |
d538ee1b | 13 | #include <dm.h> |
d722e864 | 14 | #include <console.h> |
042272a6 | 15 | #include <malloc.h> |
89c53891 | 16 | #include <asm/io.h> |
d722e864 MS |
17 | #include <phy.h> |
18 | #include <miiphy.h> | |
7fd70820 | 19 | #include <fdtdec.h> |
5d97dff0 | 20 | #include <linux/errno.h> |
4d2749be | 21 | #include <linux/kernel.h> |
39e020ef | 22 | #include <asm/io.h> |
7fd70820 | 23 | |
d538ee1b | 24 | DECLARE_GLOBAL_DATA_PTR; |
89c53891 | 25 | |
89c53891 | 26 | #define ENET_ADDR_LENGTH 6 |
4d2749be | 27 | #define ETH_FCS_LEN 4 /* Octets in the FCS */ |
89c53891 MS |
28 | |
29 | /* Xmit complete */ | |
30 | #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL | |
31 | /* Xmit interrupt enable bit */ | |
32 | #define XEL_TSR_XMIT_IE_MASK 0x00000008UL | |
89c53891 MS |
33 | /* Program the MAC address */ |
34 | #define XEL_TSR_PROGRAM_MASK 0x00000002UL | |
35 | /* define for programming the MAC address into the EMAC Lite */ | |
36 | #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) | |
37 | ||
38 | /* Transmit packet length upper byte */ | |
39 | #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL | |
40 | /* Transmit packet length lower byte */ | |
41 | #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL | |
42 | ||
43 | /* Recv complete */ | |
44 | #define XEL_RSR_RECV_DONE_MASK 0x00000001UL | |
45 | /* Recv interrupt enable bit */ | |
46 | #define XEL_RSR_RECV_IE_MASK 0x00000008UL | |
47 | ||
d722e864 MS |
48 | /* MDIO Address Register Bit Masks */ |
49 | #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ | |
50 | #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ | |
51 | #define XEL_MDIOADDR_PHYADR_SHIFT 5 | |
52 | #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ | |
53 | ||
54 | /* MDIO Write Data Register Bit Masks */ | |
55 | #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ | |
56 | ||
57 | /* MDIO Read Data Register Bit Masks */ | |
58 | #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ | |
59 | ||
60 | /* MDIO Control Register Bit Masks */ | |
61 | #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ | |
62 | #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ | |
63 | ||
9a23c496 MS |
64 | struct emaclite_regs { |
65 | u32 tx_ping; /* 0x0 - TX Ping buffer */ | |
66 | u32 reserved1[504]; | |
67 | u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ | |
68 | u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ | |
69 | u32 mdiord;/* 0x7ec - MDIO Read Data Register */ | |
70 | u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ | |
71 | u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ | |
72 | u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ | |
73 | u32 tx_ping_tsr; /* 0x7fc - Tx status */ | |
74 | u32 tx_pong; /* 0x800 - TX Pong buffer */ | |
75 | u32 reserved2[508]; | |
76 | u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ | |
77 | u32 reserved3; /* 0xff8 */ | |
78 | u32 tx_pong_tsr; /* 0xffc - Tx status */ | |
79 | u32 rx_ping; /* 0x1000 - Receive Buffer */ | |
80 | u32 reserved4[510]; | |
81 | u32 rx_ping_rsr; /* 0x17fc - Rx status */ | |
82 | u32 rx_pong; /* 0x1800 - Receive Buffer */ | |
83 | u32 reserved5[510]; | |
84 | u32 rx_pong_rsr; /* 0x1ffc - Rx status */ | |
85 | }; | |
86 | ||
773cfa8d | 87 | struct xemaclite { |
4d2749be | 88 | bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ |
947324b9 MS |
89 | u32 txpp; /* TX ping pong buffer */ |
90 | u32 rxpp; /* RX ping pong buffer */ | |
d722e864 | 91 | int phyaddr; |
9a23c496 | 92 | struct emaclite_regs *regs; |
d722e864 MS |
93 | struct phy_device *phydev; |
94 | struct mii_dev *bus; | |
773cfa8d | 95 | }; |
89c53891 | 96 | |
f412b6ab | 97 | static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ |
89c53891 | 98 | |
5ac83801 | 99 | static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) |
89c53891 | 100 | { |
042272a6 | 101 | u32 i; |
89c53891 MS |
102 | u32 alignbuffer; |
103 | u32 *to32ptr; | |
104 | u32 *from32ptr; | |
105 | u8 *to8ptr; | |
106 | u8 *from8ptr; | |
107 | ||
108 | from32ptr = (u32 *) srcptr; | |
109 | ||
110 | /* Word aligned buffer, no correction needed. */ | |
111 | to32ptr = (u32 *) destptr; | |
112 | while (bytecount > 3) { | |
113 | *to32ptr++ = *from32ptr++; | |
114 | bytecount -= 4; | |
115 | } | |
116 | to8ptr = (u8 *) to32ptr; | |
117 | ||
118 | alignbuffer = *from32ptr++; | |
5ac83801 | 119 | from8ptr = (u8 *) &alignbuffer; |
89c53891 | 120 | |
5ac83801 | 121 | for (i = 0; i < bytecount; i++) |
89c53891 | 122 | *to8ptr++ = *from8ptr++; |
89c53891 MS |
123 | } |
124 | ||
00702518 | 125 | static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) |
89c53891 | 126 | { |
042272a6 | 127 | u32 i; |
89c53891 MS |
128 | u32 alignbuffer; |
129 | u32 *to32ptr = (u32 *) destptr; | |
130 | u32 *from32ptr; | |
131 | u8 *to8ptr; | |
132 | u8 *from8ptr; | |
133 | ||
134 | from32ptr = (u32 *) srcptr; | |
135 | while (bytecount > 3) { | |
136 | ||
137 | *to32ptr++ = *from32ptr++; | |
138 | bytecount -= 4; | |
139 | } | |
140 | ||
141 | alignbuffer = 0; | |
5ac83801 | 142 | to8ptr = (u8 *) &alignbuffer; |
89c53891 MS |
143 | from8ptr = (u8 *) from32ptr; |
144 | ||
5ac83801 | 145 | for (i = 0; i < bytecount; i++) |
89c53891 | 146 | *to8ptr++ = *from8ptr++; |
89c53891 MS |
147 | |
148 | *to32ptr++ = alignbuffer; | |
149 | } | |
150 | ||
d722e864 MS |
151 | static int wait_for_bit(const char *func, u32 *reg, const u32 mask, |
152 | bool set, unsigned int timeout) | |
153 | { | |
154 | u32 val; | |
155 | unsigned long start = get_timer(0); | |
156 | ||
157 | while (1) { | |
611fe0bd | 158 | val = __raw_readl(reg); |
d722e864 MS |
159 | |
160 | if (!set) | |
161 | val = ~val; | |
162 | ||
163 | if ((val & mask) == mask) | |
164 | return 0; | |
165 | ||
166 | if (get_timer(start) > timeout) | |
167 | break; | |
168 | ||
169 | if (ctrlc()) { | |
170 | puts("Abort\n"); | |
171 | return -EINTR; | |
172 | } | |
173 | ||
174 | udelay(1); | |
175 | } | |
176 | ||
177 | debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", | |
178 | func, reg, mask, set); | |
179 | ||
180 | return -ETIMEDOUT; | |
181 | } | |
182 | ||
9a23c496 | 183 | static int mdio_wait(struct emaclite_regs *regs) |
d722e864 | 184 | { |
9a23c496 | 185 | return wait_for_bit(__func__, ®s->mdioctrl, |
d722e864 MS |
186 | XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); |
187 | } | |
188 | ||
9a23c496 | 189 | static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, |
d722e864 MS |
190 | u16 *data) |
191 | { | |
9a23c496 MS |
192 | struct emaclite_regs *regs = emaclite->regs; |
193 | ||
194 | if (mdio_wait(regs)) | |
d722e864 MS |
195 | return 1; |
196 | ||
611fe0bd ZLK |
197 | u32 ctrl_reg = __raw_readl(®s->mdioctrl); |
198 | __raw_writel(XEL_MDIOADDR_OP_MASK | |
199 | | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | |
200 | | registernum), ®s->mdioaddr); | |
201 | __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl); | |
d722e864 | 202 | |
9a23c496 | 203 | if (mdio_wait(regs)) |
d722e864 MS |
204 | return 1; |
205 | ||
206 | /* Read data */ | |
611fe0bd | 207 | *data = __raw_readl(®s->mdiord); |
d722e864 MS |
208 | return 0; |
209 | } | |
210 | ||
9a23c496 | 211 | static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, |
d722e864 MS |
212 | u16 data) |
213 | { | |
9a23c496 MS |
214 | struct emaclite_regs *regs = emaclite->regs; |
215 | ||
216 | if (mdio_wait(regs)) | |
d722e864 MS |
217 | return 1; |
218 | ||
219 | /* | |
220 | * Write the PHY address, register number and clear the OP bit in the | |
221 | * MDIO Address register and then write the value into the MDIO Write | |
222 | * Data register. Finally, set the Status bit in the MDIO Control | |
223 | * register to start a MDIO write transaction. | |
224 | */ | |
611fe0bd ZLK |
225 | u32 ctrl_reg = __raw_readl(®s->mdioctrl); |
226 | __raw_writel(~XEL_MDIOADDR_OP_MASK | |
227 | & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | |
228 | | registernum), ®s->mdioaddr); | |
229 | __raw_writel(data, ®s->mdiowr); | |
230 | __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl); | |
d722e864 | 231 | |
9a23c496 | 232 | if (mdio_wait(regs)) |
d722e864 MS |
233 | return 1; |
234 | ||
235 | return 0; | |
236 | } | |
d722e864 | 237 | |
f03ec010 | 238 | static void emaclite_stop(struct udevice *dev) |
89c53891 | 239 | { |
f03ec010 | 240 | debug("eth_stop\n"); |
89c53891 MS |
241 | } |
242 | ||
d722e864 MS |
243 | /* Use MII register 1 (MII status register) to detect PHY */ |
244 | #define PHY_DETECT_REG 1 | |
245 | ||
246 | /* Mask used to verify certain PHY features (or register contents) | |
247 | * in the register above: | |
248 | * 0x1000: 10Mbps full duplex support | |
249 | * 0x0800: 10Mbps half duplex support | |
250 | * 0x0008: Auto-negotiation support | |
251 | */ | |
252 | #define PHY_DETECT_MASK 0x1808 | |
253 | ||
d538ee1b | 254 | static int setup_phy(struct udevice *dev) |
d722e864 | 255 | { |
55259e7c | 256 | int i, ret; |
d722e864 | 257 | u16 phyreg; |
d538ee1b | 258 | struct xemaclite *emaclite = dev_get_priv(dev); |
d722e864 MS |
259 | struct phy_device *phydev; |
260 | ||
261 | u32 supported = SUPPORTED_10baseT_Half | | |
262 | SUPPORTED_10baseT_Full | | |
263 | SUPPORTED_100baseT_Half | | |
264 | SUPPORTED_100baseT_Full; | |
265 | ||
266 | if (emaclite->phyaddr != -1) { | |
9a23c496 | 267 | phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); |
d722e864 MS |
268 | if ((phyreg != 0xFFFF) && |
269 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
270 | /* Found a valid PHY address */ | |
271 | debug("Default phy address %d is valid\n", | |
272 | emaclite->phyaddr); | |
273 | } else { | |
274 | debug("PHY address is not setup correctly %d\n", | |
275 | emaclite->phyaddr); | |
276 | emaclite->phyaddr = -1; | |
277 | } | |
278 | } | |
279 | ||
280 | if (emaclite->phyaddr == -1) { | |
281 | /* detect the PHY address */ | |
282 | for (i = 31; i >= 0; i--) { | |
9a23c496 | 283 | phyread(emaclite, i, PHY_DETECT_REG, &phyreg); |
d722e864 MS |
284 | if ((phyreg != 0xFFFF) && |
285 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
286 | /* Found a valid PHY address */ | |
287 | emaclite->phyaddr = i; | |
288 | debug("emaclite: Found valid phy address, %d\n", | |
289 | i); | |
290 | break; | |
291 | } | |
292 | } | |
293 | } | |
294 | ||
295 | /* interface - look at tsec */ | |
296 | phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, | |
297 | PHY_INTERFACE_MODE_MII); | |
298 | /* | |
299 | * Phy can support 1000baseT but device NOT that's why phydev->supported | |
300 | * must be setup for 1000baseT. phydev->advertising setups what speeds | |
301 | * will be used for autonegotiation where 1000baseT must be disabled. | |
302 | */ | |
303 | phydev->supported = supported | SUPPORTED_1000baseT_Half | | |
304 | SUPPORTED_1000baseT_Full; | |
305 | phydev->advertising = supported; | |
306 | emaclite->phydev = phydev; | |
307 | phy_config(phydev); | |
55259e7c MS |
308 | ret = phy_startup(phydev); |
309 | if (ret) | |
310 | return ret; | |
d722e864 MS |
311 | |
312 | if (!phydev->link) { | |
313 | printf("%s: No link.\n", phydev->dev->name); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | /* Do not setup anything */ | |
318 | return 1; | |
319 | } | |
d722e864 | 320 | |
f03ec010 | 321 | static int emaclite_start(struct udevice *dev) |
89c53891 | 322 | { |
d538ee1b MS |
323 | struct xemaclite *emaclite = dev_get_priv(dev); |
324 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
9a23c496 MS |
325 | struct emaclite_regs *regs = emaclite->regs; |
326 | ||
5ac83801 | 327 | debug("EmacLite Initialization Started\n"); |
89c53891 MS |
328 | |
329 | /* | |
330 | * TX - TX_PING & TX_PONG initialization | |
331 | */ | |
332 | /* Restart PING TX */ | |
611fe0bd | 333 | __raw_writel(0, ®s->tx_ping_tsr); |
89c53891 | 334 | /* Copy MAC address */ |
d538ee1b | 335 | xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, |
a0b2bfb0 | 336 | ENET_ADDR_LENGTH); |
89c53891 | 337 | /* Set the length */ |
611fe0bd | 338 | __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr); |
89c53891 | 339 | /* Update the MAC address in the EMAC Lite */ |
611fe0bd | 340 | __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr); |
89c53891 | 341 | /* Wait for EMAC Lite to finish with the MAC address update */ |
611fe0bd | 342 | while ((__raw_readl(®s->tx_ping_tsr) & |
8d95ddbb MS |
343 | XEL_TSR_PROG_MAC_ADDR) != 0) |
344 | ; | |
89c53891 | 345 | |
947324b9 MS |
346 | if (emaclite->txpp) { |
347 | /* The same operation with PONG TX */ | |
611fe0bd | 348 | __raw_writel(0, ®s->tx_pong_tsr); |
d538ee1b | 349 | xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, |
a0b2bfb0 | 350 | ENET_ADDR_LENGTH); |
611fe0bd ZLK |
351 | __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr); |
352 | __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr); | |
353 | while ((__raw_readl(®s->tx_pong_tsr) & | |
a0b2bfb0 | 354 | XEL_TSR_PROG_MAC_ADDR) != 0) |
947324b9 MS |
355 | ; |
356 | } | |
89c53891 MS |
357 | |
358 | /* | |
359 | * RX - RX_PING & RX_PONG initialization | |
360 | */ | |
361 | /* Write out the value to flush the RX buffer */ | |
611fe0bd | 362 | __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr); |
947324b9 MS |
363 | |
364 | if (emaclite->rxpp) | |
611fe0bd | 365 | __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr); |
89c53891 | 366 | |
611fe0bd ZLK |
367 | __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl); |
368 | if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) | |
d722e864 MS |
369 | if (!setup_phy(dev)) |
370 | return -1; | |
d538ee1b | 371 | |
5ac83801 | 372 | debug("EmacLite Initialization complete\n"); |
89c53891 MS |
373 | return 0; |
374 | } | |
375 | ||
26c7945a | 376 | static int xemaclite_txbufferavailable(struct xemaclite *emaclite) |
89c53891 | 377 | { |
26c7945a MS |
378 | u32 tmp; |
379 | struct emaclite_regs *regs = emaclite->regs; | |
773cfa8d | 380 | |
89c53891 MS |
381 | /* |
382 | * Read the other buffer register | |
383 | * and determine if the other buffer is available | |
384 | */ | |
611fe0bd | 385 | tmp = ~__raw_readl(®s->tx_ping_tsr); |
26c7945a | 386 | if (emaclite->txpp) |
611fe0bd | 387 | tmp |= ~__raw_readl(®s->tx_pong_tsr); |
89c53891 | 388 | |
26c7945a | 389 | return !(tmp & XEL_TSR_XMIT_BUSY_MASK); |
89c53891 MS |
390 | } |
391 | ||
d538ee1b | 392 | static int emaclite_send(struct udevice *dev, void *ptr, int len) |
042272a6 MS |
393 | { |
394 | u32 reg; | |
d538ee1b | 395 | struct xemaclite *emaclite = dev_get_priv(dev); |
5a4baa33 | 396 | struct emaclite_regs *regs = emaclite->regs; |
89c53891 | 397 | |
042272a6 | 398 | u32 maxtry = 1000; |
89c53891 | 399 | |
80439252 MS |
400 | if (len > PKTSIZE) |
401 | len = PKTSIZE; | |
89c53891 | 402 | |
26c7945a | 403 | while (xemaclite_txbufferavailable(emaclite) && maxtry) { |
5ac83801 | 404 | udelay(10); |
89c53891 MS |
405 | maxtry--; |
406 | } | |
407 | ||
408 | if (!maxtry) { | |
5ac83801 | 409 | printf("Error: Timeout waiting for ethernet TX buffer\n"); |
89c53891 | 410 | /* Restart PING TX */ |
611fe0bd | 411 | __raw_writel(0, ®s->tx_ping_tsr); |
947324b9 | 412 | if (emaclite->txpp) { |
611fe0bd | 413 | __raw_writel(0, ®s->tx_pong_tsr); |
947324b9 | 414 | } |
95efa79d | 415 | return -1; |
89c53891 MS |
416 | } |
417 | ||
89c53891 | 418 | /* Determine if the expected buffer address is empty */ |
611fe0bd | 419 | reg = __raw_readl(®s->tx_ping_tsr); |
15c239c8 | 420 | if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { |
00702518 | 421 | debug("Send packet from tx_ping buffer\n"); |
89c53891 | 422 | /* Write the frame to the buffer */ |
00702518 | 423 | xemaclite_alignedwrite(ptr, ®s->tx_ping, len); |
611fe0bd ZLK |
424 | __raw_writel(len |
425 | & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO), | |
426 | ®s->tx_ping_tplr); | |
427 | reg = __raw_readl(®s->tx_ping_tsr); | |
89c53891 | 428 | reg |= XEL_TSR_XMIT_BUSY_MASK; |
611fe0bd | 429 | __raw_writel(reg, ®s->tx_ping_tsr); |
95efa79d | 430 | return 0; |
89c53891 | 431 | } |
947324b9 MS |
432 | |
433 | if (emaclite->txpp) { | |
947324b9 | 434 | /* Determine if the expected buffer address is empty */ |
611fe0bd | 435 | reg = __raw_readl(®s->tx_pong_tsr); |
15c239c8 | 436 | if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { |
00702518 | 437 | debug("Send packet from tx_pong buffer\n"); |
947324b9 | 438 | /* Write the frame to the buffer */ |
00702518 | 439 | xemaclite_alignedwrite(ptr, ®s->tx_pong, len); |
611fe0bd | 440 | __raw_writel(len & |
00702518 | 441 | (XEL_TPLR_LENGTH_MASK_HI | |
611fe0bd ZLK |
442 | XEL_TPLR_LENGTH_MASK_LO), |
443 | ®s->tx_pong_tplr); | |
444 | reg = __raw_readl(®s->tx_pong_tsr); | |
947324b9 | 445 | reg |= XEL_TSR_XMIT_BUSY_MASK; |
611fe0bd | 446 | __raw_writel(reg, ®s->tx_pong_tsr); |
947324b9 | 447 | return 0; |
89c53891 | 448 | } |
89c53891 | 449 | } |
947324b9 | 450 | |
5ac83801 | 451 | puts("Error while sending frame\n"); |
95efa79d | 452 | return -1; |
89c53891 MS |
453 | } |
454 | ||
d538ee1b | 455 | static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) |
89c53891 | 456 | { |
4d2749be MS |
457 | u32 length, first_read, reg, attempt = 0; |
458 | void *addr, *ack; | |
773cfa8d | 459 | struct xemaclite *emaclite = dev->priv; |
4d2749be MS |
460 | struct emaclite_regs *regs = emaclite->regs; |
461 | struct ethernet_hdr *eth; | |
462 | struct ip_udp_hdr *ip; | |
463 | ||
464 | try_again: | |
465 | if (!emaclite->use_rx_pong_buffer_next) { | |
611fe0bd | 466 | reg = __raw_readl(®s->rx_ping_rsr); |
4d2749be MS |
467 | debug("Testing data at rx_ping\n"); |
468 | if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { | |
469 | debug("Data found in rx_ping buffer\n"); | |
470 | addr = ®s->rx_ping; | |
471 | ack = ®s->rx_ping_rsr; | |
472 | } else { | |
473 | debug("Data not found in rx_ping buffer\n"); | |
474 | /* Pong buffer is not available - return immediately */ | |
475 | if (!emaclite->rxpp) | |
476 | return -1; | |
477 | ||
478 | /* Try pong buffer if this is first attempt */ | |
479 | if (attempt++) | |
480 | return -1; | |
481 | emaclite->use_rx_pong_buffer_next = | |
482 | !emaclite->use_rx_pong_buffer_next; | |
483 | goto try_again; | |
484 | } | |
89c53891 | 485 | } else { |
611fe0bd | 486 | reg = __raw_readl(®s->rx_pong_rsr); |
4d2749be MS |
487 | debug("Testing data at rx_pong\n"); |
488 | if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { | |
489 | debug("Data found in rx_pong buffer\n"); | |
490 | addr = ®s->rx_pong; | |
491 | ack = ®s->rx_pong_rsr; | |
947324b9 | 492 | } else { |
4d2749be MS |
493 | debug("Data not found in rx_pong buffer\n"); |
494 | /* Try ping buffer if this is first attempt */ | |
495 | if (attempt++) | |
496 | return -1; | |
497 | emaclite->use_rx_pong_buffer_next = | |
498 | !emaclite->use_rx_pong_buffer_next; | |
499 | goto try_again; | |
89c53891 | 500 | } |
89c53891 | 501 | } |
4d2749be MS |
502 | |
503 | /* Read all bytes for ARP packet with 32bit alignment - 48bytes */ | |
504 | first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); | |
505 | xemaclite_alignedread(addr, etherrxbuff, first_read); | |
506 | ||
507 | /* Detect real packet size */ | |
508 | eth = (struct ethernet_hdr *)etherrxbuff; | |
509 | switch (ntohs(eth->et_protlen)) { | |
510 | case PROT_ARP: | |
511 | length = first_read; | |
512 | debug("ARP Packet %x\n", length); | |
513 | break; | |
514 | case PROT_IP: | |
515 | ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); | |
516 | length = ntohs(ip->ip_len); | |
517 | length += ETHER_HDR_SIZE + ETH_FCS_LEN; | |
518 | debug("IP Packet %x\n", length); | |
519 | break; | |
520 | default: | |
521 | debug("Other Packet\n"); | |
522 | length = PKTSIZE; | |
523 | break; | |
89c53891 MS |
524 | } |
525 | ||
4d2749be MS |
526 | /* Read the rest of the packet which is longer then first read */ |
527 | if (length != first_read) | |
528 | xemaclite_alignedread(addr + first_read, | |
529 | etherrxbuff + first_read, | |
530 | length - first_read); | |
89c53891 MS |
531 | |
532 | /* Acknowledge the frame */ | |
611fe0bd | 533 | reg = __raw_readl(ack); |
89c53891 | 534 | reg &= ~XEL_RSR_RECV_DONE_MASK; |
611fe0bd | 535 | __raw_writel(reg, ack); |
89c53891 | 536 | |
4d2749be | 537 | debug("Packet receive from 0x%p, length %dB\n", addr, length); |
f412b6ab MS |
538 | *packetp = etherrxbuff; |
539 | return length; | |
89c53891 | 540 | } |
042272a6 | 541 | |
d538ee1b MS |
542 | static int emaclite_miiphy_read(struct mii_dev *bus, int addr, |
543 | int devad, int reg) | |
d722e864 MS |
544 | { |
545 | u32 ret; | |
d538ee1b | 546 | u16 val = 0; |
d722e864 | 547 | |
d538ee1b MS |
548 | ret = phyread(bus->priv, addr, reg, &val); |
549 | debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); | |
550 | return val; | |
d722e864 MS |
551 | } |
552 | ||
d538ee1b MS |
553 | static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, |
554 | int reg, u16 value) | |
d722e864 | 555 | { |
d538ee1b MS |
556 | debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); |
557 | return phywrite(bus->priv, addr, reg, value); | |
d722e864 | 558 | } |
d722e864 | 559 | |
d538ee1b | 560 | static int emaclite_probe(struct udevice *dev) |
042272a6 | 561 | { |
d538ee1b MS |
562 | struct xemaclite *emaclite = dev_get_priv(dev); |
563 | int ret; | |
042272a6 | 564 | |
d538ee1b MS |
565 | emaclite->bus = mdio_alloc(); |
566 | emaclite->bus->read = emaclite_miiphy_read; | |
567 | emaclite->bus->write = emaclite_miiphy_write; | |
568 | emaclite->bus->priv = emaclite; | |
042272a6 | 569 | |
6516e3f2 | 570 | ret = mdio_register_seq(emaclite->bus, dev->seq); |
d538ee1b MS |
571 | if (ret) |
572 | return ret; | |
573 | ||
574 | return 0; | |
575 | } | |
773cfa8d | 576 | |
d538ee1b MS |
577 | static int emaclite_remove(struct udevice *dev) |
578 | { | |
579 | struct xemaclite *emaclite = dev_get_priv(dev); | |
580 | ||
581 | free(emaclite->phydev); | |
582 | mdio_unregister(emaclite->bus); | |
583 | mdio_free(emaclite->bus); | |
773cfa8d | 584 | |
d538ee1b MS |
585 | return 0; |
586 | } | |
947324b9 | 587 | |
d538ee1b | 588 | static const struct eth_ops emaclite_ops = { |
f03ec010 | 589 | .start = emaclite_start, |
d538ee1b MS |
590 | .send = emaclite_send, |
591 | .recv = emaclite_recv, | |
f03ec010 | 592 | .stop = emaclite_stop, |
d538ee1b MS |
593 | }; |
594 | ||
595 | static int emaclite_ofdata_to_platdata(struct udevice *dev) | |
596 | { | |
597 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
598 | struct xemaclite *emaclite = dev_get_priv(dev); | |
599 | int offset = 0; | |
042272a6 | 600 | |
a821c4af | 601 | pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); |
39e020ef ZLK |
602 | emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase, |
603 | 0x10000); | |
042272a6 | 604 | |
d722e864 | 605 | emaclite->phyaddr = -1; |
d722e864 | 606 | |
e160f7d4 | 607 | offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), |
d538ee1b MS |
608 | "phy-handle"); |
609 | if (offset > 0) | |
610 | emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, | |
611 | "reg", -1); | |
042272a6 | 612 | |
e160f7d4 | 613 | emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
d538ee1b | 614 | "xlnx,tx-ping-pong", 0); |
e160f7d4 | 615 | emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
d538ee1b | 616 | "xlnx,rx-ping-pong", 0); |
d722e864 | 617 | |
d538ee1b MS |
618 | printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, |
619 | emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); | |
d722e864 | 620 | |
d538ee1b | 621 | return 0; |
042272a6 | 622 | } |
d538ee1b MS |
623 | |
624 | static const struct udevice_id emaclite_ids[] = { | |
625 | { .compatible = "xlnx,xps-ethernetlite-1.00.a" }, | |
626 | { } | |
627 | }; | |
628 | ||
629 | U_BOOT_DRIVER(emaclite) = { | |
630 | .name = "emaclite", | |
631 | .id = UCLASS_ETH, | |
632 | .of_match = emaclite_ids, | |
633 | .ofdata_to_platdata = emaclite_ofdata_to_platdata, | |
634 | .probe = emaclite_probe, | |
635 | .remove = emaclite_remove, | |
636 | .ops = &emaclite_ops, | |
637 | .priv_auto_alloc_size = sizeof(struct xemaclite), | |
638 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
639 | }; |