[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <malloc.h>
#include <asm/io.h>

#undef DEBUG

#define ENET_ADDR_LENGTH	6

/* EmacLite constants */
#define XEL_BUFFER_OFFSET	0x0800	/* Next buffer's offset */
#define XEL_TPLR_OFFSET		0x07F4	/* Tx packet length */
#define XEL_TSR_OFFSET		0x07FC	/* Tx status */
#define XEL_RSR_OFFSET		0x17FC	/* Rx status */
#define XEL_RXBUFF_OFFSET	0x1000	/* Receive Buffer */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK	0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

struct xemaclite {
	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
};

static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

static void emaclite_halt(struct eth_device *dev)
{
	debug("eth_halt\n");
}

static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
	struct xemaclite *emaclite = dev->priv;
	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
	/* Copy MAC address */
	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
	/* Set the length */
	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	/* Update the MAC address in the EMAC Lite */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
		xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
			XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_TSR_PROG_MAC_ADDR);
		while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
			XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);

	if (emaclite->rxpp)
		out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_RSR_RECV_IE_MASK);

	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct eth_device *dev)
{
	u32 reg;
	u32 txpingbusy;
	u32 txpongbusy;
	struct xemaclite *emaclite = dev->priv;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	reg = in_be32 (dev->iobase +
			emaclite->nexttxbuffertouse + 0);
	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	reg = in_be32 (dev->iobase +
			(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	return !(txpingbusy && txpongbusy);
}

static int emaclite_send(struct eth_device *dev, void *ptr, int len)
{
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (!xemaclite_txbufferavailable(dev) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
		if (emaclite->txpp) {
			out_be32 (dev->iobase + XEL_TSR_OFFSET +
				XEL_BUFFER_OFFSET, 0);
		}
		return -1;
	}

	/* Determine the expected TX buffer address */
	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);

	/* Determine if the expected buffer address is empty */
	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {

		if (emaclite->txpp)
			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;

		debug("Send packet from 0x%x\n", baseaddress);
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, baseaddress, len);
		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
		return 0;
	}

	if (emaclite->txpp) {
		/* Switch to second buffer */
		baseaddress ^= XEL_BUFFER_OFFSET;
		/* Determine if the expected buffer address is empty */
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
			&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
			debug("Send packet from 0x%x\n", baseaddress);
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, baseaddress, len);
			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
				(XEL_TPLR_LENGTH_MASK_HI |
					XEL_TPLR_LENGTH_MASK_LO)));
			reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
				reg |= XEL_TSR_XMIT_ACTIVE_MASK;
			out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct eth_device *dev)
{
	u32 length;
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	debug("Testing data at address 0x%x\n", baseaddress);
	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
		if (emaclite->rxpp)
			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
	} else {

		if (!emaclite->rxpp) {
			debug("No data was available - address 0x%x\n",
								baseaddress);
			return 0;
		} else {
			baseaddress ^= XEL_BUFFER_OFFSET;
			reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
			if ((reg & XEL_RSR_RECV_DONE_MASK) !=
						XEL_RSR_RECV_DONE_MASK) {
				debug("No data was available - address 0x%x\n",
						baseaddress);
				return 0;
			}
		}
	}
	/* Get the length of the frame that arrived */
	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
			0xFFFF0000 ) >> 16) {
		case 0x806:
			length = 42 + 20; /* FIXME size of ARP */
			debug("ARP Packet\n");
			break;
		case 0x800:
			length = 14 + 14 +
			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
						0x10))) & 0xFFFF0000) >> 16);
			/* FIXME size of IP packet */
			debug ("IP Packet\n");
			break;
		default:
			debug("Other Packet\n");
			length = PKTSIZE;
			break;
	}

	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
			etherrxbuff, length);

	/* Acknowledge the frame */
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);

	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
	NetReceive((uchar *) etherrxbuff, length);
	return length;

}

int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
							int txpp, int rxpp)
{
	struct eth_device *dev;
	struct xemaclite *emaclite;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	emaclite = calloc(1, sizeof(struct xemaclite));
	if (emaclite == NULL) {
		free(dev);
		return -1;
	}

	dev->priv = emaclite;

	emaclite->txpp = txpp;
	emaclite->rxpp = rxpp;

	sprintf(dev->name, "Xelite.%lx", base_addr);

	dev->iobase = base_addr;
	dev->init = emaclite_init;
	dev->halt = emaclite_halt;
	dev->send = emaclite_send;
	dev->recv = emaclite_recv;

	eth_register(dev);

	return 1;
}
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
78d19a39 MS	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
89c53891	19	*
78d19a39 MS	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
89c53891 MS	25
	26	#include <common.h>
	27	#include <net.h>
	28	#include <config.h>
042272a6	29	#include <malloc.h>
89c53891 MS	30	#include <asm/io.h>
	31
	32	#undef DEBUG
	33
89c53891 MS	34	#define ENET_ADDR_LENGTH 6
	35
	36	/* EmacLite constants */
	37	#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
	38	#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
	39	#define XEL_TSR_OFFSET 0x07FC /* Tx status */
	40	#define XEL_RSR_OFFSET 0x17FC /* Rx status */
	41	#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
	42
	43	/* Xmit complete */
	44	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	45	/* Xmit interrupt enable bit */
	46	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
	47	/* Buffer is active, SW bit only */
	48	#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
	49	/* Program the MAC address */
	50	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	51	/* define for programming the MAC address into the EMAC Lite */
	52	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	53
	54	/* Transmit packet length upper byte */
	55	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	56	/* Transmit packet length lower byte */
	57	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	58
	59	/* Recv complete */
	60	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	61	/* Recv interrupt enable bit */
	62	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	63
773cfa8d	64	struct xemaclite {
042272a6 MS	65	u32 nexttxbuffertouse; /* Next TX buffer to write to */
042272a6 MS	66	u32 nextrxbuffertouse; /* Next RX buffer to read from */
947324b9 MS	67	u32 txpp; /* TX ping pong buffer */
947324b9 MS	68	u32 rxpp; /* RX ping pong buffer */
773cfa8d	69	};
89c53891	70
f2a7806f	71	static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
89c53891	72
5ac83801	73	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	74	{
042272a6	75	u32 i;
89c53891 MS	76	u32 alignbuffer;
	77	u32 *to32ptr;
	78	u32 *from32ptr;
	79	u8 *to8ptr;
	80	u8 *from8ptr;
	81
	82	from32ptr = (u32 *) srcptr;
	83
	84	/* Word aligned buffer, no correction needed. */
	85	to32ptr = (u32 *) destptr;
	86	while (bytecount > 3) {
	87	to32ptr++ = from32ptr++;
	88	bytecount -= 4;
	89	}
	90	to8ptr = (u8 *) to32ptr;
	91
	92	alignbuffer = *from32ptr++;
5ac83801	93	from8ptr = (u8 *) &alignbuffer;
89c53891	94
5ac83801	95	for (i = 0; i < bytecount; i++)
89c53891	96	to8ptr++ = from8ptr++;
89c53891 MS	97	}
89c53891 MS	98
5ac83801	99	static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
89c53891	100	{
042272a6	101	u32 i;
89c53891 MS	102	u32 alignbuffer;
	103	u32 to32ptr = (u32 ) destptr;
	104	u32 *from32ptr;
	105	u8 *to8ptr;
	106	u8 *from8ptr;
	107
	108	from32ptr = (u32 *) srcptr;
	109	while (bytecount > 3) {
	110
	111	to32ptr++ = from32ptr++;
	112	bytecount -= 4;
	113	}
	114
	115	alignbuffer = 0;
5ac83801	116	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	117	from8ptr = (u8 *) from32ptr;
89c53891 MS	118
5ac83801	119	for (i = 0; i < bytecount; i++)
89c53891	120	to8ptr++ = from8ptr++;
89c53891 MS	121
	122	*to32ptr++ = alignbuffer;
	123	}
	124
042272a6	125	static void emaclite_halt(struct eth_device *dev)
89c53891	126	{
5ac83801	127	debug("eth_halt\n");
89c53891 MS	128	}
89c53891 MS	129
042272a6	130	static int emaclite_init(struct eth_device dev, bd_t bis)
89c53891	131	{
947324b9	132	struct xemaclite *emaclite = dev->priv;
5ac83801	133	debug("EmacLite Initialization Started\n");
89c53891 MS	134
	135	/*
	136	* TX - TX_PING & TX_PONG initialization
	137	*/
	138	/* Restart PING TX */
8d95ddbb	139	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
89c53891	140	/* Copy MAC address */
5ac83801	141	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
89c53891	142	/* Set the length */
8d95ddbb	143	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
89c53891	144	/* Update the MAC address in the EMAC Lite */
8d95ddbb	145	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
89c53891	146	/* Wait for EMAC Lite to finish with the MAC address update */
8d95ddbb MS	147	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
	148	XEL_TSR_PROG_MAC_ADDR) != 0)
	149	;
89c53891	150
947324b9 MS	151	if (emaclite->txpp) {
	152	/* The same operation with PONG TX */
	153	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
	154	xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
	155	XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
	156	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	157	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
	158	XEL_TSR_PROG_MAC_ADDR);
	159	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
	160	XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
	161	;
	162	}
89c53891 MS	163
	164	/*
	165	* RX - RX_PING & RX_PONG initialization
	166	*/
	167	/* Write out the value to flush the RX buffer */
8d95ddbb	168	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
947324b9 MS	169
	170	if (emaclite->rxpp)
	171	out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
	172	XEL_RSR_RECV_IE_MASK);
89c53891	173
5ac83801	174	debug("EmacLite Initialization complete\n");
89c53891 MS	175	return 0;
	176	}
	177
773cfa8d	178	static int xemaclite_txbufferavailable(struct eth_device *dev)
89c53891 MS	179	{
	180	u32 reg;
	181	u32 txpingbusy;
	182	u32 txpongbusy;
773cfa8d MS	183	struct xemaclite *emaclite = dev->priv;
773cfa8d MS	184
89c53891 MS	185	/*
	186	* Read the other buffer register
	187	* and determine if the other buffer is available
	188	*/
773cfa8d MS	189	reg = in_be32 (dev->iobase +
773cfa8d MS	190	emaclite->nexttxbuffertouse + 0);
89c53891 MS	191	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	192	XEL_TSR_XMIT_BUSY_MASK);
	193
773cfa8d MS	194	reg = in_be32 (dev->iobase +
773cfa8d MS	195	(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
89c53891 MS	196	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	197	XEL_TSR_XMIT_BUSY_MASK);
	198
5ac83801	199	return !(txpingbusy && txpongbusy);
89c53891 MS	200	}
89c53891 MS	201
1ae6b9c4	202	static int emaclite_send(struct eth_device dev, void ptr, int len)
042272a6 MS	203	{
	204	u32 reg;
	205	u32 baseaddress;
773cfa8d	206	struct xemaclite *emaclite = dev->priv;
89c53891	207
042272a6	208	u32 maxtry = 1000;
89c53891	209
80439252 MS	210	if (len > PKTSIZE)
80439252 MS	211	len = PKTSIZE;
89c53891	212
773cfa8d	213	while (!xemaclite_txbufferavailable(dev) && maxtry) {
5ac83801	214	udelay(10);
89c53891 MS	215	maxtry--;
	216	}
	217
	218	if (!maxtry) {
5ac83801	219	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	220	/* Restart PING TX */
8d95ddbb	221	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
947324b9 MS	222	if (emaclite->txpp) {
	223	out_be32 (dev->iobase + XEL_TSR_OFFSET +
	224	XEL_BUFFER_OFFSET, 0);
	225	}
95efa79d	226	return -1;
89c53891 MS	227	}
	228
	229	/* Determine the expected TX buffer address */
773cfa8d	230	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
89c53891 MS	231
	232	/* Determine if the expected buffer address is empty */
	233	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	234	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	235	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	236	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	237
947324b9 MS	238	if (emaclite->txpp)
	239	emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
	240
5ac83801	241	debug("Send packet from 0x%x\n", baseaddress);
89c53891	242	/* Write the frame to the buffer */
1ae6b9c4	243	xemaclite_alignedwrite(ptr, baseaddress, len);
89c53891 MS	244	out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
	245	(XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO)));
	246	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	247	reg \|= XEL_TSR_XMIT_BUSY_MASK;
5ac83801	248	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
89c53891	249	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
89c53891	250	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
95efa79d	251	return 0;
89c53891	252	}
947324b9 MS	253
	254	if (emaclite->txpp) {
	255	/* Switch to second buffer */
	256	baseaddress ^= XEL_BUFFER_OFFSET;
	257	/* Determine if the expected buffer address is empty */
89c53891	258	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
947324b9 MS	259	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	260	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	261	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	262	debug("Send packet from 0x%x\n", baseaddress);
	263	/* Write the frame to the buffer */
1ae6b9c4	264	xemaclite_alignedwrite(ptr, baseaddress, len);
947324b9 MS	265	out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
	266	(XEL_TPLR_LENGTH_MASK_HI \|
	267	XEL_TPLR_LENGTH_MASK_LO)));
	268	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	269	reg \|= XEL_TSR_XMIT_BUSY_MASK;
	270	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
	271	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
	272	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
	273	return 0;
89c53891	274	}
89c53891	275	}
947324b9	276
5ac83801	277	puts("Error while sending frame\n");
95efa79d	278	return -1;
89c53891 MS	279	}
89c53891 MS	280
042272a6	281	static int emaclite_recv(struct eth_device *dev)
89c53891	282	{
042272a6 MS	283	u32 length;
	284	u32 reg;
	285	u32 baseaddress;
773cfa8d	286	struct xemaclite *emaclite = dev->priv;
89c53891	287
773cfa8d	288	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
89c53891	289	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
5ac83801	290	debug("Testing data at address 0x%x\n", baseaddress);
89c53891	291	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
947324b9 MS	292	if (emaclite->rxpp)
947324b9 MS	293	emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
89c53891	294	} else {
947324b9 MS	295
947324b9 MS	296	if (!emaclite->rxpp) {
5ac83801	297	debug("No data was available - address 0x%x\n",
947324b9	298	baseaddress);
89c53891	299	return 0;
947324b9 MS	300	} else {
	301	baseaddress ^= XEL_BUFFER_OFFSET;
	302	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	303	if ((reg & XEL_RSR_RECV_DONE_MASK) !=
	304	XEL_RSR_RECV_DONE_MASK) {
	305	debug("No data was available - address 0x%x\n",
	306	baseaddress);
	307	return 0;
	308	}
89c53891	309	}
89c53891 MS	310	}
89c53891 MS	311	/* Get the length of the frame that arrived */
3f91ec0f	312	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
89c53891 MS	313	0xFFFF0000 ) >> 16) {
	314	case 0x806:
	315	length = 42 + 20; /* FIXME size of ARP */
5ac83801	316	debug("ARP Packet\n");
89c53891 MS	317	break;
	318	case 0x800:
	319	length = 14 + 14 +
5ac83801 MS	320	(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
	321	0x10))) & 0xFFFF0000) >> 16);
	322	/* FIXME size of IP packet */
89c53891 MS	323	debug ("IP Packet\n");
	324	break;
	325	default:
80439252 MS	326	debug("Other Packet\n");
80439252 MS	327	length = PKTSIZE;
89c53891 MS	328	break;
	329	}
	330
5ac83801	331	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
89c53891 MS	332	etherrxbuff, length);
	333
	334	/* Acknowledge the frame */
	335	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	336	reg &= ~XEL_RSR_RECV_DONE_MASK;
	337	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
	338
5ac83801 MS	339	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
5ac83801 MS	340	NetReceive((uchar *) etherrxbuff, length);
95efa79d	341	return length;
89c53891 MS	342
89c53891 MS	343	}
042272a6	344
c1044a1e MS	345	int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
c1044a1e MS	346	int txpp, int rxpp)
042272a6 MS	347	{
042272a6 MS	348	struct eth_device *dev;
773cfa8d	349	struct xemaclite *emaclite;
042272a6	350
28ae02e5	351	dev = calloc(1, sizeof(*dev));
042272a6	352	if (dev == NULL)
95efa79d	353	return -1;
042272a6	354
773cfa8d MS	355	emaclite = calloc(1, sizeof(struct xemaclite));
	356	if (emaclite == NULL) {
	357	free(dev);
	358	return -1;
	359	}
	360
	361	dev->priv = emaclite;
	362
c1044a1e MS	363	emaclite->txpp = txpp;
c1044a1e MS	364	emaclite->rxpp = rxpp;
947324b9	365
9b94755a	366	sprintf(dev->name, "Xelite.%lx", base_addr);
042272a6 MS	367
042272a6 MS	368	dev->iobase = base_addr;
042272a6 MS	369	dev->init = emaclite_init;
	370	dev->halt = emaclite_halt;
	371	dev->send = emaclite_send;
	372	dev->recv = emaclite_recv;
	373
	374	eth_register(dev);
	375
95efa79d	376	return 1;
042272a6	377	}