[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <dm.h>
#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
#include <asm-generic/errno.h>
#include <linux/kernel.h>

DECLARE_GLOBAL_DATA_PTR;

#define ENET_ADDR_LENGTH	6
#define ETH_FCS_LEN		4 /* Octets in the FCS */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

/* MDIO Address Register Bit Masks */
#define XEL_MDIOADDR_REGADR_MASK  0x0000001F	/* Register Address */
#define XEL_MDIOADDR_PHYADR_MASK  0x000003E0	/* PHY Address */
#define XEL_MDIOADDR_PHYADR_SHIFT 5
#define XEL_MDIOADDR_OP_MASK	  0x00000400	/* RD/WR Operation */

/* MDIO Write Data Register Bit Masks */
#define XEL_MDIOWR_WRDATA_MASK	  0x0000FFFF	/* Data to be Written */

/* MDIO Read Data Register Bit Masks */
#define XEL_MDIORD_RDDATA_MASK	  0x0000FFFF	/* Data to be Read */

/* MDIO Control Register Bit Masks */
#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001	/* MDIO Status Mask */
#define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008	/* MDIO Enable */

struct emaclite_regs {
	u32 tx_ping; /* 0x0 - TX Ping buffer */
	u32 reserved1[504];
	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	u32 tx_pong; /* 0x800 - TX Pong buffer */
	u32 reserved2[508];
	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	u32 reserved3; /* 0xff8 */
	u32 tx_pong_tsr; /* 0xffc - Tx status */
	u32 rx_ping; /* 0x1000 - Receive Buffer */
	u32 reserved4[510];
	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	u32 rx_pong; /* 0x1800 - Receive Buffer */
	u32 reserved5[510];
	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
};

struct xemaclite {
	bool use_rx_pong_buffer_next;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
	int phyaddr;
	struct emaclite_regs *regs;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
			bool set, unsigned int timeout)
{
	u32 val;
	unsigned long start = get_timer(0);

	while (1) {
		val = readl(reg);

		if (!set)
			val = ~val;

		if ((val & mask) == mask)
			return 0;

		if (get_timer(start) > timeout)
			break;

		if (ctrlc()) {
			puts("Abort\n");
			return -EINTR;
		}

		udelay(1);
	}

	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	      func, reg, mask, set);

	return -ETIMEDOUT;
}

static int mdio_wait(struct emaclite_regs *regs)
{
	return wait_for_bit(__func__, &regs->mdioctrl,
			    XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
}

static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		   u16 *data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	u32 ctrl_reg = in_be32(&regs->mdioctrl);
	out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

	if (mdio_wait(regs))
		return 1;

	/* Read data */
	*data = in_be32(&regs->mdiord);
	return 0;
}

static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		    u16 data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	/*
	 * Write the PHY address, register number and clear the OP bit in the
	 * MDIO Address register and then write the value into the MDIO Write
	 * Data register. Finally, set the Status bit in the MDIO Control
	 * register to start a MDIO write transaction.
	 */
	u32 ctrl_reg = in_be32(&regs->mdioctrl);
	out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
	out_be32(&regs->mdiowr, data);
	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

	if (mdio_wait(regs))
		return 1;

	return 0;
}

static void emaclite_stop(struct udevice *dev)
{
	debug("eth_stop\n");
}

/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG  1

/* Mask used to verify certain PHY features (or register contents)
 * in the register above:
 *  0x1000: 10Mbps full duplex support
 *  0x0800: 10Mbps half duplex support
 *  0x0008: Auto-negotiation support
 */
#define PHY_DETECT_MASK 0x1808

static int setup_phy(struct udevice *dev)
{
	int i;
	u16 phyreg;
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct phy_device *phydev;

	u32 supported = SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full;

	if (emaclite->phyaddr != -1) {
		phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
		if ((phyreg != 0xFFFF) &&
		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
			/* Found a valid PHY address */
			debug("Default phy address %d is valid\n",
			      emaclite->phyaddr);
		} else {
			debug("PHY address is not setup correctly %d\n",
			      emaclite->phyaddr);
			emaclite->phyaddr = -1;
		}
	}

	if (emaclite->phyaddr == -1) {
		/* detect the PHY address */
		for (i = 31; i >= 0; i--) {
			phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
			if ((phyreg != 0xFFFF) &&
			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
				/* Found a valid PHY address */
				emaclite->phyaddr = i;
				debug("emaclite: Found valid phy address, %d\n",
				      i);
				break;
			}
		}
	}

	/* interface - look at tsec */
	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
			     PHY_INTERFACE_MODE_MII);
	/*
	 * Phy can support 1000baseT but device NOT that's why phydev->supported
	 * must be setup for 1000baseT. phydev->advertising setups what speeds
	 * will be used for autonegotiation where 1000baseT must be disabled.
	 */
	phydev->supported = supported | SUPPORTED_1000baseT_Half |
						SUPPORTED_1000baseT_Full;
	phydev->advertising = supported;
	emaclite->phydev = phydev;
	phy_config(phydev);
	phy_startup(phydev);

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return 0;
	}

	/* Do not setup anything */
	return 1;
}

static int emaclite_start(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct emaclite_regs *regs = emaclite->regs;

	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	out_be32(&regs->tx_ping_tsr, 0);
	/* Copy MAC address */
	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
			       ENET_ADDR_LENGTH);
	/* Set the length */
	out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
	/* Update the MAC address in the EMAC Lite */
	out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((in_be32 (&regs->tx_ping_tsr) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		out_be32(&regs->tx_pong_tsr, 0);
		xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
				       ENET_ADDR_LENGTH);
		out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
		out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
		while ((in_be32(&regs->tx_pong_tsr) &
		       XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);

	if (emaclite->rxpp)
		out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);

	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
	if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
		if (!setup_phy(dev))
			return -1;

	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
{
	u32 tmp;
	struct emaclite_regs *regs = emaclite->regs;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	tmp = ~in_be32(&regs->tx_ping_tsr);
	if (emaclite->txpp)
		tmp |= ~in_be32(&regs->tx_pong_tsr);

	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}

static int emaclite_send(struct udevice *dev, void *ptr, int len)
{
	u32 reg;
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct emaclite_regs *regs = emaclite->regs;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		out_be32(&regs->tx_ping_tsr, 0);
		if (emaclite->txpp) {
			out_be32(&regs->tx_pong_tsr, 0);
		}
		return -1;
	}

	/* Determine if the expected buffer address is empty */
	reg = in_be32(&regs->tx_ping_tsr);
	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
		debug("Send packet from tx_ping buffer\n");
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
		out_be32(&regs->tx_ping_tplr, len &
			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
		reg = in_be32(&regs->tx_ping_tsr);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		out_be32(&regs->tx_ping_tsr, reg);
		return 0;
	}

	if (emaclite->txpp) {
		/* Determine if the expected buffer address is empty */
		reg = in_be32(&regs->tx_pong_tsr);
		if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
			debug("Send packet from tx_pong buffer\n");
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
			out_be32(&regs->tx_pong_tplr, len &
				 (XEL_TPLR_LENGTH_MASK_HI |
				  XEL_TPLR_LENGTH_MASK_LO));
			reg = in_be32(&regs->tx_pong_tsr);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			out_be32(&regs->tx_pong_tsr, reg);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
{
	u32 length, first_read, reg, attempt = 0;
	void *addr, *ack;
	struct xemaclite *emaclite = dev->priv;
	struct emaclite_regs *regs = emaclite->regs;
	struct ethernet_hdr *eth;
	struct ip_udp_hdr *ip;

try_again:
	if (!emaclite->use_rx_pong_buffer_next) {
		reg = in_be32(&regs->rx_ping_rsr);
		debug("Testing data at rx_ping\n");
		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
			debug("Data found in rx_ping buffer\n");
			addr = &regs->rx_ping;
			ack = &regs->rx_ping_rsr;
		} else {
			debug("Data not found in rx_ping buffer\n");
			/* Pong buffer is not available - return immediately */
			if (!emaclite->rxpp)
				return -1;

			/* Try pong buffer if this is first attempt */
			if (attempt++)
				return -1;
			emaclite->use_rx_pong_buffer_next =
					!emaclite->use_rx_pong_buffer_next;
			goto try_again;
		}
	} else {
		reg = in_be32(&regs->rx_pong_rsr);
		debug("Testing data at rx_pong\n");
		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
			debug("Data found in rx_pong buffer\n");
			addr = &regs->rx_pong;
			ack = &regs->rx_pong_rsr;
		} else {
			debug("Data not found in rx_pong buffer\n");
			/* Try ping buffer if this is first attempt */
			if (attempt++)
				return -1;
			emaclite->use_rx_pong_buffer_next =
					!emaclite->use_rx_pong_buffer_next;
			goto try_again;
		}
	}

	/* Read all bytes for ARP packet with 32bit alignment - 48bytes  */
	first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
	xemaclite_alignedread(addr, etherrxbuff, first_read);

	/* Detect real packet size */
	eth = (struct ethernet_hdr *)etherrxbuff;
	switch (ntohs(eth->et_protlen)) {
	case PROT_ARP:
		length = first_read;
		debug("ARP Packet %x\n", length);
		break;
	case PROT_IP:
		ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
		length = ntohs(ip->ip_len);
		length += ETHER_HDR_SIZE + ETH_FCS_LEN;
		debug("IP Packet %x\n", length);
		break;
	default:
		debug("Other Packet\n");
		length = PKTSIZE;
		break;
	}

	/* Read the rest of the packet which is longer then first read */
	if (length != first_read)
		xemaclite_alignedread(addr + first_read,
				      etherrxbuff + first_read,
				      length - first_read);

	/* Acknowledge the frame */
	reg = in_be32(ack);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	out_be32(ack, reg);

	debug("Packet receive from 0x%p, length %dB\n", addr, length);
	*packetp = etherrxbuff;
	return length;
}

static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
				int devad, int reg)
{
	u32 ret;
	u16 val = 0;

	ret = phyread(bus->priv, addr, reg, &val);
	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
	return val;
}

static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
				 int reg, u16 value)
{
	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
	return phywrite(bus->priv, addr, reg, value);
}

static int emaclite_probe(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);
	int ret;

	emaclite->bus = mdio_alloc();
	emaclite->bus->read = emaclite_miiphy_read;
	emaclite->bus->write = emaclite_miiphy_write;
	emaclite->bus->priv = emaclite;
	strcpy(emaclite->bus->name, "emaclite");

	ret = mdio_register(emaclite->bus);
	if (ret)
		return ret;

	return 0;
}

static int emaclite_remove(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);

	free(emaclite->phydev);
	mdio_unregister(emaclite->bus);
	mdio_free(emaclite->bus);

	return 0;
}

static const struct eth_ops emaclite_ops = {
	.start = emaclite_start,
	.send = emaclite_send,
	.recv = emaclite_recv,
	.stop = emaclite_stop,
};

static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct xemaclite *emaclite = dev_get_priv(dev);
	int offset = 0;

	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
	emaclite->regs = (struct emaclite_regs *)pdata->iobase;

	emaclite->phyaddr = -1;

	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
				      "phy-handle");
	if (offset > 0)
		emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
						   "reg", -1);

	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
					"xlnx,tx-ping-pong", 0);
	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
					"xlnx,rx-ping-pong", 0);

	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);

	return 0;
}

static const struct udevice_id emaclite_ids[] = {
	{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
	{ }
};

U_BOOT_DRIVER(emaclite) = {
	.name   = "emaclite",
	.id     = UCLASS_ETH,
	.of_match = emaclite_ids,
	.ofdata_to_platdata = emaclite_ofdata_to_platdata,
	.probe  = emaclite_probe,
	.remove = emaclite_remove,
	.ops    = &emaclite_ops,
	.priv_auto_alloc_size = sizeof(struct xemaclite),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
78d19a39	8	*/
89c53891 MS	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <config.h>
d538ee1b	13	#include <dm.h>
d722e864	14	#include <console.h>
042272a6	15	#include <malloc.h>
89c53891	16	#include <asm/io.h>
d722e864 MS	17	#include <phy.h>
d722e864 MS	18	#include <miiphy.h>
7fd70820	19	#include <fdtdec.h>
d722e864	20	#include <asm-generic/errno.h>
4d2749be	21	#include <linux/kernel.h>
7fd70820	22
d538ee1b	23	DECLARE_GLOBAL_DATA_PTR;
89c53891	24
89c53891	25	#define ENET_ADDR_LENGTH 6
4d2749be	26	#define ETH_FCS_LEN 4 /* Octets in the FCS */
89c53891 MS	27
	28	/* Xmit complete */
	29	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	30	/* Xmit interrupt enable bit */
	31	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
89c53891 MS	32	/* Program the MAC address */
	33	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	34	/* define for programming the MAC address into the EMAC Lite */
	35	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	36
	37	/* Transmit packet length upper byte */
	38	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	39	/* Transmit packet length lower byte */
	40	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	41
	42	/* Recv complete */
	43	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	44	/* Recv interrupt enable bit */
	45	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	46
d722e864 MS	47	/* MDIO Address Register Bit Masks */
	48	#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
	49	#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
	50	#define XEL_MDIOADDR_PHYADR_SHIFT 5
	51	#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
	52
	53	/* MDIO Write Data Register Bit Masks */
	54	#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
	55
	56	/* MDIO Read Data Register Bit Masks */
	57	#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
	58
	59	/* MDIO Control Register Bit Masks */
	60	#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
	61	#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
	62
9a23c496 MS	63	struct emaclite_regs {
	64	u32 tx_ping; /* 0x0 - TX Ping buffer */
	65	u32 reserved1[504];
	66	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	67	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	68	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	69	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	70	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	71	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	72	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	73	u32 tx_pong; /* 0x800 - TX Pong buffer */
	74	u32 reserved2[508];
	75	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	76	u32 reserved3; /* 0xff8 */
	77	u32 tx_pong_tsr; /* 0xffc - Tx status */
	78	u32 rx_ping; /* 0x1000 - Receive Buffer */
	79	u32 reserved4[510];
	80	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	81	u32 rx_pong; /* 0x1800 - Receive Buffer */
	82	u32 reserved5[510];
	83	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
	84	};
	85
773cfa8d	86	struct xemaclite {
4d2749be	87	bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
947324b9 MS	88	u32 txpp; /* TX ping pong buffer */
947324b9 MS	89	u32 rxpp; /* RX ping pong buffer */
d722e864	90	int phyaddr;
9a23c496	91	struct emaclite_regs *regs;
d722e864 MS	92	struct phy_device *phydev;
d722e864 MS	93	struct mii_dev *bus;
773cfa8d	94	};
89c53891	95
f412b6ab	96	static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
89c53891	97
5ac83801	98	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	99	{
042272a6	100	u32 i;
89c53891 MS	101	u32 alignbuffer;
	102	u32 *to32ptr;
	103	u32 *from32ptr;
	104	u8 *to8ptr;
	105	u8 *from8ptr;
	106
	107	from32ptr = (u32 *) srcptr;
	108
	109	/* Word aligned buffer, no correction needed. */
	110	to32ptr = (u32 *) destptr;
	111	while (bytecount > 3) {
	112	to32ptr++ = from32ptr++;
	113	bytecount -= 4;
	114	}
	115	to8ptr = (u8 *) to32ptr;
	116
	117	alignbuffer = *from32ptr++;
5ac83801	118	from8ptr = (u8 *) &alignbuffer;
89c53891	119
5ac83801	120	for (i = 0; i < bytecount; i++)
89c53891	121	to8ptr++ = from8ptr++;
89c53891 MS	122	}
89c53891 MS	123
00702518	124	static void xemaclite_alignedwrite(void srcptr, u32 destptr, u32 bytecount)
89c53891	125	{
042272a6	126	u32 i;
89c53891 MS	127	u32 alignbuffer;
	128	u32 to32ptr = (u32 ) destptr;
	129	u32 *from32ptr;
	130	u8 *to8ptr;
	131	u8 *from8ptr;
	132
	133	from32ptr = (u32 *) srcptr;
	134	while (bytecount > 3) {
	135
	136	to32ptr++ = from32ptr++;
	137	bytecount -= 4;
	138	}
	139
	140	alignbuffer = 0;
5ac83801	141	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	142	from8ptr = (u8 *) from32ptr;
89c53891 MS	143
5ac83801	144	for (i = 0; i < bytecount; i++)
89c53891	145	to8ptr++ = from8ptr++;
89c53891 MS	146
	147	*to32ptr++ = alignbuffer;
	148	}
	149
d722e864 MS	150	static int wait_for_bit(const char func, u32 reg, const u32 mask,
	151	bool set, unsigned int timeout)
	152	{
	153	u32 val;
	154	unsigned long start = get_timer(0);
	155
	156	while (1) {
	157	val = readl(reg);
	158
	159	if (!set)
	160	val = ~val;
	161
	162	if ((val & mask) == mask)
	163	return 0;
	164
	165	if (get_timer(start) > timeout)
	166	break;
	167
	168	if (ctrlc()) {
	169	puts("Abort\n");
	170	return -EINTR;
	171	}
	172
	173	udelay(1);
	174	}
	175
	176	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	177	func, reg, mask, set);
	178
	179	return -ETIMEDOUT;
	180	}
	181
9a23c496	182	static int mdio_wait(struct emaclite_regs *regs)
d722e864	183	{
9a23c496	184	return wait_for_bit(__func__, &regs->mdioctrl,
d722e864 MS	185	XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
	186	}
	187
9a23c496	188	static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	189	u16 *data)
d722e864 MS	190	{
9a23c496 MS	191	struct emaclite_regs *regs = emaclite->regs;
	192
	193	if (mdio_wait(regs))
d722e864 MS	194	return 1;
d722e864 MS	195
9a23c496 MS	196	u32 ctrl_reg = in_be32(&regs->mdioctrl);
9a23c496 MS	197	out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK \|
d722e864	198	((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) \| registernum));
9a23c496	199	out_be32(&regs->mdioctrl, ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK);
d722e864	200
9a23c496	201	if (mdio_wait(regs))
d722e864 MS	202	return 1;
	203
	204	/* Read data */
9a23c496	205	*data = in_be32(&regs->mdiord);
d722e864 MS	206	return 0;
	207	}
	208
9a23c496	209	static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	210	u16 data)
d722e864 MS	211	{
9a23c496 MS	212	struct emaclite_regs *regs = emaclite->regs;
	213
	214	if (mdio_wait(regs))
d722e864 MS	215	return 1;
	216
	217	/*
	218	* Write the PHY address, register number and clear the OP bit in the
	219	* MDIO Address register and then write the value into the MDIO Write
	220	* Data register. Finally, set the Status bit in the MDIO Control
	221	* register to start a MDIO write transaction.
	222	*/
9a23c496 MS	223	u32 ctrl_reg = in_be32(&regs->mdioctrl);
9a23c496 MS	224	out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
d722e864	225	((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) \| registernum));
9a23c496 MS	226	out_be32(&regs->mdiowr, data);
9a23c496 MS	227	out_be32(&regs->mdioctrl, ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK);
d722e864	228
9a23c496	229	if (mdio_wait(regs))
d722e864 MS	230	return 1;
	231
	232	return 0;
	233	}
d722e864	234
f03ec010	235	static void emaclite_stop(struct udevice *dev)
89c53891	236	{
f03ec010	237	debug("eth_stop\n");
89c53891 MS	238	}
89c53891 MS	239
d722e864 MS	240	/* Use MII register 1 (MII status register) to detect PHY */
	241	#define PHY_DETECT_REG 1
	242
	243	/* Mask used to verify certain PHY features (or register contents)
	244	* in the register above:
	245	* 0x1000: 10Mbps full duplex support
	246	* 0x0800: 10Mbps half duplex support
	247	* 0x0008: Auto-negotiation support
	248	*/
	249	#define PHY_DETECT_MASK 0x1808
	250
d538ee1b	251	static int setup_phy(struct udevice *dev)
d722e864 MS	252	{
	253	int i;
	254	u16 phyreg;
d538ee1b	255	struct xemaclite *emaclite = dev_get_priv(dev);
d722e864 MS	256	struct phy_device *phydev;
	257
	258	u32 supported = SUPPORTED_10baseT_Half \|
	259	SUPPORTED_10baseT_Full \|
	260	SUPPORTED_100baseT_Half \|
	261	SUPPORTED_100baseT_Full;
	262
	263	if (emaclite->phyaddr != -1) {
9a23c496	264	phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
d722e864 MS	265	if ((phyreg != 0xFFFF) &&
	266	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	267	/* Found a valid PHY address */
	268	debug("Default phy address %d is valid\n",
	269	emaclite->phyaddr);
	270	} else {
	271	debug("PHY address is not setup correctly %d\n",
	272	emaclite->phyaddr);
	273	emaclite->phyaddr = -1;
	274	}
	275	}
	276
	277	if (emaclite->phyaddr == -1) {
	278	/* detect the PHY address */
	279	for (i = 31; i >= 0; i--) {
9a23c496	280	phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
d722e864 MS	281	if ((phyreg != 0xFFFF) &&
	282	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	283	/* Found a valid PHY address */
	284	emaclite->phyaddr = i;
	285	debug("emaclite: Found valid phy address, %d\n",
	286	i);
	287	break;
	288	}
	289	}
	290	}
	291
	292	/* interface - look at tsec */
	293	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
	294	PHY_INTERFACE_MODE_MII);
	295	/*
	296	* Phy can support 1000baseT but device NOT that's why phydev->supported
	297	* must be setup for 1000baseT. phydev->advertising setups what speeds
	298	* will be used for autonegotiation where 1000baseT must be disabled.
	299	*/
	300	phydev->supported = supported \| SUPPORTED_1000baseT_Half \|
	301	SUPPORTED_1000baseT_Full;
	302	phydev->advertising = supported;
	303	emaclite->phydev = phydev;
	304	phy_config(phydev);
	305	phy_startup(phydev);
	306
	307	if (!phydev->link) {
	308	printf("%s: No link.\n", phydev->dev->name);
	309	return 0;
	310	}
	311
	312	/* Do not setup anything */
	313	return 1;
	314	}
d722e864	315
f03ec010	316	static int emaclite_start(struct udevice *dev)
89c53891	317	{
d538ee1b MS	318	struct xemaclite *emaclite = dev_get_priv(dev);
d538ee1b MS	319	struct eth_pdata *pdata = dev_get_platdata(dev);
9a23c496 MS	320	struct emaclite_regs *regs = emaclite->regs;
9a23c496 MS	321
5ac83801	322	debug("EmacLite Initialization Started\n");
89c53891 MS	323
	324	/*
	325	* TX - TX_PING & TX_PONG initialization
	326	*/
	327	/* Restart PING TX */
a0b2bfb0	328	out_be32(&regs->tx_ping_tsr, 0);
89c53891	329	/* Copy MAC address */
d538ee1b	330	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
a0b2bfb0	331	ENET_ADDR_LENGTH);
89c53891	332	/* Set the length */
a0b2bfb0	333	out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
89c53891	334	/* Update the MAC address in the EMAC Lite */
a0b2bfb0	335	out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
89c53891	336	/* Wait for EMAC Lite to finish with the MAC address update */
a0b2bfb0	337	while ((in_be32 (&regs->tx_ping_tsr) &
8d95ddbb MS	338	XEL_TSR_PROG_MAC_ADDR) != 0)
8d95ddbb MS	339	;
89c53891	340
947324b9 MS	341	if (emaclite->txpp) {
947324b9 MS	342	/* The same operation with PONG TX */
a0b2bfb0	343	out_be32(&regs->tx_pong_tsr, 0);
d538ee1b	344	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
a0b2bfb0 MS	345	ENET_ADDR_LENGTH);
	346	out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
	347	out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
	348	while ((in_be32(&regs->tx_pong_tsr) &
	349	XEL_TSR_PROG_MAC_ADDR) != 0)
947324b9 MS	350	;
947324b9 MS	351	}
89c53891 MS	352
	353	/*
	354	* RX - RX_PING & RX_PONG initialization
	355	*/
	356	/* Write out the value to flush the RX buffer */
3af70909	357	out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
947324b9 MS	358
947324b9 MS	359	if (emaclite->rxpp)
3af70909	360	out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
89c53891	361
9a23c496 MS	362	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
9a23c496 MS	363	if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
d722e864 MS	364	if (!setup_phy(dev))
d722e864 MS	365	return -1;
d538ee1b	366
5ac83801	367	debug("EmacLite Initialization complete\n");
89c53891 MS	368	return 0;
	369	}
	370
26c7945a	371	static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
89c53891	372	{
26c7945a MS	373	u32 tmp;
26c7945a MS	374	struct emaclite_regs *regs = emaclite->regs;
773cfa8d	375
89c53891 MS	376	/*
	377	* Read the other buffer register
	378	* and determine if the other buffer is available
	379	*/
26c7945a MS	380	tmp = ~in_be32(&regs->tx_ping_tsr);
	381	if (emaclite->txpp)
	382	tmp \|= ~in_be32(&regs->tx_pong_tsr);
89c53891	383
26c7945a	384	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
89c53891 MS	385	}
89c53891 MS	386
d538ee1b	387	static int emaclite_send(struct udevice dev, void ptr, int len)
042272a6 MS	388	{
042272a6 MS	389	u32 reg;
d538ee1b	390	struct xemaclite *emaclite = dev_get_priv(dev);
5a4baa33	391	struct emaclite_regs *regs = emaclite->regs;
89c53891	392
042272a6	393	u32 maxtry = 1000;
89c53891	394
80439252 MS	395	if (len > PKTSIZE)
80439252 MS	396	len = PKTSIZE;
89c53891	397
26c7945a	398	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
5ac83801	399	udelay(10);
89c53891 MS	400	maxtry--;
	401	}
	402
	403	if (!maxtry) {
5ac83801	404	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	405	/* Restart PING TX */
5a4baa33	406	out_be32(&regs->tx_ping_tsr, 0);
947324b9	407	if (emaclite->txpp) {
5a4baa33	408	out_be32(&regs->tx_pong_tsr, 0);
947324b9	409	}
95efa79d	410	return -1;
89c53891 MS	411	}
89c53891 MS	412
89c53891	413	/* Determine if the expected buffer address is empty */
00702518	414	reg = in_be32(&regs->tx_ping_tsr);
15c239c8	415	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
00702518	416	debug("Send packet from tx_ping buffer\n");
89c53891	417	/* Write the frame to the buffer */
00702518 MS	418	xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
	419	out_be32(&regs->tx_ping_tplr, len &
	420	(XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO));
	421	reg = in_be32(&regs->tx_ping_tsr);
89c53891	422	reg \|= XEL_TSR_XMIT_BUSY_MASK;
00702518	423	out_be32(&regs->tx_ping_tsr, reg);
95efa79d	424	return 0;
89c53891	425	}
947324b9 MS	426
947324b9 MS	427	if (emaclite->txpp) {
947324b9	428	/* Determine if the expected buffer address is empty */
00702518	429	reg = in_be32(&regs->tx_pong_tsr);
15c239c8	430	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
00702518	431	debug("Send packet from tx_pong buffer\n");
947324b9	432	/* Write the frame to the buffer */
00702518 MS	433	xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
	434	out_be32(&regs->tx_pong_tplr, len &
	435	(XEL_TPLR_LENGTH_MASK_HI \|
	436	XEL_TPLR_LENGTH_MASK_LO));
	437	reg = in_be32(&regs->tx_pong_tsr);
947324b9	438	reg \|= XEL_TSR_XMIT_BUSY_MASK;
00702518	439	out_be32(&regs->tx_pong_tsr, reg);
947324b9	440	return 0;
89c53891	441	}
89c53891	442	}
947324b9	443
5ac83801	444	puts("Error while sending frame\n");
95efa79d	445	return -1;
89c53891 MS	446	}
89c53891 MS	447
d538ee1b	448	static int emaclite_recv(struct udevice dev, int flags, uchar *packetp)
89c53891	449	{
4d2749be MS	450	u32 length, first_read, reg, attempt = 0;
4d2749be MS	451	void addr, ack;
773cfa8d	452	struct xemaclite *emaclite = dev->priv;
4d2749be MS	453	struct emaclite_regs *regs = emaclite->regs;
	454	struct ethernet_hdr *eth;
	455	struct ip_udp_hdr *ip;
	456
	457	try_again:
	458	if (!emaclite->use_rx_pong_buffer_next) {
	459	reg = in_be32(&regs->rx_ping_rsr);
	460	debug("Testing data at rx_ping\n");
	461	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
	462	debug("Data found in rx_ping buffer\n");
	463	addr = &regs->rx_ping;
	464	ack = &regs->rx_ping_rsr;
	465	} else {
	466	debug("Data not found in rx_ping buffer\n");
	467	/* Pong buffer is not available - return immediately */
	468	if (!emaclite->rxpp)
	469	return -1;
	470
	471	/* Try pong buffer if this is first attempt */
	472	if (attempt++)
	473	return -1;
	474	emaclite->use_rx_pong_buffer_next =
	475	!emaclite->use_rx_pong_buffer_next;
	476	goto try_again;
	477	}
89c53891	478	} else {
4d2749be MS	479	reg = in_be32(&regs->rx_pong_rsr);
	480	debug("Testing data at rx_pong\n");
	481	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
	482	debug("Data found in rx_pong buffer\n");
	483	addr = &regs->rx_pong;
	484	ack = &regs->rx_pong_rsr;
947324b9	485	} else {
4d2749be MS	486	debug("Data not found in rx_pong buffer\n");
	487	/* Try ping buffer if this is first attempt */
	488	if (attempt++)
	489	return -1;
	490	emaclite->use_rx_pong_buffer_next =
	491	!emaclite->use_rx_pong_buffer_next;
	492	goto try_again;
89c53891	493	}
89c53891	494	}
4d2749be MS	495
	496	/* Read all bytes for ARP packet with 32bit alignment - 48bytes */
	497	first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
	498	xemaclite_alignedread(addr, etherrxbuff, first_read);
	499
	500	/* Detect real packet size */
	501	eth = (struct ethernet_hdr *)etherrxbuff;
	502	switch (ntohs(eth->et_protlen)) {
	503	case PROT_ARP:
	504	length = first_read;
	505	debug("ARP Packet %x\n", length);
	506	break;
	507	case PROT_IP:
	508	ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
	509	length = ntohs(ip->ip_len);
	510	length += ETHER_HDR_SIZE + ETH_FCS_LEN;
	511	debug("IP Packet %x\n", length);
	512	break;
	513	default:
	514	debug("Other Packet\n");
	515	length = PKTSIZE;
	516	break;
89c53891 MS	517	}
89c53891 MS	518
4d2749be MS	519	/* Read the rest of the packet which is longer then first read */
	520	if (length != first_read)
	521	xemaclite_alignedread(addr + first_read,
	522	etherrxbuff + first_read,
	523	length - first_read);
89c53891 MS	524
89c53891 MS	525	/* Acknowledge the frame */
4d2749be	526	reg = in_be32(ack);
89c53891	527	reg &= ~XEL_RSR_RECV_DONE_MASK;
4d2749be	528	out_be32(ack, reg);
89c53891	529
4d2749be	530	debug("Packet receive from 0x%p, length %dB\n", addr, length);
f412b6ab MS	531	*packetp = etherrxbuff;
f412b6ab MS	532	return length;
89c53891	533	}
042272a6	534
d538ee1b MS	535	static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
d538ee1b MS	536	int devad, int reg)
d722e864 MS	537	{
d722e864 MS	538	u32 ret;
d538ee1b	539	u16 val = 0;
d722e864	540
d538ee1b MS	541	ret = phyread(bus->priv, addr, reg, &val);
	542	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
	543	return val;
d722e864 MS	544	}
d722e864 MS	545
d538ee1b MS	546	static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
d538ee1b MS	547	int reg, u16 value)
d722e864	548	{
d538ee1b MS	549	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
d538ee1b MS	550	return phywrite(bus->priv, addr, reg, value);
d722e864	551	}
d722e864	552
d538ee1b	553	static int emaclite_probe(struct udevice *dev)
042272a6	554	{
d538ee1b MS	555	struct xemaclite *emaclite = dev_get_priv(dev);
d538ee1b MS	556	int ret;
042272a6	557
d538ee1b MS	558	emaclite->bus = mdio_alloc();
	559	emaclite->bus->read = emaclite_miiphy_read;
	560	emaclite->bus->write = emaclite_miiphy_write;
	561	emaclite->bus->priv = emaclite;
	562	strcpy(emaclite->bus->name, "emaclite");
042272a6	563
d538ee1b MS	564	ret = mdio_register(emaclite->bus);
	565	if (ret)
	566	return ret;
	567
	568	return 0;
	569	}
773cfa8d	570
d538ee1b MS	571	static int emaclite_remove(struct udevice *dev)
	572	{
	573	struct xemaclite *emaclite = dev_get_priv(dev);
	574
	575	free(emaclite->phydev);
	576	mdio_unregister(emaclite->bus);
	577	mdio_free(emaclite->bus);
773cfa8d	578
d538ee1b MS	579	return 0;
d538ee1b MS	580	}
947324b9	581
d538ee1b	582	static const struct eth_ops emaclite_ops = {
f03ec010	583	.start = emaclite_start,
d538ee1b MS	584	.send = emaclite_send,
d538ee1b MS	585	.recv = emaclite_recv,
f03ec010	586	.stop = emaclite_stop,
d538ee1b MS	587	};
	588
	589	static int emaclite_ofdata_to_platdata(struct udevice *dev)
	590	{
	591	struct eth_pdata *pdata = dev_get_platdata(dev);
	592	struct xemaclite *emaclite = dev_get_priv(dev);
	593	int offset = 0;
042272a6	594
d538ee1b MS	595	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
d538ee1b MS	596	emaclite->regs = (struct emaclite_regs *)pdata->iobase;
042272a6	597
d722e864	598	emaclite->phyaddr = -1;
d722e864	599
d538ee1b MS	600	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
	601	"phy-handle");
	602	if (offset > 0)
	603	emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
	604	"reg", -1);
042272a6	605
d538ee1b MS	606	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	607	"xlnx,tx-ping-pong", 0);
	608	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	609	"xlnx,rx-ping-pong", 0);
d722e864	610
d538ee1b MS	611	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
d538ee1b MS	612	emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
d722e864	613
d538ee1b	614	return 0;
042272a6	615	}
d538ee1b MS	616
	617	static const struct udevice_id emaclite_ids[] = {
	618	{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
	619	{ }
	620	};
	621
	622	U_BOOT_DRIVER(emaclite) = {
	623	.name = "emaclite",
	624	.id = UCLASS_ETH,
	625	.of_match = emaclite_ids,
	626	.ofdata_to_platdata = emaclite_ofdata_to_platdata,
	627	.probe = emaclite_probe,
	628	.remove = emaclite_remove,
	629	.ops = &emaclite_ops,
	630	.priv_auto_alloc_size = sizeof(struct xemaclite),
	631	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	632	};