]>
Commit | Line | Data |
---|---|---|
185f7d9a MS |
1 | /* |
2 | * (C) Copyright 2011 Michal Simek | |
3 | * | |
4 | * Michal SIMEK <monstr@monstr.eu> | |
5 | * | |
6 | * Based on Xilinx gmac driver: | |
7 | * (C) Copyright 2011 Xilinx | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
185f7d9a MS |
10 | */ |
11 | ||
a765bdd1 | 12 | #include <clk.h> |
185f7d9a | 13 | #include <common.h> |
6889ca71 | 14 | #include <dm.h> |
185f7d9a | 15 | #include <net.h> |
2fd2489b | 16 | #include <netdev.h> |
185f7d9a | 17 | #include <config.h> |
b8de29fe | 18 | #include <console.h> |
185f7d9a MS |
19 | #include <malloc.h> |
20 | #include <asm/io.h> | |
21 | #include <phy.h> | |
22 | #include <miiphy.h> | |
e7138b34 | 23 | #include <wait_bit.h> |
185f7d9a | 24 | #include <watchdog.h> |
96f4f149 | 25 | #include <asm/system.h> |
01fbf310 | 26 | #include <asm/arch/hardware.h> |
80243528 | 27 | #include <asm/arch/sys_proto.h> |
5d97dff0 | 28 | #include <linux/errno.h> |
185f7d9a | 29 | |
6889ca71 MS |
30 | DECLARE_GLOBAL_DATA_PTR; |
31 | ||
185f7d9a MS |
32 | /* Bit/mask specification */ |
33 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ | |
34 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ | |
35 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ | |
36 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ | |
37 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ | |
38 | ||
39 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ | |
40 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ | |
41 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ | |
42 | ||
43 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ | |
44 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ | |
45 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ | |
46 | ||
47 | /* Wrap bit, last descriptor */ | |
48 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 | |
49 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ | |
23a598f7 | 50 | #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ |
185f7d9a | 51 | |
185f7d9a MS |
52 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
53 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ | |
54 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ | |
55 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ | |
56 | ||
27183d7c SDPP |
57 | #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ |
58 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ | |
59 | #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ | |
60 | #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ | |
4eaf8f54 | 61 | #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ |
27183d7c | 62 | #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ |
f17ea71d | 63 | #ifdef CONFIG_ARM64 |
27183d7c | 64 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ |
f17ea71d | 65 | #else |
27183d7c | 66 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ |
f17ea71d | 67 | #endif |
185f7d9a | 68 | |
8a584c8a SDPP |
69 | #ifdef CONFIG_ARM64 |
70 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ | |
71 | #else | |
72 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ | |
73 | #endif | |
74 | ||
75 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ | |
76 | ZYNQ_GEM_NWCFG_FDEN | \ | |
185f7d9a MS |
77 | ZYNQ_GEM_NWCFG_FSREM | \ |
78 | ZYNQ_GEM_NWCFG_MDCCLKDIV) | |
79 | ||
80 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ | |
81 | ||
82 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ | |
83 | /* Use full configured addressable space (8 Kb) */ | |
84 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 | |
85 | /* Use full configured addressable space (4 Kb) */ | |
86 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 | |
87 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ | |
88 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 | |
89 | ||
90 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ | |
91 | ZYNQ_GEM_DMACR_RXSIZE | \ | |
92 | ZYNQ_GEM_DMACR_TXSIZE | \ | |
93 | ZYNQ_GEM_DMACR_RXBUF) | |
94 | ||
e4d2318a MS |
95 | #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ |
96 | ||
845ee5f6 SDPP |
97 | #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 |
98 | ||
f97d7e8b MS |
99 | /* Use MII register 1 (MII status register) to detect PHY */ |
100 | #define PHY_DETECT_REG 1 | |
101 | ||
102 | /* Mask used to verify certain PHY features (or register contents) | |
103 | * in the register above: | |
104 | * 0x1000: 10Mbps full duplex support | |
105 | * 0x0800: 10Mbps half duplex support | |
106 | * 0x0008: Auto-negotiation support | |
107 | */ | |
108 | #define PHY_DETECT_MASK 0x1808 | |
109 | ||
a5144237 ST |
110 | /* TX BD status masks */ |
111 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff | |
112 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 | |
113 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 | |
114 | ||
97598fcf SB |
115 | /* Clock frequencies for different speeds */ |
116 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL | |
117 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL | |
118 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL | |
119 | ||
185f7d9a MS |
120 | /* Device registers */ |
121 | struct zynq_gem_regs { | |
97a51a03 MS |
122 | u32 nwctrl; /* 0x0 - Network Control reg */ |
123 | u32 nwcfg; /* 0x4 - Network Config reg */ | |
124 | u32 nwsr; /* 0x8 - Network Status reg */ | |
185f7d9a | 125 | u32 reserved1; |
97a51a03 MS |
126 | u32 dmacr; /* 0x10 - DMA Control reg */ |
127 | u32 txsr; /* 0x14 - TX Status reg */ | |
128 | u32 rxqbase; /* 0x18 - RX Q Base address reg */ | |
129 | u32 txqbase; /* 0x1c - TX Q Base address reg */ | |
130 | u32 rxsr; /* 0x20 - RX Status reg */ | |
185f7d9a | 131 | u32 reserved2[2]; |
97a51a03 | 132 | u32 idr; /* 0x2c - Interrupt Disable reg */ |
185f7d9a | 133 | u32 reserved3; |
97a51a03 | 134 | u32 phymntnc; /* 0x34 - Phy Maintaince reg */ |
185f7d9a | 135 | u32 reserved4[18]; |
97a51a03 MS |
136 | u32 hashl; /* 0x80 - Hash Low address reg */ |
137 | u32 hashh; /* 0x84 - Hash High address reg */ | |
185f7d9a MS |
138 | #define LADDR_LOW 0 |
139 | #define LADDR_HIGH 1 | |
97a51a03 MS |
140 | u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ |
141 | u32 match[4]; /* 0xa8 - Type ID1 Match reg */ | |
185f7d9a | 142 | u32 reserved6[18]; |
0ebf4041 MS |
143 | #define STAT_SIZE 44 |
144 | u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ | |
845ee5f6 SDPP |
145 | u32 reserved9[20]; |
146 | u32 pcscntrl; | |
147 | u32 reserved7[143]; | |
603ff008 EI |
148 | u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ |
149 | u32 reserved8[15]; | |
150 | u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ | |
185f7d9a MS |
151 | }; |
152 | ||
153 | /* BD descriptors */ | |
154 | struct emac_bd { | |
155 | u32 addr; /* Next descriptor pointer */ | |
156 | u32 status; | |
157 | }; | |
158 | ||
eda9d307 | 159 | #define RX_BUF 32 |
a5144237 ST |
160 | /* Page table entries are set to 1MB, or multiples of 1MB |
161 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
162 | */ | |
163 | #define BD_SPACE 0x100000 | |
164 | /* BD separation space */ | |
ff475878 | 165 | #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) |
185f7d9a | 166 | |
603ff008 EI |
167 | /* Setup the first free TX descriptor */ |
168 | #define TX_FREE_DESC 2 | |
169 | ||
185f7d9a MS |
170 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ |
171 | struct zynq_gem_priv { | |
a5144237 ST |
172 | struct emac_bd *tx_bd; |
173 | struct emac_bd *rx_bd; | |
174 | char *rxbuffers; | |
185f7d9a MS |
175 | u32 rxbd_current; |
176 | u32 rx_first_buf; | |
177 | int phyaddr; | |
05868759 | 178 | int init; |
f2fc2768 | 179 | struct zynq_gem_regs *iobase; |
16ce6de8 | 180 | phy_interface_t interface; |
185f7d9a | 181 | struct phy_device *phydev; |
20671a98 | 182 | int phy_of_handle; |
185f7d9a | 183 | struct mii_dev *bus; |
a765bdd1 | 184 | struct clk clk; |
dd12a27c | 185 | bool int_pcs; |
185f7d9a MS |
186 | }; |
187 | ||
f2fc2768 MS |
188 | static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
189 | u32 op, u16 *data) | |
185f7d9a MS |
190 | { |
191 | u32 mgtcr; | |
f2fc2768 | 192 | struct zynq_gem_regs *regs = priv->iobase; |
b908fcad | 193 | int err; |
185f7d9a | 194 | |
48263504 ÁFR |
195 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
196 | true, 20000, false); | |
b908fcad MS |
197 | if (err) |
198 | return err; | |
185f7d9a MS |
199 | |
200 | /* Construct mgtcr mask for the operation */ | |
201 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | | |
202 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | | |
203 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; | |
204 | ||
205 | /* Write mgtcr and wait for completion */ | |
206 | writel(mgtcr, ®s->phymntnc); | |
207 | ||
48263504 ÁFR |
208 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
209 | true, 20000, false); | |
b908fcad MS |
210 | if (err) |
211 | return err; | |
185f7d9a MS |
212 | |
213 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) | |
214 | *data = readl(®s->phymntnc); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
f2fc2768 MS |
219 | static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
220 | u32 regnum, u16 *val) | |
185f7d9a | 221 | { |
198e9a4f MS |
222 | u32 ret; |
223 | ||
f2fc2768 MS |
224 | ret = phy_setup_op(priv, phy_addr, regnum, |
225 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); | |
198e9a4f MS |
226 | |
227 | if (!ret) | |
228 | debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, | |
229 | phy_addr, regnum, *val); | |
230 | ||
231 | return ret; | |
185f7d9a MS |
232 | } |
233 | ||
f2fc2768 MS |
234 | static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
235 | u32 regnum, u16 data) | |
185f7d9a | 236 | { |
198e9a4f MS |
237 | debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
238 | regnum, data); | |
239 | ||
f2fc2768 MS |
240 | return phy_setup_op(priv, phy_addr, regnum, |
241 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); | |
185f7d9a MS |
242 | } |
243 | ||
6889ca71 | 244 | static int phy_detection(struct udevice *dev) |
f97d7e8b MS |
245 | { |
246 | int i; | |
247 | u16 phyreg; | |
248 | struct zynq_gem_priv *priv = dev->priv; | |
249 | ||
250 | if (priv->phyaddr != -1) { | |
f2fc2768 | 251 | phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); |
f97d7e8b MS |
252 | if ((phyreg != 0xFFFF) && |
253 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
254 | /* Found a valid PHY address */ | |
255 | debug("Default phy address %d is valid\n", | |
256 | priv->phyaddr); | |
b904725a | 257 | return 0; |
f97d7e8b MS |
258 | } else { |
259 | debug("PHY address is not setup correctly %d\n", | |
260 | priv->phyaddr); | |
261 | priv->phyaddr = -1; | |
262 | } | |
263 | } | |
264 | ||
265 | debug("detecting phy address\n"); | |
266 | if (priv->phyaddr == -1) { | |
267 | /* detect the PHY address */ | |
268 | for (i = 31; i >= 0; i--) { | |
f2fc2768 | 269 | phyread(priv, i, PHY_DETECT_REG, &phyreg); |
f97d7e8b MS |
270 | if ((phyreg != 0xFFFF) && |
271 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
272 | /* Found a valid PHY address */ | |
273 | priv->phyaddr = i; | |
274 | debug("Found valid phy address, %d\n", i); | |
b904725a | 275 | return 0; |
f97d7e8b MS |
276 | } |
277 | } | |
278 | } | |
279 | printf("PHY is not detected\n"); | |
b904725a | 280 | return -1; |
f97d7e8b MS |
281 | } |
282 | ||
6889ca71 | 283 | static int zynq_gem_setup_mac(struct udevice *dev) |
185f7d9a MS |
284 | { |
285 | u32 i, macaddrlow, macaddrhigh; | |
6889ca71 MS |
286 | struct eth_pdata *pdata = dev_get_platdata(dev); |
287 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
288 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a MS |
289 | |
290 | /* Set the MAC bits [31:0] in BOT */ | |
6889ca71 MS |
291 | macaddrlow = pdata->enetaddr[0]; |
292 | macaddrlow |= pdata->enetaddr[1] << 8; | |
293 | macaddrlow |= pdata->enetaddr[2] << 16; | |
294 | macaddrlow |= pdata->enetaddr[3] << 24; | |
185f7d9a MS |
295 | |
296 | /* Set MAC bits [47:32] in TOP */ | |
6889ca71 MS |
297 | macaddrhigh = pdata->enetaddr[4]; |
298 | macaddrhigh |= pdata->enetaddr[5] << 8; | |
185f7d9a MS |
299 | |
300 | for (i = 0; i < 4; i++) { | |
301 | writel(0, ®s->laddr[i][LADDR_LOW]); | |
302 | writel(0, ®s->laddr[i][LADDR_HIGH]); | |
303 | /* Do not use MATCHx register */ | |
304 | writel(0, ®s->match[i]); | |
305 | } | |
306 | ||
307 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); | |
308 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
6889ca71 | 313 | static int zynq_phy_init(struct udevice *dev) |
185f7d9a | 314 | { |
b904725a | 315 | int ret; |
6889ca71 MS |
316 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
317 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a MS |
318 | const u32 supported = SUPPORTED_10baseT_Half | |
319 | SUPPORTED_10baseT_Full | | |
320 | SUPPORTED_100baseT_Half | | |
321 | SUPPORTED_100baseT_Full | | |
322 | SUPPORTED_1000baseT_Half | | |
323 | SUPPORTED_1000baseT_Full; | |
324 | ||
c8e29271 MS |
325 | /* Enable only MDIO bus */ |
326 | writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); | |
327 | ||
a06c341f SDPP |
328 | if (priv->interface != PHY_INTERFACE_MODE_SGMII) { |
329 | ret = phy_detection(dev); | |
330 | if (ret) { | |
331 | printf("GEM PHY init failed\n"); | |
332 | return ret; | |
333 | } | |
68cc3bd8 MS |
334 | } |
335 | ||
336 | priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, | |
337 | priv->interface); | |
90c6f2e2 MS |
338 | if (!priv->phydev) |
339 | return -ENODEV; | |
68cc3bd8 | 340 | |
2c2ab8d6 | 341 | priv->phydev->supported &= supported | ADVERTISED_Pause | |
68cc3bd8 MS |
342 | ADVERTISED_Asym_Pause; |
343 | priv->phydev->advertising = priv->phydev->supported; | |
68cc3bd8 | 344 | |
20671a98 | 345 | if (priv->phy_of_handle > 0) |
e160f7d4 | 346 | dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); |
20671a98 | 347 | |
7a673f0b | 348 | return phy_config(priv->phydev); |
68cc3bd8 MS |
349 | } |
350 | ||
6889ca71 | 351 | static int zynq_gem_init(struct udevice *dev) |
68cc3bd8 | 352 | { |
a06c341f | 353 | u32 i, nwconfig; |
55259e7c | 354 | int ret; |
68cc3bd8 | 355 | unsigned long clk_rate = 0; |
6889ca71 MS |
356 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
357 | struct zynq_gem_regs *regs = priv->iobase; | |
68cc3bd8 MS |
358 | struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
359 | struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; | |
360 | ||
05868759 MS |
361 | if (!priv->init) { |
362 | /* Disable all interrupts */ | |
363 | writel(0xFFFFFFFF, ®s->idr); | |
364 | ||
365 | /* Disable the receiver & transmitter */ | |
366 | writel(0, ®s->nwctrl); | |
367 | writel(0, ®s->txsr); | |
368 | writel(0, ®s->rxsr); | |
369 | writel(0, ®s->phymntnc); | |
370 | ||
371 | /* Clear the Hash registers for the mac address | |
372 | * pointed by AddressPtr | |
373 | */ | |
374 | writel(0x0, ®s->hashl); | |
375 | /* Write bits [63:32] in TOP */ | |
376 | writel(0x0, ®s->hashh); | |
377 | ||
378 | /* Clear all counters */ | |
0ebf4041 | 379 | for (i = 0; i < STAT_SIZE; i++) |
05868759 MS |
380 | readl(®s->stat[i]); |
381 | ||
382 | /* Setup RxBD space */ | |
a5144237 | 383 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
05868759 MS |
384 | |
385 | for (i = 0; i < RX_BUF; i++) { | |
386 | priv->rx_bd[i].status = 0xF0000000; | |
387 | priv->rx_bd[i].addr = | |
5b47d407 | 388 | ((ulong)(priv->rxbuffers) + |
185f7d9a | 389 | (i * PKTSIZE_ALIGN)); |
05868759 MS |
390 | } |
391 | /* WRAP bit to last BD */ | |
392 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; | |
393 | /* Write RxBDs to IP */ | |
5b47d407 | 394 | writel((ulong)priv->rx_bd, ®s->rxqbase); |
185f7d9a | 395 | |
05868759 MS |
396 | /* Setup for DMA Configuration register */ |
397 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); | |
185f7d9a | 398 | |
05868759 | 399 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
80243528 | 400 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
185f7d9a | 401 | |
603ff008 EI |
402 | /* Disable the second priority queue */ |
403 | dummy_tx_bd->addr = 0; | |
404 | dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | | |
405 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
406 | ZYNQ_GEM_TXBUF_USED_MASK; | |
407 | ||
408 | dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | | |
409 | ZYNQ_GEM_RXBUF_NEW_MASK; | |
410 | dummy_rx_bd->status = 0; | |
603ff008 EI |
411 | |
412 | writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); | |
413 | writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); | |
414 | ||
05868759 MS |
415 | priv->init++; |
416 | } | |
417 | ||
55259e7c MS |
418 | ret = phy_startup(priv->phydev); |
419 | if (ret) | |
420 | return ret; | |
185f7d9a | 421 | |
64a7ead6 MS |
422 | if (!priv->phydev->link) { |
423 | printf("%s: No link.\n", priv->phydev->dev->name); | |
4ed4aa20 MS |
424 | return -1; |
425 | } | |
426 | ||
a06c341f SDPP |
427 | nwconfig = ZYNQ_GEM_NWCFG_INIT; |
428 | ||
dd12a27c SDPP |
429 | /* |
430 | * Set SGMII enable PCS selection only if internal PCS/PMA | |
431 | * core is used and interface is SGMII. | |
432 | */ | |
433 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && | |
434 | priv->int_pcs) { | |
a06c341f SDPP |
435 | nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | |
436 | ZYNQ_GEM_NWCFG_PCS_SEL; | |
845ee5f6 SDPP |
437 | #ifdef CONFIG_ARM64 |
438 | writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, | |
439 | ®s->pcscntrl); | |
440 | #endif | |
441 | } | |
a06c341f | 442 | |
64a7ead6 | 443 | switch (priv->phydev->speed) { |
80243528 | 444 | case SPEED_1000: |
a06c341f | 445 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, |
80243528 | 446 | ®s->nwcfg); |
97598fcf | 447 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
80243528 MS |
448 | break; |
449 | case SPEED_100: | |
a06c341f | 450 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, |
242b1547 | 451 | ®s->nwcfg); |
97598fcf | 452 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
80243528 MS |
453 | break; |
454 | case SPEED_10: | |
97598fcf | 455 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
80243528 MS |
456 | break; |
457 | } | |
01fbf310 | 458 | |
eff55c55 SH |
459 | ret = clk_set_rate(&priv->clk, clk_rate); |
460 | if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { | |
461 | dev_err(dev, "failed to set tx clock rate\n"); | |
462 | return ret; | |
463 | } | |
464 | ||
465 | ret = clk_enable(&priv->clk); | |
466 | if (ret && ret != -ENOSYS) { | |
467 | dev_err(dev, "failed to enable tx clock\n"); | |
468 | return ret; | |
469 | } | |
80243528 MS |
470 | |
471 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | | |
472 | ZYNQ_GEM_NWCTRL_TXEN_MASK); | |
473 | ||
185f7d9a MS |
474 | return 0; |
475 | } | |
476 | ||
6889ca71 | 477 | static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
185f7d9a | 478 | { |
a5144237 | 479 | u32 addr, size; |
6889ca71 MS |
480 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
481 | struct zynq_gem_regs *regs = priv->iobase; | |
23a598f7 | 482 | struct emac_bd *current_bd = &priv->tx_bd[1]; |
185f7d9a | 483 | |
185f7d9a | 484 | /* Setup Tx BD */ |
a5144237 ST |
485 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
486 | ||
5b47d407 | 487 | priv->tx_bd->addr = (ulong)ptr; |
a5144237 | 488 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | |
23a598f7 MS |
489 | ZYNQ_GEM_TXBUF_LAST_MASK; |
490 | /* Dummy descriptor to mark it as the last in descriptor chain */ | |
491 | current_bd->addr = 0x0; | |
492 | current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | | |
493 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
494 | ZYNQ_GEM_TXBUF_USED_MASK; | |
185f7d9a | 495 | |
45c07741 MS |
496 | /* setup BD */ |
497 | writel((ulong)priv->tx_bd, ®s->txqbase); | |
498 | ||
5b47d407 | 499 | addr = (ulong) ptr; |
a5144237 ST |
500 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
501 | size = roundup(len, ARCH_DMA_MINALIGN); | |
502 | flush_dcache_range(addr, addr + size); | |
96f4f149 | 503 | |
5b47d407 | 504 | addr = (ulong)priv->rxbuffers; |
96f4f149 SDPP |
505 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
506 | size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); | |
507 | flush_dcache_range(addr, addr + size); | |
a5144237 | 508 | barrier(); |
185f7d9a MS |
509 | |
510 | /* Start transmit */ | |
511 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); | |
512 | ||
a5144237 | 513 | /* Read TX BD status */ |
a5144237 ST |
514 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) |
515 | printf("TX buffers exhausted in mid frame\n"); | |
185f7d9a | 516 | |
48263504 ÁFR |
517 | return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, |
518 | true, 20000, true); | |
185f7d9a MS |
519 | } |
520 | ||
521 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ | |
6889ca71 | 522 | static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
185f7d9a MS |
523 | { |
524 | int frame_len; | |
9d9211ac | 525 | u32 addr; |
6889ca71 | 526 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
185f7d9a | 527 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
185f7d9a MS |
528 | |
529 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) | |
9d9211ac | 530 | return -1; |
185f7d9a MS |
531 | |
532 | if (!(current_bd->status & | |
533 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { | |
534 | printf("GEM: SOF or EOF not set for last buffer received!\n"); | |
9d9211ac | 535 | return -1; |
185f7d9a MS |
536 | } |
537 | ||
538 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; | |
9d9211ac MS |
539 | if (!frame_len) { |
540 | printf("%s: Zero size packet?\n", __func__); | |
541 | return -1; | |
542 | } | |
a5144237 | 543 | |
9d9211ac MS |
544 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
545 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
546 | *packetp = (uchar *)(uintptr_t)addr; | |
185f7d9a | 547 | |
9d9211ac MS |
548 | return frame_len; |
549 | } | |
185f7d9a | 550 | |
9d9211ac MS |
551 | static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) |
552 | { | |
553 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
554 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; | |
555 | struct emac_bd *first_bd; | |
556 | ||
557 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { | |
558 | priv->rx_first_buf = priv->rxbd_current; | |
559 | } else { | |
560 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
561 | current_bd->status = 0xF0000000; /* FIXME */ | |
562 | } | |
185f7d9a | 563 | |
9d9211ac MS |
564 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { |
565 | first_bd = &priv->rx_bd[priv->rx_first_buf]; | |
566 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
567 | first_bd->status = 0xF0000000; | |
185f7d9a MS |
568 | } |
569 | ||
9d9211ac MS |
570 | if ((++priv->rxbd_current) >= RX_BUF) |
571 | priv->rxbd_current = 0; | |
572 | ||
da872d7c | 573 | return 0; |
185f7d9a MS |
574 | } |
575 | ||
6889ca71 | 576 | static void zynq_gem_halt(struct udevice *dev) |
185f7d9a | 577 | { |
6889ca71 MS |
578 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
579 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a | 580 | |
80243528 MS |
581 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
582 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); | |
185f7d9a MS |
583 | } |
584 | ||
a509a1d4 JH |
585 | __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
586 | { | |
587 | return -ENOSYS; | |
588 | } | |
589 | ||
590 | static int zynq_gem_read_rom_mac(struct udevice *dev) | |
591 | { | |
a509a1d4 JH |
592 | struct eth_pdata *pdata = dev_get_platdata(dev); |
593 | ||
b2330897 OS |
594 | if (!pdata) |
595 | return -ENOSYS; | |
a509a1d4 | 596 | |
b2330897 | 597 | return zynq_board_read_rom_ethaddr(pdata->enetaddr); |
a509a1d4 JH |
598 | } |
599 | ||
6889ca71 MS |
600 | static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
601 | int devad, int reg) | |
185f7d9a | 602 | { |
6889ca71 | 603 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 604 | int ret; |
6889ca71 | 605 | u16 val; |
185f7d9a | 606 | |
6889ca71 MS |
607 | ret = phyread(priv, addr, reg, &val); |
608 | debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); | |
609 | return val; | |
185f7d9a MS |
610 | } |
611 | ||
6889ca71 MS |
612 | static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
613 | int reg, u16 value) | |
185f7d9a | 614 | { |
6889ca71 | 615 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 616 | |
6889ca71 MS |
617 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
618 | return phywrite(priv, addr, reg, value); | |
185f7d9a MS |
619 | } |
620 | ||
6889ca71 | 621 | static int zynq_gem_probe(struct udevice *dev) |
185f7d9a | 622 | { |
a5144237 | 623 | void *bd_space; |
6889ca71 MS |
624 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
625 | int ret; | |
185f7d9a | 626 | |
a5144237 ST |
627 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
628 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); | |
629 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); | |
630 | ||
96f4f149 | 631 | /* Align bd_space to MMU_SECTION_SHIFT */ |
a5144237 | 632 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); |
9ce1edc8 MS |
633 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
634 | BD_SPACE, DCACHE_OFF); | |
a5144237 ST |
635 | |
636 | /* Initialize the bd spaces for tx and rx bd's */ | |
637 | priv->tx_bd = (struct emac_bd *)bd_space; | |
5b47d407 | 638 | priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
a5144237 | 639 | |
a765bdd1 SDPP |
640 | ret = clk_get_by_name(dev, "tx_clk", &priv->clk); |
641 | if (ret < 0) { | |
642 | dev_err(dev, "failed to get clock\n"); | |
643 | return -EINVAL; | |
644 | } | |
a765bdd1 | 645 | |
6889ca71 MS |
646 | priv->bus = mdio_alloc(); |
647 | priv->bus->read = zynq_gem_miiphy_read; | |
648 | priv->bus->write = zynq_gem_miiphy_write; | |
649 | priv->bus->priv = priv; | |
185f7d9a | 650 | |
6516e3f2 | 651 | ret = mdio_register_seq(priv->bus, dev->seq); |
6889ca71 MS |
652 | if (ret) |
653 | return ret; | |
185f7d9a | 654 | |
e76d2dca | 655 | return zynq_phy_init(dev); |
6889ca71 | 656 | } |
185f7d9a | 657 | |
6889ca71 MS |
658 | static int zynq_gem_remove(struct udevice *dev) |
659 | { | |
660 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
185f7d9a | 661 | |
6889ca71 MS |
662 | free(priv->phydev); |
663 | mdio_unregister(priv->bus); | |
664 | mdio_free(priv->bus); | |
185f7d9a | 665 | |
6889ca71 MS |
666 | return 0; |
667 | } | |
668 | ||
669 | static const struct eth_ops zynq_gem_ops = { | |
670 | .start = zynq_gem_init, | |
671 | .send = zynq_gem_send, | |
672 | .recv = zynq_gem_recv, | |
9d9211ac | 673 | .free_pkt = zynq_gem_free_pkt, |
6889ca71 MS |
674 | .stop = zynq_gem_halt, |
675 | .write_hwaddr = zynq_gem_setup_mac, | |
a509a1d4 | 676 | .read_rom_hwaddr = zynq_gem_read_rom_mac, |
6889ca71 | 677 | }; |
c8e29271 | 678 | |
6889ca71 MS |
679 | static int zynq_gem_ofdata_to_platdata(struct udevice *dev) |
680 | { | |
681 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
682 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
e160f7d4 | 683 | int node = dev_of_offset(dev); |
3cdb1450 | 684 | const char *phy_mode; |
6889ca71 | 685 | |
a821c4af | 686 | pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); |
6889ca71 MS |
687 | priv->iobase = (struct zynq_gem_regs *)pdata->iobase; |
688 | /* Hardcode for now */ | |
bcdfef7a | 689 | priv->phyaddr = -1; |
6889ca71 | 690 | |
e160f7d4 SG |
691 | priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, |
692 | "phy-handle"); | |
20671a98 DM |
693 | if (priv->phy_of_handle > 0) |
694 | priv->phyaddr = fdtdec_get_int(gd->fdt_blob, | |
695 | priv->phy_of_handle, "reg", -1); | |
6889ca71 | 696 | |
e160f7d4 | 697 | phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); |
3cdb1450 MS |
698 | if (phy_mode) |
699 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
700 | if (pdata->phy_interface == -1) { | |
701 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
702 | return -EINVAL; | |
703 | } | |
704 | priv->interface = pdata->phy_interface; | |
705 | ||
dd12a27c SDPP |
706 | priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, |
707 | "is-internal-pcspma"); | |
708 | ||
15a2acdf | 709 | printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, |
3cdb1450 | 710 | priv->phyaddr, phy_string_for_interface(priv->interface)); |
6889ca71 MS |
711 | |
712 | return 0; | |
185f7d9a | 713 | } |
6889ca71 MS |
714 | |
715 | static const struct udevice_id zynq_gem_ids[] = { | |
716 | { .compatible = "cdns,zynqmp-gem" }, | |
717 | { .compatible = "cdns,zynq-gem" }, | |
718 | { .compatible = "cdns,gem" }, | |
719 | { } | |
720 | }; | |
721 | ||
722 | U_BOOT_DRIVER(zynq_gem) = { | |
723 | .name = "zynq_gem", | |
724 | .id = UCLASS_ETH, | |
725 | .of_match = zynq_gem_ids, | |
726 | .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, | |
727 | .probe = zynq_gem_probe, | |
728 | .remove = zynq_gem_remove, | |
729 | .ops = &zynq_gem_ops, | |
730 | .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), | |
731 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
732 | }; |