[people/ms/u-boot.git] / drivers / net / zynq_gem.c

/*
 * (C) Copyright 2011 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * Based on Xilinx gmac driver:
 * (C) Copyright 2011 Xilinx
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>

#if !defined(CONFIG_PHYLIB)
# error XILINX_GEM_ETHERNET requires PHYLIB
#endif

/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK	0x20000000 /* read operation */
#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK	0x10000000 /* write operation */
#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK	23 /* Shift bits for PHYAD */
#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK	18 /* Shift bits for PHREG */

#define ZYNQ_GEM_RXBUF_EOF_MASK		0x00008000 /* End of frame. */
#define ZYNQ_GEM_RXBUF_SOF_MASK		0x00004000 /* Start of frame. */
#define ZYNQ_GEM_RXBUF_LEN_MASK		0x00003FFF /* Mask for length field */

#define ZYNQ_GEM_RXBUF_WRAP_MASK	0x00000002 /* Wrap bit, last BD */
#define ZYNQ_GEM_RXBUF_NEW_MASK		0x00000001 /* Used bit.. */
#define ZYNQ_GEM_RXBUF_ADD_MASK		0xFFFFFFFC /* Mask for address */

/* Wrap bit, last descriptor */
#define ZYNQ_GEM_TXBUF_WRAP_MASK	0x40000000
#define ZYNQ_GEM_TXBUF_LAST_MASK	0x00008000 /* Last buffer */

#define ZYNQ_GEM_NWCTRL_TXEN_MASK	0x00000008 /* Enable transmit */
#define ZYNQ_GEM_NWCTRL_RXEN_MASK	0x00000004 /* Enable receive */
#define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
#define ZYNQ_GEM_NWCTRL_STARTTX_MASK	0x00000200 /* Start tx (tx_go) */

#define ZYNQ_GEM_NWCFG_SPEED100		0x000000001 /* 100 Mbps operation */
#define ZYNQ_GEM_NWCFG_SPEED1000	0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN		0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM		0x000020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x000080000 /* Div pclk by 32, 80MHz */
#define ZYNQ_GEM_NWCFG_MDCCLKDIV2	0x0000c0000 /* Div pclk by 48, 120MHz */

#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH	(1 << 21) /* 64 bit bus */
#else
# define ZYNQ_GEM_DBUS_WIDTH	(0 << 21) /* 32 bit bus */
#endif

#define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_DBUS_WIDTH | \
					ZYNQ_GEM_NWCFG_FDEN | \
					ZYNQ_GEM_NWCFG_FSREM | \
					ZYNQ_GEM_NWCFG_MDCCLKDIV)

#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */

#define ZYNQ_GEM_DMACR_BLENGTH		0x00000004 /* INCR4 AHB bursts */
/* Use full configured addressable space (8 Kb) */
#define ZYNQ_GEM_DMACR_RXSIZE		0x00000300
/* Use full configured addressable space (4 Kb) */
#define ZYNQ_GEM_DMACR_TXSIZE		0x00000400
/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
#define ZYNQ_GEM_DMACR_RXBUF		0x00180000

#define ZYNQ_GEM_DMACR_INIT		(ZYNQ_GEM_DMACR_BLENGTH | \
					ZYNQ_GEM_DMACR_RXSIZE | \
					ZYNQ_GEM_DMACR_TXSIZE | \
					ZYNQ_GEM_DMACR_RXBUF)

/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG  1

/* Mask used to verify certain PHY features (or register contents)
 * in the register above:
 *  0x1000: 10Mbps full duplex support
 *  0x0800: 10Mbps half duplex support
 *  0x0008: Auto-negotiation support
 */
#define PHY_DETECT_MASK 0x1808

/* TX BD status masks */
#define ZYNQ_GEM_TXBUF_FRMLEN_MASK	0x000007ff
#define ZYNQ_GEM_TXBUF_EXHAUSTED	0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN		0x10000000

/* Clock frequencies for different speeds */
#define ZYNQ_GEM_FREQUENCY_10	2500000UL
#define ZYNQ_GEM_FREQUENCY_100	25000000UL
#define ZYNQ_GEM_FREQUENCY_1000	125000000UL

/* Device registers */
struct zynq_gem_regs {
	u32 nwctrl; /* Network Control reg */
	u32 nwcfg; /* Network Config reg */
	u32 nwsr; /* Network Status reg */
	u32 reserved1;
	u32 dmacr; /* DMA Control reg */
	u32 txsr; /* TX Status reg */
	u32 rxqbase; /* RX Q Base address reg */
	u32 txqbase; /* TX Q Base address reg */
	u32 rxsr; /* RX Status reg */
	u32 reserved2[2];
	u32 idr; /* Interrupt Disable reg */
	u32 reserved3;
	u32 phymntnc; /* Phy Maintaince reg */
	u32 reserved4[18];
	u32 hashl; /* Hash Low address reg */
	u32 hashh; /* Hash High address reg */
#define LADDR_LOW	0
#define LADDR_HIGH	1
	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
	u32 match[4]; /* Type ID1 Match reg */
	u32 reserved6[18];
	u32 stat[44]; /* Octects transmitted Low reg - stat start */
};

/* BD descriptors */
struct emac_bd {
	u32 addr; /* Next descriptor pointer */
	u32 status;
};

#define RX_BUF 32
/* Page table entries are set to 1MB, or multiples of 1MB
 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 */
#define BD_SPACE	0x100000
/* BD separation space */
#define BD_SEPRN_SPACE	64

/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
struct zynq_gem_priv {
	struct emac_bd *tx_bd;
	struct emac_bd *rx_bd;
	char *rxbuffers;
	u32 rxbd_current;
	u32 rx_first_buf;
	int phyaddr;
	u32 emio;
	int init;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

static inline int mdio_wait(struct eth_device *dev)
{
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
	u32 timeout = 20000;

	/* Wait till MDIO interface is ready to accept a new transaction. */
	while (--timeout) {
		if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
			break;
		WATCHDOG_RESET();
	}

	if (!timeout) {
		printf("%s: Timeout\n", __func__);
		return 1;
	}

	return 0;
}

static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
							u32 op, u16 *data)
{
	u32 mgtcr;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	if (mdio_wait(dev))
		return 1;

	/* Construct mgtcr mask for the operation */
	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
		(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
		(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;

	/* Write mgtcr and wait for completion */
	writel(mgtcr, &regs->phymntnc);

	if (mdio_wait(dev))
		return 1;

	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
		*data = readl(&regs->phymntnc);

	return 0;
}

static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
{
	u32 ret;

	ret = phy_setup_op(dev, phy_addr, regnum,
				ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);

	if (!ret)
		debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
		      phy_addr, regnum, *val);

	return ret;
}

static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
{
	debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
	      regnum, data);

	return phy_setup_op(dev, phy_addr, regnum,
				ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}

static void phy_detection(struct eth_device *dev)
{
	int i;
	u16 phyreg;
	struct zynq_gem_priv *priv = dev->priv;

	if (priv->phyaddr != -1) {
		phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
		if ((phyreg != 0xFFFF) &&
		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
			/* Found a valid PHY address */
			debug("Default phy address %d is valid\n",
			      priv->phyaddr);
			return;
		} else {
			debug("PHY address is not setup correctly %d\n",
			      priv->phyaddr);
			priv->phyaddr = -1;
		}
	}

	debug("detecting phy address\n");
	if (priv->phyaddr == -1) {
		/* detect the PHY address */
		for (i = 31; i >= 0; i--) {
			phyread(dev, i, PHY_DETECT_REG, &phyreg);
			if ((phyreg != 0xFFFF) &&
			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
				/* Found a valid PHY address */
				priv->phyaddr = i;
				debug("Found valid phy address, %d\n", i);
				return;
			}
		}
	}
	printf("PHY is not detected\n");
}

static int zynq_gem_setup_mac(struct eth_device *dev)
{
	u32 i, macaddrlow, macaddrhigh;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	/* Set the MAC bits [31:0] in BOT */
	macaddrlow = dev->enetaddr[0];
	macaddrlow |= dev->enetaddr[1] << 8;
	macaddrlow |= dev->enetaddr[2] << 16;
	macaddrlow |= dev->enetaddr[3] << 24;

	/* Set MAC bits [47:32] in TOP */
	macaddrhigh = dev->enetaddr[4];
	macaddrhigh |= dev->enetaddr[5] << 8;

	for (i = 0; i < 4; i++) {
		writel(0, &regs->laddr[i][LADDR_LOW]);
		writel(0, &regs->laddr[i][LADDR_HIGH]);
		/* Do not use MATCHx register */
		writel(0, &regs->match[i]);
	}

	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);

	return 0;
}

static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
	u32 i;
	unsigned long clk_rate = 0;
	struct phy_device *phydev;
	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
				offsetof(struct zynq_gem_regs, stat)) / 4;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
	struct zynq_gem_priv *priv = dev->priv;
	const u32 supported = SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full |
			SUPPORTED_1000baseT_Half |
			SUPPORTED_1000baseT_Full;

	if (!priv->init) {
		/* Disable all interrupts */
		writel(0xFFFFFFFF, &regs->idr);

		/* Disable the receiver & transmitter */
		writel(0, &regs->nwctrl);
		writel(0, &regs->txsr);
		writel(0, &regs->rxsr);
		writel(0, &regs->phymntnc);

		/* Clear the Hash registers for the mac address
		 * pointed by AddressPtr
		 */
		writel(0x0, &regs->hashl);
		/* Write bits [63:32] in TOP */
		writel(0x0, &regs->hashh);

		/* Clear all counters */
		for (i = 0; i <= stat_size; i++)
			readl(&regs->stat[i]);

		/* Setup RxBD space */
		memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));

		for (i = 0; i < RX_BUF; i++) {
			priv->rx_bd[i].status = 0xF0000000;
			priv->rx_bd[i].addr =
					((ulong)(priv->rxbuffers) +
							(i * PKTSIZE_ALIGN));
		}
		/* WRAP bit to last BD */
		priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
		/* Write RxBDs to IP */
		writel((ulong)priv->rx_bd, &regs->rxqbase);

		/* Setup for DMA Configuration register */
		writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);

		/* Setup for Network Control register, MDIO, Rx and Tx enable */
		setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);

		priv->init++;
	}

	phy_detection(dev);

	/* interface - look at tsec */
	phydev = phy_connect(priv->bus, priv->phyaddr, dev,
			     PHY_INTERFACE_MODE_MII);

	phydev->supported = supported | ADVERTISED_Pause |
			    ADVERTISED_Asym_Pause;
	phydev->advertising = phydev->supported;
	priv->phydev = phydev;
	phy_config(phydev);
	phy_startup(phydev);

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return -1;
	}

	switch (phydev->speed) {
	case SPEED_1000:
		writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
		       &regs->nwcfg);
		clk_rate = ZYNQ_GEM_FREQUENCY_1000;
		break;
	case SPEED_100:
		clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
				ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
		clk_rate = ZYNQ_GEM_FREQUENCY_100;
		break;
	case SPEED_10:
		clk_rate = ZYNQ_GEM_FREQUENCY_10;
		break;
	}

	/* Change the rclk and clk only not using EMIO interface */
	if (!priv->emio)
		zynq_slcr_gem_clk_setup(dev->iobase !=
					ZYNQ_GEM_BASEADDR0, clk_rate);

	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
					ZYNQ_GEM_NWCTRL_TXEN_MASK);

	return 0;
}

static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
{
	u32 addr, size;
	struct zynq_gem_priv *priv = dev->priv;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	/* setup BD */
	writel((ulong)priv->tx_bd, &regs->txqbase);

	/* Setup Tx BD */
	memset(priv->tx_bd, 0, sizeof(struct emac_bd));

	priv->tx_bd->addr = (ulong)ptr;
	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
			       ZYNQ_GEM_TXBUF_LAST_MASK |
			       ZYNQ_GEM_TXBUF_WRAP_MASK;

	addr = (ulong) ptr;
	addr &= ~(ARCH_DMA_MINALIGN - 1);
	size = roundup(len, ARCH_DMA_MINALIGN);
	flush_dcache_range(addr, addr + size);

	addr = (ulong)priv->rxbuffers;
	addr &= ~(ARCH_DMA_MINALIGN - 1);
	size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
	flush_dcache_range(addr, addr + size);
	barrier();

	/* Start transmit */
	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);

	/* Read TX BD status */
	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
		printf("TX underrun\n");
	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
		printf("TX buffers exhausted in mid frame\n");

	return 0;
}

/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
static int zynq_gem_recv(struct eth_device *dev)
{
	int frame_len;
	struct zynq_gem_priv *priv = dev->priv;
	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
	struct emac_bd *first_bd;

	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
		return 0;

	if (!(current_bd->status &
			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
		printf("GEM: SOF or EOF not set for last buffer received!\n");
		return 0;
	}

	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
	if (frame_len) {
		u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
		addr &= ~(ARCH_DMA_MINALIGN - 1);

		net_process_received_packet((u8 *)(ulong)addr, frame_len);

		if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
			priv->rx_first_buf = priv->rxbd_current;
		else {
			current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
			current_bd->status = 0xF0000000; /* FIXME */
		}

		if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
			first_bd = &priv->rx_bd[priv->rx_first_buf];
			first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
			first_bd->status = 0xF0000000;
		}

		if ((++priv->rxbd_current) >= RX_BUF)
			priv->rxbd_current = 0;
	}

	return frame_len;
}

static void zynq_gem_halt(struct eth_device *dev)
{
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
						ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
}

static int zynq_gem_miiphyread(const char *devname, uchar addr,
							uchar reg, ushort *val)
{
	struct eth_device *dev = eth_get_dev();
	int ret;

	ret = phyread(dev, addr, reg, val);
	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
	return ret;
}

static int zynq_gem_miiphy_write(const char *devname, uchar addr,
							uchar reg, ushort val)
{
	struct eth_device *dev = eth_get_dev();

	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
	return phywrite(dev, addr, reg, val);
}

int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
			int phy_addr, u32 emio)
{
	struct eth_device *dev;
	struct zynq_gem_priv *priv;
	void *bd_space;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
	if (dev->priv == NULL) {
		free(dev);
		return -1;
	}
	priv = dev->priv;

	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);

	/* Align bd_space to MMU_SECTION_SHIFT */
	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
					BD_SPACE, DCACHE_OFF);

	/* Initialize the bd spaces for tx and rx bd's */
	priv->tx_bd = (struct emac_bd *)bd_space;
	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);

	priv->phyaddr = phy_addr;
	priv->emio = emio;

	sprintf(dev->name, "Gem.%lx", base_addr);

	dev->iobase = base_addr;

	dev->init = zynq_gem_init;
	dev->halt = zynq_gem_halt;
	dev->send = zynq_gem_send;
	dev->recv = zynq_gem_recv;
	dev->write_hwaddr = zynq_gem_setup_mac;

	eth_register(dev);

	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return 1;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
int zynq_gem_of_init(const void *blob)
{
	int offset = 0;
	u32 ret = 0;
	u32 reg, phy_reg;

	debug("ZYNQ GEM: Initialization\n");

	do {
		offset = fdt_node_offset_by_compatible(blob, offset,
					"xlnx,ps7-ethernet-1.00.a");
		if (offset != -1) {
			reg = fdtdec_get_addr(blob, offset, "reg");
			if (reg != FDT_ADDR_T_NONE) {
				offset = fdtdec_lookup_phandle(blob, offset,
							       "phy-handle");
				if (offset != -1)
					phy_reg = fdtdec_get_addr(blob, offset,
								  "reg");
				else
					phy_reg = 0;

				debug("ZYNQ GEM: addr %x, phyaddr %x\n",
				      reg, phy_reg);

				ret |= zynq_gem_initialize(NULL, reg,
							   phy_reg, 0);

			} else {
				debug("ZYNQ GEM: Can't get base address\n");
				return -1;
			}
		}
	} while (offset != -1);

	return ret;
}
#endif
Commit	Line	Data
185f7d9a MS	1	/*
	2	* (C) Copyright 2011 Michal Simek
	3	*
	4	* Michal SIMEK <monstr@monstr.eu>
	5	*
	6	* Based on Xilinx gmac driver:
	7	* (C) Copyright 2011 Xilinx
	8	*
3765b3e7	9	* SPDX-License-Identifier: GPL-2.0+
185f7d9a MS	10	*/
	11
	12	#include <common.h>
	13	#include <net.h>
2fd2489b	14	#include <netdev.h>
185f7d9a	15	#include <config.h>
f88a6869 MS	16	#include <fdtdec.h>
f88a6869 MS	17	#include <libfdt.h>
185f7d9a MS	18	#include <malloc.h>
	19	#include <asm/io.h>
	20	#include <phy.h>
	21	#include <miiphy.h>
	22	#include <watchdog.h>
96f4f149	23	#include <asm/system.h>
01fbf310	24	#include <asm/arch/hardware.h>
80243528	25	#include <asm/arch/sys_proto.h>
185f7d9a MS	26
	27	#if !defined(CONFIG_PHYLIB)
	28	# error XILINX_GEM_ETHERNET requires PHYLIB
	29	#endif
	30
	31	/* Bit/mask specification */
	32	#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
	33	#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
	34	#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
	35	#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
	36	#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
	37
	38	#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
	39	#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
	40	#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
	41
	42	#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
	43	#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
	44	#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
	45
	46	/* Wrap bit, last descriptor */
	47	#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
	48	#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
	49
185f7d9a MS	50	#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
	51	#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
	52	#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
	53	#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
	54
80243528 MS	55	#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
	56	#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
	57	#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
	58	#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
185f7d9a	59	#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
80243528	60	#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
185f7d9a	61
8a584c8a SDPP	62	#ifdef CONFIG_ARM64
	63	# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
	64	#else
	65	# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
	66	#endif
	67
	68	#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH \| \
	69	ZYNQ_GEM_NWCFG_FDEN \| \
185f7d9a MS	70	ZYNQ_GEM_NWCFG_FSREM \| \
	71	ZYNQ_GEM_NWCFG_MDCCLKDIV)
	72
	73	#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
	74
	75	#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
	76	/* Use full configured addressable space (8 Kb) */
	77	#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
	78	/* Use full configured addressable space (4 Kb) */
	79	#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
	80	/* Set with binary 00011000 to use 1536 byte(1max length frame/buffer) /
	81	#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
	82
	83	#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH \| \
	84	ZYNQ_GEM_DMACR_RXSIZE \| \
	85	ZYNQ_GEM_DMACR_TXSIZE \| \
	86	ZYNQ_GEM_DMACR_RXBUF)
	87
f97d7e8b MS	88	/* Use MII register 1 (MII status register) to detect PHY */
	89	#define PHY_DETECT_REG 1
	90
	91	/* Mask used to verify certain PHY features (or register contents)
	92	* in the register above:
	93	* 0x1000: 10Mbps full duplex support
	94	* 0x0800: 10Mbps half duplex support
	95	* 0x0008: Auto-negotiation support
	96	*/
	97	#define PHY_DETECT_MASK 0x1808
	98
a5144237 ST	99	/* TX BD status masks */
	100	#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
	101	#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
	102	#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
	103
97598fcf SB	104	/* Clock frequencies for different speeds */
	105	#define ZYNQ_GEM_FREQUENCY_10 2500000UL
	106	#define ZYNQ_GEM_FREQUENCY_100 25000000UL
	107	#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
	108
185f7d9a MS	109	/* Device registers */
	110	struct zynq_gem_regs {
	111	u32 nwctrl; /* Network Control reg */
	112	u32 nwcfg; /* Network Config reg */
	113	u32 nwsr; /* Network Status reg */
	114	u32 reserved1;
	115	u32 dmacr; /* DMA Control reg */
	116	u32 txsr; /* TX Status reg */
	117	u32 rxqbase; /* RX Q Base address reg */
	118	u32 txqbase; /* TX Q Base address reg */
	119	u32 rxsr; /* RX Status reg */
	120	u32 reserved2[2];
	121	u32 idr; /* Interrupt Disable reg */
	122	u32 reserved3;
	123	u32 phymntnc; /* Phy Maintaince reg */
	124	u32 reserved4[18];
	125	u32 hashl; /* Hash Low address reg */
	126	u32 hashh; /* Hash High address reg */
	127	#define LADDR_LOW 0
	128	#define LADDR_HIGH 1
	129	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
	130	u32 match[4]; /* Type ID1 Match reg */
	131	u32 reserved6[18];
	132	u32 stat[44]; /* Octects transmitted Low reg - stat start */
	133	};
	134
	135	/* BD descriptors */
	136	struct emac_bd {
	137	u32 addr; /* Next descriptor pointer */
	138	u32 status;
	139	};
	140
eda9d307	141	#define RX_BUF 32
a5144237 ST	142	/* Page table entries are set to 1MB, or multiples of 1MB
	143	* (not < 1MB). driver uses less bd's so use 1MB bdspace.
	144	*/
	145	#define BD_SPACE 0x100000
	146	/* BD separation space */
	147	#define BD_SEPRN_SPACE 64
185f7d9a MS	148
	149	/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
	150	struct zynq_gem_priv {
a5144237 ST	151	struct emac_bd *tx_bd;
	152	struct emac_bd *rx_bd;
	153	char *rxbuffers;
185f7d9a MS	154	u32 rxbd_current;
	155	u32 rx_first_buf;
	156	int phyaddr;
01fbf310	157	u32 emio;
05868759	158	int init;
185f7d9a MS	159	struct phy_device *phydev;
	160	struct mii_dev *bus;
	161	};
	162
	163	static inline int mdio_wait(struct eth_device *dev)
	164	{
	165	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
4c8b7bf4	166	u32 timeout = 20000;
185f7d9a MS	167
	168	/* Wait till MDIO interface is ready to accept a new transaction. */
	169	while (--timeout) {
	170	if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
	171	break;
	172	WATCHDOG_RESET();
	173	}
	174
	175	if (!timeout) {
	176	printf("%s: Timeout\n", __func__);
	177	return 1;
	178	}
	179
	180	return 0;
	181	}
	182
	183	static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
	184	u32 op, u16 *data)
	185	{
	186	u32 mgtcr;
	187	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	188
	189	if (mdio_wait(dev))
	190	return 1;
	191
	192	/* Construct mgtcr mask for the operation */
	193	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK \| op \|
	194	(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) \|
	195	(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) \| *data;
	196
	197	/* Write mgtcr and wait for completion */
	198	writel(mgtcr, &regs->phymntnc);
	199
	200	if (mdio_wait(dev))
	201	return 1;
	202
	203	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
	204	*data = readl(&regs->phymntnc);
	205
	206	return 0;
	207	}
	208
	209	static u32 phyread(struct eth_device dev, u32 phy_addr, u32 regnum, u16 val)
	210	{
198e9a4f MS	211	u32 ret;
	212
	213	ret = phy_setup_op(dev, phy_addr, regnum,
185f7d9a	214	ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
198e9a4f MS	215
	216	if (!ret)
	217	debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
	218	phy_addr, regnum, *val);
	219
	220	return ret;
185f7d9a MS	221	}
	222
	223	static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
	224	{
198e9a4f MS	225	debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
	226	regnum, data);
	227
185f7d9a MS	228	return phy_setup_op(dev, phy_addr, regnum,
	229	ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
	230	}
	231
f97d7e8b MS	232	static void phy_detection(struct eth_device *dev)
	233	{
	234	int i;
	235	u16 phyreg;
	236	struct zynq_gem_priv *priv = dev->priv;
	237
	238	if (priv->phyaddr != -1) {
	239	phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
	240	if ((phyreg != 0xFFFF) &&
	241	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	242	/* Found a valid PHY address */
	243	debug("Default phy address %d is valid\n",
	244	priv->phyaddr);
	245	return;
	246	} else {
	247	debug("PHY address is not setup correctly %d\n",
	248	priv->phyaddr);
	249	priv->phyaddr = -1;
	250	}
	251	}
	252
	253	debug("detecting phy address\n");
	254	if (priv->phyaddr == -1) {
	255	/* detect the PHY address */
	256	for (i = 31; i >= 0; i--) {
	257	phyread(dev, i, PHY_DETECT_REG, &phyreg);
	258	if ((phyreg != 0xFFFF) &&
	259	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	260	/* Found a valid PHY address */
	261	priv->phyaddr = i;
	262	debug("Found valid phy address, %d\n", i);
	263	return;
	264	}
	265	}
	266	}
	267	printf("PHY is not detected\n");
	268	}
	269
185f7d9a MS	270	static int zynq_gem_setup_mac(struct eth_device *dev)
	271	{
	272	u32 i, macaddrlow, macaddrhigh;
	273	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	274
	275	/* Set the MAC bits [31:0] in BOT */
	276	macaddrlow = dev->enetaddr[0];
	277	macaddrlow \|= dev->enetaddr[1] << 8;
	278	macaddrlow \|= dev->enetaddr[2] << 16;
	279	macaddrlow \|= dev->enetaddr[3] << 24;
	280
	281	/* Set MAC bits [47:32] in TOP */
	282	macaddrhigh = dev->enetaddr[4];
	283	macaddrhigh \|= dev->enetaddr[5] << 8;
	284
	285	for (i = 0; i < 4; i++) {
	286	writel(0, &regs->laddr[i][LADDR_LOW]);
	287	writel(0, &regs->laddr[i][LADDR_HIGH]);
	288	/* Do not use MATCHx register */
	289	writel(0, &regs->match[i]);
	290	}
	291
	292	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
	293	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
	294
	295	return 0;
	296	}
	297
	298	static int zynq_gem_init(struct eth_device dev, bd_t bis)
	299	{
97598fcf SB	300	u32 i;
97598fcf SB	301	unsigned long clk_rate = 0;
185f7d9a MS	302	struct phy_device *phydev;
	303	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
	304	offsetof(struct zynq_gem_regs, stat)) / 4;
	305	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	306	struct zynq_gem_priv *priv = dev->priv;
	307	const u32 supported = SUPPORTED_10baseT_Half \|
	308	SUPPORTED_10baseT_Full \|
	309	SUPPORTED_100baseT_Half \|
	310	SUPPORTED_100baseT_Full \|
	311	SUPPORTED_1000baseT_Half \|
	312	SUPPORTED_1000baseT_Full;
	313
05868759 MS	314	if (!priv->init) {
	315	/* Disable all interrupts */
	316	writel(0xFFFFFFFF, &regs->idr);
	317
	318	/* Disable the receiver & transmitter */
	319	writel(0, &regs->nwctrl);
	320	writel(0, &regs->txsr);
	321	writel(0, &regs->rxsr);
	322	writel(0, &regs->phymntnc);
	323
	324	/* Clear the Hash registers for the mac address
	325	* pointed by AddressPtr
	326	*/
	327	writel(0x0, &regs->hashl);
	328	/* Write bits [63:32] in TOP */
	329	writel(0x0, &regs->hashh);
	330
	331	/* Clear all counters */
	332	for (i = 0; i <= stat_size; i++)
	333	readl(&regs->stat[i]);
	334
	335	/* Setup RxBD space */
a5144237	336	memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
05868759 MS	337
	338	for (i = 0; i < RX_BUF; i++) {
	339	priv->rx_bd[i].status = 0xF0000000;
	340	priv->rx_bd[i].addr =
5b47d407	341	((ulong)(priv->rxbuffers) +
185f7d9a	342	(i * PKTSIZE_ALIGN));
05868759 MS	343	}
	344	/* WRAP bit to last BD */
	345	priv->rx_bd[--i].addr \|= ZYNQ_GEM_RXBUF_WRAP_MASK;
	346	/* Write RxBDs to IP */
5b47d407	347	writel((ulong)priv->rx_bd, &regs->rxqbase);
185f7d9a	348
05868759 MS	349	/* Setup for DMA Configuration register */
05868759 MS	350	writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
185f7d9a	351
05868759	352	/* Setup for Network Control register, MDIO, Rx and Tx enable */
80243528	353	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
185f7d9a	354
05868759 MS	355	priv->init++;
	356	}
	357
f97d7e8b MS	358	phy_detection(dev);
f97d7e8b MS	359
185f7d9a	360	/* interface - look at tsec */
c1a9fa4b MS	361	phydev = phy_connect(priv->bus, priv->phyaddr, dev,
c1a9fa4b MS	362	PHY_INTERFACE_MODE_MII);
185f7d9a	363
80243528 MS	364	phydev->supported = supported \| ADVERTISED_Pause \|
80243528 MS	365	ADVERTISED_Asym_Pause;
185f7d9a MS	366	phydev->advertising = phydev->supported;
	367	priv->phydev = phydev;
	368	phy_config(phydev);
	369	phy_startup(phydev);
	370
4ed4aa20 MS	371	if (!phydev->link) {
	372	printf("%s: No link.\n", phydev->dev->name);
	373	return -1;
	374	}
	375
80243528 MS	376	switch (phydev->speed) {
	377	case SPEED_1000:
	378	writel(ZYNQ_GEM_NWCFG_INIT \| ZYNQ_GEM_NWCFG_SPEED1000,
	379	&regs->nwcfg);
97598fcf	380	clk_rate = ZYNQ_GEM_FREQUENCY_1000;
80243528 MS	381	break;
	382	case SPEED_100:
	383	clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
	384	ZYNQ_GEM_NWCFG_INIT \| ZYNQ_GEM_NWCFG_SPEED100);
97598fcf	385	clk_rate = ZYNQ_GEM_FREQUENCY_100;
80243528 MS	386	break;
80243528 MS	387	case SPEED_10:
97598fcf	388	clk_rate = ZYNQ_GEM_FREQUENCY_10;
80243528 MS	389	break;
80243528 MS	390	}
01fbf310 DA	391
	392	/* Change the rclk and clk only not using EMIO interface */
	393	if (!priv->emio)
	394	zynq_slcr_gem_clk_setup(dev->iobase !=
97598fcf	395	ZYNQ_GEM_BASEADDR0, clk_rate);
80243528 MS	396
	397	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK \|
	398	ZYNQ_GEM_NWCTRL_TXEN_MASK);
	399
185f7d9a MS	400	return 0;
	401	}
	402
	403	static int zynq_gem_send(struct eth_device dev, void ptr, int len)
	404	{
a5144237	405	u32 addr, size;
185f7d9a MS	406	struct zynq_gem_priv *priv = dev->priv;
185f7d9a MS	407	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
185f7d9a MS	408
185f7d9a MS	409	/* setup BD */
5b47d407	410	writel((ulong)priv->tx_bd, &regs->txqbase);
185f7d9a MS	411
185f7d9a MS	412	/* Setup Tx BD */
a5144237 ST	413	memset(priv->tx_bd, 0, sizeof(struct emac_bd));
a5144237 ST	414
5b47d407	415	priv->tx_bd->addr = (ulong)ptr;
a5144237	416	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) \|
e65d33cf MS	417	ZYNQ_GEM_TXBUF_LAST_MASK \|
e65d33cf MS	418	ZYNQ_GEM_TXBUF_WRAP_MASK;
185f7d9a	419
5b47d407	420	addr = (ulong) ptr;
a5144237 ST	421	addr &= ~(ARCH_DMA_MINALIGN - 1);
	422	size = roundup(len, ARCH_DMA_MINALIGN);
	423	flush_dcache_range(addr, addr + size);
96f4f149	424
5b47d407	425	addr = (ulong)priv->rxbuffers;
96f4f149 SDPP	426	addr &= ~(ARCH_DMA_MINALIGN - 1);
	427	size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
	428	flush_dcache_range(addr, addr + size);
a5144237	429	barrier();
185f7d9a MS	430
	431	/* Start transmit */
	432	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
	433
a5144237 ST	434	/* Read TX BD status */
	435	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
	436	printf("TX underrun\n");
	437	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
	438	printf("TX buffers exhausted in mid frame\n");
185f7d9a	439
185f7d9a MS	440	return 0;
	441	}
	442
	443	/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
	444	static int zynq_gem_recv(struct eth_device *dev)
	445	{
	446	int frame_len;
	447	struct zynq_gem_priv *priv = dev->priv;
	448	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
	449	struct emac_bd *first_bd;
	450
	451	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
	452	return 0;
	453
	454	if (!(current_bd->status &
	455	(ZYNQ_GEM_RXBUF_SOF_MASK \| ZYNQ_GEM_RXBUF_EOF_MASK))) {
	456	printf("GEM: SOF or EOF not set for last buffer received!\n");
	457	return 0;
	458	}
	459
	460	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
	461	if (frame_len) {
a5144237 ST	462	u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
a5144237 ST	463	addr &= ~(ARCH_DMA_MINALIGN - 1);
a5144237	464
5b47d407	465	net_process_received_packet((u8 *)(ulong)addr, frame_len);
185f7d9a MS	466
	467	if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
	468	priv->rx_first_buf = priv->rxbd_current;
	469	else {
	470	current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
	471	current_bd->status = 0xF0000000; /* FIXME */
	472	}
	473
	474	if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
	475	first_bd = &priv->rx_bd[priv->rx_first_buf];
	476	first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
	477	first_bd->status = 0xF0000000;
	478	}
	479
	480	if ((++priv->rxbd_current) >= RX_BUF)
	481	priv->rxbd_current = 0;
185f7d9a MS	482	}
185f7d9a MS	483
3b90d0af	484	return frame_len;
185f7d9a MS	485	}
	486
	487	static void zynq_gem_halt(struct eth_device *dev)
	488	{
	489	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	490
80243528 MS	491	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK \|
80243528 MS	492	ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
185f7d9a MS	493	}
	494
	495	static int zynq_gem_miiphyread(const char *devname, uchar addr,
	496	uchar reg, ushort *val)
	497	{
	498	struct eth_device *dev = eth_get_dev();
	499	int ret;
	500
	501	ret = phyread(dev, addr, reg, val);
	502	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
	503	return ret;
	504	}
	505
	506	static int zynq_gem_miiphy_write(const char *devname, uchar addr,
	507	uchar reg, ushort val)
	508	{
	509	struct eth_device *dev = eth_get_dev();
	510
	511	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
	512	return phywrite(dev, addr, reg, val);
	513	}
	514
58405378 MS	515	int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
58405378 MS	516	int phy_addr, u32 emio)
185f7d9a MS	517	{
	518	struct eth_device *dev;
	519	struct zynq_gem_priv *priv;
a5144237	520	void *bd_space;
185f7d9a MS	521
	522	dev = calloc(1, sizeof(*dev));
	523	if (dev == NULL)
	524	return -1;
	525
	526	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
	527	if (dev->priv == NULL) {
	528	free(dev);
	529	return -1;
	530	}
	531	priv = dev->priv;
	532
a5144237 ST	533	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	534	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	535	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
	536
96f4f149	537	/* Align bd_space to MMU_SECTION_SHIFT */
a5144237	538	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
9ce1edc8 MS	539	mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
9ce1edc8 MS	540	BD_SPACE, DCACHE_OFF);
a5144237 ST	541
	542	/* Initialize the bd spaces for tx and rx bd's */
	543	priv->tx_bd = (struct emac_bd *)bd_space;
5b47d407	544	priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
a5144237	545
117cd4cc	546	priv->phyaddr = phy_addr;
01fbf310	547	priv->emio = emio;
185f7d9a	548
58405378	549	sprintf(dev->name, "Gem.%lx", base_addr);
185f7d9a MS	550
	551	dev->iobase = base_addr;
	552
	553	dev->init = zynq_gem_init;
	554	dev->halt = zynq_gem_halt;
	555	dev->send = zynq_gem_send;
	556	dev->recv = zynq_gem_recv;
	557	dev->write_hwaddr = zynq_gem_setup_mac;
	558
	559	eth_register(dev);
	560
	561	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
	562	priv->bus = miiphy_get_dev_by_name(dev->name);
	563
	564	return 1;
	565	}
f88a6869	566
0f925822	567	#if CONFIG_IS_ENABLED(OF_CONTROL)
f88a6869 MS	568	int zynq_gem_of_init(const void *blob)
	569	{
	570	int offset = 0;
	571	u32 ret = 0;
	572	u32 reg, phy_reg;
	573
	574	debug("ZYNQ GEM: Initialization\n");
	575
	576	do {
	577	offset = fdt_node_offset_by_compatible(blob, offset,
	578	"xlnx,ps7-ethernet-1.00.a");
	579	if (offset != -1) {
	580	reg = fdtdec_get_addr(blob, offset, "reg");
	581	if (reg != FDT_ADDR_T_NONE) {
	582	offset = fdtdec_lookup_phandle(blob, offset,
	583	"phy-handle");
	584	if (offset != -1)
	585	phy_reg = fdtdec_get_addr(blob, offset,
	586	"reg");
	587	else
	588	phy_reg = 0;
	589
	590	debug("ZYNQ GEM: addr %x, phyaddr %x\n",
	591	reg, phy_reg);
	592
	593	ret \|= zynq_gem_initialize(NULL, reg,
	594	phy_reg, 0);
	595
	596	} else {
	597	debug("ZYNQ GEM: Can't get base address\n");
	598	return -1;
	599	}
	600	}
	601	} while (offset != -1);
	602
	603	return ret;
	604	}
	605	#endif