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185f7d9a MS |
1 | /* |
2 | * (C) Copyright 2011 Michal Simek | |
3 | * | |
4 | * Michal SIMEK <monstr@monstr.eu> | |
5 | * | |
6 | * Based on Xilinx gmac driver: | |
7 | * (C) Copyright 2011 Xilinx | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
185f7d9a MS |
10 | */ |
11 | ||
12 | #include <common.h> | |
6889ca71 | 13 | #include <dm.h> |
185f7d9a | 14 | #include <net.h> |
2fd2489b | 15 | #include <netdev.h> |
185f7d9a | 16 | #include <config.h> |
b8de29fe | 17 | #include <console.h> |
185f7d9a MS |
18 | #include <malloc.h> |
19 | #include <asm/io.h> | |
20 | #include <phy.h> | |
21 | #include <miiphy.h> | |
e7138b34 | 22 | #include <wait_bit.h> |
185f7d9a | 23 | #include <watchdog.h> |
96f4f149 | 24 | #include <asm/system.h> |
01fbf310 | 25 | #include <asm/arch/hardware.h> |
80243528 | 26 | #include <asm/arch/sys_proto.h> |
5d97dff0 | 27 | #include <linux/errno.h> |
185f7d9a | 28 | |
6889ca71 MS |
29 | DECLARE_GLOBAL_DATA_PTR; |
30 | ||
185f7d9a MS |
31 | /* Bit/mask specification */ |
32 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ | |
33 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ | |
34 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ | |
35 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ | |
36 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ | |
37 | ||
38 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ | |
39 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ | |
40 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ | |
41 | ||
42 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ | |
43 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ | |
44 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ | |
45 | ||
46 | /* Wrap bit, last descriptor */ | |
47 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 | |
48 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ | |
23a598f7 | 49 | #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ |
185f7d9a | 50 | |
185f7d9a MS |
51 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
52 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ | |
53 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ | |
54 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ | |
55 | ||
80243528 MS |
56 | #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ |
57 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ | |
58 | #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ | |
59 | #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ | |
a06c341f SDPP |
60 | #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ |
61 | #define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ | |
f17ea71d MS |
62 | #ifdef CONFIG_ARM64 |
63 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ | |
64 | #else | |
6777f386 | 65 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ |
f17ea71d | 66 | #endif |
185f7d9a | 67 | |
8a584c8a SDPP |
68 | #ifdef CONFIG_ARM64 |
69 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ | |
70 | #else | |
71 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ | |
72 | #endif | |
73 | ||
74 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ | |
75 | ZYNQ_GEM_NWCFG_FDEN | \ | |
185f7d9a MS |
76 | ZYNQ_GEM_NWCFG_FSREM | \ |
77 | ZYNQ_GEM_NWCFG_MDCCLKDIV) | |
78 | ||
79 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ | |
80 | ||
81 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ | |
82 | /* Use full configured addressable space (8 Kb) */ | |
83 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 | |
84 | /* Use full configured addressable space (4 Kb) */ | |
85 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 | |
86 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ | |
87 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 | |
88 | ||
89 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ | |
90 | ZYNQ_GEM_DMACR_RXSIZE | \ | |
91 | ZYNQ_GEM_DMACR_TXSIZE | \ | |
92 | ZYNQ_GEM_DMACR_RXBUF) | |
93 | ||
e4d2318a MS |
94 | #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ |
95 | ||
845ee5f6 SDPP |
96 | #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 |
97 | ||
f97d7e8b MS |
98 | /* Use MII register 1 (MII status register) to detect PHY */ |
99 | #define PHY_DETECT_REG 1 | |
100 | ||
101 | /* Mask used to verify certain PHY features (or register contents) | |
102 | * in the register above: | |
103 | * 0x1000: 10Mbps full duplex support | |
104 | * 0x0800: 10Mbps half duplex support | |
105 | * 0x0008: Auto-negotiation support | |
106 | */ | |
107 | #define PHY_DETECT_MASK 0x1808 | |
108 | ||
a5144237 ST |
109 | /* TX BD status masks */ |
110 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff | |
111 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 | |
112 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 | |
113 | ||
97598fcf SB |
114 | /* Clock frequencies for different speeds */ |
115 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL | |
116 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL | |
117 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL | |
118 | ||
185f7d9a MS |
119 | /* Device registers */ |
120 | struct zynq_gem_regs { | |
97a51a03 MS |
121 | u32 nwctrl; /* 0x0 - Network Control reg */ |
122 | u32 nwcfg; /* 0x4 - Network Config reg */ | |
123 | u32 nwsr; /* 0x8 - Network Status reg */ | |
185f7d9a | 124 | u32 reserved1; |
97a51a03 MS |
125 | u32 dmacr; /* 0x10 - DMA Control reg */ |
126 | u32 txsr; /* 0x14 - TX Status reg */ | |
127 | u32 rxqbase; /* 0x18 - RX Q Base address reg */ | |
128 | u32 txqbase; /* 0x1c - TX Q Base address reg */ | |
129 | u32 rxsr; /* 0x20 - RX Status reg */ | |
185f7d9a | 130 | u32 reserved2[2]; |
97a51a03 | 131 | u32 idr; /* 0x2c - Interrupt Disable reg */ |
185f7d9a | 132 | u32 reserved3; |
97a51a03 | 133 | u32 phymntnc; /* 0x34 - Phy Maintaince reg */ |
185f7d9a | 134 | u32 reserved4[18]; |
97a51a03 MS |
135 | u32 hashl; /* 0x80 - Hash Low address reg */ |
136 | u32 hashh; /* 0x84 - Hash High address reg */ | |
185f7d9a MS |
137 | #define LADDR_LOW 0 |
138 | #define LADDR_HIGH 1 | |
97a51a03 MS |
139 | u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ |
140 | u32 match[4]; /* 0xa8 - Type ID1 Match reg */ | |
185f7d9a | 141 | u32 reserved6[18]; |
0ebf4041 MS |
142 | #define STAT_SIZE 44 |
143 | u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ | |
845ee5f6 SDPP |
144 | u32 reserved9[20]; |
145 | u32 pcscntrl; | |
146 | u32 reserved7[143]; | |
603ff008 EI |
147 | u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ |
148 | u32 reserved8[15]; | |
149 | u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ | |
185f7d9a MS |
150 | }; |
151 | ||
152 | /* BD descriptors */ | |
153 | struct emac_bd { | |
154 | u32 addr; /* Next descriptor pointer */ | |
155 | u32 status; | |
156 | }; | |
157 | ||
eda9d307 | 158 | #define RX_BUF 32 |
a5144237 ST |
159 | /* Page table entries are set to 1MB, or multiples of 1MB |
160 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
161 | */ | |
162 | #define BD_SPACE 0x100000 | |
163 | /* BD separation space */ | |
ff475878 | 164 | #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) |
185f7d9a | 165 | |
603ff008 EI |
166 | /* Setup the first free TX descriptor */ |
167 | #define TX_FREE_DESC 2 | |
168 | ||
185f7d9a MS |
169 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ |
170 | struct zynq_gem_priv { | |
a5144237 ST |
171 | struct emac_bd *tx_bd; |
172 | struct emac_bd *rx_bd; | |
173 | char *rxbuffers; | |
185f7d9a MS |
174 | u32 rxbd_current; |
175 | u32 rx_first_buf; | |
176 | int phyaddr; | |
01fbf310 | 177 | u32 emio; |
05868759 | 178 | int init; |
f2fc2768 | 179 | struct zynq_gem_regs *iobase; |
16ce6de8 | 180 | phy_interface_t interface; |
185f7d9a | 181 | struct phy_device *phydev; |
20671a98 | 182 | int phy_of_handle; |
185f7d9a MS |
183 | struct mii_dev *bus; |
184 | }; | |
185 | ||
3fac2724 | 186 | static inline int mdio_wait(struct zynq_gem_regs *regs) |
185f7d9a | 187 | { |
4c8b7bf4 | 188 | u32 timeout = 20000; |
185f7d9a MS |
189 | |
190 | /* Wait till MDIO interface is ready to accept a new transaction. */ | |
191 | while (--timeout) { | |
192 | if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) | |
193 | break; | |
194 | WATCHDOG_RESET(); | |
195 | } | |
196 | ||
197 | if (!timeout) { | |
198 | printf("%s: Timeout\n", __func__); | |
199 | return 1; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
f2fc2768 MS |
205 | static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
206 | u32 op, u16 *data) | |
185f7d9a MS |
207 | { |
208 | u32 mgtcr; | |
f2fc2768 | 209 | struct zynq_gem_regs *regs = priv->iobase; |
185f7d9a | 210 | |
3fac2724 | 211 | if (mdio_wait(regs)) |
185f7d9a MS |
212 | return 1; |
213 | ||
214 | /* Construct mgtcr mask for the operation */ | |
215 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | | |
216 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | | |
217 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; | |
218 | ||
219 | /* Write mgtcr and wait for completion */ | |
220 | writel(mgtcr, ®s->phymntnc); | |
221 | ||
3fac2724 | 222 | if (mdio_wait(regs)) |
185f7d9a MS |
223 | return 1; |
224 | ||
225 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) | |
226 | *data = readl(®s->phymntnc); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
f2fc2768 MS |
231 | static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
232 | u32 regnum, u16 *val) | |
185f7d9a | 233 | { |
198e9a4f MS |
234 | u32 ret; |
235 | ||
f2fc2768 MS |
236 | ret = phy_setup_op(priv, phy_addr, regnum, |
237 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); | |
198e9a4f MS |
238 | |
239 | if (!ret) | |
240 | debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, | |
241 | phy_addr, regnum, *val); | |
242 | ||
243 | return ret; | |
185f7d9a MS |
244 | } |
245 | ||
f2fc2768 MS |
246 | static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
247 | u32 regnum, u16 data) | |
185f7d9a | 248 | { |
198e9a4f MS |
249 | debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
250 | regnum, data); | |
251 | ||
f2fc2768 MS |
252 | return phy_setup_op(priv, phy_addr, regnum, |
253 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); | |
185f7d9a MS |
254 | } |
255 | ||
6889ca71 | 256 | static int phy_detection(struct udevice *dev) |
f97d7e8b MS |
257 | { |
258 | int i; | |
259 | u16 phyreg; | |
260 | struct zynq_gem_priv *priv = dev->priv; | |
261 | ||
262 | if (priv->phyaddr != -1) { | |
f2fc2768 | 263 | phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); |
f97d7e8b MS |
264 | if ((phyreg != 0xFFFF) && |
265 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
266 | /* Found a valid PHY address */ | |
267 | debug("Default phy address %d is valid\n", | |
268 | priv->phyaddr); | |
b904725a | 269 | return 0; |
f97d7e8b MS |
270 | } else { |
271 | debug("PHY address is not setup correctly %d\n", | |
272 | priv->phyaddr); | |
273 | priv->phyaddr = -1; | |
274 | } | |
275 | } | |
276 | ||
277 | debug("detecting phy address\n"); | |
278 | if (priv->phyaddr == -1) { | |
279 | /* detect the PHY address */ | |
280 | for (i = 31; i >= 0; i--) { | |
f2fc2768 | 281 | phyread(priv, i, PHY_DETECT_REG, &phyreg); |
f97d7e8b MS |
282 | if ((phyreg != 0xFFFF) && |
283 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
284 | /* Found a valid PHY address */ | |
285 | priv->phyaddr = i; | |
286 | debug("Found valid phy address, %d\n", i); | |
b904725a | 287 | return 0; |
f97d7e8b MS |
288 | } |
289 | } | |
290 | } | |
291 | printf("PHY is not detected\n"); | |
b904725a | 292 | return -1; |
f97d7e8b MS |
293 | } |
294 | ||
6889ca71 | 295 | static int zynq_gem_setup_mac(struct udevice *dev) |
185f7d9a MS |
296 | { |
297 | u32 i, macaddrlow, macaddrhigh; | |
6889ca71 MS |
298 | struct eth_pdata *pdata = dev_get_platdata(dev); |
299 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
300 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a MS |
301 | |
302 | /* Set the MAC bits [31:0] in BOT */ | |
6889ca71 MS |
303 | macaddrlow = pdata->enetaddr[0]; |
304 | macaddrlow |= pdata->enetaddr[1] << 8; | |
305 | macaddrlow |= pdata->enetaddr[2] << 16; | |
306 | macaddrlow |= pdata->enetaddr[3] << 24; | |
185f7d9a MS |
307 | |
308 | /* Set MAC bits [47:32] in TOP */ | |
6889ca71 MS |
309 | macaddrhigh = pdata->enetaddr[4]; |
310 | macaddrhigh |= pdata->enetaddr[5] << 8; | |
185f7d9a MS |
311 | |
312 | for (i = 0; i < 4; i++) { | |
313 | writel(0, ®s->laddr[i][LADDR_LOW]); | |
314 | writel(0, ®s->laddr[i][LADDR_HIGH]); | |
315 | /* Do not use MATCHx register */ | |
316 | writel(0, ®s->match[i]); | |
317 | } | |
318 | ||
319 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); | |
320 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
6889ca71 | 325 | static int zynq_phy_init(struct udevice *dev) |
185f7d9a | 326 | { |
b904725a | 327 | int ret; |
6889ca71 MS |
328 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
329 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a MS |
330 | const u32 supported = SUPPORTED_10baseT_Half | |
331 | SUPPORTED_10baseT_Full | | |
332 | SUPPORTED_100baseT_Half | | |
333 | SUPPORTED_100baseT_Full | | |
334 | SUPPORTED_1000baseT_Half | | |
335 | SUPPORTED_1000baseT_Full; | |
336 | ||
c8e29271 MS |
337 | /* Enable only MDIO bus */ |
338 | writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); | |
339 | ||
a06c341f SDPP |
340 | if (priv->interface != PHY_INTERFACE_MODE_SGMII) { |
341 | ret = phy_detection(dev); | |
342 | if (ret) { | |
343 | printf("GEM PHY init failed\n"); | |
344 | return ret; | |
345 | } | |
68cc3bd8 MS |
346 | } |
347 | ||
348 | priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, | |
349 | priv->interface); | |
90c6f2e2 MS |
350 | if (!priv->phydev) |
351 | return -ENODEV; | |
68cc3bd8 MS |
352 | |
353 | priv->phydev->supported = supported | ADVERTISED_Pause | | |
354 | ADVERTISED_Asym_Pause; | |
355 | priv->phydev->advertising = priv->phydev->supported; | |
68cc3bd8 | 356 | |
20671a98 DM |
357 | if (priv->phy_of_handle > 0) |
358 | priv->phydev->dev->of_offset = priv->phy_of_handle; | |
359 | ||
7a673f0b | 360 | return phy_config(priv->phydev); |
68cc3bd8 MS |
361 | } |
362 | ||
6889ca71 | 363 | static int zynq_gem_init(struct udevice *dev) |
68cc3bd8 | 364 | { |
a06c341f | 365 | u32 i, nwconfig; |
55259e7c | 366 | int ret; |
68cc3bd8 | 367 | unsigned long clk_rate = 0; |
6889ca71 MS |
368 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
369 | struct zynq_gem_regs *regs = priv->iobase; | |
68cc3bd8 MS |
370 | struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
371 | struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; | |
372 | ||
05868759 MS |
373 | if (!priv->init) { |
374 | /* Disable all interrupts */ | |
375 | writel(0xFFFFFFFF, ®s->idr); | |
376 | ||
377 | /* Disable the receiver & transmitter */ | |
378 | writel(0, ®s->nwctrl); | |
379 | writel(0, ®s->txsr); | |
380 | writel(0, ®s->rxsr); | |
381 | writel(0, ®s->phymntnc); | |
382 | ||
383 | /* Clear the Hash registers for the mac address | |
384 | * pointed by AddressPtr | |
385 | */ | |
386 | writel(0x0, ®s->hashl); | |
387 | /* Write bits [63:32] in TOP */ | |
388 | writel(0x0, ®s->hashh); | |
389 | ||
390 | /* Clear all counters */ | |
0ebf4041 | 391 | for (i = 0; i < STAT_SIZE; i++) |
05868759 MS |
392 | readl(®s->stat[i]); |
393 | ||
394 | /* Setup RxBD space */ | |
a5144237 | 395 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
05868759 MS |
396 | |
397 | for (i = 0; i < RX_BUF; i++) { | |
398 | priv->rx_bd[i].status = 0xF0000000; | |
399 | priv->rx_bd[i].addr = | |
5b47d407 | 400 | ((ulong)(priv->rxbuffers) + |
185f7d9a | 401 | (i * PKTSIZE_ALIGN)); |
05868759 MS |
402 | } |
403 | /* WRAP bit to last BD */ | |
404 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; | |
405 | /* Write RxBDs to IP */ | |
5b47d407 | 406 | writel((ulong)priv->rx_bd, ®s->rxqbase); |
185f7d9a | 407 | |
05868759 MS |
408 | /* Setup for DMA Configuration register */ |
409 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); | |
185f7d9a | 410 | |
05868759 | 411 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
80243528 | 412 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
185f7d9a | 413 | |
603ff008 EI |
414 | /* Disable the second priority queue */ |
415 | dummy_tx_bd->addr = 0; | |
416 | dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | | |
417 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
418 | ZYNQ_GEM_TXBUF_USED_MASK; | |
419 | ||
420 | dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | | |
421 | ZYNQ_GEM_RXBUF_NEW_MASK; | |
422 | dummy_rx_bd->status = 0; | |
423 | flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + | |
424 | sizeof(dummy_tx_bd)); | |
425 | flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + | |
426 | sizeof(dummy_rx_bd)); | |
427 | ||
428 | writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); | |
429 | writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); | |
430 | ||
05868759 MS |
431 | priv->init++; |
432 | } | |
433 | ||
55259e7c MS |
434 | ret = phy_startup(priv->phydev); |
435 | if (ret) | |
436 | return ret; | |
185f7d9a | 437 | |
64a7ead6 MS |
438 | if (!priv->phydev->link) { |
439 | printf("%s: No link.\n", priv->phydev->dev->name); | |
4ed4aa20 MS |
440 | return -1; |
441 | } | |
442 | ||
a06c341f SDPP |
443 | nwconfig = ZYNQ_GEM_NWCFG_INIT; |
444 | ||
845ee5f6 | 445 | if (priv->interface == PHY_INTERFACE_MODE_SGMII) { |
a06c341f SDPP |
446 | nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | |
447 | ZYNQ_GEM_NWCFG_PCS_SEL; | |
845ee5f6 SDPP |
448 | #ifdef CONFIG_ARM64 |
449 | writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, | |
450 | ®s->pcscntrl); | |
451 | #endif | |
452 | } | |
a06c341f | 453 | |
64a7ead6 | 454 | switch (priv->phydev->speed) { |
80243528 | 455 | case SPEED_1000: |
a06c341f | 456 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, |
80243528 | 457 | ®s->nwcfg); |
97598fcf | 458 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
80243528 MS |
459 | break; |
460 | case SPEED_100: | |
a06c341f | 461 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, |
242b1547 | 462 | ®s->nwcfg); |
97598fcf | 463 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
80243528 MS |
464 | break; |
465 | case SPEED_10: | |
97598fcf | 466 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
80243528 MS |
467 | break; |
468 | } | |
01fbf310 DA |
469 | |
470 | /* Change the rclk and clk only not using EMIO interface */ | |
471 | if (!priv->emio) | |
6889ca71 | 472 | zynq_slcr_gem_clk_setup((ulong)priv->iobase != |
97598fcf | 473 | ZYNQ_GEM_BASEADDR0, clk_rate); |
80243528 MS |
474 | |
475 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | | |
476 | ZYNQ_GEM_NWCTRL_TXEN_MASK); | |
477 | ||
185f7d9a MS |
478 | return 0; |
479 | } | |
480 | ||
6889ca71 | 481 | static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
185f7d9a | 482 | { |
a5144237 | 483 | u32 addr, size; |
6889ca71 MS |
484 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
485 | struct zynq_gem_regs *regs = priv->iobase; | |
23a598f7 | 486 | struct emac_bd *current_bd = &priv->tx_bd[1]; |
185f7d9a | 487 | |
185f7d9a | 488 | /* Setup Tx BD */ |
a5144237 ST |
489 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
490 | ||
5b47d407 | 491 | priv->tx_bd->addr = (ulong)ptr; |
a5144237 | 492 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | |
23a598f7 MS |
493 | ZYNQ_GEM_TXBUF_LAST_MASK; |
494 | /* Dummy descriptor to mark it as the last in descriptor chain */ | |
495 | current_bd->addr = 0x0; | |
496 | current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | | |
497 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
498 | ZYNQ_GEM_TXBUF_USED_MASK; | |
185f7d9a | 499 | |
45c07741 MS |
500 | /* setup BD */ |
501 | writel((ulong)priv->tx_bd, ®s->txqbase); | |
502 | ||
5b47d407 | 503 | addr = (ulong) ptr; |
a5144237 ST |
504 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
505 | size = roundup(len, ARCH_DMA_MINALIGN); | |
506 | flush_dcache_range(addr, addr + size); | |
96f4f149 | 507 | |
5b47d407 | 508 | addr = (ulong)priv->rxbuffers; |
96f4f149 SDPP |
509 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
510 | size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); | |
511 | flush_dcache_range(addr, addr + size); | |
a5144237 | 512 | barrier(); |
185f7d9a MS |
513 | |
514 | /* Start transmit */ | |
515 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); | |
516 | ||
a5144237 | 517 | /* Read TX BD status */ |
a5144237 ST |
518 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) |
519 | printf("TX buffers exhausted in mid frame\n"); | |
185f7d9a | 520 | |
e4d2318a | 521 | return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, |
e7138b34 | 522 | true, 20000, true); |
185f7d9a MS |
523 | } |
524 | ||
525 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ | |
6889ca71 | 526 | static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
185f7d9a MS |
527 | { |
528 | int frame_len; | |
9d9211ac | 529 | u32 addr; |
6889ca71 | 530 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
185f7d9a | 531 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
185f7d9a MS |
532 | |
533 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) | |
9d9211ac | 534 | return -1; |
185f7d9a MS |
535 | |
536 | if (!(current_bd->status & | |
537 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { | |
538 | printf("GEM: SOF or EOF not set for last buffer received!\n"); | |
9d9211ac | 539 | return -1; |
185f7d9a MS |
540 | } |
541 | ||
542 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; | |
9d9211ac MS |
543 | if (!frame_len) { |
544 | printf("%s: Zero size packet?\n", __func__); | |
545 | return -1; | |
546 | } | |
a5144237 | 547 | |
9d9211ac MS |
548 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
549 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
550 | *packetp = (uchar *)(uintptr_t)addr; | |
185f7d9a | 551 | |
9d9211ac MS |
552 | return frame_len; |
553 | } | |
185f7d9a | 554 | |
9d9211ac MS |
555 | static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) |
556 | { | |
557 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
558 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; | |
559 | struct emac_bd *first_bd; | |
560 | ||
561 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { | |
562 | priv->rx_first_buf = priv->rxbd_current; | |
563 | } else { | |
564 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
565 | current_bd->status = 0xF0000000; /* FIXME */ | |
566 | } | |
185f7d9a | 567 | |
9d9211ac MS |
568 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { |
569 | first_bd = &priv->rx_bd[priv->rx_first_buf]; | |
570 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
571 | first_bd->status = 0xF0000000; | |
185f7d9a MS |
572 | } |
573 | ||
9d9211ac MS |
574 | if ((++priv->rxbd_current) >= RX_BUF) |
575 | priv->rxbd_current = 0; | |
576 | ||
da872d7c | 577 | return 0; |
185f7d9a MS |
578 | } |
579 | ||
6889ca71 | 580 | static void zynq_gem_halt(struct udevice *dev) |
185f7d9a | 581 | { |
6889ca71 MS |
582 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
583 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a | 584 | |
80243528 MS |
585 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
586 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); | |
185f7d9a MS |
587 | } |
588 | ||
a509a1d4 JH |
589 | __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
590 | { | |
591 | return -ENOSYS; | |
592 | } | |
593 | ||
594 | static int zynq_gem_read_rom_mac(struct udevice *dev) | |
595 | { | |
596 | int retval; | |
597 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
598 | ||
599 | retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); | |
600 | if (retval == -ENOSYS) | |
601 | retval = 0; | |
602 | ||
603 | return retval; | |
604 | } | |
605 | ||
6889ca71 MS |
606 | static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
607 | int devad, int reg) | |
185f7d9a | 608 | { |
6889ca71 | 609 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 610 | int ret; |
6889ca71 | 611 | u16 val; |
185f7d9a | 612 | |
6889ca71 MS |
613 | ret = phyread(priv, addr, reg, &val); |
614 | debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); | |
615 | return val; | |
185f7d9a MS |
616 | } |
617 | ||
6889ca71 MS |
618 | static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
619 | int reg, u16 value) | |
185f7d9a | 620 | { |
6889ca71 | 621 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 622 | |
6889ca71 MS |
623 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
624 | return phywrite(priv, addr, reg, value); | |
185f7d9a MS |
625 | } |
626 | ||
6889ca71 | 627 | static int zynq_gem_probe(struct udevice *dev) |
185f7d9a | 628 | { |
a5144237 | 629 | void *bd_space; |
6889ca71 MS |
630 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
631 | int ret; | |
185f7d9a | 632 | |
a5144237 ST |
633 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
634 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); | |
635 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); | |
636 | ||
96f4f149 | 637 | /* Align bd_space to MMU_SECTION_SHIFT */ |
a5144237 | 638 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); |
9ce1edc8 MS |
639 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
640 | BD_SPACE, DCACHE_OFF); | |
a5144237 ST |
641 | |
642 | /* Initialize the bd spaces for tx and rx bd's */ | |
643 | priv->tx_bd = (struct emac_bd *)bd_space; | |
5b47d407 | 644 | priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
a5144237 | 645 | |
6889ca71 MS |
646 | priv->bus = mdio_alloc(); |
647 | priv->bus->read = zynq_gem_miiphy_read; | |
648 | priv->bus->write = zynq_gem_miiphy_write; | |
649 | priv->bus->priv = priv; | |
650 | strcpy(priv->bus->name, "gem"); | |
185f7d9a | 651 | |
6889ca71 MS |
652 | ret = mdio_register(priv->bus); |
653 | if (ret) | |
654 | return ret; | |
185f7d9a | 655 | |
e76d2dca | 656 | return zynq_phy_init(dev); |
6889ca71 | 657 | } |
185f7d9a | 658 | |
6889ca71 MS |
659 | static int zynq_gem_remove(struct udevice *dev) |
660 | { | |
661 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
185f7d9a | 662 | |
6889ca71 MS |
663 | free(priv->phydev); |
664 | mdio_unregister(priv->bus); | |
665 | mdio_free(priv->bus); | |
185f7d9a | 666 | |
6889ca71 MS |
667 | return 0; |
668 | } | |
669 | ||
670 | static const struct eth_ops zynq_gem_ops = { | |
671 | .start = zynq_gem_init, | |
672 | .send = zynq_gem_send, | |
673 | .recv = zynq_gem_recv, | |
9d9211ac | 674 | .free_pkt = zynq_gem_free_pkt, |
6889ca71 MS |
675 | .stop = zynq_gem_halt, |
676 | .write_hwaddr = zynq_gem_setup_mac, | |
a509a1d4 | 677 | .read_rom_hwaddr = zynq_gem_read_rom_mac, |
6889ca71 | 678 | }; |
c8e29271 | 679 | |
6889ca71 MS |
680 | static int zynq_gem_ofdata_to_platdata(struct udevice *dev) |
681 | { | |
682 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
683 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
3cdb1450 | 684 | const char *phy_mode; |
6889ca71 MS |
685 | |
686 | pdata->iobase = (phys_addr_t)dev_get_addr(dev); | |
687 | priv->iobase = (struct zynq_gem_regs *)pdata->iobase; | |
688 | /* Hardcode for now */ | |
689 | priv->emio = 0; | |
bcdfef7a | 690 | priv->phyaddr = -1; |
6889ca71 | 691 | |
20671a98 DM |
692 | priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, |
693 | dev->of_offset, "phy-handle"); | |
694 | if (priv->phy_of_handle > 0) | |
695 | priv->phyaddr = fdtdec_get_int(gd->fdt_blob, | |
696 | priv->phy_of_handle, "reg", -1); | |
6889ca71 | 697 | |
3cdb1450 MS |
698 | phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); |
699 | if (phy_mode) | |
700 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
701 | if (pdata->phy_interface == -1) { | |
702 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
703 | return -EINVAL; | |
704 | } | |
705 | priv->interface = pdata->phy_interface; | |
706 | ||
a06c341f SDPP |
707 | priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); |
708 | ||
3cdb1450 MS |
709 | printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, |
710 | priv->phyaddr, phy_string_for_interface(priv->interface)); | |
6889ca71 MS |
711 | |
712 | return 0; | |
185f7d9a | 713 | } |
6889ca71 MS |
714 | |
715 | static const struct udevice_id zynq_gem_ids[] = { | |
716 | { .compatible = "cdns,zynqmp-gem" }, | |
717 | { .compatible = "cdns,zynq-gem" }, | |
718 | { .compatible = "cdns,gem" }, | |
719 | { } | |
720 | }; | |
721 | ||
722 | U_BOOT_DRIVER(zynq_gem) = { | |
723 | .name = "zynq_gem", | |
724 | .id = UCLASS_ETH, | |
725 | .of_match = zynq_gem_ids, | |
726 | .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, | |
727 | .probe = zynq_gem_probe, | |
728 | .remove = zynq_gem_remove, | |
729 | .ops = &zynq_gem_ops, | |
730 | .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), | |
731 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
732 | }; |