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185f7d9a MS |
1 | /* |
2 | * (C) Copyright 2011 Michal Simek | |
3 | * | |
4 | * Michal SIMEK <monstr@monstr.eu> | |
5 | * | |
6 | * Based on Xilinx gmac driver: | |
7 | * (C) Copyright 2011 Xilinx | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
185f7d9a MS |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <net.h> | |
2fd2489b | 14 | #include <netdev.h> |
185f7d9a | 15 | #include <config.h> |
f88a6869 MS |
16 | #include <fdtdec.h> |
17 | #include <libfdt.h> | |
185f7d9a MS |
18 | #include <malloc.h> |
19 | #include <asm/io.h> | |
20 | #include <phy.h> | |
21 | #include <miiphy.h> | |
22 | #include <watchdog.h> | |
01fbf310 | 23 | #include <asm/arch/hardware.h> |
80243528 | 24 | #include <asm/arch/sys_proto.h> |
185f7d9a MS |
25 | |
26 | #if !defined(CONFIG_PHYLIB) | |
27 | # error XILINX_GEM_ETHERNET requires PHYLIB | |
28 | #endif | |
29 | ||
30 | /* Bit/mask specification */ | |
31 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ | |
32 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ | |
33 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ | |
34 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ | |
35 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ | |
36 | ||
37 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ | |
38 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ | |
39 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ | |
40 | ||
41 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ | |
42 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ | |
43 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ | |
44 | ||
45 | /* Wrap bit, last descriptor */ | |
46 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 | |
47 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ | |
48 | ||
185f7d9a MS |
49 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
50 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ | |
51 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ | |
52 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ | |
53 | ||
80243528 MS |
54 | #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ |
55 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ | |
56 | #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ | |
57 | #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ | |
185f7d9a | 58 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ |
80243528 | 59 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ |
185f7d9a | 60 | |
8a584c8a SDPP |
61 | #ifdef CONFIG_ARM64 |
62 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ | |
63 | #else | |
64 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ | |
65 | #endif | |
66 | ||
67 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ | |
68 | ZYNQ_GEM_NWCFG_FDEN | \ | |
185f7d9a MS |
69 | ZYNQ_GEM_NWCFG_FSREM | \ |
70 | ZYNQ_GEM_NWCFG_MDCCLKDIV) | |
71 | ||
72 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ | |
73 | ||
74 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ | |
75 | /* Use full configured addressable space (8 Kb) */ | |
76 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 | |
77 | /* Use full configured addressable space (4 Kb) */ | |
78 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 | |
79 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ | |
80 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 | |
81 | ||
82 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ | |
83 | ZYNQ_GEM_DMACR_RXSIZE | \ | |
84 | ZYNQ_GEM_DMACR_TXSIZE | \ | |
85 | ZYNQ_GEM_DMACR_RXBUF) | |
86 | ||
f97d7e8b MS |
87 | /* Use MII register 1 (MII status register) to detect PHY */ |
88 | #define PHY_DETECT_REG 1 | |
89 | ||
90 | /* Mask used to verify certain PHY features (or register contents) | |
91 | * in the register above: | |
92 | * 0x1000: 10Mbps full duplex support | |
93 | * 0x0800: 10Mbps half duplex support | |
94 | * 0x0008: Auto-negotiation support | |
95 | */ | |
96 | #define PHY_DETECT_MASK 0x1808 | |
97 | ||
a5144237 ST |
98 | /* TX BD status masks */ |
99 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff | |
100 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 | |
101 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 | |
102 | ||
97598fcf SB |
103 | /* Clock frequencies for different speeds */ |
104 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL | |
105 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL | |
106 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL | |
107 | ||
185f7d9a MS |
108 | /* Device registers */ |
109 | struct zynq_gem_regs { | |
110 | u32 nwctrl; /* Network Control reg */ | |
111 | u32 nwcfg; /* Network Config reg */ | |
112 | u32 nwsr; /* Network Status reg */ | |
113 | u32 reserved1; | |
114 | u32 dmacr; /* DMA Control reg */ | |
115 | u32 txsr; /* TX Status reg */ | |
116 | u32 rxqbase; /* RX Q Base address reg */ | |
117 | u32 txqbase; /* TX Q Base address reg */ | |
118 | u32 rxsr; /* RX Status reg */ | |
119 | u32 reserved2[2]; | |
120 | u32 idr; /* Interrupt Disable reg */ | |
121 | u32 reserved3; | |
122 | u32 phymntnc; /* Phy Maintaince reg */ | |
123 | u32 reserved4[18]; | |
124 | u32 hashl; /* Hash Low address reg */ | |
125 | u32 hashh; /* Hash High address reg */ | |
126 | #define LADDR_LOW 0 | |
127 | #define LADDR_HIGH 1 | |
128 | u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ | |
129 | u32 match[4]; /* Type ID1 Match reg */ | |
130 | u32 reserved6[18]; | |
131 | u32 stat[44]; /* Octects transmitted Low reg - stat start */ | |
132 | }; | |
133 | ||
134 | /* BD descriptors */ | |
135 | struct emac_bd { | |
136 | u32 addr; /* Next descriptor pointer */ | |
137 | u32 status; | |
138 | }; | |
139 | ||
140 | #define RX_BUF 3 | |
a5144237 ST |
141 | /* Page table entries are set to 1MB, or multiples of 1MB |
142 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
143 | */ | |
144 | #define BD_SPACE 0x100000 | |
145 | /* BD separation space */ | |
146 | #define BD_SEPRN_SPACE 64 | |
185f7d9a MS |
147 | |
148 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ | |
149 | struct zynq_gem_priv { | |
a5144237 ST |
150 | struct emac_bd *tx_bd; |
151 | struct emac_bd *rx_bd; | |
152 | char *rxbuffers; | |
185f7d9a MS |
153 | u32 rxbd_current; |
154 | u32 rx_first_buf; | |
155 | int phyaddr; | |
01fbf310 | 156 | u32 emio; |
05868759 | 157 | int init; |
185f7d9a MS |
158 | struct phy_device *phydev; |
159 | struct mii_dev *bus; | |
160 | }; | |
161 | ||
162 | static inline int mdio_wait(struct eth_device *dev) | |
163 | { | |
164 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
165 | u32 timeout = 200; | |
166 | ||
167 | /* Wait till MDIO interface is ready to accept a new transaction. */ | |
168 | while (--timeout) { | |
169 | if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) | |
170 | break; | |
171 | WATCHDOG_RESET(); | |
172 | } | |
173 | ||
174 | if (!timeout) { | |
175 | printf("%s: Timeout\n", __func__); | |
176 | return 1; | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, | |
183 | u32 op, u16 *data) | |
184 | { | |
185 | u32 mgtcr; | |
186 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
187 | ||
188 | if (mdio_wait(dev)) | |
189 | return 1; | |
190 | ||
191 | /* Construct mgtcr mask for the operation */ | |
192 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | | |
193 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | | |
194 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; | |
195 | ||
196 | /* Write mgtcr and wait for completion */ | |
197 | writel(mgtcr, ®s->phymntnc); | |
198 | ||
199 | if (mdio_wait(dev)) | |
200 | return 1; | |
201 | ||
202 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) | |
203 | *data = readl(®s->phymntnc); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) | |
209 | { | |
210 | return phy_setup_op(dev, phy_addr, regnum, | |
211 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); | |
212 | } | |
213 | ||
214 | static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) | |
215 | { | |
216 | return phy_setup_op(dev, phy_addr, regnum, | |
217 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); | |
218 | } | |
219 | ||
f97d7e8b MS |
220 | static void phy_detection(struct eth_device *dev) |
221 | { | |
222 | int i; | |
223 | u16 phyreg; | |
224 | struct zynq_gem_priv *priv = dev->priv; | |
225 | ||
226 | if (priv->phyaddr != -1) { | |
227 | phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); | |
228 | if ((phyreg != 0xFFFF) && | |
229 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
230 | /* Found a valid PHY address */ | |
231 | debug("Default phy address %d is valid\n", | |
232 | priv->phyaddr); | |
233 | return; | |
234 | } else { | |
235 | debug("PHY address is not setup correctly %d\n", | |
236 | priv->phyaddr); | |
237 | priv->phyaddr = -1; | |
238 | } | |
239 | } | |
240 | ||
241 | debug("detecting phy address\n"); | |
242 | if (priv->phyaddr == -1) { | |
243 | /* detect the PHY address */ | |
244 | for (i = 31; i >= 0; i--) { | |
245 | phyread(dev, i, PHY_DETECT_REG, &phyreg); | |
246 | if ((phyreg != 0xFFFF) && | |
247 | ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { | |
248 | /* Found a valid PHY address */ | |
249 | priv->phyaddr = i; | |
250 | debug("Found valid phy address, %d\n", i); | |
251 | return; | |
252 | } | |
253 | } | |
254 | } | |
255 | printf("PHY is not detected\n"); | |
256 | } | |
257 | ||
185f7d9a MS |
258 | static int zynq_gem_setup_mac(struct eth_device *dev) |
259 | { | |
260 | u32 i, macaddrlow, macaddrhigh; | |
261 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
262 | ||
263 | /* Set the MAC bits [31:0] in BOT */ | |
264 | macaddrlow = dev->enetaddr[0]; | |
265 | macaddrlow |= dev->enetaddr[1] << 8; | |
266 | macaddrlow |= dev->enetaddr[2] << 16; | |
267 | macaddrlow |= dev->enetaddr[3] << 24; | |
268 | ||
269 | /* Set MAC bits [47:32] in TOP */ | |
270 | macaddrhigh = dev->enetaddr[4]; | |
271 | macaddrhigh |= dev->enetaddr[5] << 8; | |
272 | ||
273 | for (i = 0; i < 4; i++) { | |
274 | writel(0, ®s->laddr[i][LADDR_LOW]); | |
275 | writel(0, ®s->laddr[i][LADDR_HIGH]); | |
276 | /* Do not use MATCHx register */ | |
277 | writel(0, ®s->match[i]); | |
278 | } | |
279 | ||
280 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); | |
281 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | static int zynq_gem_init(struct eth_device *dev, bd_t * bis) | |
287 | { | |
97598fcf SB |
288 | u32 i; |
289 | unsigned long clk_rate = 0; | |
185f7d9a MS |
290 | struct phy_device *phydev; |
291 | const u32 stat_size = (sizeof(struct zynq_gem_regs) - | |
292 | offsetof(struct zynq_gem_regs, stat)) / 4; | |
293 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
294 | struct zynq_gem_priv *priv = dev->priv; | |
295 | const u32 supported = SUPPORTED_10baseT_Half | | |
296 | SUPPORTED_10baseT_Full | | |
297 | SUPPORTED_100baseT_Half | | |
298 | SUPPORTED_100baseT_Full | | |
299 | SUPPORTED_1000baseT_Half | | |
300 | SUPPORTED_1000baseT_Full; | |
301 | ||
05868759 MS |
302 | if (!priv->init) { |
303 | /* Disable all interrupts */ | |
304 | writel(0xFFFFFFFF, ®s->idr); | |
305 | ||
306 | /* Disable the receiver & transmitter */ | |
307 | writel(0, ®s->nwctrl); | |
308 | writel(0, ®s->txsr); | |
309 | writel(0, ®s->rxsr); | |
310 | writel(0, ®s->phymntnc); | |
311 | ||
312 | /* Clear the Hash registers for the mac address | |
313 | * pointed by AddressPtr | |
314 | */ | |
315 | writel(0x0, ®s->hashl); | |
316 | /* Write bits [63:32] in TOP */ | |
317 | writel(0x0, ®s->hashh); | |
318 | ||
319 | /* Clear all counters */ | |
320 | for (i = 0; i <= stat_size; i++) | |
321 | readl(®s->stat[i]); | |
322 | ||
323 | /* Setup RxBD space */ | |
a5144237 | 324 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
05868759 MS |
325 | |
326 | for (i = 0; i < RX_BUF; i++) { | |
327 | priv->rx_bd[i].status = 0xF0000000; | |
328 | priv->rx_bd[i].addr = | |
a5144237 | 329 | ((u32)(priv->rxbuffers) + |
185f7d9a | 330 | (i * PKTSIZE_ALIGN)); |
05868759 MS |
331 | } |
332 | /* WRAP bit to last BD */ | |
333 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; | |
334 | /* Write RxBDs to IP */ | |
a5144237 | 335 | writel((u32)priv->rx_bd, ®s->rxqbase); |
185f7d9a | 336 | |
05868759 MS |
337 | /* Setup for DMA Configuration register */ |
338 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); | |
185f7d9a | 339 | |
05868759 | 340 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
80243528 | 341 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
185f7d9a | 342 | |
05868759 MS |
343 | priv->init++; |
344 | } | |
345 | ||
f97d7e8b MS |
346 | phy_detection(dev); |
347 | ||
185f7d9a | 348 | /* interface - look at tsec */ |
c1a9fa4b MS |
349 | phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
350 | PHY_INTERFACE_MODE_MII); | |
185f7d9a | 351 | |
80243528 MS |
352 | phydev->supported = supported | ADVERTISED_Pause | |
353 | ADVERTISED_Asym_Pause; | |
185f7d9a MS |
354 | phydev->advertising = phydev->supported; |
355 | priv->phydev = phydev; | |
356 | phy_config(phydev); | |
357 | phy_startup(phydev); | |
358 | ||
4ed4aa20 MS |
359 | if (!phydev->link) { |
360 | printf("%s: No link.\n", phydev->dev->name); | |
361 | return -1; | |
362 | } | |
363 | ||
80243528 MS |
364 | switch (phydev->speed) { |
365 | case SPEED_1000: | |
366 | writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, | |
367 | ®s->nwcfg); | |
97598fcf | 368 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
80243528 MS |
369 | break; |
370 | case SPEED_100: | |
371 | clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, | |
372 | ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); | |
97598fcf | 373 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
80243528 MS |
374 | break; |
375 | case SPEED_10: | |
97598fcf | 376 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
80243528 MS |
377 | break; |
378 | } | |
01fbf310 DA |
379 | |
380 | /* Change the rclk and clk only not using EMIO interface */ | |
381 | if (!priv->emio) | |
382 | zynq_slcr_gem_clk_setup(dev->iobase != | |
97598fcf | 383 | ZYNQ_GEM_BASEADDR0, clk_rate); |
80243528 MS |
384 | |
385 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | | |
386 | ZYNQ_GEM_NWCTRL_TXEN_MASK); | |
387 | ||
185f7d9a MS |
388 | return 0; |
389 | } | |
390 | ||
391 | static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) | |
392 | { | |
a5144237 | 393 | u32 addr, size; |
185f7d9a MS |
394 | struct zynq_gem_priv *priv = dev->priv; |
395 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
185f7d9a MS |
396 | |
397 | /* setup BD */ | |
a5144237 | 398 | writel((u32)priv->tx_bd, ®s->txqbase); |
185f7d9a MS |
399 | |
400 | /* Setup Tx BD */ | |
a5144237 ST |
401 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
402 | ||
403 | priv->tx_bd->addr = (u32)ptr; | |
404 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | | |
405 | ZYNQ_GEM_TXBUF_LAST_MASK; | |
185f7d9a | 406 | |
a5144237 ST |
407 | addr = (u32) ptr; |
408 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
409 | size = roundup(len, ARCH_DMA_MINALIGN); | |
410 | flush_dcache_range(addr, addr + size); | |
411 | barrier(); | |
185f7d9a MS |
412 | |
413 | /* Start transmit */ | |
414 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); | |
415 | ||
a5144237 ST |
416 | /* Read TX BD status */ |
417 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) | |
418 | printf("TX underrun\n"); | |
419 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) | |
420 | printf("TX buffers exhausted in mid frame\n"); | |
185f7d9a | 421 | |
185f7d9a MS |
422 | return 0; |
423 | } | |
424 | ||
425 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ | |
426 | static int zynq_gem_recv(struct eth_device *dev) | |
427 | { | |
428 | int frame_len; | |
429 | struct zynq_gem_priv *priv = dev->priv; | |
430 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; | |
431 | struct emac_bd *first_bd; | |
432 | ||
433 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) | |
434 | return 0; | |
435 | ||
436 | if (!(current_bd->status & | |
437 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { | |
438 | printf("GEM: SOF or EOF not set for last buffer received!\n"); | |
439 | return 0; | |
440 | } | |
441 | ||
442 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; | |
443 | if (frame_len) { | |
a5144237 ST |
444 | u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
445 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
446 | u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); | |
447 | invalidate_dcache_range(addr, addr + size); | |
448 | ||
1fd92db8 | 449 | net_process_received_packet((u8 *)addr, frame_len); |
185f7d9a MS |
450 | |
451 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) | |
452 | priv->rx_first_buf = priv->rxbd_current; | |
453 | else { | |
454 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
455 | current_bd->status = 0xF0000000; /* FIXME */ | |
456 | } | |
457 | ||
458 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { | |
459 | first_bd = &priv->rx_bd[priv->rx_first_buf]; | |
460 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
461 | first_bd->status = 0xF0000000; | |
462 | } | |
463 | ||
464 | if ((++priv->rxbd_current) >= RX_BUF) | |
465 | priv->rxbd_current = 0; | |
185f7d9a MS |
466 | } |
467 | ||
3b90d0af | 468 | return frame_len; |
185f7d9a MS |
469 | } |
470 | ||
471 | static void zynq_gem_halt(struct eth_device *dev) | |
472 | { | |
473 | struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; | |
474 | ||
80243528 MS |
475 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
476 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); | |
185f7d9a MS |
477 | } |
478 | ||
479 | static int zynq_gem_miiphyread(const char *devname, uchar addr, | |
480 | uchar reg, ushort *val) | |
481 | { | |
482 | struct eth_device *dev = eth_get_dev(); | |
483 | int ret; | |
484 | ||
485 | ret = phyread(dev, addr, reg, val); | |
486 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); | |
487 | return ret; | |
488 | } | |
489 | ||
490 | static int zynq_gem_miiphy_write(const char *devname, uchar addr, | |
491 | uchar reg, ushort val) | |
492 | { | |
493 | struct eth_device *dev = eth_get_dev(); | |
494 | ||
495 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); | |
496 | return phywrite(dev, addr, reg, val); | |
497 | } | |
498 | ||
58405378 MS |
499 | int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, |
500 | int phy_addr, u32 emio) | |
185f7d9a MS |
501 | { |
502 | struct eth_device *dev; | |
503 | struct zynq_gem_priv *priv; | |
a5144237 | 504 | void *bd_space; |
185f7d9a MS |
505 | |
506 | dev = calloc(1, sizeof(*dev)); | |
507 | if (dev == NULL) | |
508 | return -1; | |
509 | ||
510 | dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); | |
511 | if (dev->priv == NULL) { | |
512 | free(dev); | |
513 | return -1; | |
514 | } | |
515 | priv = dev->priv; | |
516 | ||
a5144237 ST |
517 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
518 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); | |
519 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); | |
520 | ||
521 | /* Align bd_space to 1MB */ | |
522 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); | |
9ce1edc8 MS |
523 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
524 | BD_SPACE, DCACHE_OFF); | |
a5144237 ST |
525 | |
526 | /* Initialize the bd spaces for tx and rx bd's */ | |
527 | priv->tx_bd = (struct emac_bd *)bd_space; | |
528 | priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); | |
529 | ||
117cd4cc | 530 | priv->phyaddr = phy_addr; |
01fbf310 | 531 | priv->emio = emio; |
185f7d9a | 532 | |
58405378 | 533 | sprintf(dev->name, "Gem.%lx", base_addr); |
185f7d9a MS |
534 | |
535 | dev->iobase = base_addr; | |
536 | ||
537 | dev->init = zynq_gem_init; | |
538 | dev->halt = zynq_gem_halt; | |
539 | dev->send = zynq_gem_send; | |
540 | dev->recv = zynq_gem_recv; | |
541 | dev->write_hwaddr = zynq_gem_setup_mac; | |
542 | ||
543 | eth_register(dev); | |
544 | ||
545 | miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); | |
546 | priv->bus = miiphy_get_dev_by_name(dev->name); | |
547 | ||
548 | return 1; | |
549 | } | |
f88a6869 MS |
550 | |
551 | #ifdef CONFIG_OF_CONTROL | |
552 | int zynq_gem_of_init(const void *blob) | |
553 | { | |
554 | int offset = 0; | |
555 | u32 ret = 0; | |
556 | u32 reg, phy_reg; | |
557 | ||
558 | debug("ZYNQ GEM: Initialization\n"); | |
559 | ||
560 | do { | |
561 | offset = fdt_node_offset_by_compatible(blob, offset, | |
562 | "xlnx,ps7-ethernet-1.00.a"); | |
563 | if (offset != -1) { | |
564 | reg = fdtdec_get_addr(blob, offset, "reg"); | |
565 | if (reg != FDT_ADDR_T_NONE) { | |
566 | offset = fdtdec_lookup_phandle(blob, offset, | |
567 | "phy-handle"); | |
568 | if (offset != -1) | |
569 | phy_reg = fdtdec_get_addr(blob, offset, | |
570 | "reg"); | |
571 | else | |
572 | phy_reg = 0; | |
573 | ||
574 | debug("ZYNQ GEM: addr %x, phyaddr %x\n", | |
575 | reg, phy_reg); | |
576 | ||
577 | ret |= zynq_gem_initialize(NULL, reg, | |
578 | phy_reg, 0); | |
579 | ||
580 | } else { | |
581 | debug("ZYNQ GEM: Can't get base address\n"); | |
582 | return -1; | |
583 | } | |
584 | } | |
585 | } while (offset != -1); | |
586 | ||
587 | return ret; | |
588 | } | |
589 | #endif |