]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
185f7d9a MS |
2 | /* |
3 | * (C) Copyright 2011 Michal Simek | |
4 | * | |
5 | * Michal SIMEK <monstr@monstr.eu> | |
6 | * | |
7 | * Based on Xilinx gmac driver: | |
8 | * (C) Copyright 2011 Xilinx | |
185f7d9a MS |
9 | */ |
10 | ||
a765bdd1 | 11 | #include <clk.h> |
185f7d9a | 12 | #include <common.h> |
1eb69ae4 | 13 | #include <cpu_func.h> |
6889ca71 | 14 | #include <dm.h> |
185f7d9a | 15 | #include <net.h> |
2fd2489b | 16 | #include <netdev.h> |
185f7d9a | 17 | #include <config.h> |
b8de29fe | 18 | #include <console.h> |
185f7d9a | 19 | #include <malloc.h> |
90526e9f | 20 | #include <asm/cache.h> |
185f7d9a MS |
21 | #include <asm/io.h> |
22 | #include <phy.h> | |
23 | #include <miiphy.h> | |
e7138b34 | 24 | #include <wait_bit.h> |
185f7d9a | 25 | #include <watchdog.h> |
96f4f149 | 26 | #include <asm/system.h> |
01fbf310 | 27 | #include <asm/arch/hardware.h> |
80243528 | 28 | #include <asm/arch/sys_proto.h> |
336d4615 | 29 | #include <dm/device_compat.h> |
61b29b82 | 30 | #include <linux/err.h> |
5d97dff0 | 31 | #include <linux/errno.h> |
185f7d9a | 32 | |
185f7d9a MS |
33 | /* Bit/mask specification */ |
34 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ | |
35 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ | |
36 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ | |
37 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ | |
38 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ | |
39 | ||
40 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ | |
41 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ | |
42 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ | |
43 | ||
44 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ | |
45 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ | |
46 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ | |
47 | ||
48 | /* Wrap bit, last descriptor */ | |
49 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 | |
50 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ | |
23a598f7 | 51 | #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ |
185f7d9a | 52 | |
185f7d9a MS |
53 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
54 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ | |
55 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ | |
56 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ | |
57 | ||
27183d7c SDPP |
58 | #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ |
59 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ | |
60 | #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ | |
61 | #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ | |
4eaf8f54 | 62 | #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ |
27183d7c | 63 | #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ |
f17ea71d | 64 | #ifdef CONFIG_ARM64 |
27183d7c | 65 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ |
f17ea71d | 66 | #else |
27183d7c | 67 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ |
f17ea71d | 68 | #endif |
185f7d9a | 69 | |
8a584c8a SDPP |
70 | #ifdef CONFIG_ARM64 |
71 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ | |
72 | #else | |
73 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ | |
74 | #endif | |
75 | ||
76 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ | |
77 | ZYNQ_GEM_NWCFG_FDEN | \ | |
185f7d9a MS |
78 | ZYNQ_GEM_NWCFG_FSREM | \ |
79 | ZYNQ_GEM_NWCFG_MDCCLKDIV) | |
80 | ||
81 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ | |
82 | ||
83 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ | |
84 | /* Use full configured addressable space (8 Kb) */ | |
85 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 | |
86 | /* Use full configured addressable space (4 Kb) */ | |
87 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 | |
88 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ | |
89 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 | |
90 | ||
9a7799f4 VK |
91 | #if defined(CONFIG_PHYS_64BIT) |
92 | # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */ | |
93 | #else | |
94 | # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */ | |
95 | #endif | |
96 | ||
185f7d9a MS |
97 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ |
98 | ZYNQ_GEM_DMACR_RXSIZE | \ | |
99 | ZYNQ_GEM_DMACR_TXSIZE | \ | |
9a7799f4 VK |
100 | ZYNQ_GEM_DMACR_RXBUF | \ |
101 | ZYNQ_GEM_DMA_BUS_WIDTH) | |
185f7d9a | 102 | |
e4d2318a MS |
103 | #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ |
104 | ||
845ee5f6 SDPP |
105 | #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 |
106 | ||
5f68f44c SDPP |
107 | #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23) |
108 | ||
f97d7e8b MS |
109 | /* Use MII register 1 (MII status register) to detect PHY */ |
110 | #define PHY_DETECT_REG 1 | |
111 | ||
112 | /* Mask used to verify certain PHY features (or register contents) | |
113 | * in the register above: | |
114 | * 0x1000: 10Mbps full duplex support | |
115 | * 0x0800: 10Mbps half duplex support | |
116 | * 0x0008: Auto-negotiation support | |
117 | */ | |
118 | #define PHY_DETECT_MASK 0x1808 | |
119 | ||
a5144237 ST |
120 | /* TX BD status masks */ |
121 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff | |
122 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 | |
123 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 | |
124 | ||
97598fcf SB |
125 | /* Clock frequencies for different speeds */ |
126 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL | |
127 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL | |
128 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL | |
129 | ||
185f7d9a MS |
130 | /* Device registers */ |
131 | struct zynq_gem_regs { | |
97a51a03 MS |
132 | u32 nwctrl; /* 0x0 - Network Control reg */ |
133 | u32 nwcfg; /* 0x4 - Network Config reg */ | |
134 | u32 nwsr; /* 0x8 - Network Status reg */ | |
185f7d9a | 135 | u32 reserved1; |
97a51a03 MS |
136 | u32 dmacr; /* 0x10 - DMA Control reg */ |
137 | u32 txsr; /* 0x14 - TX Status reg */ | |
138 | u32 rxqbase; /* 0x18 - RX Q Base address reg */ | |
139 | u32 txqbase; /* 0x1c - TX Q Base address reg */ | |
140 | u32 rxsr; /* 0x20 - RX Status reg */ | |
185f7d9a | 141 | u32 reserved2[2]; |
97a51a03 | 142 | u32 idr; /* 0x2c - Interrupt Disable reg */ |
185f7d9a | 143 | u32 reserved3; |
97a51a03 | 144 | u32 phymntnc; /* 0x34 - Phy Maintaince reg */ |
185f7d9a | 145 | u32 reserved4[18]; |
97a51a03 MS |
146 | u32 hashl; /* 0x80 - Hash Low address reg */ |
147 | u32 hashh; /* 0x84 - Hash High address reg */ | |
185f7d9a MS |
148 | #define LADDR_LOW 0 |
149 | #define LADDR_HIGH 1 | |
97a51a03 MS |
150 | u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ |
151 | u32 match[4]; /* 0xa8 - Type ID1 Match reg */ | |
185f7d9a | 152 | u32 reserved6[18]; |
0ebf4041 MS |
153 | #define STAT_SIZE 44 |
154 | u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ | |
845ee5f6 SDPP |
155 | u32 reserved9[20]; |
156 | u32 pcscntrl; | |
5f68f44c SDPP |
157 | u32 rserved12[36]; |
158 | u32 dcfg6; /* 0x294 Design config reg6 */ | |
159 | u32 reserved7[106]; | |
603ff008 EI |
160 | u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ |
161 | u32 reserved8[15]; | |
162 | u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ | |
9a7799f4 VK |
163 | u32 reserved10[17]; |
164 | u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */ | |
165 | u32 reserved11[2]; | |
166 | u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */ | |
185f7d9a MS |
167 | }; |
168 | ||
169 | /* BD descriptors */ | |
170 | struct emac_bd { | |
171 | u32 addr; /* Next descriptor pointer */ | |
172 | u32 status; | |
9a7799f4 VK |
173 | #if defined(CONFIG_PHYS_64BIT) |
174 | u32 addr_hi; | |
175 | u32 reserved; | |
176 | #endif | |
185f7d9a MS |
177 | }; |
178 | ||
8af4c4dc | 179 | /* Reduce amount of BUFs if you have limited amount of memory */ |
eda9d307 | 180 | #define RX_BUF 32 |
a5144237 ST |
181 | /* Page table entries are set to 1MB, or multiples of 1MB |
182 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
183 | */ | |
184 | #define BD_SPACE 0x100000 | |
185 | /* BD separation space */ | |
ff475878 | 186 | #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) |
185f7d9a | 187 | |
603ff008 EI |
188 | /* Setup the first free TX descriptor */ |
189 | #define TX_FREE_DESC 2 | |
190 | ||
185f7d9a MS |
191 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ |
192 | struct zynq_gem_priv { | |
a5144237 ST |
193 | struct emac_bd *tx_bd; |
194 | struct emac_bd *rx_bd; | |
195 | char *rxbuffers; | |
185f7d9a MS |
196 | u32 rxbd_current; |
197 | u32 rx_first_buf; | |
198 | int phyaddr; | |
05868759 | 199 | int init; |
f2fc2768 | 200 | struct zynq_gem_regs *iobase; |
25de8a8d | 201 | struct zynq_gem_regs *mdiobase; |
16ce6de8 | 202 | phy_interface_t interface; |
185f7d9a | 203 | struct phy_device *phydev; |
26026e69 | 204 | ofnode phy_of_node; |
185f7d9a | 205 | struct mii_dev *bus; |
a765bdd1 | 206 | struct clk clk; |
69065e8f | 207 | u32 max_speed; |
dd12a27c | 208 | bool int_pcs; |
5f68f44c | 209 | bool dma_64bit; |
185f7d9a MS |
210 | }; |
211 | ||
b33d4a5f | 212 | static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
f2fc2768 | 213 | u32 op, u16 *data) |
185f7d9a MS |
214 | { |
215 | u32 mgtcr; | |
25de8a8d | 216 | struct zynq_gem_regs *regs = priv->mdiobase; |
b908fcad | 217 | int err; |
185f7d9a | 218 | |
48263504 ÁFR |
219 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
220 | true, 20000, false); | |
b908fcad MS |
221 | if (err) |
222 | return err; | |
185f7d9a MS |
223 | |
224 | /* Construct mgtcr mask for the operation */ | |
225 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | | |
226 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | | |
227 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; | |
228 | ||
229 | /* Write mgtcr and wait for completion */ | |
230 | writel(mgtcr, ®s->phymntnc); | |
231 | ||
48263504 ÁFR |
232 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
233 | true, 20000, false); | |
b908fcad MS |
234 | if (err) |
235 | return err; | |
185f7d9a MS |
236 | |
237 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) | |
238 | *data = readl(®s->phymntnc); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
b33d4a5f | 243 | static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
f2fc2768 | 244 | u32 regnum, u16 *val) |
185f7d9a | 245 | { |
b33d4a5f | 246 | int ret; |
198e9a4f | 247 | |
f2fc2768 MS |
248 | ret = phy_setup_op(priv, phy_addr, regnum, |
249 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); | |
198e9a4f MS |
250 | |
251 | if (!ret) | |
252 | debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, | |
253 | phy_addr, regnum, *val); | |
254 | ||
255 | return ret; | |
185f7d9a MS |
256 | } |
257 | ||
b33d4a5f | 258 | static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
f2fc2768 | 259 | u32 regnum, u16 data) |
185f7d9a | 260 | { |
198e9a4f MS |
261 | debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
262 | regnum, data); | |
263 | ||
f2fc2768 MS |
264 | return phy_setup_op(priv, phy_addr, regnum, |
265 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); | |
185f7d9a MS |
266 | } |
267 | ||
6889ca71 | 268 | static int zynq_gem_setup_mac(struct udevice *dev) |
185f7d9a MS |
269 | { |
270 | u32 i, macaddrlow, macaddrhigh; | |
6889ca71 MS |
271 | struct eth_pdata *pdata = dev_get_platdata(dev); |
272 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
273 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a MS |
274 | |
275 | /* Set the MAC bits [31:0] in BOT */ | |
6889ca71 MS |
276 | macaddrlow = pdata->enetaddr[0]; |
277 | macaddrlow |= pdata->enetaddr[1] << 8; | |
278 | macaddrlow |= pdata->enetaddr[2] << 16; | |
279 | macaddrlow |= pdata->enetaddr[3] << 24; | |
185f7d9a MS |
280 | |
281 | /* Set MAC bits [47:32] in TOP */ | |
6889ca71 MS |
282 | macaddrhigh = pdata->enetaddr[4]; |
283 | macaddrhigh |= pdata->enetaddr[5] << 8; | |
185f7d9a MS |
284 | |
285 | for (i = 0; i < 4; i++) { | |
286 | writel(0, ®s->laddr[i][LADDR_LOW]); | |
287 | writel(0, ®s->laddr[i][LADDR_HIGH]); | |
288 | /* Do not use MATCHx register */ | |
289 | writel(0, ®s->match[i]); | |
290 | } | |
291 | ||
292 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); | |
293 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
6889ca71 | 298 | static int zynq_phy_init(struct udevice *dev) |
185f7d9a | 299 | { |
b904725a | 300 | int ret; |
6889ca71 | 301 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
25de8a8d | 302 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
185f7d9a MS |
303 | const u32 supported = SUPPORTED_10baseT_Half | |
304 | SUPPORTED_10baseT_Full | | |
305 | SUPPORTED_100baseT_Half | | |
306 | SUPPORTED_100baseT_Full | | |
307 | SUPPORTED_1000baseT_Half | | |
308 | SUPPORTED_1000baseT_Full; | |
309 | ||
c8e29271 | 310 | /* Enable only MDIO bus */ |
25de8a8d | 311 | writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); |
c8e29271 | 312 | |
68cc3bd8 MS |
313 | priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
314 | priv->interface); | |
90c6f2e2 MS |
315 | if (!priv->phydev) |
316 | return -ENODEV; | |
68cc3bd8 | 317 | |
69065e8f SDPP |
318 | if (priv->max_speed) { |
319 | ret = phy_set_supported(priv->phydev, priv->max_speed); | |
320 | if (ret) | |
321 | return ret; | |
322 | } | |
323 | ||
51c019ff SDPP |
324 | priv->phydev->supported &= supported | ADVERTISED_Pause | |
325 | ADVERTISED_Asym_Pause; | |
326 | ||
68cc3bd8 | 327 | priv->phydev->advertising = priv->phydev->supported; |
26026e69 | 328 | priv->phydev->node = priv->phy_of_node; |
20671a98 | 329 | |
7a673f0b | 330 | return phy_config(priv->phydev); |
68cc3bd8 MS |
331 | } |
332 | ||
6889ca71 | 333 | static int zynq_gem_init(struct udevice *dev) |
68cc3bd8 | 334 | { |
a06c341f | 335 | u32 i, nwconfig; |
55259e7c | 336 | int ret; |
68cc3bd8 | 337 | unsigned long clk_rate = 0; |
6889ca71 MS |
338 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
339 | struct zynq_gem_regs *regs = priv->iobase; | |
25de8a8d | 340 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
68cc3bd8 MS |
341 | struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
342 | struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; | |
343 | ||
5f68f44c SDPP |
344 | if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B) |
345 | priv->dma_64bit = true; | |
346 | else | |
347 | priv->dma_64bit = false; | |
348 | ||
349 | #if defined(CONFIG_PHYS_64BIT) | |
350 | if (!priv->dma_64bit) { | |
351 | printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n", | |
352 | __func__); | |
353 | return -EINVAL; | |
354 | } | |
355 | #else | |
356 | if (priv->dma_64bit) | |
357 | debug("WARN: %s: Not using 64-bit dma even HW supports it\n", | |
358 | __func__); | |
359 | #endif | |
360 | ||
05868759 MS |
361 | if (!priv->init) { |
362 | /* Disable all interrupts */ | |
363 | writel(0xFFFFFFFF, ®s->idr); | |
364 | ||
365 | /* Disable the receiver & transmitter */ | |
366 | writel(0, ®s->nwctrl); | |
367 | writel(0, ®s->txsr); | |
368 | writel(0, ®s->rxsr); | |
369 | writel(0, ®s->phymntnc); | |
370 | ||
371 | /* Clear the Hash registers for the mac address | |
372 | * pointed by AddressPtr | |
373 | */ | |
374 | writel(0x0, ®s->hashl); | |
375 | /* Write bits [63:32] in TOP */ | |
376 | writel(0x0, ®s->hashh); | |
377 | ||
378 | /* Clear all counters */ | |
0ebf4041 | 379 | for (i = 0; i < STAT_SIZE; i++) |
05868759 MS |
380 | readl(®s->stat[i]); |
381 | ||
382 | /* Setup RxBD space */ | |
a5144237 | 383 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
05868759 MS |
384 | |
385 | for (i = 0; i < RX_BUF; i++) { | |
386 | priv->rx_bd[i].status = 0xF0000000; | |
387 | priv->rx_bd[i].addr = | |
9a7799f4 VK |
388 | (lower_32_bits((ulong)(priv->rxbuffers) |
389 | + (i * PKTSIZE_ALIGN))); | |
390 | #if defined(CONFIG_PHYS_64BIT) | |
391 | priv->rx_bd[i].addr_hi = | |
392 | (upper_32_bits((ulong)(priv->rxbuffers) | |
393 | + (i * PKTSIZE_ALIGN))); | |
394 | #endif | |
395 | } | |
05868759 MS |
396 | /* WRAP bit to last BD */ |
397 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; | |
398 | /* Write RxBDs to IP */ | |
9a7799f4 VK |
399 | writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase); |
400 | #if defined(CONFIG_PHYS_64BIT) | |
401 | writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase); | |
402 | #endif | |
185f7d9a | 403 | |
05868759 MS |
404 | /* Setup for DMA Configuration register */ |
405 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); | |
185f7d9a | 406 | |
05868759 | 407 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
25de8a8d | 408 | setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
185f7d9a | 409 | |
603ff008 EI |
410 | /* Disable the second priority queue */ |
411 | dummy_tx_bd->addr = 0; | |
9a7799f4 VK |
412 | #if defined(CONFIG_PHYS_64BIT) |
413 | dummy_tx_bd->addr_hi = 0; | |
414 | #endif | |
603ff008 EI |
415 | dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
416 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
417 | ZYNQ_GEM_TXBUF_USED_MASK; | |
418 | ||
419 | dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | | |
420 | ZYNQ_GEM_RXBUF_NEW_MASK; | |
9a7799f4 VK |
421 | #if defined(CONFIG_PHYS_64BIT) |
422 | dummy_rx_bd->addr_hi = 0; | |
423 | #endif | |
603ff008 | 424 | dummy_rx_bd->status = 0; |
603ff008 EI |
425 | |
426 | writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); | |
427 | writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); | |
428 | ||
05868759 MS |
429 | priv->init++; |
430 | } | |
431 | ||
55259e7c MS |
432 | ret = phy_startup(priv->phydev); |
433 | if (ret) | |
434 | return ret; | |
185f7d9a | 435 | |
64a7ead6 MS |
436 | if (!priv->phydev->link) { |
437 | printf("%s: No link.\n", priv->phydev->dev->name); | |
4ed4aa20 MS |
438 | return -1; |
439 | } | |
440 | ||
a06c341f SDPP |
441 | nwconfig = ZYNQ_GEM_NWCFG_INIT; |
442 | ||
dd12a27c SDPP |
443 | /* |
444 | * Set SGMII enable PCS selection only if internal PCS/PMA | |
445 | * core is used and interface is SGMII. | |
446 | */ | |
447 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && | |
448 | priv->int_pcs) { | |
a06c341f SDPP |
449 | nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | |
450 | ZYNQ_GEM_NWCFG_PCS_SEL; | |
845ee5f6 SDPP |
451 | #ifdef CONFIG_ARM64 |
452 | writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, | |
453 | ®s->pcscntrl); | |
454 | #endif | |
455 | } | |
a06c341f | 456 | |
64a7ead6 | 457 | switch (priv->phydev->speed) { |
80243528 | 458 | case SPEED_1000: |
a06c341f | 459 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, |
80243528 | 460 | ®s->nwcfg); |
97598fcf | 461 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
80243528 MS |
462 | break; |
463 | case SPEED_100: | |
a06c341f | 464 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, |
242b1547 | 465 | ®s->nwcfg); |
97598fcf | 466 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
80243528 MS |
467 | break; |
468 | case SPEED_10: | |
97598fcf | 469 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
80243528 MS |
470 | break; |
471 | } | |
01fbf310 | 472 | |
eff55c55 SH |
473 | ret = clk_set_rate(&priv->clk, clk_rate); |
474 | if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { | |
475 | dev_err(dev, "failed to set tx clock rate\n"); | |
476 | return ret; | |
477 | } | |
478 | ||
479 | ret = clk_enable(&priv->clk); | |
480 | if (ret && ret != -ENOSYS) { | |
481 | dev_err(dev, "failed to enable tx clock\n"); | |
482 | return ret; | |
483 | } | |
80243528 MS |
484 | |
485 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | | |
486 | ZYNQ_GEM_NWCTRL_TXEN_MASK); | |
487 | ||
185f7d9a MS |
488 | return 0; |
489 | } | |
490 | ||
6889ca71 | 491 | static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
185f7d9a | 492 | { |
9a7799f4 VK |
493 | dma_addr_t addr; |
494 | u32 size; | |
6889ca71 MS |
495 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
496 | struct zynq_gem_regs *regs = priv->iobase; | |
23a598f7 | 497 | struct emac_bd *current_bd = &priv->tx_bd[1]; |
185f7d9a | 498 | |
185f7d9a | 499 | /* Setup Tx BD */ |
a5144237 ST |
500 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
501 | ||
9a7799f4 VK |
502 | priv->tx_bd->addr = lower_32_bits((ulong)ptr); |
503 | #if defined(CONFIG_PHYS_64BIT) | |
504 | priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr); | |
505 | #endif | |
a5144237 | 506 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | |
23a598f7 MS |
507 | ZYNQ_GEM_TXBUF_LAST_MASK; |
508 | /* Dummy descriptor to mark it as the last in descriptor chain */ | |
509 | current_bd->addr = 0x0; | |
9a7799f4 VK |
510 | #if defined(CONFIG_PHYS_64BIT) |
511 | current_bd->addr_hi = 0x0; | |
512 | #endif | |
23a598f7 MS |
513 | current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
514 | ZYNQ_GEM_TXBUF_LAST_MASK| | |
515 | ZYNQ_GEM_TXBUF_USED_MASK; | |
185f7d9a | 516 | |
45c07741 | 517 | /* setup BD */ |
9a7799f4 VK |
518 | writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase); |
519 | #if defined(CONFIG_PHYS_64BIT) | |
520 | writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase); | |
521 | #endif | |
45c07741 | 522 | |
5b47d407 | 523 | addr = (ulong) ptr; |
a5144237 ST |
524 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
525 | size = roundup(len, ARCH_DMA_MINALIGN); | |
526 | flush_dcache_range(addr, addr + size); | |
527 | barrier(); | |
185f7d9a MS |
528 | |
529 | /* Start transmit */ | |
530 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); | |
531 | ||
a5144237 | 532 | /* Read TX BD status */ |
a5144237 ST |
533 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) |
534 | printf("TX buffers exhausted in mid frame\n"); | |
185f7d9a | 535 | |
48263504 ÁFR |
536 | return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, |
537 | true, 20000, true); | |
185f7d9a MS |
538 | } |
539 | ||
540 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ | |
6889ca71 | 541 | static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
185f7d9a MS |
542 | { |
543 | int frame_len; | |
9a7799f4 | 544 | dma_addr_t addr; |
6889ca71 | 545 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
185f7d9a | 546 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
185f7d9a MS |
547 | |
548 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) | |
9d9211ac | 549 | return -1; |
185f7d9a MS |
550 | |
551 | if (!(current_bd->status & | |
552 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { | |
553 | printf("GEM: SOF or EOF not set for last buffer received!\n"); | |
9d9211ac | 554 | return -1; |
185f7d9a MS |
555 | } |
556 | ||
557 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; | |
9d9211ac MS |
558 | if (!frame_len) { |
559 | printf("%s: Zero size packet?\n", __func__); | |
560 | return -1; | |
561 | } | |
a5144237 | 562 | |
9a7799f4 VK |
563 | #if defined(CONFIG_PHYS_64BIT) |
564 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) | |
565 | | ((dma_addr_t)current_bd->addr_hi << 32)); | |
566 | #else | |
9d9211ac | 567 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
9a7799f4 | 568 | #endif |
9d9211ac | 569 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
9a7799f4 | 570 | |
9d9211ac | 571 | *packetp = (uchar *)(uintptr_t)addr; |
185f7d9a | 572 | |
10598580 ST |
573 | invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
574 | barrier(); | |
575 | ||
9d9211ac MS |
576 | return frame_len; |
577 | } | |
185f7d9a | 578 | |
9d9211ac MS |
579 | static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) |
580 | { | |
581 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
582 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; | |
583 | struct emac_bd *first_bd; | |
0f8defd8 | 584 | dma_addr_t addr; |
9d9211ac MS |
585 | |
586 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { | |
587 | priv->rx_first_buf = priv->rxbd_current; | |
588 | } else { | |
589 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
590 | current_bd->status = 0xF0000000; /* FIXME */ | |
591 | } | |
185f7d9a | 592 | |
9d9211ac MS |
593 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { |
594 | first_bd = &priv->rx_bd[priv->rx_first_buf]; | |
595 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; | |
596 | first_bd->status = 0xF0000000; | |
185f7d9a MS |
597 | } |
598 | ||
0f8defd8 ARS |
599 | /* Flush the cache for the packet as well */ |
600 | #if defined(CONFIG_PHYS_64BIT) | |
601 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) | |
602 | | ((dma_addr_t)current_bd->addr_hi << 32)); | |
603 | #else | |
604 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; | |
605 | #endif | |
606 | flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, | |
607 | ARCH_DMA_MINALIGN)); | |
608 | barrier(); | |
609 | ||
9d9211ac MS |
610 | if ((++priv->rxbd_current) >= RX_BUF) |
611 | priv->rxbd_current = 0; | |
612 | ||
da872d7c | 613 | return 0; |
185f7d9a MS |
614 | } |
615 | ||
6889ca71 | 616 | static void zynq_gem_halt(struct udevice *dev) |
185f7d9a | 617 | { |
6889ca71 MS |
618 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
619 | struct zynq_gem_regs *regs = priv->iobase; | |
185f7d9a | 620 | |
80243528 MS |
621 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
622 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); | |
185f7d9a MS |
623 | } |
624 | ||
a509a1d4 JH |
625 | __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
626 | { | |
627 | return -ENOSYS; | |
628 | } | |
629 | ||
630 | static int zynq_gem_read_rom_mac(struct udevice *dev) | |
631 | { | |
a509a1d4 JH |
632 | struct eth_pdata *pdata = dev_get_platdata(dev); |
633 | ||
b2330897 OS |
634 | if (!pdata) |
635 | return -ENOSYS; | |
a509a1d4 | 636 | |
b2330897 | 637 | return zynq_board_read_rom_ethaddr(pdata->enetaddr); |
a509a1d4 JH |
638 | } |
639 | ||
6889ca71 MS |
640 | static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
641 | int devad, int reg) | |
185f7d9a | 642 | { |
6889ca71 | 643 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 644 | int ret; |
d1b226b7 | 645 | u16 val = 0; |
185f7d9a | 646 | |
6889ca71 MS |
647 | ret = phyread(priv, addr, reg, &val); |
648 | debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); | |
649 | return val; | |
185f7d9a MS |
650 | } |
651 | ||
6889ca71 MS |
652 | static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
653 | int reg, u16 value) | |
185f7d9a | 654 | { |
6889ca71 | 655 | struct zynq_gem_priv *priv = bus->priv; |
185f7d9a | 656 | |
6889ca71 MS |
657 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
658 | return phywrite(priv, addr, reg, value); | |
185f7d9a MS |
659 | } |
660 | ||
6889ca71 | 661 | static int zynq_gem_probe(struct udevice *dev) |
185f7d9a | 662 | { |
a5144237 | 663 | void *bd_space; |
6889ca71 MS |
664 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
665 | int ret; | |
185f7d9a | 666 | |
a5144237 ST |
667 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
668 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); | |
5b2c9a6c MS |
669 | if (!priv->rxbuffers) |
670 | return -ENOMEM; | |
671 | ||
a5144237 | 672 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); |
b6779274 | 673 | ulong addr = (ulong)priv->rxbuffers; |
10598580 ST |
674 | flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
675 | barrier(); | |
a5144237 | 676 | |
96f4f149 | 677 | /* Align bd_space to MMU_SECTION_SHIFT */ |
a5144237 | 678 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); |
58ecd9ad MS |
679 | if (!bd_space) { |
680 | ret = -ENOMEM; | |
681 | goto err1; | |
682 | } | |
5b2c9a6c | 683 | |
9ce1edc8 MS |
684 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
685 | BD_SPACE, DCACHE_OFF); | |
a5144237 ST |
686 | |
687 | /* Initialize the bd spaces for tx and rx bd's */ | |
688 | priv->tx_bd = (struct emac_bd *)bd_space; | |
5b47d407 | 689 | priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
a5144237 | 690 | |
a765bdd1 SDPP |
691 | ret = clk_get_by_name(dev, "tx_clk", &priv->clk); |
692 | if (ret < 0) { | |
693 | dev_err(dev, "failed to get clock\n"); | |
58ecd9ad | 694 | goto err1; |
a765bdd1 | 695 | } |
a765bdd1 | 696 | |
6889ca71 MS |
697 | priv->bus = mdio_alloc(); |
698 | priv->bus->read = zynq_gem_miiphy_read; | |
699 | priv->bus->write = zynq_gem_miiphy_write; | |
700 | priv->bus->priv = priv; | |
185f7d9a | 701 | |
6516e3f2 | 702 | ret = mdio_register_seq(priv->bus, dev->seq); |
6889ca71 | 703 | if (ret) |
58ecd9ad | 704 | goto err2; |
185f7d9a | 705 | |
58ecd9ad MS |
706 | ret = zynq_phy_init(dev); |
707 | if (ret) | |
708 | goto err2; | |
709 | ||
710 | return ret; | |
711 | ||
712 | err2: | |
713 | free(priv->rxbuffers); | |
714 | err1: | |
715 | free(priv->tx_bd); | |
716 | return ret; | |
6889ca71 | 717 | } |
185f7d9a | 718 | |
6889ca71 MS |
719 | static int zynq_gem_remove(struct udevice *dev) |
720 | { | |
721 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
185f7d9a | 722 | |
6889ca71 MS |
723 | free(priv->phydev); |
724 | mdio_unregister(priv->bus); | |
725 | mdio_free(priv->bus); | |
185f7d9a | 726 | |
6889ca71 MS |
727 | return 0; |
728 | } | |
729 | ||
730 | static const struct eth_ops zynq_gem_ops = { | |
731 | .start = zynq_gem_init, | |
732 | .send = zynq_gem_send, | |
733 | .recv = zynq_gem_recv, | |
9d9211ac | 734 | .free_pkt = zynq_gem_free_pkt, |
6889ca71 MS |
735 | .stop = zynq_gem_halt, |
736 | .write_hwaddr = zynq_gem_setup_mac, | |
a509a1d4 | 737 | .read_rom_hwaddr = zynq_gem_read_rom_mac, |
6889ca71 | 738 | }; |
c8e29271 | 739 | |
6889ca71 MS |
740 | static int zynq_gem_ofdata_to_platdata(struct udevice *dev) |
741 | { | |
742 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
743 | struct zynq_gem_priv *priv = dev_get_priv(dev); | |
26026e69 | 744 | struct ofnode_phandle_args phandle_args; |
3cdb1450 | 745 | const char *phy_mode; |
6889ca71 | 746 | |
26026e69 | 747 | pdata->iobase = (phys_addr_t)dev_read_addr(dev); |
6889ca71 | 748 | priv->iobase = (struct zynq_gem_regs *)pdata->iobase; |
25de8a8d | 749 | priv->mdiobase = priv->iobase; |
6889ca71 | 750 | /* Hardcode for now */ |
bcdfef7a | 751 | priv->phyaddr = -1; |
6889ca71 | 752 | |
3888c8d1 MS |
753 | if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, |
754 | &phandle_args)) { | |
755 | debug("phy-handle does exist %s\n", dev->name); | |
756 | priv->phyaddr = ofnode_read_u32_default(phandle_args.node, | |
757 | "reg", -1); | |
758 | priv->phy_of_node = phandle_args.node; | |
759 | priv->max_speed = ofnode_read_u32_default(phandle_args.node, | |
760 | "max-speed", | |
761 | SPEED_1000); | |
26026e69 | 762 | } |
6889ca71 | 763 | |
26026e69 | 764 | phy_mode = dev_read_prop(dev, "phy-mode", NULL); |
3cdb1450 MS |
765 | if (phy_mode) |
766 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
767 | if (pdata->phy_interface == -1) { | |
768 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
769 | return -EINVAL; | |
770 | } | |
771 | priv->interface = pdata->phy_interface; | |
772 | ||
26026e69 | 773 | priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); |
dd12a27c | 774 | |
25de8a8d MS |
775 | printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n", |
776 | (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr, | |
777 | phy_string_for_interface(priv->interface)); | |
6889ca71 MS |
778 | |
779 | return 0; | |
185f7d9a | 780 | } |
6889ca71 MS |
781 | |
782 | static const struct udevice_id zynq_gem_ids[] = { | |
1ff8bdb8 | 783 | { .compatible = "cdns,versal-gem" }, |
6889ca71 MS |
784 | { .compatible = "cdns,zynqmp-gem" }, |
785 | { .compatible = "cdns,zynq-gem" }, | |
786 | { .compatible = "cdns,gem" }, | |
787 | { } | |
788 | }; | |
789 | ||
790 | U_BOOT_DRIVER(zynq_gem) = { | |
791 | .name = "zynq_gem", | |
792 | .id = UCLASS_ETH, | |
793 | .of_match = zynq_gem_ids, | |
794 | .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, | |
795 | .probe = zynq_gem_probe, | |
796 | .remove = zynq_gem_remove, | |
797 | .ops = &zynq_gem_ops, | |
798 | .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), | |
799 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
800 | }; |