[people/ms/u-boot.git] / drivers / net / zynq_gem.c

/*
 * (C) Copyright 2011 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * Based on Xilinx gmac driver:
 * (C) Copyright 2011 Xilinx
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>

#if !defined(CONFIG_PHYLIB)
# error XILINX_GEM_ETHERNET requires PHYLIB
#endif

/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK	0x40020000 /* operation mask bits */
#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK	0x20000000 /* read operation */
#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK	0x10000000 /* write operation */
#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK	23 /* Shift bits for PHYAD */
#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK	18 /* Shift bits for PHREG */

#define ZYNQ_GEM_RXBUF_EOF_MASK		0x00008000 /* End of frame. */
#define ZYNQ_GEM_RXBUF_SOF_MASK		0x00004000 /* Start of frame. */
#define ZYNQ_GEM_RXBUF_LEN_MASK		0x00003FFF /* Mask for length field */

#define ZYNQ_GEM_RXBUF_WRAP_MASK	0x00000002 /* Wrap bit, last BD */
#define ZYNQ_GEM_RXBUF_NEW_MASK		0x00000001 /* Used bit.. */
#define ZYNQ_GEM_RXBUF_ADD_MASK		0xFFFFFFFC /* Mask for address */

/* Wrap bit, last descriptor */
#define ZYNQ_GEM_TXBUF_WRAP_MASK	0x40000000
#define ZYNQ_GEM_TXBUF_LAST_MASK	0x00008000 /* Last buffer */

#define ZYNQ_GEM_NWCTRL_TXEN_MASK	0x00000008 /* Enable transmit */
#define ZYNQ_GEM_NWCTRL_RXEN_MASK	0x00000004 /* Enable receive */
#define ZYNQ_GEM_NWCTRL_MDEN_MASK	0x00000010 /* Enable MDIO port */
#define ZYNQ_GEM_NWCTRL_STARTTX_MASK	0x00000200 /* Start tx (tx_go) */

#define ZYNQ_GEM_NWCFG_SPEED100		0x000000001 /* 100 Mbps operation */
#define ZYNQ_GEM_NWCFG_SPEED1000	0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN		0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM		0x000020000 /* FCS removal */
#define ZYNQ_GEM_NWCFG_MDCCLKDIV	0x000080000 /* Div pclk by 32, 80MHz */
#define ZYNQ_GEM_NWCFG_MDCCLKDIV2	0x0000c0000 /* Div pclk by 48, 120MHz */

#define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_NWCFG_FDEN | \
					ZYNQ_GEM_NWCFG_FSREM | \
					ZYNQ_GEM_NWCFG_MDCCLKDIV)

#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK	0x00000004 /* PHY management idle */

#define ZYNQ_GEM_DMACR_BLENGTH		0x00000004 /* INCR4 AHB bursts */
/* Use full configured addressable space (8 Kb) */
#define ZYNQ_GEM_DMACR_RXSIZE		0x00000300
/* Use full configured addressable space (4 Kb) */
#define ZYNQ_GEM_DMACR_TXSIZE		0x00000400
/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
#define ZYNQ_GEM_DMACR_RXBUF		0x00180000

#define ZYNQ_GEM_DMACR_INIT		(ZYNQ_GEM_DMACR_BLENGTH | \
					ZYNQ_GEM_DMACR_RXSIZE | \
					ZYNQ_GEM_DMACR_TXSIZE | \
					ZYNQ_GEM_DMACR_RXBUF)

/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG  1

/* Mask used to verify certain PHY features (or register contents)
 * in the register above:
 *  0x1000: 10Mbps full duplex support
 *  0x0800: 10Mbps half duplex support
 *  0x0008: Auto-negotiation support
 */
#define PHY_DETECT_MASK 0x1808

/* TX BD status masks */
#define ZYNQ_GEM_TXBUF_FRMLEN_MASK	0x000007ff
#define ZYNQ_GEM_TXBUF_EXHAUSTED	0x08000000
#define ZYNQ_GEM_TXBUF_UNDERRUN		0x10000000

/* Device registers */
struct zynq_gem_regs {
	u32 nwctrl; /* Network Control reg */
	u32 nwcfg; /* Network Config reg */
	u32 nwsr; /* Network Status reg */
	u32 reserved1;
	u32 dmacr; /* DMA Control reg */
	u32 txsr; /* TX Status reg */
	u32 rxqbase; /* RX Q Base address reg */
	u32 txqbase; /* TX Q Base address reg */
	u32 rxsr; /* RX Status reg */
	u32 reserved2[2];
	u32 idr; /* Interrupt Disable reg */
	u32 reserved3;
	u32 phymntnc; /* Phy Maintaince reg */
	u32 reserved4[18];
	u32 hashl; /* Hash Low address reg */
	u32 hashh; /* Hash High address reg */
#define LADDR_LOW	0
#define LADDR_HIGH	1
	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
	u32 match[4]; /* Type ID1 Match reg */
	u32 reserved6[18];
	u32 stat[44]; /* Octects transmitted Low reg - stat start */
};

/* BD descriptors */
struct emac_bd {
	u32 addr; /* Next descriptor pointer */
	u32 status;
};

#define RX_BUF 3
/* Page table entries are set to 1MB, or multiples of 1MB
 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
 */
#define BD_SPACE	0x100000
/* BD separation space */
#define BD_SEPRN_SPACE	64

/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
struct zynq_gem_priv {
	struct emac_bd *tx_bd;
	struct emac_bd *rx_bd;
	char *rxbuffers;
	u32 rxbd_current;
	u32 rx_first_buf;
	int phyaddr;
	u32 emio;
	int init;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

static inline int mdio_wait(struct eth_device *dev)
{
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
	u32 timeout = 200;

	/* Wait till MDIO interface is ready to accept a new transaction. */
	while (--timeout) {
		if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
			break;
		WATCHDOG_RESET();
	}

	if (!timeout) {
		printf("%s: Timeout\n", __func__);
		return 1;
	}

	return 0;
}

static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
							u32 op, u16 *data)
{
	u32 mgtcr;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	if (mdio_wait(dev))
		return 1;

	/* Construct mgtcr mask for the operation */
	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
		(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
		(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;

	/* Write mgtcr and wait for completion */
	writel(mgtcr, &regs->phymntnc);

	if (mdio_wait(dev))
		return 1;

	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
		*data = readl(&regs->phymntnc);

	return 0;
}

static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
{
	return phy_setup_op(dev, phy_addr, regnum,
				ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
}

static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
{
	return phy_setup_op(dev, phy_addr, regnum,
				ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}

static void phy_detection(struct eth_device *dev)
{
	int i;
	u16 phyreg;
	struct zynq_gem_priv *priv = dev->priv;

	if (priv->phyaddr != -1) {
		phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
		if ((phyreg != 0xFFFF) &&
		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
			/* Found a valid PHY address */
			debug("Default phy address %d is valid\n",
			      priv->phyaddr);
			return;
		} else {
			debug("PHY address is not setup correctly %d\n",
			      priv->phyaddr);
			priv->phyaddr = -1;
		}
	}

	debug("detecting phy address\n");
	if (priv->phyaddr == -1) {
		/* detect the PHY address */
		for (i = 31; i >= 0; i--) {
			phyread(dev, i, PHY_DETECT_REG, &phyreg);
			if ((phyreg != 0xFFFF) &&
			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
				/* Found a valid PHY address */
				priv->phyaddr = i;
				debug("Found valid phy address, %d\n", i);
				return;
			}
		}
	}
	printf("PHY is not detected\n");
}

static int zynq_gem_setup_mac(struct eth_device *dev)
{
	u32 i, macaddrlow, macaddrhigh;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	/* Set the MAC bits [31:0] in BOT */
	macaddrlow = dev->enetaddr[0];
	macaddrlow |= dev->enetaddr[1] << 8;
	macaddrlow |= dev->enetaddr[2] << 16;
	macaddrlow |= dev->enetaddr[3] << 24;

	/* Set MAC bits [47:32] in TOP */
	macaddrhigh = dev->enetaddr[4];
	macaddrhigh |= dev->enetaddr[5] << 8;

	for (i = 0; i < 4; i++) {
		writel(0, &regs->laddr[i][LADDR_LOW]);
		writel(0, &regs->laddr[i][LADDR_HIGH]);
		/* Do not use MATCHx register */
		writel(0, &regs->match[i]);
	}

	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);

	return 0;
}

static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
{
	u32 i, rclk, clk = 0;
	struct phy_device *phydev;
	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
				offsetof(struct zynq_gem_regs, stat)) / 4;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
	struct zynq_gem_priv *priv = dev->priv;
	const u32 supported = SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full |
			SUPPORTED_1000baseT_Half |
			SUPPORTED_1000baseT_Full;

	if (!priv->init) {
		/* Disable all interrupts */
		writel(0xFFFFFFFF, &regs->idr);

		/* Disable the receiver & transmitter */
		writel(0, &regs->nwctrl);
		writel(0, &regs->txsr);
		writel(0, &regs->rxsr);
		writel(0, &regs->phymntnc);

		/* Clear the Hash registers for the mac address
		 * pointed by AddressPtr
		 */
		writel(0x0, &regs->hashl);
		/* Write bits [63:32] in TOP */
		writel(0x0, &regs->hashh);

		/* Clear all counters */
		for (i = 0; i <= stat_size; i++)
			readl(&regs->stat[i]);

		/* Setup RxBD space */
		memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));

		for (i = 0; i < RX_BUF; i++) {
			priv->rx_bd[i].status = 0xF0000000;
			priv->rx_bd[i].addr =
					((u32)(priv->rxbuffers) +
							(i * PKTSIZE_ALIGN));
		}
		/* WRAP bit to last BD */
		priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
		/* Write RxBDs to IP */
		writel((u32)priv->rx_bd, &regs->rxqbase);

		/* Setup for DMA Configuration register */
		writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);

		/* Setup for Network Control register, MDIO, Rx and Tx enable */
		setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);

		priv->init++;
	}

	phy_detection(dev);

	/* interface - look at tsec */
	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);

	phydev->supported = supported | ADVERTISED_Pause |
			    ADVERTISED_Asym_Pause;
	phydev->advertising = phydev->supported;
	priv->phydev = phydev;
	phy_config(phydev);
	phy_startup(phydev);

	switch (phydev->speed) {
	case SPEED_1000:
		writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
		       &regs->nwcfg);
		rclk = (0 << 4) | (1 << 0);
		clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
		break;
	case SPEED_100:
		clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
				ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
		rclk = 1 << 0;
		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
		break;
	case SPEED_10:
		rclk = 1 << 0;
		/* FIXME untested */
		clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
		break;
	}

	/* Change the rclk and clk only not using EMIO interface */
	if (!priv->emio)
		zynq_slcr_gem_clk_setup(dev->iobase !=
					ZYNQ_GEM_BASEADDR0, rclk, clk);

	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
					ZYNQ_GEM_NWCTRL_TXEN_MASK);

	return 0;
}

static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
{
	u32 addr, size;
	struct zynq_gem_priv *priv = dev->priv;
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	/* setup BD */
	writel((u32)priv->tx_bd, &regs->txqbase);

	/* Setup Tx BD */
	memset(priv->tx_bd, 0, sizeof(struct emac_bd));

	priv->tx_bd->addr = (u32)ptr;
	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
				ZYNQ_GEM_TXBUF_LAST_MASK;

	addr = (u32) ptr;
	addr &= ~(ARCH_DMA_MINALIGN - 1);
	size = roundup(len, ARCH_DMA_MINALIGN);
	flush_dcache_range(addr, addr + size);
	barrier();

	/* Start transmit */
	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);

	/* Read TX BD status */
	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
		printf("TX underrun\n");
	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
		printf("TX buffers exhausted in mid frame\n");

	return 0;
}

/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
static int zynq_gem_recv(struct eth_device *dev)
{
	int frame_len;
	struct zynq_gem_priv *priv = dev->priv;
	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
	struct emac_bd *first_bd;

	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
		return 0;

	if (!(current_bd->status &
			(ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
		printf("GEM: SOF or EOF not set for last buffer received!\n");
		return 0;
	}

	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
	if (frame_len) {
		u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
		addr &= ~(ARCH_DMA_MINALIGN - 1);
		u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
		invalidate_dcache_range(addr, addr + size);

		NetReceive((u8 *)addr, frame_len);

		if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
			priv->rx_first_buf = priv->rxbd_current;
		else {
			current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
			current_bd->status = 0xF0000000; /* FIXME */
		}

		if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
			first_bd = &priv->rx_bd[priv->rx_first_buf];
			first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
			first_bd->status = 0xF0000000;
		}

		if ((++priv->rxbd_current) >= RX_BUF)
			priv->rxbd_current = 0;
	}

	return frame_len;
}

static void zynq_gem_halt(struct eth_device *dev)
{
	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;

	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
						ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
}

static int zynq_gem_miiphyread(const char *devname, uchar addr,
							uchar reg, ushort *val)
{
	struct eth_device *dev = eth_get_dev();
	int ret;

	ret = phyread(dev, addr, reg, val);
	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
	return ret;
}

static int zynq_gem_miiphy_write(const char *devname, uchar addr,
							uchar reg, ushort val)
{
	struct eth_device *dev = eth_get_dev();

	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
	return phywrite(dev, addr, reg, val);
}

int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
{
	struct eth_device *dev;
	struct zynq_gem_priv *priv;
	void *bd_space;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
	if (dev->priv == NULL) {
		free(dev);
		return -1;
	}
	priv = dev->priv;

	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);

	/* Align bd_space to 1MB */
	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);

	/* Initialize the bd spaces for tx and rx bd's */
	priv->tx_bd = (struct emac_bd *)bd_space;
	priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);

	priv->phyaddr = phy_addr;
	priv->emio = emio;

	sprintf(dev->name, "Gem.%x", base_addr);

	dev->iobase = base_addr;

	dev->init = zynq_gem_init;
	dev->halt = zynq_gem_halt;
	dev->send = zynq_gem_send;
	dev->recv = zynq_gem_recv;
	dev->write_hwaddr = zynq_gem_setup_mac;

	eth_register(dev);

	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
	priv->bus = miiphy_get_dev_by_name(dev->name);

	return 1;
}
Commit	Line	Data
185f7d9a MS	1	/*
	2	* (C) Copyright 2011 Michal Simek
	3	*
	4	* Michal SIMEK <monstr@monstr.eu>
	5	*
	6	* Based on Xilinx gmac driver:
	7	* (C) Copyright 2011 Xilinx
	8	*
3765b3e7	9	* SPDX-License-Identifier: GPL-2.0+
185f7d9a MS	10	*/
	11
	12	#include <common.h>
	13	#include <net.h>
	14	#include <config.h>
	15	#include <malloc.h>
	16	#include <asm/io.h>
	17	#include <phy.h>
	18	#include <miiphy.h>
	19	#include <watchdog.h>
01fbf310	20	#include <asm/arch/hardware.h>
80243528	21	#include <asm/arch/sys_proto.h>
185f7d9a MS	22
	23	#if !defined(CONFIG_PHYLIB)
	24	# error XILINX_GEM_ETHERNET requires PHYLIB
	25	#endif
	26
	27	/* Bit/mask specification */
	28	#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
	29	#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
	30	#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
	31	#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
	32	#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
	33
	34	#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
	35	#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
	36	#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
	37
	38	#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
	39	#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
	40	#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
	41
	42	/* Wrap bit, last descriptor */
	43	#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
	44	#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
	45
185f7d9a MS	46	#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
	47	#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
	48	#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
	49	#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
	50
80243528 MS	51	#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
	52	#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
	53	#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
	54	#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
185f7d9a	55	#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
80243528	56	#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
185f7d9a	57
80243528	58	#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN \| \
185f7d9a MS	59	ZYNQ_GEM_NWCFG_FSREM \| \
	60	ZYNQ_GEM_NWCFG_MDCCLKDIV)
	61
	62	#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
	63
	64	#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
	65	/* Use full configured addressable space (8 Kb) */
	66	#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
	67	/* Use full configured addressable space (4 Kb) */
	68	#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
	69	/* Set with binary 00011000 to use 1536 byte(1max length frame/buffer) /
	70	#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
	71
	72	#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH \| \
	73	ZYNQ_GEM_DMACR_RXSIZE \| \
	74	ZYNQ_GEM_DMACR_TXSIZE \| \
	75	ZYNQ_GEM_DMACR_RXBUF)
	76
f97d7e8b MS	77	/* Use MII register 1 (MII status register) to detect PHY */
	78	#define PHY_DETECT_REG 1
	79
	80	/* Mask used to verify certain PHY features (or register contents)
	81	* in the register above:
	82	* 0x1000: 10Mbps full duplex support
	83	* 0x0800: 10Mbps half duplex support
	84	* 0x0008: Auto-negotiation support
	85	*/
	86	#define PHY_DETECT_MASK 0x1808
	87
a5144237 ST	88	/* TX BD status masks */
	89	#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
	90	#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
	91	#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
	92
185f7d9a MS	93	/* Device registers */
	94	struct zynq_gem_regs {
	95	u32 nwctrl; /* Network Control reg */
	96	u32 nwcfg; /* Network Config reg */
	97	u32 nwsr; /* Network Status reg */
	98	u32 reserved1;
	99	u32 dmacr; /* DMA Control reg */
	100	u32 txsr; /* TX Status reg */
	101	u32 rxqbase; /* RX Q Base address reg */
	102	u32 txqbase; /* TX Q Base address reg */
	103	u32 rxsr; /* RX Status reg */
	104	u32 reserved2[2];
	105	u32 idr; /* Interrupt Disable reg */
	106	u32 reserved3;
	107	u32 phymntnc; /* Phy Maintaince reg */
	108	u32 reserved4[18];
	109	u32 hashl; /* Hash Low address reg */
	110	u32 hashh; /* Hash High address reg */
	111	#define LADDR_LOW 0
	112	#define LADDR_HIGH 1
	113	u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
	114	u32 match[4]; /* Type ID1 Match reg */
	115	u32 reserved6[18];
	116	u32 stat[44]; /* Octects transmitted Low reg - stat start */
	117	};
	118
	119	/* BD descriptors */
	120	struct emac_bd {
	121	u32 addr; /* Next descriptor pointer */
	122	u32 status;
	123	};
	124
	125	#define RX_BUF 3
a5144237 ST	126	/* Page table entries are set to 1MB, or multiples of 1MB
	127	* (not < 1MB). driver uses less bd's so use 1MB bdspace.
	128	*/
	129	#define BD_SPACE 0x100000
	130	/* BD separation space */
	131	#define BD_SEPRN_SPACE 64
185f7d9a MS	132
	133	/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
	134	struct zynq_gem_priv {
a5144237 ST	135	struct emac_bd *tx_bd;
	136	struct emac_bd *rx_bd;
	137	char *rxbuffers;
185f7d9a MS	138	u32 rxbd_current;
	139	u32 rx_first_buf;
	140	int phyaddr;
01fbf310	141	u32 emio;
05868759	142	int init;
185f7d9a MS	143	struct phy_device *phydev;
	144	struct mii_dev *bus;
	145	};
	146
	147	static inline int mdio_wait(struct eth_device *dev)
	148	{
	149	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	150	u32 timeout = 200;
	151
	152	/* Wait till MDIO interface is ready to accept a new transaction. */
	153	while (--timeout) {
	154	if (readl(&regs->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
	155	break;
	156	WATCHDOG_RESET();
	157	}
	158
	159	if (!timeout) {
	160	printf("%s: Timeout\n", __func__);
	161	return 1;
	162	}
	163
	164	return 0;
	165	}
	166
	167	static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
	168	u32 op, u16 *data)
	169	{
	170	u32 mgtcr;
	171	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	172
	173	if (mdio_wait(dev))
	174	return 1;
	175
	176	/* Construct mgtcr mask for the operation */
	177	mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK \| op \|
	178	(phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) \|
	179	(regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) \| *data;
	180
	181	/* Write mgtcr and wait for completion */
	182	writel(mgtcr, &regs->phymntnc);
	183
	184	if (mdio_wait(dev))
	185	return 1;
	186
	187	if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
	188	*data = readl(&regs->phymntnc);
	189
	190	return 0;
	191	}
	192
	193	static u32 phyread(struct eth_device dev, u32 phy_addr, u32 regnum, u16 val)
	194	{
	195	return phy_setup_op(dev, phy_addr, regnum,
	196	ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
	197	}
	198
	199	static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
	200	{
	201	return phy_setup_op(dev, phy_addr, regnum,
	202	ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
	203	}
	204
f97d7e8b MS	205	static void phy_detection(struct eth_device *dev)
	206	{
	207	int i;
	208	u16 phyreg;
	209	struct zynq_gem_priv *priv = dev->priv;
	210
	211	if (priv->phyaddr != -1) {
	212	phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
	213	if ((phyreg != 0xFFFF) &&
	214	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	215	/* Found a valid PHY address */
	216	debug("Default phy address %d is valid\n",
	217	priv->phyaddr);
	218	return;
	219	} else {
	220	debug("PHY address is not setup correctly %d\n",
	221	priv->phyaddr);
	222	priv->phyaddr = -1;
	223	}
	224	}
	225
	226	debug("detecting phy address\n");
	227	if (priv->phyaddr == -1) {
	228	/* detect the PHY address */
	229	for (i = 31; i >= 0; i--) {
	230	phyread(dev, i, PHY_DETECT_REG, &phyreg);
	231	if ((phyreg != 0xFFFF) &&
	232	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	233	/* Found a valid PHY address */
	234	priv->phyaddr = i;
	235	debug("Found valid phy address, %d\n", i);
	236	return;
	237	}
	238	}
	239	}
	240	printf("PHY is not detected\n");
	241	}
	242
185f7d9a MS	243	static int zynq_gem_setup_mac(struct eth_device *dev)
	244	{
	245	u32 i, macaddrlow, macaddrhigh;
	246	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	247
	248	/* Set the MAC bits [31:0] in BOT */
	249	macaddrlow = dev->enetaddr[0];
	250	macaddrlow \|= dev->enetaddr[1] << 8;
	251	macaddrlow \|= dev->enetaddr[2] << 16;
	252	macaddrlow \|= dev->enetaddr[3] << 24;
	253
	254	/* Set MAC bits [47:32] in TOP */
	255	macaddrhigh = dev->enetaddr[4];
	256	macaddrhigh \|= dev->enetaddr[5] << 8;
	257
	258	for (i = 0; i < 4; i++) {
	259	writel(0, &regs->laddr[i][LADDR_LOW]);
	260	writel(0, &regs->laddr[i][LADDR_HIGH]);
	261	/* Do not use MATCHx register */
	262	writel(0, &regs->match[i]);
	263	}
	264
	265	writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
	266	writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
	267
	268	return 0;
	269	}
	270
	271	static int zynq_gem_init(struct eth_device dev, bd_t bis)
	272	{
80243528	273	u32 i, rclk, clk = 0;
185f7d9a MS	274	struct phy_device *phydev;
	275	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
	276	offsetof(struct zynq_gem_regs, stat)) / 4;
	277	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	278	struct zynq_gem_priv *priv = dev->priv;
	279	const u32 supported = SUPPORTED_10baseT_Half \|
	280	SUPPORTED_10baseT_Full \|
	281	SUPPORTED_100baseT_Half \|
	282	SUPPORTED_100baseT_Full \|
	283	SUPPORTED_1000baseT_Half \|
	284	SUPPORTED_1000baseT_Full;
	285
05868759 MS	286	if (!priv->init) {
	287	/* Disable all interrupts */
	288	writel(0xFFFFFFFF, &regs->idr);
	289
	290	/* Disable the receiver & transmitter */
	291	writel(0, &regs->nwctrl);
	292	writel(0, &regs->txsr);
	293	writel(0, &regs->rxsr);
	294	writel(0, &regs->phymntnc);
	295
	296	/* Clear the Hash registers for the mac address
	297	* pointed by AddressPtr
	298	*/
	299	writel(0x0, &regs->hashl);
	300	/* Write bits [63:32] in TOP */
	301	writel(0x0, &regs->hashh);
	302
	303	/* Clear all counters */
	304	for (i = 0; i <= stat_size; i++)
	305	readl(&regs->stat[i]);
	306
	307	/* Setup RxBD space */
a5144237	308	memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
05868759 MS	309
	310	for (i = 0; i < RX_BUF; i++) {
	311	priv->rx_bd[i].status = 0xF0000000;
	312	priv->rx_bd[i].addr =
a5144237	313	((u32)(priv->rxbuffers) +
185f7d9a	314	(i * PKTSIZE_ALIGN));
05868759 MS	315	}
	316	/* WRAP bit to last BD */
	317	priv->rx_bd[--i].addr \|= ZYNQ_GEM_RXBUF_WRAP_MASK;
	318	/* Write RxBDs to IP */
a5144237	319	writel((u32)priv->rx_bd, &regs->rxqbase);
185f7d9a	320
05868759 MS	321	/* Setup for DMA Configuration register */
05868759 MS	322	writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
185f7d9a	323
05868759	324	/* Setup for Network Control register, MDIO, Rx and Tx enable */
80243528	325	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
185f7d9a	326
05868759 MS	327	priv->init++;
	328	}
	329
f97d7e8b MS	330	phy_detection(dev);
f97d7e8b MS	331
185f7d9a MS	332	/* interface - look at tsec */
	333	phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
	334
80243528 MS	335	phydev->supported = supported \| ADVERTISED_Pause \|
80243528 MS	336	ADVERTISED_Asym_Pause;
185f7d9a MS	337	phydev->advertising = phydev->supported;
	338	priv->phydev = phydev;
	339	phy_config(phydev);
	340	phy_startup(phydev);
	341
80243528 MS	342	switch (phydev->speed) {
	343	case SPEED_1000:
	344	writel(ZYNQ_GEM_NWCFG_INIT \| ZYNQ_GEM_NWCFG_SPEED1000,
	345	&regs->nwcfg);
	346	rclk = (0 << 4) \| (1 << 0);
	347	clk = (1 << 20) \| (8 << 8) \| (0 << 4) \| (1 << 0);
	348	break;
	349	case SPEED_100:
	350	clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
	351	ZYNQ_GEM_NWCFG_INIT \| ZYNQ_GEM_NWCFG_SPEED100);
	352	rclk = 1 << 0;
	353	clk = (5 << 20) \| (8 << 8) \| (0 << 4) \| (1 << 0);
	354	break;
	355	case SPEED_10:
	356	rclk = 1 << 0;
	357	/* FIXME untested */
	358	clk = (5 << 20) \| (8 << 8) \| (0 << 4) \| (1 << 0);
	359	break;
	360	}
01fbf310 DA	361
	362	/* Change the rclk and clk only not using EMIO interface */
	363	if (!priv->emio)
	364	zynq_slcr_gem_clk_setup(dev->iobase !=
	365	ZYNQ_GEM_BASEADDR0, rclk, clk);
80243528 MS	366
	367	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK \|
	368	ZYNQ_GEM_NWCTRL_TXEN_MASK);
	369
185f7d9a MS	370	return 0;
	371	}
	372
	373	static int zynq_gem_send(struct eth_device dev, void ptr, int len)
	374	{
a5144237	375	u32 addr, size;
185f7d9a MS	376	struct zynq_gem_priv *priv = dev->priv;
185f7d9a MS	377	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
185f7d9a MS	378
185f7d9a MS	379	/* setup BD */
a5144237	380	writel((u32)priv->tx_bd, &regs->txqbase);
185f7d9a MS	381
185f7d9a MS	382	/* Setup Tx BD */
a5144237 ST	383	memset(priv->tx_bd, 0, sizeof(struct emac_bd));
	384
	385	priv->tx_bd->addr = (u32)ptr;
	386	priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) \|
	387	ZYNQ_GEM_TXBUF_LAST_MASK;
185f7d9a	388
a5144237 ST	389	addr = (u32) ptr;
	390	addr &= ~(ARCH_DMA_MINALIGN - 1);
	391	size = roundup(len, ARCH_DMA_MINALIGN);
	392	flush_dcache_range(addr, addr + size);
	393	barrier();
185f7d9a MS	394
	395	/* Start transmit */
	396	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
	397
a5144237 ST	398	/* Read TX BD status */
	399	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
	400	printf("TX underrun\n");
	401	if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
	402	printf("TX buffers exhausted in mid frame\n");
185f7d9a	403
185f7d9a MS	404	return 0;
	405	}
	406
	407	/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
	408	static int zynq_gem_recv(struct eth_device *dev)
	409	{
	410	int frame_len;
	411	struct zynq_gem_priv *priv = dev->priv;
	412	struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
	413	struct emac_bd *first_bd;
	414
	415	if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
	416	return 0;
	417
	418	if (!(current_bd->status &
	419	(ZYNQ_GEM_RXBUF_SOF_MASK \| ZYNQ_GEM_RXBUF_EOF_MASK))) {
	420	printf("GEM: SOF or EOF not set for last buffer received!\n");
	421	return 0;
	422	}
	423
	424	frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
	425	if (frame_len) {
a5144237 ST	426	u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
	427	addr &= ~(ARCH_DMA_MINALIGN - 1);
	428	u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
	429	invalidate_dcache_range(addr, addr + size);
	430
	431	NetReceive((u8 *)addr, frame_len);
185f7d9a MS	432
	433	if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
	434	priv->rx_first_buf = priv->rxbd_current;
	435	else {
	436	current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
	437	current_bd->status = 0xF0000000; /* FIXME */
	438	}
	439
	440	if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
	441	first_bd = &priv->rx_bd[priv->rx_first_buf];
	442	first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
	443	first_bd->status = 0xF0000000;
	444	}
	445
	446	if ((++priv->rxbd_current) >= RX_BUF)
	447	priv->rxbd_current = 0;
185f7d9a MS	448	}
185f7d9a MS	449
3b90d0af	450	return frame_len;
185f7d9a MS	451	}
	452
	453	static void zynq_gem_halt(struct eth_device *dev)
	454	{
	455	struct zynq_gem_regs regs = (struct zynq_gem_regs )dev->iobase;
	456
80243528 MS	457	clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK \|
80243528 MS	458	ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
185f7d9a MS	459	}
	460
	461	static int zynq_gem_miiphyread(const char *devname, uchar addr,
	462	uchar reg, ushort *val)
	463	{
	464	struct eth_device *dev = eth_get_dev();
	465	int ret;
	466
	467	ret = phyread(dev, addr, reg, val);
	468	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
	469	return ret;
	470	}
	471
	472	static int zynq_gem_miiphy_write(const char *devname, uchar addr,
	473	uchar reg, ushort val)
	474	{
	475	struct eth_device *dev = eth_get_dev();
	476
	477	debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
	478	return phywrite(dev, addr, reg, val);
	479	}
	480
01fbf310	481	int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
185f7d9a MS	482	{
	483	struct eth_device *dev;
	484	struct zynq_gem_priv *priv;
a5144237	485	void *bd_space;
185f7d9a MS	486
	487	dev = calloc(1, sizeof(*dev));
	488	if (dev == NULL)
	489	return -1;
	490
	491	dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
	492	if (dev->priv == NULL) {
	493	free(dev);
	494	return -1;
	495	}
	496	priv = dev->priv;
	497
a5144237 ST	498	/* Align rxbuffers to ARCH_DMA_MINALIGN */
	499	priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
	500	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
	501
	502	/* Align bd_space to 1MB */
	503	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
	504	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
	505
	506	/* Initialize the bd spaces for tx and rx bd's */
	507	priv->tx_bd = (struct emac_bd *)bd_space;
	508	priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
	509
117cd4cc	510	priv->phyaddr = phy_addr;
01fbf310	511	priv->emio = emio;
185f7d9a MS	512
	513	sprintf(dev->name, "Gem.%x", base_addr);
	514
	515	dev->iobase = base_addr;
	516
	517	dev->init = zynq_gem_init;
	518	dev->halt = zynq_gem_halt;
	519	dev->send = zynq_gem_send;
	520	dev->recv = zynq_gem_recv;
	521	dev->write_hwaddr = zynq_gem_setup_mac;
	522
	523	eth_register(dev);
	524
	525	miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
	526	priv->bus = miiphy_get_dev_by_name(dev->name);
	527
	528	return 1;
	529	}