]> git.ipfire.org Git - thirdparty/kernel/stable.git/blame - drivers/nvme/host/core.c
projects / thirdparty / kernel / stable.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme: merge nvme_ns_ioctl into nvme_ioctl
[thirdparty/kernel/stable.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
5fd4ce1b 9#include <linux/delay.h>
21d34711 10#include <linux/errno.h>
1673f1f0 11#include <linux/hdreg.h>
21d34711 12#include <linux/kernel.h>
5bae7f73
CH		 13#include <linux/module.h>
14#include <linux/list_sort.h>
21d34711
CH		 15#include <linux/slab.h>
16#include <linux/types.h>
1673f1f0
CH		 17#include <linux/pr.h>
18#include <linux/ptrace.h>
19#include <linux/nvme_ioctl.h>
20#include <linux/t10-pi.h>
c5552fde 21#include <linux/pm_qos.h>
1673f1f0 22#include <asm/unaligned.h>
21d34711 23
3d030e41
JT		 24#define CREATE_TRACE_POINTS
25#include "trace.h"
26
21d34711 27#include "nvme.h"
038bd4cb 28#include "fabrics.h"
21d34711 29
f3ca80fc
CH		 30#define NVME_MINORS (1U << MINORBITS)
31
8ae4e447
MO		 32unsigned int admin_timeout = 60;
33module_param(admin_timeout, uint, 0644);
ba0ba7d3 34MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 35EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 36
8ae4e447
MO		 37unsigned int nvme_io_timeout = 30;
38module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 39MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 40EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 41
b3b1b0b0 42static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 43module_param(shutdown_timeout, byte, 0644);
44MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
45
44e44b29
CH		 46static u8 nvme_max_retries = 5;
47module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 48MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 49
9947d6a0 50static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 51module_param(default_ps_max_latency_us, ulong, 0644);
52MODULE_PARM_DESC(default_ps_max_latency_us,
53 "max power saving latency for new devices; use PM QOS to change per device");
54
c35e30b4
AL		 55static bool force_apst;
56module_param(force_apst, bool, 0644);
57MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
58
f5d11840
JA		 59static bool streams;
60module_param(streams, bool, 0644);
61MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
62
b227c59b
RS		 63/*
64 * nvme_wq - hosts nvme related works that are not reset or delete
65 * nvme_reset_wq - hosts nvme reset works
66 * nvme_delete_wq - hosts nvme delete works
67 *
68 * nvme_wq will host works such are scan, aen handling, fw activation,
69 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
70 * runs reset works which also flush works hosted on nvme_wq for
71 * serialization purposes. nvme_delete_wq host controller deletion
72 * works which flush reset works for serialization.
73 */
9a6327d2
SG		 74struct workqueue_struct *nvme_wq;
75EXPORT_SYMBOL_GPL(nvme_wq);
76
b227c59b
RS		 77struct workqueue_struct *nvme_reset_wq;
78EXPORT_SYMBOL_GPL(nvme_reset_wq);
79
80struct workqueue_struct *nvme_delete_wq;
81EXPORT_SYMBOL_GPL(nvme_delete_wq);
82
ab9e00cc
CH		 83static DEFINE_IDA(nvme_subsystems_ida);
84static LIST_HEAD(nvme_subsystems);
85static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 86
9843f685 87static DEFINE_IDA(nvme_instance_ida);
a6a5149b 88static dev_t nvme_chr_devt;
f3ca80fc 89static struct class *nvme_class;
ab9e00cc 90static struct class *nvme_subsys_class;
f3ca80fc 91
84fef62d 92static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 93static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 94static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
95 unsigned nsid);
96
97static void nvme_set_queue_dying(struct nvme_ns *ns)
98{
99 /*
100 * Revalidating a dead namespace sets capacity to 0. This will end
101 * buffered writers dirtying pages that can't be synced.
102 */
103 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
104 return;
105 revalidate_disk(ns->disk);
106 blk_set_queue_dying(ns->queue);
107 /* Forcibly unquiesce queues to avoid blocking dispatch */
108 blk_mq_unquiesce_queue(ns->queue);
109}
f3ca80fc 110
50e8d8ee
CH		 111static void nvme_queue_scan(struct nvme_ctrl *ctrl)
112{
113 /*
114 * Only new queue scan work when admin and IO queues are both alive
115 */
116 if (ctrl->state == NVME_CTRL_LIVE)
117 queue_work(nvme_wq, &ctrl->scan_work);
118}
119
d86c4d8e
CH		 120int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
121{
122 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
123 return -EBUSY;
b227c59b 124 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 125 return -EBUSY;
126 return 0;
127}
128EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
129
79c48ccf 130int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 131{
132 int ret;
133
134 ret = nvme_reset_ctrl(ctrl);
8000d1fd 135 if (!ret) {
d86c4d8e 136 flush_work(&ctrl->reset_work);
4e50d9eb
CM		 137 if (ctrl->state != NVME_CTRL_LIVE &&
138 ctrl->state != NVME_CTRL_ADMIN_ONLY)
8000d1fd
NC		 139 ret = -ENETRESET;
140 }
141
d86c4d8e
CH		 142 return ret;
143}
79c48ccf 144EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 145
a686ed75 146static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 147{
77d0612d
MG		 148 dev_info(ctrl->device,
149 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
150
4054637c 151 flush_work(&ctrl->reset_work);
6cd53d14
CH		 152 nvme_stop_ctrl(ctrl);
153 nvme_remove_namespaces(ctrl);
c5017e85 154 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 155 nvme_uninit_ctrl(ctrl);
156 nvme_put_ctrl(ctrl);
c5017e85
CH		 157}
158
a686ed75
BVA		 159static void nvme_delete_ctrl_work(struct work_struct *work)
160{
161 struct nvme_ctrl *ctrl =
162 container_of(work, struct nvme_ctrl, delete_work);
163
164 nvme_do_delete_ctrl(ctrl);
165}
166
c5017e85
CH		 167int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
168{
169 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
170 return -EBUSY;
b227c59b 171 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 172 return -EBUSY;
173 return 0;
174}
175EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
176
d84c4b02 177static int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85
CH		 178{
179 int ret = 0;
180
181 /*
01fc08ff
YY		 182 * Keep a reference until nvme_do_delete_ctrl() complete,
183 * since ->delete_ctrl can free the controller.
c5017e85
CH		 184 */
185 nvme_get_ctrl(ctrl);
b9c77583
BVA		 186 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
187 ret = -EBUSY;
c5017e85 188 if (!ret)
b9c77583 189 nvme_do_delete_ctrl(ctrl);
c5017e85
CH		 190 nvme_put_ctrl(ctrl);
191 return ret;
192}
c5017e85 193
715ea9e0
CH		 194static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
195{
196 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
197}
198
2a842aca 199static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 200{
201 switch (nvme_req(req)->status & 0x7ff) {
202 case NVME_SC_SUCCESS:
2a842aca 203 return BLK_STS_OK;
27fa9bc5 204 case NVME_SC_CAP_EXCEEDED:
2a842aca 205 return BLK_STS_NOSPC;
e96fef2c
KB		 206 case NVME_SC_LBA_RANGE:
207 return BLK_STS_TARGET;
208 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 209 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 210 case NVME_SC_INVALID_OPCODE:
211 case NVME_SC_INVALID_FIELD:
212 case NVME_SC_INVALID_NS:
2a842aca 213 return BLK_STS_NOTSUPP;
e02ab023
JG		 214 case NVME_SC_WRITE_FAULT:
215 case NVME_SC_READ_ERROR:
216 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 217 case NVME_SC_ACCESS_DENIED:
218 case NVME_SC_READ_ONLY:
e96fef2c 219 case NVME_SC_COMPARE_FAILED:
2a842aca 220 return BLK_STS_MEDIUM;
a751da33
CH		 221 case NVME_SC_GUARD_CHECK:
222 case NVME_SC_APPTAG_CHECK:
223 case NVME_SC_REFTAG_CHECK:
224 case NVME_SC_INVALID_PI:
225 return BLK_STS_PROTECTION;
226 case NVME_SC_RESERVATION_CONFLICT:
227 return BLK_STS_NEXUS;
2a842aca
CH		 228 default:
229 return BLK_STS_IOERR;
27fa9bc5
CH		 230 }
231}
27fa9bc5 232
f6324b1b 233static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 234{
f6324b1b
CH		 235 if (blk_noretry_request(req))
236 return false;
27fa9bc5 237 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 238 return false;
44e44b29 239 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 240 return false;
241 return true;
77f02a7a
CH		 242}
243
49cd84b6
KB		 244static void nvme_retry_req(struct request *req)
245{
246 struct nvme_ns *ns = req->q->queuedata;
247 unsigned long delay = 0;
248 u16 crd;
249
250 /* The mask and shift result must be <= 3 */
251 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
252 if (ns && crd)
253 delay = ns->ctrl->crdt[crd - 1] * 100;
254
255 nvme_req(req)->retries++;
256 blk_mq_requeue_request(req, false);
257 blk_mq_delay_kick_requeue_list(req->q, delay);
258}
259
77f02a7a
CH		 260void nvme_complete_rq(struct request *req)
261{
908e4564
KB		 262 blk_status_t status = nvme_error_status(req);
263
ca5554a6
JT		 264 trace_nvme_complete_rq(req);
265
6e3ca03e
SG		 266 if (nvme_req(req)->ctrl->kas)
267 nvme_req(req)->ctrl->comp_seen = true;
268
908e4564 269 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
8decf5d5
CH		 270 if ((req->cmd_flags & REQ_NVME_MPATH) &&
271 blk_path_error(status)) {
32acab31
CH		 272 nvme_failover_req(req);
273 return;
274 }
275
276 if (!blk_queue_dying(req->q)) {
49cd84b6 277 nvme_retry_req(req);
32acab31
CH		 278 return;
279 }
77f02a7a 280 }
908e4564 281 blk_mq_end_request(req, status);
77f02a7a
CH		 282}
283EXPORT_SYMBOL_GPL(nvme_complete_rq);
284
7baa8572 285bool nvme_cancel_request(struct request *req, void *data, bool reserved)
c55a2fd4 286{
c55a2fd4
ML		 287 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
288 "Cancelling I/O %d", req->tag);
289
e54b064c 290 nvme_req(req)->status = NVME_SC_ABORT_REQ;
eb3afb75 291 blk_mq_complete_request_sync(req);
7baa8572 292 return true;
c55a2fd4
ML		 293}
294EXPORT_SYMBOL_GPL(nvme_cancel_request);
295
bb8d261e
CH		 296bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
297 enum nvme_ctrl_state new_state)
298{
f6b6a28e 299 enum nvme_ctrl_state old_state;
0a72bbba 300 unsigned long flags;
bb8d261e
CH		 301 bool changed = false;
302
0a72bbba 303 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 304
305 old_state = ctrl->state;
bb8d261e 306 switch (new_state) {
2b1b7e78
JW		 307 case NVME_CTRL_ADMIN_ONLY:
308 switch (old_state) {
ad6a0a52 309 case NVME_CTRL_CONNECTING:
2b1b7e78
JW		 310 changed = true;
311 /* FALLTHRU */
312 default:
313 break;
314 }
315 break;
bb8d261e
CH		 316 case NVME_CTRL_LIVE:
317 switch (old_state) {
7d2e8008 318 case NVME_CTRL_NEW:
bb8d261e 319 case NVME_CTRL_RESETTING:
ad6a0a52 320 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 321 changed = true;
322 /* FALLTHRU */
323 default:
324 break;
325 }
326 break;
327 case NVME_CTRL_RESETTING:
328 switch (old_state) {
329 case NVME_CTRL_NEW:
def61eca 330 case NVME_CTRL_LIVE:
2b1b7e78 331 case NVME_CTRL_ADMIN_ONLY:
def61eca
CH		 332 changed = true;
333 /* FALLTHRU */
334 default:
335 break;
336 }
337 break;
ad6a0a52 338 case NVME_CTRL_CONNECTING:
def61eca 339 switch (old_state) {
b754a32c 340 case NVME_CTRL_NEW:
3cec7f9d 341 case NVME_CTRL_RESETTING:
bb8d261e
CH		 342 changed = true;
343 /* FALLTHRU */
344 default:
345 break;
346 }
347 break;
348 case NVME_CTRL_DELETING:
349 switch (old_state) {
350 case NVME_CTRL_LIVE:
2b1b7e78 351 case NVME_CTRL_ADMIN_ONLY:
bb8d261e 352 case NVME_CTRL_RESETTING:
ad6a0a52 353 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 354 changed = true;
355 /* FALLTHRU */
356 default:
357 break;
358 }
359 break;
0ff9d4e1
KB		 360 case NVME_CTRL_DEAD:
361 switch (old_state) {
362 case NVME_CTRL_DELETING:
363 changed = true;
364 /* FALLTHRU */
365 default:
366 break;
367 }
368 break;
bb8d261e
CH		 369 default:
370 break;
371 }
bb8d261e
CH		 372
373 if (changed)
374 ctrl->state = new_state;
375
0a72bbba 376 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 377 if (changed && ctrl->state == NVME_CTRL_LIVE)
378 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 379 return changed;
380}
381EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
382
ed754e5d
CH		 383static void nvme_free_ns_head(struct kref *ref)
384{
385 struct nvme_ns_head *head =
386 container_of(ref, struct nvme_ns_head, ref);
387
32acab31 388 nvme_mpath_remove_disk(head);
ed754e5d
CH		 389 ida_simple_remove(&head->subsys->ns_ida, head->instance);
390 list_del_init(&head->entry);
4317228a 391 cleanup_srcu_struct_quiesced(&head->srcu);
12d9f070 392 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 393 kfree(head);
394}
395
396static void nvme_put_ns_head(struct nvme_ns_head *head)
397{
398 kref_put(&head->ref, nvme_free_ns_head);
399}
400
1673f1f0
CH		 401static void nvme_free_ns(struct kref *kref)
402{
403 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
404
b0b4e09c
MB		 405 if (ns->ndev)
406 nvme_nvm_unregister(ns);
1673f1f0 407
1673f1f0 408 put_disk(ns->disk);
ed754e5d 409 nvme_put_ns_head(ns->head);
075790eb 410 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 411 kfree(ns);
412}
413
5bae7f73 414static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 415{
416 kref_put(&ns->kref, nvme_free_ns);
417}
418
bb06ec31
JS		 419static inline void nvme_clear_nvme_request(struct request *req)
420{
421 if (!(req->rq_flags & RQF_DONTPREP)) {
422 nvme_req(req)->retries = 0;
423 nvme_req(req)->flags = 0;
424 req->rq_flags |= RQF_DONTPREP;
425 }
426}
427
4160982e 428struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 429 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 430{
aebf526b 431 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 432 struct request *req;
21d34711 433
eb71f435 434 if (qid == NVME_QID_ANY) {
aebf526b 435 req = blk_mq_alloc_request(q, op, flags);
eb71f435 436 } else {
aebf526b 437 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 438 qid ? qid - 1 : 0);
439 }
21d34711 440 if (IS_ERR(req))
4160982e 441 return req;
21d34711 442
21d34711 443 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 444 nvme_clear_nvme_request(req);
d49187e9 445 nvme_req(req)->cmd = cmd;
21d34711 446
4160982e
CH		 447 return req;
448}
576d55d6 449EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 450
f5d11840
JA		 451static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
452{
453 struct nvme_command c;
454
455 memset(&c, 0, sizeof(c));
456
457 c.directive.opcode = nvme_admin_directive_send;
62346eae 458 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 459 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
460 c.directive.dtype = NVME_DIR_IDENTIFY;
461 c.directive.tdtype = NVME_DIR_STREAMS;
462 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
463
464 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
465}
466
467static int nvme_disable_streams(struct nvme_ctrl *ctrl)
468{
469 return nvme_toggle_streams(ctrl, false);
470}
471
472static int nvme_enable_streams(struct nvme_ctrl *ctrl)
473{
474 return nvme_toggle_streams(ctrl, true);
475}
476
477static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
478 struct streams_directive_params *s, u32 nsid)
479{
480 struct nvme_command c;
481
482 memset(&c, 0, sizeof(c));
483 memset(s, 0, sizeof(*s));
484
485 c.directive.opcode = nvme_admin_directive_recv;
486 c.directive.nsid = cpu_to_le32(nsid);
a082b426 487 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 488 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
489 c.directive.dtype = NVME_DIR_STREAMS;
490
491 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
492}
493
494static int nvme_configure_directives(struct nvme_ctrl *ctrl)
495{
496 struct streams_directive_params s;
497 int ret;
498
499 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
500 return 0;
501 if (!streams)
502 return 0;
503
504 ret = nvme_enable_streams(ctrl);
505 if (ret)
506 return ret;
507
62346eae 508 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 509 if (ret)
510 return ret;
511
512 ctrl->nssa = le16_to_cpu(s.nssa);
513 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
514 dev_info(ctrl->device, "too few streams (%u) available\n",
515 ctrl->nssa);
516 nvme_disable_streams(ctrl);
517 return 0;
518 }
519
520 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
521 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
522 return 0;
523}
524
525/*
526 * Check if 'req' has a write hint associated with it. If it does, assign
527 * a valid namespace stream to the write.
528 */
529static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
530 struct request *req, u16 *control,
531 u32 *dsmgmt)
532{
533 enum rw_hint streamid = req->write_hint;
534
535 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
536 streamid = 0;
537 else {
538 streamid--;
539 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
540 return;
541
542 *control |= NVME_RW_DTYPE_STREAMS;
543 *dsmgmt |= streamid << 16;
544 }
545
546 if (streamid < ARRAY_SIZE(req->q->write_hints))
547 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
548}
549
8093f7ca
ML		 550static inline void nvme_setup_flush(struct nvme_ns *ns,
551 struct nvme_command *cmnd)
552{
8093f7ca 553 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 554 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 555}
556
fc17b653 557static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 558 struct nvme_command *cmnd)
559{
b35ba01e 560 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 561 struct nvme_dsm_range *range;
b35ba01e 562 struct bio *bio;
8093f7ca 563
cb5b7262
JA		 564 range = kmalloc_array(segments, sizeof(*range),
565 GFP_ATOMIC | __GFP_NOWARN);
566 if (!range) {
567 /*
568 * If we fail allocation our range, fallback to the controller
569 * discard page. If that's also busy, it's safe to return
570 * busy, as we know we can make progress once that's freed.
571 */
572 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
573 return BLK_STS_RESOURCE;
574
575 range = page_address(ns->ctrl->discard_page);
576 }
8093f7ca 577
b35ba01e
CH		 578 __rq_for_each_bio(bio, req) {
579 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
580 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
581
8cb6af7b
KB		 582 if (n < segments) {
583 range[n].cattr = cpu_to_le32(0);
584 range[n].nlb = cpu_to_le32(nlb);
585 range[n].slba = cpu_to_le64(slba);
586 }
b35ba01e
CH		 587 n++;
588 }
589
590 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 591 if (virt_to_page(range) == ns->ctrl->discard_page)
592 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
593 else
594 kfree(range);
fc17b653 595 return BLK_STS_IOERR;
b35ba01e 596 }
8093f7ca 597
8093f7ca 598 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 599 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 600 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 601 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
602
f9d03f96
CH		 603 req->special_vec.bv_page = virt_to_page(range);
604 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 605 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 606 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 607
fc17b653 608 return BLK_STS_OK;
8093f7ca 609}
8093f7ca 610
6e02318e
CK		 611static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
612 struct request *req, struct nvme_command *cmnd)
613{
614 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
615 return nvme_setup_discard(ns, req, cmnd);
616
617 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
618 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
619 cmnd->write_zeroes.slba =
620 cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
621 cmnd->write_zeroes.length =
622 cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
623 cmnd->write_zeroes.control = 0;
624 return BLK_STS_OK;
625}
626
ebe6d874
CH		 627static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
628 struct request *req, struct nvme_command *cmnd)
8093f7ca 629{
f5d11840 630 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 631 u16 control = 0;
632 u32 dsmgmt = 0;
633
634 if (req->cmd_flags & REQ_FUA)
635 control |= NVME_RW_FUA;
636 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
637 control |= NVME_RW_LR;
638
639 if (req->cmd_flags & REQ_RAHEAD)
640 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
641
8093f7ca 642 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 643 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 644 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
645 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
646
f5d11840
JA		 647 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
648 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
649
8093f7ca 650 if (ns->ms) {
715ea9e0
CH		 651 /*
652 * If formated with metadata, the block layer always provides a
653 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
654 * we enable the PRACT bit for protection information or set the
655 * namespace capacity to zero to prevent any I/O.
656 */
657 if (!blk_integrity_rq(req)) {
658 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
659 return BLK_STS_NOTSUPP;
660 control |= NVME_RW_PRINFO_PRACT;
f7f1fc36
MG		 661 } else if (req_op(req) == REQ_OP_WRITE) {
662 t10_pi_prepare(req, ns->pi_type);
715ea9e0
CH		 663 }
664
8093f7ca
ML		 665 switch (ns->pi_type) {
666 case NVME_NS_DPS_PI_TYPE3:
667 control |= NVME_RW_PRINFO_PRCHK_GUARD;
668 break;
669 case NVME_NS_DPS_PI_TYPE1:
670 case NVME_NS_DPS_PI_TYPE2:
671 control |= NVME_RW_PRINFO_PRCHK_GUARD |
672 NVME_RW_PRINFO_PRCHK_REF;
ddd0bc75 673 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML		 674 break;
675 }
8093f7ca
ML		 676 }
677
678 cmnd->rw.control = cpu_to_le16(control);
679 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 680 return 0;
8093f7ca
ML		 681}
682
f7f1fc36
MG		 683void nvme_cleanup_cmd(struct request *req)
684{
685 if (blk_integrity_rq(req) && req_op(req) == REQ_OP_READ &&
686 nvme_req(req)->status == 0) {
687 struct nvme_ns *ns = req->rq_disk->private_data;
688
689 t10_pi_complete(req, ns->pi_type,
690 blk_rq_bytes(req) >> ns->lba_shift);
691 }
692 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
cb5b7262
JA		 693 struct nvme_ns *ns = req->rq_disk->private_data;
694 struct page *page = req->special_vec.bv_page;
695
696 if (page == ns->ctrl->discard_page)
697 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
698 else
699 kfree(page_address(page) + req->special_vec.bv_offset);
f7f1fc36
MG		 700 }
701}
702EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
703
fc17b653 704blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 705 struct nvme_command *cmd)
706{
fc17b653 707 blk_status_t ret = BLK_STS_OK;
8093f7ca 708
bb06ec31 709 nvme_clear_nvme_request(req);
987f699a 710
11902035 711 memset(cmd, 0, sizeof(*cmd));
aebf526b
CH		 712 switch (req_op(req)) {
713 case REQ_OP_DRV_IN:
714 case REQ_OP_DRV_OUT:
d49187e9 715 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 716 break;
717 case REQ_OP_FLUSH:
8093f7ca 718 nvme_setup_flush(ns, cmd);
aebf526b 719 break;
e850fd16 720 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 721 ret = nvme_setup_write_zeroes(ns, req, cmd);
722 break;
aebf526b 723 case REQ_OP_DISCARD:
8093f7ca 724 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 725 break;
726 case REQ_OP_READ:
727 case REQ_OP_WRITE:
ebe6d874 728 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 729 break;
730 default:
731 WARN_ON_ONCE(1);
fc17b653 732 return BLK_STS_IOERR;
aebf526b 733 }
8093f7ca 734
721b3917 735 cmd->common.command_id = req->tag;
5d87eb94 736 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 737 return ret;
738}
739EXPORT_SYMBOL_GPL(nvme_setup_cmd);
740
6287b51c
SG		 741static void nvme_end_sync_rq(struct request *rq, blk_status_t error)
742{
743 struct completion *waiting = rq->end_io_data;
744
745 rq->end_io_data = NULL;
746 complete(waiting);
747}
748
749static void nvme_execute_rq_polled(struct request_queue *q,
750 struct gendisk *bd_disk, struct request *rq, int at_head)
751{
752 DECLARE_COMPLETION_ONSTACK(wait);
753
754 WARN_ON_ONCE(!test_bit(QUEUE_FLAG_POLL, &q->queue_flags));
755
756 rq->cmd_flags |= REQ_HIPRI;
757 rq->end_io_data = &wait;
758 blk_execute_rq_nowait(q, bd_disk, rq, at_head, nvme_end_sync_rq);
759
760 while (!completion_done(&wait)) {
761 blk_poll(q, request_to_qc_t(rq->mq_hctx, rq), true);
762 cond_resched();
763 }
764}
765
4160982e
CH		 766/*
767 * Returns 0 on success. If the result is negative, it's a Linux error code;
768 * if the result is positive, it's an NVM Express status code
769 */
770int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 771 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 772 unsigned timeout, int qid, int at_head,
6287b51c 773 blk_mq_req_flags_t flags, bool poll)
4160982e
CH		 774{
775 struct request *req;
776 int ret;
777
eb71f435 778 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 779 if (IS_ERR(req))
780 return PTR_ERR(req);
781
782 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
783
21d34711
CH		 784 if (buffer && bufflen) {
785 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
786 if (ret)
787 goto out;
4160982e
CH		 788 }
789
6287b51c
SG		 790 if (poll)
791 nvme_execute_rq_polled(req->q, NULL, req, at_head);
792 else
793 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 794 if (result)
795 *result = nvme_req(req)->result;
27fa9bc5
CH		 796 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
797 ret = -EINTR;
798 else
799 ret = nvme_req(req)->status;
4160982e
CH		 800 out:
801 blk_mq_free_request(req);
802 return ret;
803}
eb71f435 804EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 805
806int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
807 void *buffer, unsigned bufflen)
808{
eb71f435 809 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
6287b51c 810 NVME_QID_ANY, 0, 0, false);
4160982e 811}
576d55d6 812EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 813
1cad6562
CH		 814static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
815 unsigned len, u32 seed, bool write)
816{
817 struct bio_integrity_payload *bip;
818 int ret = -ENOMEM;
819 void *buf;
820
821 buf = kmalloc(len, GFP_KERNEL);
822 if (!buf)
823 goto out;
824
825 ret = -EFAULT;
826 if (write && copy_from_user(buf, ubuf, len))
827 goto out_free_meta;
828
829 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
830 if (IS_ERR(bip)) {
831 ret = PTR_ERR(bip);
832 goto out_free_meta;
833 }
834
835 bip->bip_iter.bi_size = len;
836 bip->bip_iter.bi_sector = seed;
837 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
838 offset_in_page(buf));
839 if (ret == len)
840 return buf;
841 ret = -ENOMEM;
842out_free_meta:
843 kfree(buf);
844out:
845 return ERR_PTR(ret);
846}
847
63263d60 848static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 849 struct nvme_command *cmd, void __user *ubuffer,
850 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
851 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 852{
7a5abb4b 853 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 854 struct nvme_ns *ns = q->queuedata;
855 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 856 struct request *req;
0b7f1f26
KB		 857 struct bio *bio = NULL;
858 void *meta = NULL;
4160982e
CH		 859 int ret;
860
eb71f435 861 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 862 if (IS_ERR(req))
863 return PTR_ERR(req);
864
865 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 866 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 867
868 if (ubuffer && bufflen) {
21d34711
CH		 869 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
870 GFP_KERNEL);
871 if (ret)
872 goto out;
873 bio = req->bio;
74d46992 874 bio->bi_disk = disk;
1cad6562
CH		 875 if (disk && meta_buffer && meta_len) {
876 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
877 meta_seed, write);
878 if (IS_ERR(meta)) {
879 ret = PTR_ERR(meta);
0b7f1f26
KB		 880 goto out_unmap;
881 }
f31a2110 882 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 883 }
884 }
1cad6562 885
0b7f1f26 886 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 887 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
888 ret = -EINTR;
889 else
890 ret = nvme_req(req)->status;
21d34711 891 if (result)
d49187e9 892 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 893 if (meta && !ret && !write) {
894 if (copy_to_user(meta_buffer, meta, meta_len))
895 ret = -EFAULT;
896 }
0b7f1f26
KB		 897 kfree(meta);
898 out_unmap:
74d46992 899 if (bio)
0b7f1f26 900 blk_rq_unmap_user(bio);
21d34711
CH		 901 out:
902 blk_mq_free_request(req);
903 return ret;
904}
905
2a842aca 906static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 907{
908 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 909 unsigned long flags;
910 bool startka = false;
038bd4cb
SG		 911
912 blk_mq_free_request(rq);
913
2a842aca 914 if (status) {
038bd4cb 915 dev_err(ctrl->device,
2a842aca
CH		 916 "failed nvme_keep_alive_end_io error=%d\n",
917 status);
038bd4cb
SG		 918 return;
919 }
920
6e3ca03e 921 ctrl->comp_seen = false;
86880d64
JS		 922 spin_lock_irqsave(&ctrl->lock, flags);
923 if (ctrl->state == NVME_CTRL_LIVE ||
924 ctrl->state == NVME_CTRL_CONNECTING)
925 startka = true;
926 spin_unlock_irqrestore(&ctrl->lock, flags);
927 if (startka)
928 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
038bd4cb
SG		 929}
930
931static int nvme_keep_alive(struct nvme_ctrl *ctrl)
932{
038bd4cb
SG		 933 struct request *rq;
934
0a34e466 935 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 936 NVME_QID_ANY);
937 if (IS_ERR(rq))
938 return PTR_ERR(rq);
939
940 rq->timeout = ctrl->kato * HZ;
941 rq->end_io_data = ctrl;
942
943 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
944
945 return 0;
946}
947
948static void nvme_keep_alive_work(struct work_struct *work)
949{
950 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
951 struct nvme_ctrl, ka_work);
6e3ca03e
SG		 952 bool comp_seen = ctrl->comp_seen;
953
954 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
955 dev_dbg(ctrl->device,
956 "reschedule traffic based keep-alive timer\n");
957 ctrl->comp_seen = false;
958 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
959 return;
960 }
038bd4cb
SG		 961
962 if (nvme_keep_alive(ctrl)) {
963 /* allocation failure, reset the controller */
964 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 965 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 966 return;
967 }
968}
969
00b683db 970static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 971{
972 if (unlikely(ctrl->kato == 0))
973 return;
974
038bd4cb
SG		 975 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
976}
038bd4cb
SG		 977
978void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
979{
980 if (unlikely(ctrl->kato == 0))
981 return;
982
983 cancel_delayed_work_sync(&ctrl->ka_work);
984}
985EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
986
3f7f25a9 987static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 988{
989 struct nvme_command c = { };
990 int error;
991
992 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
993 c.identify.opcode = nvme_admin_identify;
986994a2 994 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 995
996 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
997 if (!*id)
998 return -ENOMEM;
999
1000 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1001 sizeof(struct nvme_id_ctrl));
1002 if (error)
1003 kfree(*id);
1004 return error;
1005}
1006
cdbff4f2 1007static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 1008 struct nvme_ns_ids *ids)
3b22ba26
JT		 1009{
1010 struct nvme_command c = { };
1011 int status;
1012 void *data;
1013 int pos;
1014 int len;
1015
1016 c.identify.opcode = nvme_admin_identify;
1017 c.identify.nsid = cpu_to_le32(nsid);
1018 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1019
1020 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1021 if (!data)
1022 return -ENOMEM;
1023
cdbff4f2 1024 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 1025 NVME_IDENTIFY_DATA_SIZE);
1026 if (status)
1027 goto free_data;
1028
1029 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1030 struct nvme_ns_id_desc *cur = data + pos;
1031
1032 if (cur->nidl == 0)
1033 break;
1034
1035 switch (cur->nidt) {
1036 case NVME_NIDT_EUI64:
1037 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 1038 dev_warn(ctrl->device,
3b22ba26
JT		 1039 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
1040 cur->nidl);
1041 goto free_data;
1042 }
1043 len = NVME_NIDT_EUI64_LEN;
002fab04 1044 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1045 break;
1046 case NVME_NIDT_NGUID:
1047 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 1048 dev_warn(ctrl->device,
3b22ba26
JT		 1049 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
1050 cur->nidl);
1051 goto free_data;
1052 }
1053 len = NVME_NIDT_NGUID_LEN;
002fab04 1054 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1055 break;
1056 case NVME_NIDT_UUID:
1057 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 1058 dev_warn(ctrl->device,
3b22ba26
JT		 1059 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
1060 cur->nidl);
1061 goto free_data;
1062 }
1063 len = NVME_NIDT_UUID_LEN;
002fab04 1064 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 1065 break;
1066 default:
53b3a661 1067 /* Skip unknown types */
3b22ba26
JT		 1068 len = cur->nidl;
1069 break;
1070 }
1071
1072 len += sizeof(*cur);
1073 }
1074free_data:
1075 kfree(data);
1076 return status;
1077}
1078
540c801c
KB		 1079static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
1080{
1081 struct nvme_command c = { };
1082
1083 c.identify.opcode = nvme_admin_identify;
986994a2 1084 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 1085 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 1086 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
1087 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 1088}
1089
cdbff4f2
CH		 1090static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
1091 unsigned nsid)
21d34711 1092{
cdbff4f2 1093 struct nvme_id_ns *id;
21d34711
CH		 1094 struct nvme_command c = { };
1095 int error;
1096
1097 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1098 c.identify.opcode = nvme_admin_identify;
1099 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1100 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1101
cdbff4f2
CH		 1102 id = kmalloc(sizeof(*id), GFP_KERNEL);
1103 if (!id)
1104 return NULL;
21d34711 1105
cdbff4f2
CH		 1106 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1107 if (error) {
1108 dev_warn(ctrl->device, "Identify namespace failed\n");
1109 kfree(id);
1110 return NULL;
1111 }
1112
1113 return id;
21d34711
CH		 1114}
1115
3f7f25a9 1116static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 1117 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 1118{
1119 struct nvme_command c;
d49187e9 1120 union nvme_result res;
1cb3cce5 1121 int ret;
21d34711
CH		 1122
1123 memset(&c, 0, sizeof(c));
1124 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 1125 c.features.fid = cpu_to_le32(fid);
1126 c.features.dword11 = cpu_to_le32(dword11);
1127
d49187e9 1128 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
6287b51c 1129 buffer, buflen, 0, NVME_QID_ANY, 0, 0, false);
9b47f77a 1130 if (ret >= 0 && result)
d49187e9 1131 *result = le32_to_cpu(res.u32);
1cb3cce5 1132 return ret;
21d34711
CH		 1133}
1134
9a0be7ab
CH		 1135int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1136{
1137 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1138 u32 result;
1139 int status, nr_io_queues;
1140
1a6fe74d 1141 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1142 &result);
f5fa90dc 1143 if (status < 0)
9a0be7ab
CH		 1144 return status;
1145
f5fa90dc
CH		 1146 /*
1147 * Degraded controllers might return an error when setting the queue
1148 * count. We still want to be able to bring them online and offer
1149 * access to the admin queue, as that might be only way to fix them up.
1150 */
1151 if (status > 0) {
f0425db0 1152 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1153 *count = 0;
1154 } else {
1155 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1156 *count = min(*count, nr_io_queues);
1157 }
1158
9a0be7ab
CH		 1159 return 0;
1160}
576d55d6 1161EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1162
c0561f82 1163#define NVME_AEN_SUPPORTED \
0d0b660f 1164 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | NVME_AEN_CFG_ANA_CHANGE)
c0561f82
HR		 1165
1166static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1167{
fa441b71 1168 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1169 int status;
1170
fa441b71
WZ		 1171 if (!supported_aens)
1172 return;
1173
1174 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1175 NULL, 0, &result);
c0561f82
HR		 1176 if (status)
1177 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1178 supported_aens);
c0561f82
HR		 1179}
1180
1673f1f0
CH		 1181static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1182{
1183 struct nvme_user_io io;
1184 struct nvme_command c;
1185 unsigned length, meta_len;
1186 void __user *metadata;
1187
1188 if (copy_from_user(&io, uio, sizeof(io)))
1189 return -EFAULT;
63088ec7
KB		 1190 if (io.flags)
1191 return -EINVAL;
1673f1f0
CH		 1192
1193 switch (io.opcode) {
1194 case nvme_cmd_write:
1195 case nvme_cmd_read:
1196 case nvme_cmd_compare:
1197 break;
1198 default:
1199 return -EINVAL;
1200 }
1201
1202 length = (io.nblocks + 1) << ns->lba_shift;
1203 meta_len = (io.nblocks + 1) * ns->ms;
1204 metadata = (void __user *)(uintptr_t)io.metadata;
1205
1206 if (ns->ext) {
1207 length += meta_len;
1208 meta_len = 0;
1209 } else if (meta_len) {
1210 if ((io.metadata & 3) || !io.metadata)
1211 return -EINVAL;
1212 }
1213
1214 memset(&c, 0, sizeof(c));
1215 c.rw.opcode = io.opcode;
1216 c.rw.flags = io.flags;
ed754e5d 1217 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1218 c.rw.slba = cpu_to_le64(io.slba);
1219 c.rw.length = cpu_to_le16(io.nblocks);
1220 c.rw.control = cpu_to_le16(io.control);
1221 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1222 c.rw.reftag = cpu_to_le32(io.reftag);
1223 c.rw.apptag = cpu_to_le16(io.apptag);
1224 c.rw.appmask = cpu_to_le16(io.appmask);
1225
63263d60 1226 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0 1227 (void __user *)(uintptr_t)io.addr, length,
202359c0 1228 metadata, meta_len, lower_32_bits(io.slba), NULL, 0);
1673f1f0
CH		 1229}
1230
84fef62d
KB		 1231static u32 nvme_known_admin_effects(u8 opcode)
1232{
1233 switch (opcode) {
1234 case nvme_admin_format_nvm:
1235 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1236 NVME_CMD_EFFECTS_CSE_MASK;
1237 case nvme_admin_sanitize_nvm:
1238 return NVME_CMD_EFFECTS_CSE_MASK;
1239 default:
1240 break;
1241 }
1242 return 0;
1243}
1244
1245static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1246 u8 opcode)
1247{
1248 u32 effects = 0;
1249
1250 if (ns) {
1251 if (ctrl->effects)
1252 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
415df90b 1253 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
84fef62d
KB		 1254 dev_warn(ctrl->device,
1255 "IO command:%02x has unhandled effects:%08x\n",
1256 opcode, effects);
1257 return 0;
1258 }
1259
1260 if (ctrl->effects)
62843c2e 1261 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1262 else
1263 effects = nvme_known_admin_effects(opcode);
1264
1265 /*
1266 * For simplicity, IO to all namespaces is quiesced even if the command
1267 * effects say only one namespace is affected.
1268 */
1269 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
e7ad43c3 1270 mutex_lock(&ctrl->scan_lock);
84fef62d
KB		 1271 nvme_start_freeze(ctrl);
1272 nvme_wait_freeze(ctrl);
1273 }
1274 return effects;
1275}
1276
1277static void nvme_update_formats(struct nvme_ctrl *ctrl)
1278{
cf39a6bc 1279 struct nvme_ns *ns;
84fef62d 1280
cf39a6bc
SB		 1281 down_read(&ctrl->namespaces_rwsem);
1282 list_for_each_entry(ns, &ctrl->namespaces, list)
1283 if (ns->disk && nvme_revalidate_disk(ns->disk))
1284 nvme_set_queue_dying(ns);
1285 up_read(&ctrl->namespaces_rwsem);
3fd176b7 1286
cf39a6bc 1287 nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
84fef62d
KB		 1288}
1289
1290static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1291{
1292 /*
1293 * Revalidate LBA changes prior to unfreezing. This is necessary to
1294 * prevent memory corruption if a logical block size was changed by
1295 * this command.
1296 */
1297 if (effects & NVME_CMD_EFFECTS_LBCC)
1298 nvme_update_formats(ctrl);
e7ad43c3 1299 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
84fef62d 1300 nvme_unfreeze(ctrl);
e7ad43c3
KB		 1301 mutex_unlock(&ctrl->scan_lock);
1302 }
84fef62d
KB		 1303 if (effects & NVME_CMD_EFFECTS_CCC)
1304 nvme_init_identify(ctrl);
1305 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1306 nvme_queue_scan(ctrl);
1307}
1308
f3ca80fc 1309static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1310 struct nvme_passthru_cmd __user *ucmd)
1311{
1312 struct nvme_passthru_cmd cmd;
1313 struct nvme_command c;
1314 unsigned timeout = 0;
84fef62d 1315 u32 effects;
1673f1f0
CH		 1316 int status;
1317
1318 if (!capable(CAP_SYS_ADMIN))
1319 return -EACCES;
1320 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1321 return -EFAULT;
63088ec7
KB		 1322 if (cmd.flags)
1323 return -EINVAL;
1673f1f0
CH		 1324
1325 memset(&c, 0, sizeof(c));
1326 c.common.opcode = cmd.opcode;
1327 c.common.flags = cmd.flags;
1328 c.common.nsid = cpu_to_le32(cmd.nsid);
1329 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1330 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
b7c8f366
CK		 1331 c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1332 c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1333 c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1334 c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1335 c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1336 c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1673f1f0
CH		 1337
1338 if (cmd.timeout_ms)
1339 timeout = msecs_to_jiffies(cmd.timeout_ms);
1340
84fef62d 1341 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1342 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1343 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
9b382768 1344 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata_len,
63263d60 1345 0, &cmd.result, timeout);
84fef62d
KB		 1346 nvme_passthru_end(ctrl, effects);
1347
1673f1f0
CH		 1348 if (status >= 0) {
1349 if (put_user(cmd.result, &ucmd->result))
1350 return -EFAULT;
1351 }
1352
1353 return status;
1354}
1355
32acab31
CH		 1356/*
1357 * Issue ioctl requests on the first available path. Note that unlike normal
1358 * block layer requests we will not retry failed request on another controller.
1359 */
1360static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1361 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1362{
32acab31
CH		 1363#ifdef CONFIG_NVME_MULTIPATH
1364 if (disk->fops == &nvme_ns_head_ops) {
9dae6465
CH		 1365 struct nvme_ns *ns;
1366
32acab31
CH		 1367 *head = disk->private_data;
1368 *srcu_idx = srcu_read_lock(&(*head)->srcu);
9dae6465
CH		 1369 ns = nvme_find_path(*head);
1370 if (!ns)
1371 srcu_read_unlock(&(*head)->srcu, *srcu_idx);
1372 return ns;
32acab31
CH		 1373 }
1374#endif
1375 *head = NULL;
1376 *srcu_idx = -1;
1377 return disk->private_data;
1378}
1673f1f0 1379
32acab31
CH		 1380static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1381{
1382 if (head)
1383 srcu_read_unlock(&head->srcu, idx);
1384}
1673f1f0 1385
32acab31
CH		 1386static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1387 unsigned int cmd, unsigned long arg)
1673f1f0 1388{
32acab31 1389 struct nvme_ns_head *head = NULL;
44dbc060 1390 void __user *argp = (void __user *)arg;
32acab31
CH		 1391 struct nvme_ns *ns;
1392 int srcu_idx, ret;
1393
1394 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1395 if (unlikely(!ns))
9dae6465
CH		 1396 return -EWOULDBLOCK;
1397
44dbc060
CH		 1398 switch (cmd) {
1399 case NVME_IOCTL_ID:
1400 force_successful_syscall_return();
1401 ret = ns->head->ns_id;
1402 break;
1403 case NVME_IOCTL_ADMIN_CMD:
1404 ret = nvme_user_cmd(ns->ctrl, NULL, argp);
1405 break;
1406 case NVME_IOCTL_IO_CMD:
1407 ret = nvme_user_cmd(ns->ctrl, ns, argp);
1408 break;
1409 case NVME_IOCTL_SUBMIT_IO:
1410 ret = nvme_submit_io(ns, argp);
1411 break;
1412 default:
1413 if (ns->ndev)
1414 ret = nvme_nvm_ioctl(ns, cmd, arg);
1415 else if (is_sed_ioctl(cmd))
1416 ret = sed_ioctl(ns->ctrl->opal_dev, cmd, argp);
1417 else
1418 ret = -ENOTTY;
1419 }
1420
32acab31
CH		 1421 nvme_put_ns_from_disk(head, srcu_idx);
1422 return ret;
1673f1f0 1423}
1673f1f0
CH		 1424
1425static int nvme_open(struct block_device *bdev, fmode_t mode)
1426{
c6424a90
CH		 1427 struct nvme_ns *ns = bdev->bd_disk->private_data;
1428
32acab31
CH		 1429#ifdef CONFIG_NVME_MULTIPATH
1430 /* should never be called due to GENHD_FL_HIDDEN */
1431 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1432 goto fail;
32acab31 1433#endif
c6424a90 1434 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1435 goto fail;
1436 if (!try_module_get(ns->ctrl->ops->module))
1437 goto fail_put_ns;
1438
c6424a90 1439 return 0;
85088c4a
NC		 1440
1441fail_put_ns:
1442 nvme_put_ns(ns);
1443fail:
1444 return -ENXIO;
1673f1f0
CH		 1445}
1446
1447static void nvme_release(struct gendisk *disk, fmode_t mode)
1448{
85088c4a
NC		 1449 struct nvme_ns *ns = disk->private_data;
1450
1451 module_put(ns->ctrl->ops->module);
1452 nvme_put_ns(ns);
1673f1f0
CH		 1453}
1454
1455static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1456{
1457 /* some standard values */
1458 geo->heads = 1 << 6;
1459 geo->sectors = 1 << 5;
1460 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1461 return 0;
1462}
1463
1464#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1465static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1466{
1467 struct blk_integrity integrity;
1468
fa9a89fc 1469 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1470 switch (pi_type) {
1673f1f0
CH		 1471 case NVME_NS_DPS_PI_TYPE3:
1472 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1473 integrity.tag_size = sizeof(u16) + sizeof(u32);
1474 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1475 break;
1476 case NVME_NS_DPS_PI_TYPE1:
1477 case NVME_NS_DPS_PI_TYPE2:
1478 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1479 integrity.tag_size = sizeof(u16);
1480 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1481 break;
1482 default:
1483 integrity.profile = NULL;
1484 break;
1485 }
39b7baa4
CH		 1486 integrity.tuple_size = ms;
1487 blk_integrity_register(disk, &integrity);
1488 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1489}
1490#else
39b7baa4 1491static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1492{
1493}
1494#endif /* CONFIG_BLK_DEV_INTEGRITY */
1495
6b8190d6
SB		 1496static void nvme_set_chunk_size(struct nvme_ns *ns)
1497{
1498 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1499 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1500}
1501
26318571 1502static void nvme_config_discard(struct gendisk *disk, struct nvme_ns *ns)
1673f1f0 1503{
3831761e 1504 struct nvme_ctrl *ctrl = ns->ctrl;
26318571 1505 struct request_queue *queue = disk->queue;
30e5e929
CH		 1506 u32 size = queue_logical_block_size(queue);
1507
3831761e
JA		 1508 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1509 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1510 return;
1511 }
1512
1513 if (ctrl->nr_streams && ns->sws && ns->sgs)
1514 size *= ns->sws * ns->sgs;
08095e70 1515
b35ba01e
CH		 1516 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1517 NVME_DSM_MAX_RANGES);
1518
b224f613 1519 queue->limits.discard_alignment = 0;
30e5e929 1520 queue->limits.discard_granularity = size;
f5d11840 1521
3831761e
JA		 1522 /* If discard is already enabled, don't reset queue limits */
1523 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1524 return;
1525
30e5e929
CH		 1526 blk_queue_max_discard_sectors(queue, UINT_MAX);
1527 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1528
1529 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1530 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1531}
1532
9f0916ab 1533static void nvme_config_write_zeroes(struct gendisk *disk, struct nvme_ns *ns)
6e02318e
CK		 1534{
1535 u32 max_sectors;
1536 unsigned short bs = 1 << ns->lba_shift;
1537
7b210e4e
CH		 1538 if (!(ns->ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) ||
1539 (ns->ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
6e02318e
CK		 1540 return;
1541 /*
1542 * Even though NVMe spec explicitly states that MDTS is not
1543 * applicable to the write-zeroes:- "The restriction does not apply to
1544 * commands that do not transfer data between the host and the
1545 * controller (e.g., Write Uncorrectable ro Write Zeroes command).".
1546 * In order to be more cautious use controller's max_hw_sectors value
1547 * to configure the maximum sectors for the write-zeroes which is
1548 * configured based on the controller's MDTS field in the
1549 * nvme_init_identify() if available.
1550 */
1551 if (ns->ctrl->max_hw_sectors == UINT_MAX)
1552 max_sectors = ((u32)(USHRT_MAX + 1) * bs) >> 9;
1553 else
1554 max_sectors = ((u32)(ns->ctrl->max_hw_sectors + 1) * bs) >> 9;
1555
9f0916ab 1556 blk_queue_max_write_zeroes_sectors(disk->queue, max_sectors);
6e02318e
CK		 1557}
1558
cdbff4f2 1559static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1560 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1561{
002fab04
CH		 1562 memset(ids, 0, sizeof(*ids));
1563
cdbff4f2 1564 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1565 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1566 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1567 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1568 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1569 /* Don't treat error as fatal we potentially
1570 * already have a NGUID or EUI-64
1571 */
002fab04 1572 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1573 dev_warn(ctrl->device,
3b22ba26
JT		 1574 "%s: Identify Descriptors failed\n", __func__);
1575 }
ac81bfa9
MB		 1576}
1577
ed754e5d
CH		 1578static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1579{
1580 return !uuid_is_null(&ids->uuid) ||
1581 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1582 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1583}
1584
002fab04
CH		 1585static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1586{
1587 return uuid_equal(&a->uuid, &b->uuid) &&
1588 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1589 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1590}
1591
24b0b58c
CH		 1592static void nvme_update_disk_info(struct gendisk *disk,
1593 struct nvme_ns *ns, struct nvme_id_ns *id)
1594{
1595 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1596 unsigned short bs = 1 << ns->lba_shift;
24b0b58c 1597
12b83abc
SG		 1598 if (ns->lba_shift > PAGE_SHIFT) {
1599 /* unsupported block size, set capacity to 0 later */
1600 bs = (1 << 9);
1601 }
24b0b58c
CH		 1602 blk_mq_freeze_queue(disk->queue);
1603 blk_integrity_unregister(disk);
1604
cee160fd
JL		 1605 blk_queue_logical_block_size(disk->queue, bs);
1606 blk_queue_physical_block_size(disk->queue, bs);
1607 blk_queue_io_min(disk->queue, bs);
1608
24b0b58c
CH		 1609 if (ns->ms && !ns->ext &&
1610 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1611 nvme_init_integrity(disk, ns->ms, ns->pi_type);
12b83abc
SG		 1612 if ((ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk)) ||
1613 ns->lba_shift > PAGE_SHIFT)
24b0b58c 1614 capacity = 0;
24b0b58c 1615
3831761e 1616 set_capacity(disk, capacity);
b1aafb35 1617
26318571 1618 nvme_config_discard(disk, ns);
9f0916ab 1619 nvme_config_write_zeroes(disk, ns);
1293477f
CK		 1620
1621 if (id->nsattr & (1 << 0))
1622 set_disk_ro(disk, true);
1623 else
1624 set_disk_ro(disk, false);
1625
24b0b58c
CH		 1626 blk_mq_unfreeze_queue(disk->queue);
1627}
1628
ac81bfa9
MB		 1629static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1630{
1631 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1632
1633 /*
1634 * If identify namespace failed, use default 512 byte block size so
1635 * block layer can use before failing read/write for 0 capacity.
1636 */
c81bfba9 1637 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1638 if (ns->lba_shift == 0)
1639 ns->lba_shift = 9;
6b8190d6 1640 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1641 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1642 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1643 /* the PI implementation requires metadata equal t10 pi tuple size */
1644 if (ns->ms == sizeof(struct t10_pi_tuple))
1645 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1646 else
1647 ns->pi_type = 0;
1673f1f0 1648
6b8190d6
SB		 1649 if (ns->noiob)
1650 nvme_set_chunk_size(ns);
24b0b58c 1651 nvme_update_disk_info(disk, ns, id);
32acab31 1652#ifdef CONFIG_NVME_MULTIPATH
8f676b85 1653 if (ns->head->disk) {
32acab31 1654 nvme_update_disk_info(ns->head->disk, ns, id);
8f676b85
SG		 1655 blk_queue_stack_limits(ns->head->disk->queue, ns->queue);
1656 }
32acab31 1657#endif
ac81bfa9 1658}
1673f1f0 1659
ac81bfa9
MB		 1660static int nvme_revalidate_disk(struct gendisk *disk)
1661{
1662 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1663 struct nvme_ctrl *ctrl = ns->ctrl;
1664 struct nvme_id_ns *id;
002fab04 1665 struct nvme_ns_ids ids;
cdbff4f2 1666 int ret = 0;
ac81bfa9
MB		 1667
1668 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1669 set_capacity(disk, 0);
1670 return -ENODEV;
1671 }
1672
ed754e5d 1673 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1674 if (!id)
1675 return -ENODEV;
ac81bfa9 1676
cdbff4f2
CH		 1677 if (id->ncap == 0) {
1678 ret = -ENODEV;
1679 goto out;
1680 }
ac81bfa9 1681
5e0fab57 1682 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1683 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1684 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1685 dev_err(ctrl->device,
ed754e5d 1686 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1687 ret = -ENODEV;
1688 }
1689
cdbff4f2
CH		 1690out:
1691 kfree(id);
1692 return ret;
1673f1f0
CH		 1693}
1694
1695static char nvme_pr_type(enum pr_type type)
1696{
1697 switch (type) {
1698 case PR_WRITE_EXCLUSIVE:
1699 return 1;
1700 case PR_EXCLUSIVE_ACCESS:
1701 return 2;
1702 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1703 return 3;
1704 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1705 return 4;
1706 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1707 return 5;
1708 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1709 return 6;
1710 default:
1711 return 0;
1712 }
1713};
1714
1715static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1716 u64 key, u64 sa_key, u8 op)
1717{
32acab31
CH		 1718 struct nvme_ns_head *head = NULL;
1719 struct nvme_ns *ns;
1673f1f0 1720 struct nvme_command c;
32acab31 1721 int srcu_idx, ret;
1673f1f0
CH		 1722 u8 data[16] = { 0, };
1723
b0d61d58
KB		 1724 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1725 if (unlikely(!ns))
1726 return -EWOULDBLOCK;
1727
1673f1f0
CH		 1728 put_unaligned_le64(key, &data[0]);
1729 put_unaligned_le64(sa_key, &data[8]);
1730
1731 memset(&c, 0, sizeof(c));
1732 c.common.opcode = op;
b0d61d58 1733 c.common.nsid = cpu_to_le32(ns->head->ns_id);
b7c8f366 1734 c.common.cdw10 = cpu_to_le32(cdw10);
1673f1f0 1735
b0d61d58 1736 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1737 nvme_put_ns_from_disk(head, srcu_idx);
1738 return ret;
1673f1f0
CH		 1739}
1740
1741static int nvme_pr_register(struct block_device *bdev, u64 old,
1742 u64 new, unsigned flags)
1743{
1744 u32 cdw10;
1745
1746 if (flags & ~PR_FL_IGNORE_KEY)
1747 return -EOPNOTSUPP;
1748
1749 cdw10 = old ? 2 : 0;
1750 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1751 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1752 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1753}
1754
1755static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1756 enum pr_type type, unsigned flags)
1757{
1758 u32 cdw10;
1759
1760 if (flags & ~PR_FL_IGNORE_KEY)
1761 return -EOPNOTSUPP;
1762
1763 cdw10 = nvme_pr_type(type) << 8;
1764 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1765 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1766}
1767
1768static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1769 enum pr_type type, bool abort)
1770{
e9a9853c 1771 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1772 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1773}
1774
1775static int nvme_pr_clear(struct block_device *bdev, u64 key)
1776{
8c0b3915 1777 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1778 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1779}
1780
1781static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1782{
e9a9853c 1783 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1784 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1785}
1786
1787static const struct pr_ops nvme_pr_ops = {
1788 .pr_register = nvme_pr_register,
1789 .pr_reserve = nvme_pr_reserve,
1790 .pr_release = nvme_pr_release,
1791 .pr_preempt = nvme_pr_preempt,
1792 .pr_clear = nvme_pr_clear,
1793};
1794
a98e58e5 1795#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1796int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1797 bool send)
a98e58e5 1798{
4f1244c8 1799 struct nvme_ctrl *ctrl = data;
a98e58e5 1800 struct nvme_command cmd;
a98e58e5
SB		 1801
1802 memset(&cmd, 0, sizeof(cmd));
1803 if (send)
1804 cmd.common.opcode = nvme_admin_security_send;
1805 else
1806 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 1807 cmd.common.nsid = 0;
b7c8f366
CK		 1808 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1809 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5
SB		 1810
1811 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
6287b51c 1812 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0, false);
a98e58e5
SB		 1813}
1814EXPORT_SYMBOL_GPL(nvme_sec_submit);
1815#endif /* CONFIG_BLK_SED_OPAL */
1816
5bae7f73 1817static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1818 .owner = THIS_MODULE,
1819 .ioctl = nvme_ioctl,
761f2e1e 1820 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1821 .open = nvme_open,
1822 .release = nvme_release,
1823 .getgeo = nvme_getgeo,
1824 .revalidate_disk= nvme_revalidate_disk,
1825 .pr_ops = &nvme_pr_ops,
1826};
1827
32acab31
CH		 1828#ifdef CONFIG_NVME_MULTIPATH
1829static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1830{
1831 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1832
1833 if (!kref_get_unless_zero(&head->ref))
1834 return -ENXIO;
1835 return 0;
1836}
1837
1838static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1839{
1840 nvme_put_ns_head(disk->private_data);
1841}
1842
1843const struct block_device_operations nvme_ns_head_ops = {
1844 .owner = THIS_MODULE,
1845 .open = nvme_ns_head_open,
1846 .release = nvme_ns_head_release,
1847 .ioctl = nvme_ioctl,
1848 .compat_ioctl = nvme_ioctl,
1849 .getgeo = nvme_getgeo,
1850 .pr_ops = &nvme_pr_ops,
1851};
1852#endif /* CONFIG_NVME_MULTIPATH */
1853
5fd4ce1b
CH		 1854static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1855{
1856 unsigned long timeout =
1857 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1858 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1859 int ret;
1860
1861 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1862 if (csts == ~0)
1863 return -ENODEV;
5fd4ce1b
CH		 1864 if ((csts & NVME_CSTS_RDY) == bit)
1865 break;
1866
1867 msleep(100);
1868 if (fatal_signal_pending(current))
1869 return -EINTR;
1870 if (time_after(jiffies, timeout)) {
1b3c47c1 1871 dev_err(ctrl->device,
5fd4ce1b
CH		 1872 "Device not ready; aborting %s\n", enabled ?
1873 "initialisation" : "reset");
1874 return -ENODEV;
1875 }
1876 }
1877
1878 return ret;
1879}
1880
1881/*
1882 * If the device has been passed off to us in an enabled state, just clear
1883 * the enabled bit. The spec says we should set the 'shutdown notification
1884 * bits', but doing so may cause the device to complete commands to the
1885 * admin queue ... and we don't know what memory that might be pointing at!
1886 */
1887int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1888{
1889 int ret;
1890
1891 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1892 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1893
1894 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1895 if (ret)
1896 return ret;
54adc010 1897
b5a10c5f 1898 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1899 msleep(NVME_QUIRK_DELAY_AMOUNT);
1900
5fd4ce1b
CH		 1901 return nvme_wait_ready(ctrl, cap, false);
1902}
576d55d6 1903EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1904
1905int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1906{
1907 /*
1908 * Default to a 4K page size, with the intention to update this
1909 * path in the future to accomodate architectures with differing
1910 * kernel and IO page sizes.
1911 */
1912 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1913 int ret;
1914
1915 if (page_shift < dev_page_min) {
1b3c47c1 1916 dev_err(ctrl->device,
5fd4ce1b
CH		 1917 "Minimum device page size %u too large for host (%u)\n",
1918 1 << dev_page_min, 1 << page_shift);
1919 return -ENODEV;
1920 }
1921
1922 ctrl->page_size = 1 << page_shift;
1923
1924 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1925 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1926 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1927 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1928 ctrl->ctrl_config |= NVME_CC_ENABLE;
1929
1930 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1931 if (ret)
1932 return ret;
1933 return nvme_wait_ready(ctrl, cap, true);
1934}
576d55d6 1935EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1936
1937int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1938{
07fbd32a 1939 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1940 u32 csts;
1941 int ret;
1942
1943 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1944 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1945
1946 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1947 if (ret)
1948 return ret;
1949
1950 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1951 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1952 break;
1953
1954 msleep(100);
1955 if (fatal_signal_pending(current))
1956 return -EINTR;
1957 if (time_after(jiffies, timeout)) {
1b3c47c1 1958 dev_err(ctrl->device,
5fd4ce1b
CH		 1959 "Device shutdown incomplete; abort shutdown\n");
1960 return -ENODEV;
1961 }
1962 }
1963
1964 return ret;
1965}
576d55d6 1966EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1967
da35825d
CH		 1968static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1969 struct request_queue *q)
1970{
7c88cb00
JA		 1971 bool vwc = false;
1972
da35825d 1973 if (ctrl->max_hw_sectors) {
45686b61
CH		 1974 u32 max_segments =
1975 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1976
943e942e 1977 max_segments = min_not_zero(max_segments, ctrl->max_segments);
da35825d 1978 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1979 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1980 }
249159c5
KB		 1981 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1982 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1983 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1984 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1985 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1986 vwc = true;
1987 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1988}
1989
dbf86b39
JD		 1990static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1991{
1992 __le64 ts;
1993 int ret;
1994
1995 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1996 return 0;
1997
1998 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1999 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2000 NULL);
2001 if (ret)
2002 dev_warn_once(ctrl->device,
2003 "could not set timestamp (%d)\n", ret);
2004 return ret;
2005}
2006
49cd84b6
KB		 2007static int nvme_configure_acre(struct nvme_ctrl *ctrl)
2008{
2009 struct nvme_feat_host_behavior *host;
2010 int ret;
2011
2012 /* Don't bother enabling the feature if retry delay is not reported */
2013 if (!ctrl->crdt[0])
2014 return 0;
2015
2016 host = kzalloc(sizeof(*host), GFP_KERNEL);
2017 if (!host)
2018 return 0;
2019
2020 host->acre = NVME_ENABLE_ACRE;
2021 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2022 host, sizeof(*host), NULL);
2023 kfree(host);
2024 return ret;
2025}
2026
634b8325 2027static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 2028{
2029 /*
2030 * APST (Autonomous Power State Transition) lets us program a
2031 * table of power state transitions that the controller will
2032 * perform automatically. We configure it with a simple
2033 * heuristic: we are willing to spend at most 2% of the time
2034 * transitioning between power states. Therefore, when running
2035 * in any given state, we will enter the next lower-power
76e4ad09 2036 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 2037 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 2038 * the requested maximum latency.
2039 *
2040 * We will not autonomously enter any non-operational state for
2041 * which the total latency exceeds ps_max_latency_us. Users
2042 * can set ps_max_latency_us to zero to turn off APST.
2043 */
2044
2045 unsigned apste;
2046 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 2047 u64 max_lat_us = 0;
2048 int max_ps = -1;
c5552fde
AL		 2049 int ret;
2050
2051 /*
2052 * If APST isn't supported or if we haven't been initialized yet,
2053 * then don't do anything.
2054 */
2055 if (!ctrl->apsta)
634b8325 2056 return 0;
c5552fde
AL		 2057
2058 if (ctrl->npss > 31) {
2059 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2060 return 0;
c5552fde
AL		 2061 }
2062
2063 table = kzalloc(sizeof(*table), GFP_KERNEL);
2064 if (!table)
634b8325 2065 return 0;
c5552fde 2066
76a5af84 2067 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 2068 /* Turn off APST. */
2069 apste = 0;
fb0dc399 2070 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 2071 } else {
2072 __le64 target = cpu_to_le64(0);
2073 int state;
2074
2075 /*
2076 * Walk through all states from lowest- to highest-power.
2077 * According to the spec, lower-numbered states use more
2078 * power. NPSS, despite the name, is the index of the
2079 * lowest-power state, not the number of states.
2080 */
2081 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 2082 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 2083
2084 if (target)
2085 table->entries[state] = target;
2086
ff5350a8
AL		 2087 /*
2088 * Don't allow transitions to the deepest state
2089 * if it's quirked off.
2090 */
2091 if (state == ctrl->npss &&
2092 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2093 continue;
2094
c5552fde
AL		 2095 /*
2096 * Is this state a useful non-operational state for
2097 * higher-power states to autonomously transition to?
2098 */
2099 if (!(ctrl->psd[state].flags &
2100 NVME_PS_FLAGS_NON_OP_STATE))
2101 continue;
2102
da87591b
KHF		 2103 exit_latency_us =
2104 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2105 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 2106 continue;
2107
da87591b
KHF		 2108 total_latency_us =
2109 exit_latency_us +
2110 le32_to_cpu(ctrl->psd[state].entry_lat);
2111
c5552fde
AL		 2112 /*
2113 * This state is good. Use it as the APST idle
2114 * target for higher power states.
2115 */
2116 transition_ms = total_latency_us + 19;
2117 do_div(transition_ms, 20);
2118 if (transition_ms > (1 << 24) - 1)
2119 transition_ms = (1 << 24) - 1;
2120
2121 target = cpu_to_le64((state << 3) |
2122 (transition_ms << 8));
fb0dc399
AL		 2123
2124 if (max_ps == -1)
2125 max_ps = state;
2126
2127 if (total_latency_us > max_lat_us)
2128 max_lat_us = total_latency_us;
c5552fde
AL		 2129 }
2130
2131 apste = 1;
fb0dc399
AL		 2132
2133 if (max_ps == -1) {
2134 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2135 } else {
2136 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2137 max_ps, max_lat_us, (int)sizeof(*table), table);
2138 }
c5552fde
AL		 2139 }
2140
2141 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2142 table, sizeof(*table), NULL);
2143 if (ret)
2144 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
2145
2146 kfree(table);
634b8325 2147 return ret;
c5552fde
AL		 2148}
2149
2150static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2151{
2152 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2153 u64 latency;
2154
2155 switch (val) {
2156 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2157 case PM_QOS_LATENCY_ANY:
2158 latency = U64_MAX;
2159 break;
2160
2161 default:
2162 latency = val;
2163 }
2164
2165 if (ctrl->ps_max_latency_us != latency) {
2166 ctrl->ps_max_latency_us = latency;
2167 nvme_configure_apst(ctrl);
2168 }
2169}
2170
bd4da3ab
AL		 2171struct nvme_core_quirk_entry {
2172 /*
2173 * NVMe model and firmware strings are padded with spaces. For
2174 * simplicity, strings in the quirk table are padded with NULLs
2175 * instead.
2176 */
2177 u16 vid;
2178 const char *mn;
2179 const char *fr;
2180 unsigned long quirks;
2181};
2182
2183static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2184 {
be56945c
AL		 2185 /*
2186 * This Toshiba device seems to die using any APST states. See:
2187 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2188 */
2189 .vid = 0x1179,
2190 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2191 .quirks = NVME_QUIRK_NO_APST,
be56945c 2192 }
bd4da3ab
AL		 2193};
2194
2195/* match is null-terminated but idstr is space-padded. */
2196static bool string_matches(const char *idstr, const char *match, size_t len)
2197{
2198 size_t matchlen;
2199
2200 if (!match)
2201 return true;
2202
2203 matchlen = strlen(match);
2204 WARN_ON_ONCE(matchlen > len);
2205
2206 if (memcmp(idstr, match, matchlen))
2207 return false;
2208
2209 for (; matchlen < len; matchlen++)
2210 if (idstr[matchlen] != ' ')
2211 return false;
2212
2213 return true;
2214}
2215
2216static bool quirk_matches(const struct nvme_id_ctrl *id,
2217 const struct nvme_core_quirk_entry *q)
2218{
2219 return q->vid == le16_to_cpu(id->vid) &&
2220 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2221 string_matches(id->fr, q->fr, sizeof(id->fr));
2222}
2223
ab9e00cc
CH		 2224static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2225 struct nvme_id_ctrl *id)
180de007
CH		 2226{
2227 size_t nqnlen;
2228 int off;
2229
6299358d
JD		 2230 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2231 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2232 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2233 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2234 return;
2235 }
180de007 2236
6299358d
JD		 2237 if (ctrl->vs >= NVME_VS(1, 2, 1))
2238 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2239 }
180de007
CH		 2240
2241 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2242 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2243 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2244 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2245 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2246 off += sizeof(id->sn);
ab9e00cc 2247 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2248 off += sizeof(id->mn);
ab9e00cc
CH		 2249 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2250}
2251
2252static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
2253{
2254 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
2255 kfree(subsys);
2256}
2257
2258static void nvme_release_subsystem(struct device *dev)
2259{
2260 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
2261}
2262
2263static void nvme_destroy_subsystem(struct kref *ref)
2264{
2265 struct nvme_subsystem *subsys =
2266 container_of(ref, struct nvme_subsystem, ref);
2267
2268 mutex_lock(&nvme_subsystems_lock);
2269 list_del(&subsys->entry);
2270 mutex_unlock(&nvme_subsystems_lock);
2271
ed754e5d 2272 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2273 device_del(&subsys->dev);
2274 put_device(&subsys->dev);
2275}
2276
2277static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2278{
2279 kref_put(&subsys->ref, nvme_destroy_subsystem);
2280}
2281
2282static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2283{
2284 struct nvme_subsystem *subsys;
2285
2286 lockdep_assert_held(&nvme_subsystems_lock);
2287
2288 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2289 if (strcmp(subsys->subnqn, subsysnqn))
2290 continue;
2291 if (!kref_get_unless_zero(&subsys->ref))
2292 continue;
2293 return subsys;
2294 }
2295
2296 return NULL;
2297}
2298
1e496938
HR		 2299#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2300 struct device_attribute subsys_attr_##_name = \
2301 __ATTR(_name, _mode, _show, NULL)
2302
2303static ssize_t nvme_subsys_show_nqn(struct device *dev,
2304 struct device_attribute *attr,
2305 char *buf)
2306{
2307 struct nvme_subsystem *subsys =
2308 container_of(dev, struct nvme_subsystem, dev);
2309
2310 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2311}
2312static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2313
2314#define nvme_subsys_show_str_function(field) \
2315static ssize_t subsys_##field##_show(struct device *dev, \
2316 struct device_attribute *attr, char *buf) \
2317{ \
2318 struct nvme_subsystem *subsys = \
2319 container_of(dev, struct nvme_subsystem, dev); \
2320 return sprintf(buf, "%.*s\n", \
2321 (int)sizeof(subsys->field), subsys->field); \
2322} \
2323static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2324
2325nvme_subsys_show_str_function(model);
2326nvme_subsys_show_str_function(serial);
2327nvme_subsys_show_str_function(firmware_rev);
2328
2329static struct attribute *nvme_subsys_attrs[] = {
2330 &subsys_attr_model.attr,
2331 &subsys_attr_serial.attr,
2332 &subsys_attr_firmware_rev.attr,
2333 &subsys_attr_subsysnqn.attr,
75c10e73
HR		 2334#ifdef CONFIG_NVME_MULTIPATH
2335 &subsys_attr_iopolicy.attr,
2336#endif
1e496938
HR		 2337 NULL,
2338};
2339
2340static struct attribute_group nvme_subsys_attrs_group = {
2341 .attrs = nvme_subsys_attrs,
2342};
2343
2344static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2345 &nvme_subsys_attrs_group,
2346 NULL,
2347};
2348
b837b283
IR		 2349static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2350{
2351 int count = 0;
2352 struct nvme_ctrl *ctrl;
2353
2354 mutex_lock(&subsys->lock);
2355 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2356 if (ctrl->state != NVME_CTRL_DELETING &&
2357 ctrl->state != NVME_CTRL_DEAD)
2358 count++;
2359 }
2360 mutex_unlock(&subsys->lock);
2361
2362 return count;
2363}
2364
ab9e00cc
CH		 2365static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2366{
2367 struct nvme_subsystem *subsys, *found;
2368 int ret;
2369
2370 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2371 if (!subsys)
2372 return -ENOMEM;
2373 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2374 if (ret < 0) {
2375 kfree(subsys);
2376 return ret;
2377 }
2378 subsys->instance = ret;
2379 mutex_init(&subsys->lock);
2380 kref_init(&subsys->ref);
2381 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2382 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2383 nvme_init_subnqn(subsys, ctrl, id);
2384 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2385 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2386 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2387 subsys->vendor_id = le16_to_cpu(id->vid);
2388 subsys->cmic = id->cmic;
75c10e73
HR		 2389#ifdef CONFIG_NVME_MULTIPATH
2390 subsys->iopolicy = NVME_IOPOLICY_NUMA;
2391#endif
ab9e00cc
CH		 2392
2393 subsys->dev.class = nvme_subsys_class;
2394 subsys->dev.release = nvme_release_subsystem;
1e496938 2395 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2396 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2397 device_initialize(&subsys->dev);
2398
2399 mutex_lock(&nvme_subsystems_lock);
2400 found = __nvme_find_get_subsystem(subsys->subnqn);
2401 if (found) {
2402 /*
2403 * Verify that the subsystem actually supports multiple
2404 * controllers, else bail out.
2405 */
16001c10 2406 if (!(ctrl->opts && ctrl->opts->discovery_nqn) &&
181303d0 2407 nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2408 dev_err(ctrl->device,
2409 "ignoring ctrl due to duplicate subnqn (%s).\n",
2410 found->subnqn);
2411 nvme_put_subsystem(found);
2412 ret = -EINVAL;
2413 goto out_unlock;
2414 }
2415
2416 __nvme_release_subsystem(subsys);
2417 subsys = found;
2418 } else {
2419 ret = device_add(&subsys->dev);
2420 if (ret) {
2421 dev_err(ctrl->device,
2422 "failed to register subsystem device.\n");
2423 goto out_unlock;
2424 }
ed754e5d 2425 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2426 list_add_tail(&subsys->entry, &nvme_subsystems);
2427 }
2428
2429 ctrl->subsys = subsys;
2430 mutex_unlock(&nvme_subsystems_lock);
2431
2432 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2433 dev_name(ctrl->device))) {
2434 dev_err(ctrl->device,
2435 "failed to create sysfs link from subsystem.\n");
2436 /* the transport driver will eventually put the subsystem */
2437 return -EINVAL;
2438 }
2439
2440 mutex_lock(&subsys->lock);
2441 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2442 mutex_unlock(&subsys->lock);
2443
2444 return 0;
2445
2446out_unlock:
2447 mutex_unlock(&nvme_subsystems_lock);
2448 put_device(&subsys->dev);
2449 return ret;
180de007
CH		 2450}
2451
0e98719b
CH		 2452int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
2453 void *log, size_t size, u64 offset)
c627c487
KB		 2454{
2455 struct nvme_command c = { };
70da6094
MB		 2456 unsigned long dwlen = size / 4 - 1;
2457
2458 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2459 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2460 c.get_log_page.lid = log_page;
0e98719b 2461 c.get_log_page.lsp = lsp;
70da6094
MB		 2462 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2463 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2464 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2465 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2466
2467 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2468}
2469
84fef62d
KB		 2470static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2471{
2472 int ret;
2473
2474 if (!ctrl->effects)
2475 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2476
2477 if (!ctrl->effects)
2478 return 0;
2479
0e98719b
CH		 2480 ret = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CMD_EFFECTS, 0,
2481 ctrl->effects, sizeof(*ctrl->effects), 0);
84fef62d
KB		 2482 if (ret) {
2483 kfree(ctrl->effects);
2484 ctrl->effects = NULL;
2485 }
2486 return ret;
180de007
CH		 2487}
2488
7fd8930f
CH		 2489/*
2490 * Initialize the cached copies of the Identify data and various controller
2491 * register in our nvme_ctrl structure. This should be called as soon as
2492 * the admin queue is fully up and running.
2493 */
2494int nvme_init_identify(struct nvme_ctrl *ctrl)
2495{
2496 struct nvme_id_ctrl *id;
2497 u64 cap;
2498 int ret, page_shift;
a229dbf6 2499 u32 max_hw_sectors;
76a5af84 2500 bool prev_apst_enabled;
7fd8930f 2501
f3ca80fc
CH		 2502 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2503 if (ret) {
1b3c47c1 2504 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2505 return ret;
2506 }
2507
7fd8930f
CH		 2508 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2509 if (ret) {
1b3c47c1 2510 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2511 return ret;
2512 }
2513 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2514
8ef2074d 2515 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2516 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2517
7fd8930f
CH		 2518 ret = nvme_identify_ctrl(ctrl, &id);
2519 if (ret) {
1b3c47c1 2520 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2521 return -EIO;
2522 }
2523
84fef62d
KB		 2524 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2525 ret = nvme_get_effects_log(ctrl);
2526 if (ret < 0)
75c8b19a 2527 goto out_free;
84fef62d 2528 }
180de007 2529
bd4da3ab 2530 if (!ctrl->identified) {
ab9e00cc
CH		 2531 int i;
2532
2533 ret = nvme_init_subsystem(ctrl, id);
2534 if (ret)
2535 goto out_free;
2536
bd4da3ab
AL		 2537 /*
2538 * Check for quirks. Quirk can depend on firmware version,
2539 * so, in principle, the set of quirks present can change
2540 * across a reset. As a possible future enhancement, we
2541 * could re-scan for quirks every time we reinitialize
2542 * the device, but we'd have to make sure that the driver
2543 * behaves intelligently if the quirks change.
2544 */
bd4da3ab
AL		 2545 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2546 if (quirk_matches(id, &core_quirks[i]))
2547 ctrl->quirks |= core_quirks[i].quirks;
2548 }
2549 }
2550
c35e30b4 2551 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2552 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2553 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2554 }
2555
49cd84b6
KB		 2556 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
2557 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
2558 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
2559
8a9ae523 2560 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2561 ctrl->oncs = le16_to_cpup(&id->oncs);
c0561f82 2562 ctrl->oaes = le32_to_cpu(id->oaes);
6bf25d16 2563 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2564 ctrl->vwc = id->vwc;
7fd8930f 2565 if (id->mdts)
a229dbf6 2566 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2567 else
a229dbf6
CH		 2568 max_hw_sectors = UINT_MAX;
2569 ctrl->max_hw_sectors =
2570 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2571
da35825d 2572 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2573 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2574 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 2575 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 2576 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 2577
07fbd32a
MP		 2578 if (id->rtd3e) {
2579 /* us -> s */
2580 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2581
2582 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2583 shutdown_timeout, 60);
2584
2585 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2586 dev_info(ctrl->device,
07fbd32a
MP		 2587 "Shutdown timeout set to %u seconds\n",
2588 ctrl->shutdown_timeout);
2589 } else
2590 ctrl->shutdown_timeout = shutdown_timeout;
2591
c5552fde 2592 ctrl->npss = id->npss;
76a5af84
KHF		 2593 ctrl->apsta = id->apsta;
2594 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2595 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2596 if (force_apst && id->apsta) {
f0425db0 2597 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2598 ctrl->apst_enabled = true;
c35e30b4 2599 } else {
76a5af84 2600 ctrl->apst_enabled = false;
c35e30b4
AL		 2601 }
2602 } else {
76a5af84 2603 ctrl->apst_enabled = id->apsta;
c35e30b4 2604 }
c5552fde
AL		 2605 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2606
d3d5b87d 2607 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2608 ctrl->icdoff = le16_to_cpu(id->icdoff);
2609 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2610 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2611 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2612
2613 /*
2614 * In fabrics we need to verify the cntlid matches the
2615 * admin connect
2616 */
634b8325 2617 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2618 ret = -EINVAL;
634b8325
KB		 2619 goto out_free;
2620 }
038bd4cb
SG		 2621
2622 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2623 dev_err(ctrl->device,
038bd4cb
SG		 2624 "keep-alive support is mandatory for fabrics\n");
2625 ret = -EINVAL;
634b8325 2626 goto out_free;
038bd4cb 2627 }
07bfcd09
CH		 2628 } else {
2629 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2630 ctrl->hmpre = le32_to_cpu(id->hmpre);
2631 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2632 ctrl->hmminds = le32_to_cpu(id->hmminds);
2633 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2634 }
da35825d 2635
0d0b660f 2636 ret = nvme_mpath_init(ctrl, id);
7fd8930f 2637 kfree(id);
bd4da3ab 2638
0d0b660f
CH		 2639 if (ret < 0)
2640 return ret;
2641
76a5af84 2642 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2643 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2644 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2645 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2646
634b8325
KB		 2647 ret = nvme_configure_apst(ctrl);
2648 if (ret < 0)
2649 return ret;
dbf86b39
JD		 2650
2651 ret = nvme_configure_timestamp(ctrl);
2652 if (ret < 0)
2653 return ret;
634b8325
KB		 2654
2655 ret = nvme_configure_directives(ctrl);
2656 if (ret < 0)
2657 return ret;
c5552fde 2658
49cd84b6
KB		 2659 ret = nvme_configure_acre(ctrl);
2660 if (ret < 0)
2661 return ret;
2662
bd4da3ab 2663 ctrl->identified = true;
c5552fde 2664
634b8325
KB		 2665 return 0;
2666
2667out_free:
2668 kfree(id);
07bfcd09 2669 return ret;
7fd8930f 2670}
576d55d6 2671EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2672
f3ca80fc 2673static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2674{
a6a5149b
CH		 2675 struct nvme_ctrl *ctrl =
2676 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2677
2b1b7e78
JW		 2678 switch (ctrl->state) {
2679 case NVME_CTRL_LIVE:
2680 case NVME_CTRL_ADMIN_ONLY:
2681 break;
2682 default:
a6a5149b 2683 return -EWOULDBLOCK;
2b1b7e78
JW		 2684 }
2685
a6a5149b 2686 file->private_data = ctrl;
f3ca80fc
CH		 2687 return 0;
2688}
2689
bfd89471
CH		 2690static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2691{
2692 struct nvme_ns *ns;
2693 int ret;
2694
765cc031 2695 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2696 if (list_empty(&ctrl->namespaces)) {
2697 ret = -ENOTTY;
2698 goto out_unlock;
2699 }
2700
2701 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2702 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2703 dev_warn(ctrl->device,
bfd89471
CH		 2704 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2705 ret = -EINVAL;
2706 goto out_unlock;
2707 }
2708
1b3c47c1 2709 dev_warn(ctrl->device,
bfd89471
CH		 2710 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2711 kref_get(&ns->kref);
765cc031 2712 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2713
2714 ret = nvme_user_cmd(ctrl, ns, argp);
2715 nvme_put_ns(ns);
2716 return ret;
2717
2718out_unlock:
765cc031 2719 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2720 return ret;
2721}
2722
f3ca80fc
CH		 2723static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2724 unsigned long arg)
2725{
2726 struct nvme_ctrl *ctrl = file->private_data;
2727 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2728
2729 switch (cmd) {
2730 case NVME_IOCTL_ADMIN_CMD:
2731 return nvme_user_cmd(ctrl, NULL, argp);
2732 case NVME_IOCTL_IO_CMD:
bfd89471 2733 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2734 case NVME_IOCTL_RESET:
1b3c47c1 2735 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2736 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2737 case NVME_IOCTL_SUBSYS_RESET:
2738 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2739 case NVME_IOCTL_RESCAN:
2740 nvme_queue_scan(ctrl);
2741 return 0;
f3ca80fc
CH		 2742 default:
2743 return -ENOTTY;
2744 }
2745}
2746
2747static const struct file_operations nvme_dev_fops = {
2748 .owner = THIS_MODULE,
2749 .open = nvme_dev_open,
f3ca80fc
CH		 2750 .unlocked_ioctl = nvme_dev_ioctl,
2751 .compat_ioctl = nvme_dev_ioctl,
2752};
2753
2754static ssize_t nvme_sysfs_reset(struct device *dev,
2755 struct device_attribute *attr, const char *buf,
2756 size_t count)
2757{
2758 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2759 int ret;
2760
d86c4d8e 2761 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2762 if (ret < 0)
2763 return ret;
2764 return count;
1673f1f0 2765}
f3ca80fc 2766static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2767
9ec3bb2f
KB		 2768static ssize_t nvme_sysfs_rescan(struct device *dev,
2769 struct device_attribute *attr, const char *buf,
2770 size_t count)
2771{
2772 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2773
2774 nvme_queue_scan(ctrl);
2775 return count;
2776}
2777static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2778
5b85b826
CH		 2779static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2780{
2781 struct gendisk *disk = dev_to_disk(dev);
2782
2783 if (disk->fops == &nvme_fops)
2784 return nvme_get_ns_from_dev(dev)->head;
2785 else
2786 return disk->private_data;
2787}
2788
118472ab 2789static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2790 char *buf)
118472ab 2791{
5b85b826
CH		 2792 struct nvme_ns_head *head = dev_to_ns_head(dev);
2793 struct nvme_ns_ids *ids = &head->ids;
2794 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2795 int serial_len = sizeof(subsys->serial);
2796 int model_len = sizeof(subsys->model);
118472ab 2797
002fab04
CH		 2798 if (!uuid_is_null(&ids->uuid))
2799 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2800
002fab04
CH		 2801 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2802 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2803
002fab04
CH		 2804 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2805 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2806
ab9e00cc
CH		 2807 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2808 subsys->serial[serial_len - 1] == '\0'))
118472ab 2809 serial_len--;
ab9e00cc
CH		 2810 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2811 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2812 model_len--;
2813
ab9e00cc
CH		 2814 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2815 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2816 head->ns_id);
118472ab 2817}
c828a892 2818static DEVICE_ATTR_RO(wwid);
118472ab 2819
d934f984 2820static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2821 char *buf)
d934f984 2822{
5b85b826 2823 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2824}
c828a892 2825static DEVICE_ATTR_RO(nguid);
d934f984 2826
2b9b6e86 2827static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2828 char *buf)
2b9b6e86 2829{
5b85b826 2830 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2831
2832 /* For backward compatibility expose the NGUID to userspace if
2833 * we have no UUID set
2834 */
002fab04 2835 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2836 printk_ratelimited(KERN_WARNING
2837 "No UUID available providing old NGUID\n");
002fab04 2838 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2839 }
002fab04 2840 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2841}
c828a892 2842static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2843
2844static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2845 char *buf)
2b9b6e86 2846{
5b85b826 2847 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2848}
c828a892 2849static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2850
2851static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2852 char *buf)
2b9b6e86 2853{
5b85b826 2854 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2855}
c828a892 2856static DEVICE_ATTR_RO(nsid);
2b9b6e86 2857
5b85b826 2858static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2859 &dev_attr_wwid.attr,
2b9b6e86 2860 &dev_attr_uuid.attr,
d934f984 2861 &dev_attr_nguid.attr,
2b9b6e86
KB		 2862 &dev_attr_eui.attr,
2863 &dev_attr_nsid.attr,
0d0b660f
CH		 2864#ifdef CONFIG_NVME_MULTIPATH
2865 &dev_attr_ana_grpid.attr,
2866 &dev_attr_ana_state.attr,
2867#endif
2b9b6e86
KB		 2868 NULL,
2869};
2870
5b85b826 2871static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2872 struct attribute *a, int n)
2873{
2874 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2875 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2876
2877 if (a == &dev_attr_uuid.attr) {
a04b5de5 2878 if (uuid_is_null(&ids->uuid) &&
002fab04 2879 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2880 return 0;
2881 }
2882 if (a == &dev_attr_nguid.attr) {
002fab04 2883 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2884 return 0;
2885 }
2886 if (a == &dev_attr_eui.attr) {
002fab04 2887 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2888 return 0;
2889 }
0d0b660f
CH		 2890#ifdef CONFIG_NVME_MULTIPATH
2891 if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
2892 if (dev_to_disk(dev)->fops != &nvme_fops) /* per-path attr */
2893 return 0;
2894 if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
2895 return 0;
2896 }
2897#endif
2b9b6e86
KB		 2898 return a->mode;
2899}
2900
eb090c4c 2901static const struct attribute_group nvme_ns_id_attr_group = {
5b85b826
CH		 2902 .attrs = nvme_ns_id_attrs,
2903 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2904};
2905
33b14f67
HR		 2906const struct attribute_group *nvme_ns_id_attr_groups[] = {
2907 &nvme_ns_id_attr_group,
2908#ifdef CONFIG_NVM
2909 &nvme_nvm_attr_group,
2910#endif
2911 NULL,
2912};
2913
931e1c22 2914#define nvme_show_str_function(field) \
779ff756
KB		 2915static ssize_t field##_show(struct device *dev, \
2916 struct device_attribute *attr, char *buf) \
2917{ \
2918 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2919 return sprintf(buf, "%.*s\n", \
2920 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2921} \
2922static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2923
ab9e00cc
CH		 2924nvme_show_str_function(model);
2925nvme_show_str_function(serial);
2926nvme_show_str_function(firmware_rev);
2927
931e1c22
ML		 2928#define nvme_show_int_function(field) \
2929static ssize_t field##_show(struct device *dev, \
2930 struct device_attribute *attr, char *buf) \
2931{ \
2932 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2933 return sprintf(buf, "%d\n", ctrl->field); \
2934} \
2935static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2936
931e1c22 2937nvme_show_int_function(cntlid);
103e515e 2938nvme_show_int_function(numa_node);
779ff756 2939
1a353d85
ML		 2940static ssize_t nvme_sysfs_delete(struct device *dev,
2941 struct device_attribute *attr, const char *buf,
2942 size_t count)
2943{
2944 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2945
2946 if (device_remove_file_self(dev, attr))
c5017e85 2947 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2948 return count;
2949}
2950static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2951
2952static ssize_t nvme_sysfs_show_transport(struct device *dev,
2953 struct device_attribute *attr,
2954 char *buf)
2955{
2956 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2957
2958 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2959}
2960static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2961
8432bdb2
SG		 2962static ssize_t nvme_sysfs_show_state(struct device *dev,
2963 struct device_attribute *attr,
2964 char *buf)
2965{
2966 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2967 static const char *const state_name[] = {
2968 [NVME_CTRL_NEW] = "new",
2969 [NVME_CTRL_LIVE] = "live",
2b1b7e78 2970 [NVME_CTRL_ADMIN_ONLY] = "only-admin",
8432bdb2 2971 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 2972 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 2973 [NVME_CTRL_DELETING] = "deleting",
2974 [NVME_CTRL_DEAD] = "dead",
2975 };
2976
2977 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2978 state_name[ctrl->state])
2979 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2980
2981 return sprintf(buf, "unknown state\n");
2982}
2983
2984static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2985
1a353d85
ML		 2986static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2987 struct device_attribute *attr,
2988 char *buf)
2989{
2990 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2991
ab9e00cc 2992 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2993}
2994static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2995
2996static ssize_t nvme_sysfs_show_address(struct device *dev,
2997 struct device_attribute *attr,
2998 char *buf)
2999{
3000 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3001
3002 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
3003}
3004static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
3005
779ff756
KB		 3006static struct attribute *nvme_dev_attrs[] = {
3007 &dev_attr_reset_controller.attr,
9ec3bb2f 3008 &dev_attr_rescan_controller.attr,
779ff756
KB		 3009 &dev_attr_model.attr,
3010 &dev_attr_serial.attr,
3011 &dev_attr_firmware_rev.attr,
931e1c22 3012 &dev_attr_cntlid.attr,
1a353d85
ML		 3013 &dev_attr_delete_controller.attr,
3014 &dev_attr_transport.attr,
3015 &dev_attr_subsysnqn.attr,
3016 &dev_attr_address.attr,
8432bdb2 3017 &dev_attr_state.attr,
103e515e 3018 &dev_attr_numa_node.attr,
779ff756
KB		 3019 NULL
3020};
3021
1a353d85
ML		 3022static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
3023 struct attribute *a, int n)
3024{
3025 struct device *dev = container_of(kobj, struct device, kobj);
3026 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3027
49d3d50b
CH		 3028 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
3029 return 0;
3030 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
3031 return 0;
1a353d85
ML		 3032
3033 return a->mode;
3034}
3035
779ff756 3036static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 3037 .attrs = nvme_dev_attrs,
3038 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 3039};
3040
3041static const struct attribute_group *nvme_dev_attr_groups[] = {
3042 &nvme_dev_attrs_group,
3043 NULL,
3044};
3045
ed754e5d
CH		 3046static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
3047 unsigned nsid)
3048{
3049 struct nvme_ns_head *h;
3050
3051 lockdep_assert_held(&subsys->lock);
3052
3053 list_for_each_entry(h, &subsys->nsheads, entry) {
3054 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
3055 return h;
3056 }
3057
3058 return NULL;
3059}
3060
3061static int __nvme_check_ids(struct nvme_subsystem *subsys,
3062 struct nvme_ns_head *new)
3063{
3064 struct nvme_ns_head *h;
3065
3066 lockdep_assert_held(&subsys->lock);
3067
3068 list_for_each_entry(h, &subsys->nsheads, entry) {
3069 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 3070 !list_empty(&h->list) &&
ed754e5d
CH		 3071 nvme_ns_ids_equal(&new->ids, &h->ids))
3072 return -EINVAL;
3073 }
3074
3075 return 0;
3076}
3077
3078static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
3079 unsigned nsid, struct nvme_id_ns *id)
3080{
3081 struct nvme_ns_head *head;
f3334447 3082 size_t size = sizeof(*head);
ed754e5d
CH		 3083 int ret = -ENOMEM;
3084
f3334447
CH		 3085#ifdef CONFIG_NVME_MULTIPATH
3086 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3087#endif
3088
3089 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3090 if (!head)
3091 goto out;
3092 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3093 if (ret < 0)
3094 goto out_free_head;
3095 head->instance = ret;
3096 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3097 ret = init_srcu_struct(&head->srcu);
3098 if (ret)
3099 goto out_ida_remove;
ed754e5d
CH		 3100 head->subsys = ctrl->subsys;
3101 head->ns_id = nsid;
3102 kref_init(&head->ref);
3103
3104 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
3105
3106 ret = __nvme_check_ids(ctrl->subsys, head);
3107 if (ret) {
3108 dev_err(ctrl->device,
3109 "duplicate IDs for nsid %d\n", nsid);
3110 goto out_cleanup_srcu;
3111 }
3112
32acab31
CH		 3113 ret = nvme_mpath_alloc_disk(ctrl, head);
3114 if (ret)
3115 goto out_cleanup_srcu;
3116
ed754e5d 3117 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3118
3119 kref_get(&ctrl->subsys->ref);
3120
ed754e5d
CH		 3121 return head;
3122out_cleanup_srcu:
3123 cleanup_srcu_struct(&head->srcu);
fd92c77f 3124out_ida_remove:
ed754e5d
CH		 3125 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3126out_free_head:
3127 kfree(head);
3128out:
3129 return ERR_PTR(ret);
3130}
3131
3132static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 3133 struct nvme_id_ns *id)
ed754e5d
CH		 3134{
3135 struct nvme_ctrl *ctrl = ns->ctrl;
3136 bool is_shared = id->nmic & (1 << 0);
3137 struct nvme_ns_head *head = NULL;
3138 int ret = 0;
3139
3140 mutex_lock(&ctrl->subsys->lock);
3141 if (is_shared)
3142 head = __nvme_find_ns_head(ctrl->subsys, nsid);
3143 if (!head) {
3144 head = nvme_alloc_ns_head(ctrl, nsid, id);
3145 if (IS_ERR(head)) {
3146 ret = PTR_ERR(head);
3147 goto out_unlock;
3148 }
ed754e5d
CH		 3149 } else {
3150 struct nvme_ns_ids ids;
3151
3152 nvme_report_ns_ids(ctrl, nsid, id, &ids);
3153 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
3154 dev_err(ctrl->device,
3155 "IDs don't match for shared namespace %d\n",
3156 nsid);
3157 ret = -EINVAL;
3158 goto out_unlock;
3159 }
ed754e5d
CH		 3160 }
3161
3162 list_add_tail(&ns->siblings, &head->list);
3163 ns->head = head;
3164
3165out_unlock:
3166 mutex_unlock(&ctrl->subsys->lock);
3167 return ret;
3168}
3169
5bae7f73
CH		 3170static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
3171{
3172 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
3173 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
3174
ed754e5d 3175 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 3176}
3177
32f0c4af 3178static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3179{
32f0c4af 3180 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3181
765cc031 3182 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3183 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3184 if (ns->head->ns_id == nsid) {
2dd41228
CH		 3185 if (!kref_get_unless_zero(&ns->kref))
3186 continue;
32f0c4af
KB		 3187 ret = ns;
3188 break;
3189 }
ed754e5d 3190 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3191 break;
3192 }
765cc031 3193 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3194 return ret;
5bae7f73
CH		 3195}
3196
f5d11840
JA		 3197static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
3198{
3199 struct streams_directive_params s;
3200 int ret;
3201
3202 if (!ctrl->nr_streams)
3203 return 0;
3204
ed754e5d 3205 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 3206 if (ret)
3207 return ret;
3208
3209 ns->sws = le32_to_cpu(s.sws);
3210 ns->sgs = le16_to_cpu(s.sgs);
3211
3212 if (ns->sws) {
3213 unsigned int bs = 1 << ns->lba_shift;
3214
3215 blk_queue_io_min(ns->queue, bs * ns->sws);
3216 if (ns->sgs)
3217 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
3218 }
3219
3220 return 0;
3221}
3222
ab4ab09c 3223static int nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73
CH		 3224{
3225 struct nvme_ns *ns;
3226 struct gendisk *disk;
ac81bfa9
MB		 3227 struct nvme_id_ns *id;
3228 char disk_name[DISK_NAME_LEN];
ab4ab09c 3229 int node = ctrl->numa_node, flags = GENHD_FL_EXT_DEVT, ret;
5bae7f73
CH		 3230
3231 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3232 if (!ns)
ab4ab09c 3233 return -ENOMEM;
5bae7f73
CH		 3234
3235 ns->queue = blk_mq_init_queue(ctrl->tagset);
ab4ab09c
HR		 3236 if (IS_ERR(ns->queue)) {
3237 ret = PTR_ERR(ns->queue);
ed754e5d 3238 goto out_free_ns;
ab4ab09c 3239 }
e0596ab2 3240
8b904b5b 3241 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
e0596ab2
LG		 3242 if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3243 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3244
5bae7f73
CH		 3245 ns->queue->queuedata = ns;
3246 ns->ctrl = ctrl;
3247
5bae7f73 3248 kref_init(&ns->kref);
5bae7f73 3249 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3250
3251 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3252 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3253
cdbff4f2 3254 id = nvme_identify_ns(ctrl, nsid);
ab4ab09c
HR		 3255 if (!id) {
3256 ret = -EIO;
ac81bfa9 3257 goto out_free_queue;
ab4ab09c 3258 }
ac81bfa9 3259
ab4ab09c
HR		 3260 if (id->ncap == 0) {
3261 ret = -EINVAL;
cdbff4f2 3262 goto out_free_id;
ab4ab09c 3263 }
cdbff4f2 3264
ab4ab09c
HR		 3265 ret = nvme_init_ns_head(ns, nsid, id);
3266 if (ret)
ed754e5d 3267 goto out_free_id;
654b4a4a 3268 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3269 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3270
3dc87dd0 3271 disk = alloc_disk_node(0, node);
ab4ab09c
HR		 3272 if (!disk) {
3273 ret = -ENOMEM;
ed754e5d 3274 goto out_unlink_ns;
ab4ab09c 3275 }
ac81bfa9 3276
3dc87dd0
MB		 3277 disk->fops = &nvme_fops;
3278 disk->private_data = ns;
3279 disk->queue = ns->queue;
32acab31 3280 disk->flags = flags;
3dc87dd0
MB		 3281 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3282 ns->disk = disk;
3283
3284 __nvme_revalidate_disk(disk, id);
5bae7f73 3285
85136c01 3286 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
ab4ab09c
HR		 3287 ret = nvme_nvm_register(ns, disk_name, node);
3288 if (ret) {
85136c01
MB		 3289 dev_warn(ctrl->device, "LightNVM init failure\n");
3290 goto out_put_disk;
3291 }
3292 }
3293
765cc031 3294 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3295 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3296 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3297
d22524a4 3298 nvme_get_ctrl(ctrl);
ac81bfa9 3299
33b14f67 3300 device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
32acab31 3301
0d0b660f 3302 nvme_mpath_add_disk(ns, id);
b9e03857 3303 nvme_fault_inject_init(ns);
0d0b660f
CH		 3304 kfree(id);
3305
ab4ab09c 3306 return 0;
85136c01
MB		 3307 out_put_disk:
3308 put_disk(ns->disk);
ed754e5d
CH		 3309 out_unlink_ns:
3310 mutex_lock(&ctrl->subsys->lock);
3311 list_del_rcu(&ns->siblings);
3312 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3313 nvme_put_ns_head(ns->head);
ac81bfa9
MB		 3314 out_free_id:
3315 kfree(id);
5bae7f73
CH		 3316 out_free_queue:
3317 blk_cleanup_queue(ns->queue);
3318 out_free_ns:
3319 kfree(ns);
ab4ab09c 3320 return ret;
5bae7f73
CH		 3321}
3322
3323static void nvme_ns_remove(struct nvme_ns *ns)
3324{
646017a6
KB		 3325 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3326 return;
69d3b8ac 3327
b9e03857 3328 nvme_fault_inject_fini(ns);
b0b4e09c 3329 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73 3330 del_gendisk(ns->disk);
5bae7f73 3331 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3332 if (blk_get_integrity(ns->disk))
3333 blk_integrity_unregister(ns->disk);
5bae7f73 3334 }
32f0c4af 3335
ed754e5d 3336 mutex_lock(&ns->ctrl->subsys->lock);
9941a862 3337 list_del_rcu(&ns->siblings);
48f78be3 3338 nvme_mpath_clear_current_path(ns);
ed754e5d
CH		 3339 mutex_unlock(&ns->ctrl->subsys->lock);
3340
765cc031 3341 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3342 list_del_init(&ns->list);
765cc031 3343 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3344
9941a862 3345 synchronize_srcu(&ns->head->srcu);
479a322f 3346 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3347 nvme_put_ns(ns);
3348}
3349
540c801c
KB		 3350static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3351{
3352 struct nvme_ns *ns;
3353
32f0c4af 3354 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3355 if (ns) {
b0b4e09c 3356 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3357 nvme_ns_remove(ns);
32f0c4af 3358 nvme_put_ns(ns);
540c801c
KB		 3359 } else
3360 nvme_alloc_ns(ctrl, nsid);
3361}
3362
47b0e50a
SB		 3363static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3364 unsigned nsid)
3365{
3366 struct nvme_ns *ns, *next;
6f8e0d78 3367 LIST_HEAD(rm_list);
47b0e50a 3368
765cc031 3369 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3370 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
cf39a6bc 3371 if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
6f8e0d78 3372 list_move_tail(&ns->list, &rm_list);
47b0e50a 3373 }
765cc031 3374 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3375
3376 list_for_each_entry_safe(ns, next, &rm_list, list)
3377 nvme_ns_remove(ns);
3378
47b0e50a
SB		 3379}
3380
540c801c
KB		 3381static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3382{
3383 struct nvme_ns *ns;
3384 __le32 *ns_list;
3385 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3386 int ret = 0;
3387
42595eb7 3388 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3389 if (!ns_list)
3390 return -ENOMEM;
3391
3392 for (i = 0; i < num_lists; i++) {
3393 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3394 if (ret)
47b0e50a 3395 goto free;
540c801c
KB		 3396
3397 for (j = 0; j < min(nn, 1024U); j++) {
3398 nsid = le32_to_cpu(ns_list[j]);
3399 if (!nsid)
3400 goto out;
3401
3402 nvme_validate_ns(ctrl, nsid);
3403
3404 while (++prev < nsid) {
32f0c4af
KB		 3405 ns = nvme_find_get_ns(ctrl, prev);
3406 if (ns) {
540c801c 3407 nvme_ns_remove(ns);
32f0c4af
KB		 3408 nvme_put_ns(ns);
3409 }
540c801c
KB		 3410 }
3411 }
3412 nn -= j;
3413 }
3414 out:
47b0e50a
SB		 3415 nvme_remove_invalid_namespaces(ctrl, prev);
3416 free:
540c801c
KB		 3417 kfree(ns_list);
3418 return ret;
3419}
3420
5955be21 3421static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3422{
5bae7f73
CH		 3423 unsigned i;
3424
540c801c
KB		 3425 for (i = 1; i <= nn; i++)
3426 nvme_validate_ns(ctrl, i);
3427
47b0e50a 3428 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3429}
3430
f493af37 3431static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3432{
3433 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3434 __le32 *log;
f493af37 3435 int error;
30d90964
CH		 3436
3437 log = kzalloc(log_size, GFP_KERNEL);
3438 if (!log)
f493af37 3439 return;
30d90964 3440
f493af37
CH		 3441 /*
3442 * We need to read the log to clear the AEN, but we don't want to rely
3443 * on it for the changed namespace information as userspace could have
3444 * raced with us in reading the log page, which could cause us to miss
3445 * updates.
3446 */
0e98719b
CH		 3447 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, log,
3448 log_size, 0);
f493af37 3449 if (error)
30d90964
CH		 3450 dev_warn(ctrl->device,
3451 "reading changed ns log failed: %d\n", error);
30d90964 3452
30d90964 3453 kfree(log);
30d90964
CH		 3454}
3455
5955be21 3456static void nvme_scan_work(struct work_struct *work)
5bae7f73 3457{
5955be21
CH		 3458 struct nvme_ctrl *ctrl =
3459 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3460 struct nvme_id_ctrl *id;
540c801c 3461 unsigned nn;
5bae7f73 3462
5955be21
CH		 3463 if (ctrl->state != NVME_CTRL_LIVE)
3464 return;
3465
2b1b7e78
JW		 3466 WARN_ON_ONCE(!ctrl->tagset);
3467
77016199 3468 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 3469 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 3470 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 3471 }
3472
5bae7f73
CH		 3473 if (nvme_identify_ctrl(ctrl, &id))
3474 return;
540c801c 3475
e7ad43c3 3476 mutex_lock(&ctrl->scan_lock);
540c801c 3477 nn = le32_to_cpu(id->nn);
8ef2074d 3478 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3479 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3480 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3481 goto out_free_id;
540c801c 3482 }
5955be21 3483 nvme_scan_ns_sequential(ctrl, nn);
30d90964 3484out_free_id:
e7ad43c3 3485 mutex_unlock(&ctrl->scan_lock);
30d90964 3486 kfree(id);
765cc031 3487 down_write(&ctrl->namespaces_rwsem);
540c801c 3488 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3489 up_write(&ctrl->namespaces_rwsem);
5955be21 3490}
5bae7f73 3491
32f0c4af
KB		 3492/*
3493 * This function iterates the namespace list unlocked to allow recovery from
3494 * controller failure. It is up to the caller to ensure the namespace list is
3495 * not modified by scan work while this function is executing.
3496 */
5bae7f73
CH		 3497void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3498{
3499 struct nvme_ns *ns, *next;
6f8e0d78 3500 LIST_HEAD(ns_list);
5bae7f73 3501
f6c8e432
SG		 3502 /* prevent racing with ns scanning */
3503 flush_work(&ctrl->scan_work);
3504
0ff9d4e1
KB		 3505 /*
3506 * The dead states indicates the controller was not gracefully
3507 * disconnected. In that case, we won't be able to flush any data while
3508 * removing the namespaces' disks; fail all the queues now to avoid
3509 * potentially having to clean up the failed sync later.
3510 */
3511 if (ctrl->state == NVME_CTRL_DEAD)
3512 nvme_kill_queues(ctrl);
3513
765cc031 3514 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3515 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3516 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3517
3518 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3519 nvme_ns_remove(ns);
3520}
576d55d6 3521EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3522
e3d7874d
KB		 3523static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3524{
3525 char *envp[2] = { NULL, NULL };
3526 u32 aen_result = ctrl->aen_result;
3527
3528 ctrl->aen_result = 0;
3529 if (!aen_result)
3530 return;
3531
3532 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3533 if (!envp[0])
3534 return;
3535 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3536 kfree(envp[0]);
3537}
3538
f866fc42
CH		 3539static void nvme_async_event_work(struct work_struct *work)
3540{
3541 struct nvme_ctrl *ctrl =
3542 container_of(work, struct nvme_ctrl, async_event_work);
3543
e3d7874d 3544 nvme_aen_uevent(ctrl);
ad22c355 3545 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3546}
3547
b6dccf7f
AD		 3548static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3549{
3550
3551 u32 csts;
3552
3553 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3554 return false;
3555
3556 if (csts == ~0)
3557 return false;
3558
3559 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3560}
3561
3562static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3563{
b6dccf7f
AD		 3564 struct nvme_fw_slot_info_log *log;
3565
3566 log = kmalloc(sizeof(*log), GFP_KERNEL);
3567 if (!log)
3568 return;
3569
0e98719b
CH		 3570 if (nvme_get_log(ctrl, NVME_NSID_ALL, 0, NVME_LOG_FW_SLOT, log,
3571 sizeof(*log), 0))
3572 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
b6dccf7f
AD		 3573 kfree(log);
3574}
3575
3576static void nvme_fw_act_work(struct work_struct *work)
3577{
3578 struct nvme_ctrl *ctrl = container_of(work,
3579 struct nvme_ctrl, fw_act_work);
3580 unsigned long fw_act_timeout;
3581
3582 if (ctrl->mtfa)
3583 fw_act_timeout = jiffies +
3584 msecs_to_jiffies(ctrl->mtfa * 100);
3585 else
3586 fw_act_timeout = jiffies +
3587 msecs_to_jiffies(admin_timeout * 1000);
3588
3589 nvme_stop_queues(ctrl);
3590 while (nvme_ctrl_pp_status(ctrl)) {
3591 if (time_after(jiffies, fw_act_timeout)) {
3592 dev_warn(ctrl->device,
3593 "Fw activation timeout, reset controller\n");
3594 nvme_reset_ctrl(ctrl);
3595 break;
3596 }
3597 msleep(100);
3598 }
3599
3600 if (ctrl->state != NVME_CTRL_LIVE)
3601 return;
3602
3603 nvme_start_queues(ctrl);
a806c6c8 3604 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3605 nvme_get_fw_slot_info(ctrl);
3606}
3607
868c2392
CH		 3608static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3609{
09bd1ff4
CK		 3610 u32 aer_notice_type = (result & 0xff00) >> 8;
3611
3612 switch (aer_notice_type) {
868c2392 3613 case NVME_AER_NOTICE_NS_CHANGED:
09bd1ff4 3614 trace_nvme_async_event(ctrl, aer_notice_type);
77016199 3615 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3616 nvme_queue_scan(ctrl);
3617 break;
3618 case NVME_AER_NOTICE_FW_ACT_STARTING:
09bd1ff4 3619 trace_nvme_async_event(ctrl, aer_notice_type);
868c2392
CH		 3620 queue_work(nvme_wq, &ctrl->fw_act_work);
3621 break;
0d0b660f
CH		 3622#ifdef CONFIG_NVME_MULTIPATH
3623 case NVME_AER_NOTICE_ANA:
09bd1ff4 3624 trace_nvme_async_event(ctrl, aer_notice_type);
0d0b660f
CH		 3625 if (!ctrl->ana_log_buf)
3626 break;
3627 queue_work(nvme_wq, &ctrl->ana_work);
3628 break;
3629#endif
868c2392
CH		 3630 default:
3631 dev_warn(ctrl->device, "async event result %08x\n", result);
3632 }
3633}
3634
7bf58533 3635void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3636 volatile union nvme_result *res)
f866fc42 3637{
7bf58533 3638 u32 result = le32_to_cpu(res->u32);
09bd1ff4 3639 u32 aer_type = result & 0x07;
f866fc42 3640
ad22c355 3641 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3642 return;
3643
09bd1ff4 3644 switch (aer_type) {
868c2392
CH		 3645 case NVME_AER_NOTICE:
3646 nvme_handle_aen_notice(ctrl, result);
3647 break;
e3d7874d
KB		 3648 case NVME_AER_ERROR:
3649 case NVME_AER_SMART:
3650 case NVME_AER_CSS:
3651 case NVME_AER_VS:
09bd1ff4 3652 trace_nvme_async_event(ctrl, aer_type);
e3d7874d 3653 ctrl->aen_result = result;
7bf58533
CH		 3654 break;
3655 default:
3656 break;
f866fc42 3657 }
c669ccdc 3658 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3659}
f866fc42 3660EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3661
d09f2b45 3662void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3663{
0d0b660f 3664 nvme_mpath_stop(ctrl);
d09f2b45 3665 nvme_stop_keep_alive(ctrl);
f866fc42 3666 flush_work(&ctrl->async_event_work);
b6dccf7f 3667 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 3668}
3669EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3670
3671void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3672{
3673 if (ctrl->kato)
3674 nvme_start_keep_alive(ctrl);
3675
3676 if (ctrl->queue_count > 1) {
3677 nvme_queue_scan(ctrl);
c0561f82 3678 nvme_enable_aen(ctrl);
d99ca609 3679 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3680 nvme_start_queues(ctrl);
3681 }
3682}
3683EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3684
d09f2b45
SG		 3685void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3686{
a6a5149b 3687 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3688}
576d55d6 3689EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3690
d22524a4 3691static void nvme_free_ctrl(struct device *dev)
53029b04 3692{
d22524a4
CH		 3693 struct nvme_ctrl *ctrl =
3694 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3695 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3696
9843f685 3697 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3698 kfree(ctrl->effects);
0d0b660f 3699 nvme_mpath_uninit(ctrl);
092ff052 3700 __free_page(ctrl->discard_page);
f3ca80fc 3701
ab9e00cc
CH		 3702 if (subsys) {
3703 mutex_lock(&subsys->lock);
3704 list_del(&ctrl->subsys_entry);
3705 mutex_unlock(&subsys->lock);
3706 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3707 }
f3ca80fc
CH		 3708
3709 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3710
ab9e00cc
CH		 3711 if (subsys)
3712 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3713}
3714
3715/*
3716 * Initialize a NVMe controller structures. This needs to be called during
3717 * earliest initialization so that we have the initialized structured around
3718 * during probing.
3719 */
3720int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3721 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3722{
3723 int ret;
3724
bb8d261e
CH		 3725 ctrl->state = NVME_CTRL_NEW;
3726 spin_lock_init(&ctrl->lock);
e7ad43c3 3727 mutex_init(&ctrl->scan_lock);
f3ca80fc 3728 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 3729 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 3730 ctrl->dev = dev;
3731 ctrl->ops = ops;
3732 ctrl->quirks = quirks;
5955be21 3733 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3734 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3735 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3736 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3737
230f1f9e
JS		 3738 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
3739 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
3740 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
3741
cb5b7262
JA		 3742 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
3743 PAGE_SIZE);
3744 ctrl->discard_page = alloc_page(GFP_KERNEL);
3745 if (!ctrl->discard_page) {
3746 ret = -ENOMEM;
3747 goto out;
3748 }
3749
9843f685
CH		 3750 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3751 if (ret < 0)
f3ca80fc 3752 goto out;
9843f685 3753 ctrl->instance = ret;
f3ca80fc 3754
d22524a4
CH		 3755 device_initialize(&ctrl->ctrl_device);
3756 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3757 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3758 ctrl->device->class = nvme_class;
3759 ctrl->device->parent = ctrl->dev;
3760 ctrl->device->groups = nvme_dev_attr_groups;
3761 ctrl->device->release = nvme_free_ctrl;
3762 dev_set_drvdata(ctrl->device, ctrl);
3763 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3764 if (ret)
f3ca80fc 3765 goto out_release_instance;
f3ca80fc 3766
a6a5149b
CH		 3767 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3768 ctrl->cdev.owner = ops->module;
3769 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3770 if (ret)
3771 goto out_free_name;
f3ca80fc 3772
c5552fde
AL		 3773 /*
3774 * Initialize latency tolerance controls. The sysfs files won't
3775 * be visible to userspace unless the device actually supports APST.
3776 */
3777 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3778 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3779 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3780
f3ca80fc 3781 return 0;
d22524a4 3782out_free_name:
d6a2b953 3783 kfree_const(ctrl->device->kobj.name);
f3ca80fc 3784out_release_instance:
9843f685 3785 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc 3786out:
cb5b7262
JA		 3787 if (ctrl->discard_page)
3788 __free_page(ctrl->discard_page);
f3ca80fc
CH		 3789 return ret;
3790}
576d55d6 3791EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3792
69d9a99c
KB		 3793/**
3794 * nvme_kill_queues(): Ends all namespace queues
3795 * @ctrl: the dead controller that needs to end
3796 *
3797 * Call this function when the driver determines it is unable to get the
3798 * controller in a state capable of servicing IO.
3799 */
3800void nvme_kill_queues(struct nvme_ctrl *ctrl)
3801{
3802 struct nvme_ns *ns;
3803
765cc031 3804 down_read(&ctrl->namespaces_rwsem);
82654b6b 3805
443bd90f 3806 /* Forcibly unquiesce queues to avoid blocking dispatch */
751a0cc0 3807 if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
7dd1ab16 3808 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3809
cf39a6bc
SB		 3810 list_for_each_entry(ns, &ctrl->namespaces, list)
3811 nvme_set_queue_dying(ns);
806f026f 3812
765cc031 3813 up_read(&ctrl->namespaces_rwsem);
69d9a99c 3814}
237045fc 3815EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3816
302ad8cc
KB		 3817void nvme_unfreeze(struct nvme_ctrl *ctrl)
3818{
3819 struct nvme_ns *ns;
3820
765cc031 3821 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3822 list_for_each_entry(ns, &ctrl->namespaces, list)
3823 blk_mq_unfreeze_queue(ns->queue);
765cc031 3824 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3825}
3826EXPORT_SYMBOL_GPL(nvme_unfreeze);
3827
3828void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3829{
3830 struct nvme_ns *ns;
3831
765cc031 3832 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3833 list_for_each_entry(ns, &ctrl->namespaces, list) {
3834 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3835 if (timeout <= 0)
3836 break;
3837 }
765cc031 3838 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3839}
3840EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3841
3842void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3843{
3844 struct nvme_ns *ns;
3845
765cc031 3846 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3847 list_for_each_entry(ns, &ctrl->namespaces, list)
3848 blk_mq_freeze_queue_wait(ns->queue);
765cc031 3849 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3850}
3851EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3852
3853void nvme_start_freeze(struct nvme_ctrl *ctrl)
3854{
3855 struct nvme_ns *ns;
3856
765cc031 3857 down_read(&ctrl->namespaces_rwsem);
302ad8cc 3858 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3859 blk_freeze_queue_start(ns->queue);
765cc031 3860 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3861}
3862EXPORT_SYMBOL_GPL(nvme_start_freeze);
3863
25646264 3864void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3865{
3866 struct nvme_ns *ns;
3867
765cc031 3868 down_read(&ctrl->namespaces_rwsem);
a6eaa884 3869 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3870 blk_mq_quiesce_queue(ns->queue);
765cc031 3871 up_read(&ctrl->namespaces_rwsem);
363c9aac 3872}
576d55d6 3873EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3874
25646264 3875void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3876{
3877 struct nvme_ns *ns;
3878
765cc031 3879 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 3880 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3881 blk_mq_unquiesce_queue(ns->queue);
765cc031 3882 up_read(&ctrl->namespaces_rwsem);
363c9aac 3883}
576d55d6 3884EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3885
5bae7f73
CH		 3886int __init nvme_core_init(void)
3887{
b227c59b 3888 int result = -ENOMEM;
5bae7f73 3889
9a6327d2
SG		 3890 nvme_wq = alloc_workqueue("nvme-wq",
3891 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3892 if (!nvme_wq)
b227c59b
RS		 3893 goto out;
3894
3895 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
3896 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3897 if (!nvme_reset_wq)
3898 goto destroy_wq;
3899
3900 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
3901 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3902 if (!nvme_delete_wq)
3903 goto destroy_reset_wq;
9a6327d2 3904
a6a5149b 3905 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3906 if (result < 0)
b227c59b 3907 goto destroy_delete_wq;
f3ca80fc
CH		 3908
3909 nvme_class = class_create(THIS_MODULE, "nvme");
3910 if (IS_ERR(nvme_class)) {
3911 result = PTR_ERR(nvme_class);
3912 goto unregister_chrdev;
3913 }
3914
ab9e00cc
CH		 3915 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3916 if (IS_ERR(nvme_subsys_class)) {
3917 result = PTR_ERR(nvme_subsys_class);
3918 goto destroy_class;
3919 }
5bae7f73 3920 return 0;
f3ca80fc 3921
ab9e00cc
CH		 3922destroy_class:
3923 class_destroy(nvme_class);
9a6327d2 3924unregister_chrdev:
a6a5149b 3925 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3926destroy_delete_wq:
3927 destroy_workqueue(nvme_delete_wq);
3928destroy_reset_wq:
3929 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 3930destroy_wq:
3931 destroy_workqueue(nvme_wq);
b227c59b 3932out:
f3ca80fc 3933 return result;
5bae7f73
CH		 3934}
3935
8eb5d89f 3936void __exit nvme_core_exit(void)
5bae7f73 3937{
ab9e00cc
CH		 3938 ida_destroy(&nvme_subsystems_ida);
3939 class_destroy(nvme_subsys_class);
f3ca80fc 3940 class_destroy(nvme_class);
a6a5149b 3941 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3942 destroy_workqueue(nvme_delete_wq);
3943 destroy_workqueue(nvme_reset_wq);
9a6327d2 3944 destroy_workqueue(nvme_wq);
5bae7f73 3945}
576d55d6
ML		 3946
3947MODULE_LICENSE("GPL");
3948MODULE_VERSION("1.0");
3949module_init(nvme_core_init);
3950module_exit(nvme_core_exit);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git