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nvme: don't initlialize ctrl->cntlid twice
[thirdparty/kernel/stable.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711 31
3d030e41
JT		 32#define CREATE_TRACE_POINTS
33#include "trace.h"
34
21d34711 35#include "nvme.h"
038bd4cb 36#include "fabrics.h"
21d34711 37
f3ca80fc
CH		 38#define NVME_MINORS (1U << MINORBITS)
39
8ae4e447
MO		 40unsigned int admin_timeout = 60;
41module_param(admin_timeout, uint, 0644);
ba0ba7d3 42MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 43EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 44
8ae4e447
MO		 45unsigned int nvme_io_timeout = 30;
46module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 48EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 49
b3b1b0b0 50static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 51module_param(shutdown_timeout, byte, 0644);
52MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
53
44e44b29
CH		 54static u8 nvme_max_retries = 5;
55module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 56MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
b227c59b
RS		 71/*
72 * nvme_wq - hosts nvme related works that are not reset or delete
73 * nvme_reset_wq - hosts nvme reset works
74 * nvme_delete_wq - hosts nvme delete works
75 *
76 * nvme_wq will host works such are scan, aen handling, fw activation,
77 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
78 * runs reset works which also flush works hosted on nvme_wq for
79 * serialization purposes. nvme_delete_wq host controller deletion
80 * works which flush reset works for serialization.
81 */
9a6327d2
SG		 82struct workqueue_struct *nvme_wq;
83EXPORT_SYMBOL_GPL(nvme_wq);
84
b227c59b
RS		 85struct workqueue_struct *nvme_reset_wq;
86EXPORT_SYMBOL_GPL(nvme_reset_wq);
87
88struct workqueue_struct *nvme_delete_wq;
89EXPORT_SYMBOL_GPL(nvme_delete_wq);
90
ab9e00cc
CH		 91static DEFINE_IDA(nvme_subsystems_ida);
92static LIST_HEAD(nvme_subsystems);
93static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 94
9843f685 95static DEFINE_IDA(nvme_instance_ida);
a6a5149b 96static dev_t nvme_chr_devt;
f3ca80fc 97static struct class *nvme_class;
ab9e00cc 98static struct class *nvme_subsys_class;
f3ca80fc 99
84fef62d 100static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 101static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 102static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
103 unsigned nsid);
104
105static void nvme_set_queue_dying(struct nvme_ns *ns)
106{
107 /*
108 * Revalidating a dead namespace sets capacity to 0. This will end
109 * buffered writers dirtying pages that can't be synced.
110 */
111 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
112 return;
113 revalidate_disk(ns->disk);
114 blk_set_queue_dying(ns->queue);
115 /* Forcibly unquiesce queues to avoid blocking dispatch */
116 blk_mq_unquiesce_queue(ns->queue);
117}
f3ca80fc 118
50e8d8ee
CH		 119static void nvme_queue_scan(struct nvme_ctrl *ctrl)
120{
121 /*
122 * Only new queue scan work when admin and IO queues are both alive
123 */
124 if (ctrl->state == NVME_CTRL_LIVE)
125 queue_work(nvme_wq, &ctrl->scan_work);
126}
127
d86c4d8e
CH		 128int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
129{
130 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
131 return -EBUSY;
b227c59b 132 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 133 return -EBUSY;
134 return 0;
135}
136EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
137
79c48ccf 138int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 139{
140 int ret;
141
142 ret = nvme_reset_ctrl(ctrl);
8000d1fd 143 if (!ret) {
d86c4d8e 144 flush_work(&ctrl->reset_work);
4e50d9eb
CM		 145 if (ctrl->state != NVME_CTRL_LIVE &&
146 ctrl->state != NVME_CTRL_ADMIN_ONLY)
8000d1fd
NC		 147 ret = -ENETRESET;
148 }
149
d86c4d8e
CH		 150 return ret;
151}
79c48ccf 152EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 153
c5017e85
CH		 154static void nvme_delete_ctrl_work(struct work_struct *work)
155{
156 struct nvme_ctrl *ctrl =
157 container_of(work, struct nvme_ctrl, delete_work);
158
77d0612d
MG		 159 dev_info(ctrl->device,
160 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
161
4054637c 162 flush_work(&ctrl->reset_work);
6cd53d14
CH		 163 nvme_stop_ctrl(ctrl);
164 nvme_remove_namespaces(ctrl);
c5017e85 165 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 166 nvme_uninit_ctrl(ctrl);
167 nvme_put_ctrl(ctrl);
c5017e85
CH		 168}
169
170int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
171{
172 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
173 return -EBUSY;
b227c59b 174 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 175 return -EBUSY;
176 return 0;
177}
178EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
179
180int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
181{
182 int ret = 0;
183
184 /*
185 * Keep a reference until the work is flushed since ->delete_ctrl
186 * can free the controller.
187 */
188 nvme_get_ctrl(ctrl);
189 ret = nvme_delete_ctrl(ctrl);
190 if (!ret)
191 flush_work(&ctrl->delete_work);
192 nvme_put_ctrl(ctrl);
193 return ret;
194}
195EXPORT_SYMBOL_GPL(nvme_delete_ctrl_sync);
196
715ea9e0
CH		 197static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
198{
199 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
200}
201
2a842aca 202static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 203{
204 switch (nvme_req(req)->status & 0x7ff) {
205 case NVME_SC_SUCCESS:
2a842aca 206 return BLK_STS_OK;
27fa9bc5 207 case NVME_SC_CAP_EXCEEDED:
2a842aca 208 return BLK_STS_NOSPC;
e96fef2c
KB		 209 case NVME_SC_LBA_RANGE:
210 return BLK_STS_TARGET;
211 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 212 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 213 case NVME_SC_INVALID_OPCODE:
214 case NVME_SC_INVALID_FIELD:
215 case NVME_SC_INVALID_NS:
2a842aca 216 return BLK_STS_NOTSUPP;
e02ab023
JG		 217 case NVME_SC_WRITE_FAULT:
218 case NVME_SC_READ_ERROR:
219 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 220 case NVME_SC_ACCESS_DENIED:
221 case NVME_SC_READ_ONLY:
e96fef2c 222 case NVME_SC_COMPARE_FAILED:
2a842aca 223 return BLK_STS_MEDIUM;
a751da33
CH		 224 case NVME_SC_GUARD_CHECK:
225 case NVME_SC_APPTAG_CHECK:
226 case NVME_SC_REFTAG_CHECK:
227 case NVME_SC_INVALID_PI:
228 return BLK_STS_PROTECTION;
229 case NVME_SC_RESERVATION_CONFLICT:
230 return BLK_STS_NEXUS;
2a842aca
CH		 231 default:
232 return BLK_STS_IOERR;
27fa9bc5
CH		 233 }
234}
27fa9bc5 235
f6324b1b 236static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 237{
f6324b1b
CH		 238 if (blk_noretry_request(req))
239 return false;
27fa9bc5 240 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 241 return false;
44e44b29 242 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 243 return false;
244 return true;
77f02a7a
CH		 245}
246
49cd84b6
KB		 247static void nvme_retry_req(struct request *req)
248{
249 struct nvme_ns *ns = req->q->queuedata;
250 unsigned long delay = 0;
251 u16 crd;
252
253 /* The mask and shift result must be <= 3 */
254 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
255 if (ns && crd)
256 delay = ns->ctrl->crdt[crd - 1] * 100;
257
258 nvme_req(req)->retries++;
259 blk_mq_requeue_request(req, false);
260 blk_mq_delay_kick_requeue_list(req->q, delay);
261}
262
77f02a7a
CH		 263void nvme_complete_rq(struct request *req)
264{
908e4564
KB		 265 blk_status_t status = nvme_error_status(req);
266
ca5554a6
JT		 267 trace_nvme_complete_rq(req);
268
6e3ca03e
SG		 269 if (nvme_req(req)->ctrl->kas)
270 nvme_req(req)->ctrl->comp_seen = true;
271
908e4564 272 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
8decf5d5
CH		 273 if ((req->cmd_flags & REQ_NVME_MPATH) &&
274 blk_path_error(status)) {
32acab31
CH		 275 nvme_failover_req(req);
276 return;
277 }
278
279 if (!blk_queue_dying(req->q)) {
49cd84b6 280 nvme_retry_req(req);
32acab31
CH		 281 return;
282 }
77f02a7a 283 }
908e4564 284 blk_mq_end_request(req, status);
77f02a7a
CH		 285}
286EXPORT_SYMBOL_GPL(nvme_complete_rq);
287
7baa8572 288bool nvme_cancel_request(struct request *req, void *data, bool reserved)
c55a2fd4 289{
c55a2fd4
ML		 290 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
291 "Cancelling I/O %d", req->tag);
292
e54b064c 293 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 294 blk_mq_complete_request(req);
7baa8572 295 return true;
c55a2fd4
ML		 296}
297EXPORT_SYMBOL_GPL(nvme_cancel_request);
298
bb8d261e
CH		 299bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
300 enum nvme_ctrl_state new_state)
301{
f6b6a28e 302 enum nvme_ctrl_state old_state;
0a72bbba 303 unsigned long flags;
bb8d261e
CH		 304 bool changed = false;
305
0a72bbba 306 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 307
308 old_state = ctrl->state;
bb8d261e 309 switch (new_state) {
2b1b7e78
JW		 310 case NVME_CTRL_ADMIN_ONLY:
311 switch (old_state) {
ad6a0a52 312 case NVME_CTRL_CONNECTING:
2b1b7e78
JW		 313 changed = true;
314 /* FALLTHRU */
315 default:
316 break;
317 }
318 break;
bb8d261e
CH		 319 case NVME_CTRL_LIVE:
320 switch (old_state) {
7d2e8008 321 case NVME_CTRL_NEW:
bb8d261e 322 case NVME_CTRL_RESETTING:
ad6a0a52 323 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 324 changed = true;
325 /* FALLTHRU */
326 default:
327 break;
328 }
329 break;
330 case NVME_CTRL_RESETTING:
331 switch (old_state) {
332 case NVME_CTRL_NEW:
def61eca 333 case NVME_CTRL_LIVE:
2b1b7e78 334 case NVME_CTRL_ADMIN_ONLY:
def61eca
CH		 335 changed = true;
336 /* FALLTHRU */
337 default:
338 break;
339 }
340 break;
ad6a0a52 341 case NVME_CTRL_CONNECTING:
def61eca 342 switch (old_state) {
b754a32c 343 case NVME_CTRL_NEW:
3cec7f9d 344 case NVME_CTRL_RESETTING:
bb8d261e
CH		 345 changed = true;
346 /* FALLTHRU */
347 default:
348 break;
349 }
350 break;
351 case NVME_CTRL_DELETING:
352 switch (old_state) {
353 case NVME_CTRL_LIVE:
2b1b7e78 354 case NVME_CTRL_ADMIN_ONLY:
bb8d261e 355 case NVME_CTRL_RESETTING:
ad6a0a52 356 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 357 changed = true;
358 /* FALLTHRU */
359 default:
360 break;
361 }
362 break;
0ff9d4e1
KB		 363 case NVME_CTRL_DEAD:
364 switch (old_state) {
365 case NVME_CTRL_DELETING:
366 changed = true;
367 /* FALLTHRU */
368 default:
369 break;
370 }
371 break;
bb8d261e
CH		 372 default:
373 break;
374 }
bb8d261e
CH		 375
376 if (changed)
377 ctrl->state = new_state;
378
0a72bbba 379 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 380 if (changed && ctrl->state == NVME_CTRL_LIVE)
381 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 382 return changed;
383}
384EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
385
ed754e5d
CH		 386static void nvme_free_ns_head(struct kref *ref)
387{
388 struct nvme_ns_head *head =
389 container_of(ref, struct nvme_ns_head, ref);
390
32acab31 391 nvme_mpath_remove_disk(head);
ed754e5d
CH		 392 ida_simple_remove(&head->subsys->ns_ida, head->instance);
393 list_del_init(&head->entry);
4317228a 394 cleanup_srcu_struct_quiesced(&head->srcu);
12d9f070 395 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 396 kfree(head);
397}
398
399static void nvme_put_ns_head(struct nvme_ns_head *head)
400{
401 kref_put(&head->ref, nvme_free_ns_head);
402}
403
1673f1f0
CH		 404static void nvme_free_ns(struct kref *kref)
405{
406 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
407
b0b4e09c
MB		 408 if (ns->ndev)
409 nvme_nvm_unregister(ns);
1673f1f0 410
1673f1f0 411 put_disk(ns->disk);
ed754e5d 412 nvme_put_ns_head(ns->head);
075790eb 413 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 414 kfree(ns);
415}
416
5bae7f73 417static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 418{
419 kref_put(&ns->kref, nvme_free_ns);
420}
421
bb06ec31
JS		 422static inline void nvme_clear_nvme_request(struct request *req)
423{
424 if (!(req->rq_flags & RQF_DONTPREP)) {
425 nvme_req(req)->retries = 0;
426 nvme_req(req)->flags = 0;
427 req->rq_flags |= RQF_DONTPREP;
428 }
429}
430
4160982e 431struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 432 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 433{
aebf526b 434 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 435 struct request *req;
21d34711 436
eb71f435 437 if (qid == NVME_QID_ANY) {
aebf526b 438 req = blk_mq_alloc_request(q, op, flags);
eb71f435 439 } else {
aebf526b 440 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 441 qid ? qid - 1 : 0);
442 }
21d34711 443 if (IS_ERR(req))
4160982e 444 return req;
21d34711 445
21d34711 446 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 447 nvme_clear_nvme_request(req);
d49187e9 448 nvme_req(req)->cmd = cmd;
21d34711 449
4160982e
CH		 450 return req;
451}
576d55d6 452EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 453
f5d11840
JA		 454static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
455{
456 struct nvme_command c;
457
458 memset(&c, 0, sizeof(c));
459
460 c.directive.opcode = nvme_admin_directive_send;
62346eae 461 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 462 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
463 c.directive.dtype = NVME_DIR_IDENTIFY;
464 c.directive.tdtype = NVME_DIR_STREAMS;
465 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
466
467 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
468}
469
470static int nvme_disable_streams(struct nvme_ctrl *ctrl)
471{
472 return nvme_toggle_streams(ctrl, false);
473}
474
475static int nvme_enable_streams(struct nvme_ctrl *ctrl)
476{
477 return nvme_toggle_streams(ctrl, true);
478}
479
480static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
481 struct streams_directive_params *s, u32 nsid)
482{
483 struct nvme_command c;
484
485 memset(&c, 0, sizeof(c));
486 memset(s, 0, sizeof(*s));
487
488 c.directive.opcode = nvme_admin_directive_recv;
489 c.directive.nsid = cpu_to_le32(nsid);
a082b426 490 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 491 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
492 c.directive.dtype = NVME_DIR_STREAMS;
493
494 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
495}
496
497static int nvme_configure_directives(struct nvme_ctrl *ctrl)
498{
499 struct streams_directive_params s;
500 int ret;
501
502 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
503 return 0;
504 if (!streams)
505 return 0;
506
507 ret = nvme_enable_streams(ctrl);
508 if (ret)
509 return ret;
510
62346eae 511 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 512 if (ret)
513 return ret;
514
515 ctrl->nssa = le16_to_cpu(s.nssa);
516 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
517 dev_info(ctrl->device, "too few streams (%u) available\n",
518 ctrl->nssa);
519 nvme_disable_streams(ctrl);
520 return 0;
521 }
522
523 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
524 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
525 return 0;
526}
527
528/*
529 * Check if 'req' has a write hint associated with it. If it does, assign
530 * a valid namespace stream to the write.
531 */
532static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
533 struct request *req, u16 *control,
534 u32 *dsmgmt)
535{
536 enum rw_hint streamid = req->write_hint;
537
538 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
539 streamid = 0;
540 else {
541 streamid--;
542 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
543 return;
544
545 *control |= NVME_RW_DTYPE_STREAMS;
546 *dsmgmt |= streamid << 16;
547 }
548
549 if (streamid < ARRAY_SIZE(req->q->write_hints))
550 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
551}
552
8093f7ca
ML		 553static inline void nvme_setup_flush(struct nvme_ns *ns,
554 struct nvme_command *cmnd)
555{
8093f7ca 556 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 557 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 558}
559
fc17b653 560static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 561 struct nvme_command *cmnd)
562{
b35ba01e 563 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 564 struct nvme_dsm_range *range;
b35ba01e 565 struct bio *bio;
8093f7ca 566
cb5b7262
JA		 567 range = kmalloc_array(segments, sizeof(*range),
568 GFP_ATOMIC | __GFP_NOWARN);
569 if (!range) {
570 /*
571 * If we fail allocation our range, fallback to the controller
572 * discard page. If that's also busy, it's safe to return
573 * busy, as we know we can make progress once that's freed.
574 */
575 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
576 return BLK_STS_RESOURCE;
577
578 range = page_address(ns->ctrl->discard_page);
579 }
8093f7ca 580
b35ba01e
CH		 581 __rq_for_each_bio(bio, req) {
582 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
583 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
584
8cb6af7b
KB		 585 if (n < segments) {
586 range[n].cattr = cpu_to_le32(0);
587 range[n].nlb = cpu_to_le32(nlb);
588 range[n].slba = cpu_to_le64(slba);
589 }
b35ba01e
CH		 590 n++;
591 }
592
593 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 594 if (virt_to_page(range) == ns->ctrl->discard_page)
595 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
596 else
597 kfree(range);
fc17b653 598 return BLK_STS_IOERR;
b35ba01e 599 }
8093f7ca 600
8093f7ca 601 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 602 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 603 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 604 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
605
f9d03f96
CH		 606 req->special_vec.bv_page = virt_to_page(range);
607 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 608 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 609 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 610
fc17b653 611 return BLK_STS_OK;
8093f7ca 612}
8093f7ca 613
ebe6d874
CH		 614static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
615 struct request *req, struct nvme_command *cmnd)
8093f7ca 616{
f5d11840 617 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 618 u16 control = 0;
619 u32 dsmgmt = 0;
620
621 if (req->cmd_flags & REQ_FUA)
622 control |= NVME_RW_FUA;
623 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
624 control |= NVME_RW_LR;
625
626 if (req->cmd_flags & REQ_RAHEAD)
627 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
628
8093f7ca 629 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 630 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 631 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
632 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
633
f5d11840
JA		 634 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
635 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
636
8093f7ca 637 if (ns->ms) {
715ea9e0
CH		 638 /*
639 * If formated with metadata, the block layer always provides a
640 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
641 * we enable the PRACT bit for protection information or set the
642 * namespace capacity to zero to prevent any I/O.
643 */
644 if (!blk_integrity_rq(req)) {
645 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
646 return BLK_STS_NOTSUPP;
647 control |= NVME_RW_PRINFO_PRACT;
f7f1fc36
MG		 648 } else if (req_op(req) == REQ_OP_WRITE) {
649 t10_pi_prepare(req, ns->pi_type);
715ea9e0
CH		 650 }
651
8093f7ca
ML		 652 switch (ns->pi_type) {
653 case NVME_NS_DPS_PI_TYPE3:
654 control |= NVME_RW_PRINFO_PRCHK_GUARD;
655 break;
656 case NVME_NS_DPS_PI_TYPE1:
657 case NVME_NS_DPS_PI_TYPE2:
658 control |= NVME_RW_PRINFO_PRCHK_GUARD |
659 NVME_RW_PRINFO_PRCHK_REF;
ddd0bc75 660 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML		 661 break;
662 }
8093f7ca
ML		 663 }
664
665 cmnd->rw.control = cpu_to_le16(control);
666 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 667 return 0;
8093f7ca
ML		 668}
669
f7f1fc36
MG		 670void nvme_cleanup_cmd(struct request *req)
671{
672 if (blk_integrity_rq(req) && req_op(req) == REQ_OP_READ &&
673 nvme_req(req)->status == 0) {
674 struct nvme_ns *ns = req->rq_disk->private_data;
675
676 t10_pi_complete(req, ns->pi_type,
677 blk_rq_bytes(req) >> ns->lba_shift);
678 }
679 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
cb5b7262
JA		 680 struct nvme_ns *ns = req->rq_disk->private_data;
681 struct page *page = req->special_vec.bv_page;
682
683 if (page == ns->ctrl->discard_page)
684 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
685 else
686 kfree(page_address(page) + req->special_vec.bv_offset);
f7f1fc36
MG		 687 }
688}
689EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
690
fc17b653 691blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 692 struct nvme_command *cmd)
693{
fc17b653 694 blk_status_t ret = BLK_STS_OK;
8093f7ca 695
bb06ec31 696 nvme_clear_nvme_request(req);
987f699a 697
11902035 698 memset(cmd, 0, sizeof(*cmd));
aebf526b
CH		 699 switch (req_op(req)) {
700 case REQ_OP_DRV_IN:
701 case REQ_OP_DRV_OUT:
d49187e9 702 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 703 break;
704 case REQ_OP_FLUSH:
8093f7ca 705 nvme_setup_flush(ns, cmd);
aebf526b 706 break;
e850fd16
CH		 707 case REQ_OP_WRITE_ZEROES:
708 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 709 case REQ_OP_DISCARD:
8093f7ca 710 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 711 break;
712 case REQ_OP_READ:
713 case REQ_OP_WRITE:
ebe6d874 714 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 715 break;
716 default:
717 WARN_ON_ONCE(1);
fc17b653 718 return BLK_STS_IOERR;
aebf526b 719 }
8093f7ca 720
721b3917 721 cmd->common.command_id = req->tag;
5d87eb94 722 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 723 return ret;
724}
725EXPORT_SYMBOL_GPL(nvme_setup_cmd);
726
6287b51c
SG		 727static void nvme_end_sync_rq(struct request *rq, blk_status_t error)
728{
729 struct completion *waiting = rq->end_io_data;
730
731 rq->end_io_data = NULL;
732 complete(waiting);
733}
734
735static void nvme_execute_rq_polled(struct request_queue *q,
736 struct gendisk *bd_disk, struct request *rq, int at_head)
737{
738 DECLARE_COMPLETION_ONSTACK(wait);
739
740 WARN_ON_ONCE(!test_bit(QUEUE_FLAG_POLL, &q->queue_flags));
741
742 rq->cmd_flags |= REQ_HIPRI;
743 rq->end_io_data = &wait;
744 blk_execute_rq_nowait(q, bd_disk, rq, at_head, nvme_end_sync_rq);
745
746 while (!completion_done(&wait)) {
747 blk_poll(q, request_to_qc_t(rq->mq_hctx, rq), true);
748 cond_resched();
749 }
750}
751
4160982e
CH		 752/*
753 * Returns 0 on success. If the result is negative, it's a Linux error code;
754 * if the result is positive, it's an NVM Express status code
755 */
756int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 757 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 758 unsigned timeout, int qid, int at_head,
6287b51c 759 blk_mq_req_flags_t flags, bool poll)
4160982e
CH		 760{
761 struct request *req;
762 int ret;
763
eb71f435 764 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 765 if (IS_ERR(req))
766 return PTR_ERR(req);
767
768 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
769
21d34711
CH		 770 if (buffer && bufflen) {
771 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
772 if (ret)
773 goto out;
4160982e
CH		 774 }
775
6287b51c
SG		 776 if (poll)
777 nvme_execute_rq_polled(req->q, NULL, req, at_head);
778 else
779 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 780 if (result)
781 *result = nvme_req(req)->result;
27fa9bc5
CH		 782 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
783 ret = -EINTR;
784 else
785 ret = nvme_req(req)->status;
4160982e
CH		 786 out:
787 blk_mq_free_request(req);
788 return ret;
789}
eb71f435 790EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 791
792int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
793 void *buffer, unsigned bufflen)
794{
eb71f435 795 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
6287b51c 796 NVME_QID_ANY, 0, 0, false);
4160982e 797}
576d55d6 798EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 799
1cad6562
CH		 800static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
801 unsigned len, u32 seed, bool write)
802{
803 struct bio_integrity_payload *bip;
804 int ret = -ENOMEM;
805 void *buf;
806
807 buf = kmalloc(len, GFP_KERNEL);
808 if (!buf)
809 goto out;
810
811 ret = -EFAULT;
812 if (write && copy_from_user(buf, ubuf, len))
813 goto out_free_meta;
814
815 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
816 if (IS_ERR(bip)) {
817 ret = PTR_ERR(bip);
818 goto out_free_meta;
819 }
820
821 bip->bip_iter.bi_size = len;
822 bip->bip_iter.bi_sector = seed;
823 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
824 offset_in_page(buf));
825 if (ret == len)
826 return buf;
827 ret = -ENOMEM;
828out_free_meta:
829 kfree(buf);
830out:
831 return ERR_PTR(ret);
832}
833
63263d60 834static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 835 struct nvme_command *cmd, void __user *ubuffer,
836 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
837 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 838{
7a5abb4b 839 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 840 struct nvme_ns *ns = q->queuedata;
841 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 842 struct request *req;
0b7f1f26
KB		 843 struct bio *bio = NULL;
844 void *meta = NULL;
4160982e
CH		 845 int ret;
846
eb71f435 847 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 848 if (IS_ERR(req))
849 return PTR_ERR(req);
850
851 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 852 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 853
854 if (ubuffer && bufflen) {
21d34711
CH		 855 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
856 GFP_KERNEL);
857 if (ret)
858 goto out;
859 bio = req->bio;
74d46992 860 bio->bi_disk = disk;
1cad6562
CH		 861 if (disk && meta_buffer && meta_len) {
862 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
863 meta_seed, write);
864 if (IS_ERR(meta)) {
865 ret = PTR_ERR(meta);
0b7f1f26
KB		 866 goto out_unmap;
867 }
f31a2110 868 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 869 }
870 }
1cad6562 871
0b7f1f26 872 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 873 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
874 ret = -EINTR;
875 else
876 ret = nvme_req(req)->status;
21d34711 877 if (result)
d49187e9 878 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 879 if (meta && !ret && !write) {
880 if (copy_to_user(meta_buffer, meta, meta_len))
881 ret = -EFAULT;
882 }
0b7f1f26
KB		 883 kfree(meta);
884 out_unmap:
74d46992 885 if (bio)
0b7f1f26 886 blk_rq_unmap_user(bio);
21d34711
CH		 887 out:
888 blk_mq_free_request(req);
889 return ret;
890}
891
2a842aca 892static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 893{
894 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 895 unsigned long flags;
896 bool startka = false;
038bd4cb
SG		 897
898 blk_mq_free_request(rq);
899
2a842aca 900 if (status) {
038bd4cb 901 dev_err(ctrl->device,
2a842aca
CH		 902 "failed nvme_keep_alive_end_io error=%d\n",
903 status);
038bd4cb
SG		 904 return;
905 }
906
6e3ca03e 907 ctrl->comp_seen = false;
86880d64
JS		 908 spin_lock_irqsave(&ctrl->lock, flags);
909 if (ctrl->state == NVME_CTRL_LIVE ||
910 ctrl->state == NVME_CTRL_CONNECTING)
911 startka = true;
912 spin_unlock_irqrestore(&ctrl->lock, flags);
913 if (startka)
914 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
038bd4cb
SG		 915}
916
917static int nvme_keep_alive(struct nvme_ctrl *ctrl)
918{
038bd4cb
SG		 919 struct request *rq;
920
0a34e466 921 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 922 NVME_QID_ANY);
923 if (IS_ERR(rq))
924 return PTR_ERR(rq);
925
926 rq->timeout = ctrl->kato * HZ;
927 rq->end_io_data = ctrl;
928
929 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
930
931 return 0;
932}
933
934static void nvme_keep_alive_work(struct work_struct *work)
935{
936 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
937 struct nvme_ctrl, ka_work);
6e3ca03e
SG		 938 bool comp_seen = ctrl->comp_seen;
939
940 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
941 dev_dbg(ctrl->device,
942 "reschedule traffic based keep-alive timer\n");
943 ctrl->comp_seen = false;
944 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
945 return;
946 }
038bd4cb
SG		 947
948 if (nvme_keep_alive(ctrl)) {
949 /* allocation failure, reset the controller */
950 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 951 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 952 return;
953 }
954}
955
00b683db 956static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 957{
958 if (unlikely(ctrl->kato == 0))
959 return;
960
038bd4cb
SG		 961 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
962}
038bd4cb
SG		 963
964void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
965{
966 if (unlikely(ctrl->kato == 0))
967 return;
968
969 cancel_delayed_work_sync(&ctrl->ka_work);
970}
971EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
972
3f7f25a9 973static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 974{
975 struct nvme_command c = { };
976 int error;
977
978 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
979 c.identify.opcode = nvme_admin_identify;
986994a2 980 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 981
982 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
983 if (!*id)
984 return -ENOMEM;
985
986 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
987 sizeof(struct nvme_id_ctrl));
988 if (error)
989 kfree(*id);
990 return error;
991}
992
cdbff4f2 993static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 994 struct nvme_ns_ids *ids)
3b22ba26
JT		 995{
996 struct nvme_command c = { };
997 int status;
998 void *data;
999 int pos;
1000 int len;
1001
1002 c.identify.opcode = nvme_admin_identify;
1003 c.identify.nsid = cpu_to_le32(nsid);
1004 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1005
1006 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1007 if (!data)
1008 return -ENOMEM;
1009
cdbff4f2 1010 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 1011 NVME_IDENTIFY_DATA_SIZE);
1012 if (status)
1013 goto free_data;
1014
1015 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1016 struct nvme_ns_id_desc *cur = data + pos;
1017
1018 if (cur->nidl == 0)
1019 break;
1020
1021 switch (cur->nidt) {
1022 case NVME_NIDT_EUI64:
1023 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 1024 dev_warn(ctrl->device,
3b22ba26
JT		 1025 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
1026 cur->nidl);
1027 goto free_data;
1028 }
1029 len = NVME_NIDT_EUI64_LEN;
002fab04 1030 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1031 break;
1032 case NVME_NIDT_NGUID:
1033 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 1034 dev_warn(ctrl->device,
3b22ba26
JT		 1035 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
1036 cur->nidl);
1037 goto free_data;
1038 }
1039 len = NVME_NIDT_NGUID_LEN;
002fab04 1040 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1041 break;
1042 case NVME_NIDT_UUID:
1043 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 1044 dev_warn(ctrl->device,
3b22ba26
JT		 1045 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
1046 cur->nidl);
1047 goto free_data;
1048 }
1049 len = NVME_NIDT_UUID_LEN;
002fab04 1050 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 1051 break;
1052 default:
53b3a661 1053 /* Skip unknown types */
3b22ba26
JT		 1054 len = cur->nidl;
1055 break;
1056 }
1057
1058 len += sizeof(*cur);
1059 }
1060free_data:
1061 kfree(data);
1062 return status;
1063}
1064
540c801c
KB		 1065static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
1066{
1067 struct nvme_command c = { };
1068
1069 c.identify.opcode = nvme_admin_identify;
986994a2 1070 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 1071 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 1072 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
1073 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 1074}
1075
cdbff4f2
CH		 1076static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
1077 unsigned nsid)
21d34711 1078{
cdbff4f2 1079 struct nvme_id_ns *id;
21d34711
CH		 1080 struct nvme_command c = { };
1081 int error;
1082
1083 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1084 c.identify.opcode = nvme_admin_identify;
1085 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1086 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1087
cdbff4f2
CH		 1088 id = kmalloc(sizeof(*id), GFP_KERNEL);
1089 if (!id)
1090 return NULL;
21d34711 1091
cdbff4f2
CH		 1092 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1093 if (error) {
1094 dev_warn(ctrl->device, "Identify namespace failed\n");
1095 kfree(id);
1096 return NULL;
1097 }
1098
1099 return id;
21d34711
CH		 1100}
1101
3f7f25a9 1102static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 1103 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 1104{
1105 struct nvme_command c;
d49187e9 1106 union nvme_result res;
1cb3cce5 1107 int ret;
21d34711
CH		 1108
1109 memset(&c, 0, sizeof(c));
1110 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 1111 c.features.fid = cpu_to_le32(fid);
1112 c.features.dword11 = cpu_to_le32(dword11);
1113
d49187e9 1114 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
6287b51c 1115 buffer, buflen, 0, NVME_QID_ANY, 0, 0, false);
9b47f77a 1116 if (ret >= 0 && result)
d49187e9 1117 *result = le32_to_cpu(res.u32);
1cb3cce5 1118 return ret;
21d34711
CH		 1119}
1120
9a0be7ab
CH		 1121int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1122{
1123 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1124 u32 result;
1125 int status, nr_io_queues;
1126
1a6fe74d 1127 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1128 &result);
f5fa90dc 1129 if (status < 0)
9a0be7ab
CH		 1130 return status;
1131
f5fa90dc
CH		 1132 /*
1133 * Degraded controllers might return an error when setting the queue
1134 * count. We still want to be able to bring them online and offer
1135 * access to the admin queue, as that might be only way to fix them up.
1136 */
1137 if (status > 0) {
f0425db0 1138 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1139 *count = 0;
1140 } else {
1141 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1142 *count = min(*count, nr_io_queues);
1143 }
1144
9a0be7ab
CH		 1145 return 0;
1146}
576d55d6 1147EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1148
c0561f82 1149#define NVME_AEN_SUPPORTED \
0d0b660f 1150 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | NVME_AEN_CFG_ANA_CHANGE)
c0561f82
HR		 1151
1152static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1153{
fa441b71 1154 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1155 int status;
1156
fa441b71
WZ		 1157 if (!supported_aens)
1158 return;
1159
1160 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1161 NULL, 0, &result);
c0561f82
HR		 1162 if (status)
1163 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1164 supported_aens);
c0561f82
HR		 1165}
1166
1673f1f0
CH		 1167static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1168{
1169 struct nvme_user_io io;
1170 struct nvme_command c;
1171 unsigned length, meta_len;
1172 void __user *metadata;
1173
1174 if (copy_from_user(&io, uio, sizeof(io)))
1175 return -EFAULT;
63088ec7
KB		 1176 if (io.flags)
1177 return -EINVAL;
1673f1f0
CH		 1178
1179 switch (io.opcode) {
1180 case nvme_cmd_write:
1181 case nvme_cmd_read:
1182 case nvme_cmd_compare:
1183 break;
1184 default:
1185 return -EINVAL;
1186 }
1187
1188 length = (io.nblocks + 1) << ns->lba_shift;
1189 meta_len = (io.nblocks + 1) * ns->ms;
1190 metadata = (void __user *)(uintptr_t)io.metadata;
1191
1192 if (ns->ext) {
1193 length += meta_len;
1194 meta_len = 0;
1195 } else if (meta_len) {
1196 if ((io.metadata & 3) || !io.metadata)
1197 return -EINVAL;
1198 }
1199
1200 memset(&c, 0, sizeof(c));
1201 c.rw.opcode = io.opcode;
1202 c.rw.flags = io.flags;
ed754e5d 1203 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1204 c.rw.slba = cpu_to_le64(io.slba);
1205 c.rw.length = cpu_to_le16(io.nblocks);
1206 c.rw.control = cpu_to_le16(io.control);
1207 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1208 c.rw.reftag = cpu_to_le32(io.reftag);
1209 c.rw.apptag = cpu_to_le16(io.apptag);
1210 c.rw.appmask = cpu_to_le16(io.appmask);
1211
63263d60 1212 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0 1213 (void __user *)(uintptr_t)io.addr, length,
202359c0 1214 metadata, meta_len, lower_32_bits(io.slba), NULL, 0);
1673f1f0
CH		 1215}
1216
84fef62d
KB		 1217static u32 nvme_known_admin_effects(u8 opcode)
1218{
1219 switch (opcode) {
1220 case nvme_admin_format_nvm:
1221 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1222 NVME_CMD_EFFECTS_CSE_MASK;
1223 case nvme_admin_sanitize_nvm:
1224 return NVME_CMD_EFFECTS_CSE_MASK;
1225 default:
1226 break;
1227 }
1228 return 0;
1229}
1230
1231static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1232 u8 opcode)
1233{
1234 u32 effects = 0;
1235
1236 if (ns) {
1237 if (ctrl->effects)
1238 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1239 if (effects & ~NVME_CMD_EFFECTS_CSUPP)
1240 dev_warn(ctrl->device,
1241 "IO command:%02x has unhandled effects:%08x\n",
1242 opcode, effects);
1243 return 0;
1244 }
1245
1246 if (ctrl->effects)
62843c2e 1247 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1248 else
1249 effects = nvme_known_admin_effects(opcode);
1250
1251 /*
1252 * For simplicity, IO to all namespaces is quiesced even if the command
1253 * effects say only one namespace is affected.
1254 */
1255 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
1256 nvme_start_freeze(ctrl);
1257 nvme_wait_freeze(ctrl);
1258 }
1259 return effects;
1260}
1261
1262static void nvme_update_formats(struct nvme_ctrl *ctrl)
1263{
cf39a6bc 1264 struct nvme_ns *ns;
84fef62d 1265
cf39a6bc
SB		 1266 down_read(&ctrl->namespaces_rwsem);
1267 list_for_each_entry(ns, &ctrl->namespaces, list)
1268 if (ns->disk && nvme_revalidate_disk(ns->disk))
1269 nvme_set_queue_dying(ns);
1270 up_read(&ctrl->namespaces_rwsem);
3fd176b7 1271
cf39a6bc 1272 nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
84fef62d
KB		 1273}
1274
1275static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1276{
1277 /*
1278 * Revalidate LBA changes prior to unfreezing. This is necessary to
1279 * prevent memory corruption if a logical block size was changed by
1280 * this command.
1281 */
1282 if (effects & NVME_CMD_EFFECTS_LBCC)
1283 nvme_update_formats(ctrl);
1284 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK))
1285 nvme_unfreeze(ctrl);
1286 if (effects & NVME_CMD_EFFECTS_CCC)
1287 nvme_init_identify(ctrl);
1288 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1289 nvme_queue_scan(ctrl);
1290}
1291
f3ca80fc 1292static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1293 struct nvme_passthru_cmd __user *ucmd)
1294{
1295 struct nvme_passthru_cmd cmd;
1296 struct nvme_command c;
1297 unsigned timeout = 0;
84fef62d 1298 u32 effects;
1673f1f0
CH		 1299 int status;
1300
1301 if (!capable(CAP_SYS_ADMIN))
1302 return -EACCES;
1303 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1304 return -EFAULT;
63088ec7
KB		 1305 if (cmd.flags)
1306 return -EINVAL;
1673f1f0
CH		 1307
1308 memset(&c, 0, sizeof(c));
1309 c.common.opcode = cmd.opcode;
1310 c.common.flags = cmd.flags;
1311 c.common.nsid = cpu_to_le32(cmd.nsid);
1312 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1313 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
b7c8f366
CK		 1314 c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1315 c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1316 c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1317 c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1318 c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1319 c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1673f1f0
CH		 1320
1321 if (cmd.timeout_ms)
1322 timeout = msecs_to_jiffies(cmd.timeout_ms);
1323
84fef62d 1324 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1325 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1326 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
9b382768 1327 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata_len,
63263d60 1328 0, &cmd.result, timeout);
84fef62d
KB		 1329 nvme_passthru_end(ctrl, effects);
1330
1673f1f0
CH		 1331 if (status >= 0) {
1332 if (put_user(cmd.result, &ucmd->result))
1333 return -EFAULT;
1334 }
1335
1336 return status;
1337}
1338
32acab31
CH		 1339/*
1340 * Issue ioctl requests on the first available path. Note that unlike normal
1341 * block layer requests we will not retry failed request on another controller.
1342 */
1343static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1344 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1345{
32acab31
CH		 1346#ifdef CONFIG_NVME_MULTIPATH
1347 if (disk->fops == &nvme_ns_head_ops) {
1348 *head = disk->private_data;
1349 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1350 return nvme_find_path(*head);
1351 }
1352#endif
1353 *head = NULL;
1354 *srcu_idx = -1;
1355 return disk->private_data;
1356}
1673f1f0 1357
32acab31
CH		 1358static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1359{
1360 if (head)
1361 srcu_read_unlock(&head->srcu, idx);
1362}
1673f1f0 1363
32acab31
CH		 1364static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1365{
1673f1f0
CH		 1366 switch (cmd) {
1367 case NVME_IOCTL_ID:
1368 force_successful_syscall_return();
ed754e5d 1369 return ns->head->ns_id;
1673f1f0
CH		 1370 case NVME_IOCTL_ADMIN_CMD:
1371 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1372 case NVME_IOCTL_IO_CMD:
1373 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1374 case NVME_IOCTL_SUBMIT_IO:
1375 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1376 default:
84d4add7
MB		 1377#ifdef CONFIG_NVM
1378 if (ns->ndev)
1379 return nvme_nvm_ioctl(ns, cmd, arg);
1380#endif
a98e58e5 1381 if (is_sed_ioctl(cmd))
4f1244c8 1382 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1383 (void __user *) arg);
1673f1f0
CH		 1384 return -ENOTTY;
1385 }
1386}
1387
32acab31
CH		 1388static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1389 unsigned int cmd, unsigned long arg)
1673f1f0 1390{
32acab31
CH		 1391 struct nvme_ns_head *head = NULL;
1392 struct nvme_ns *ns;
1393 int srcu_idx, ret;
1394
1395 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1396 if (unlikely(!ns))
1397 ret = -EWOULDBLOCK;
1398 else
1399 ret = nvme_ns_ioctl(ns, cmd, arg);
1400 nvme_put_ns_from_disk(head, srcu_idx);
1401 return ret;
1673f1f0 1402}
1673f1f0
CH		 1403
1404static int nvme_open(struct block_device *bdev, fmode_t mode)
1405{
c6424a90
CH		 1406 struct nvme_ns *ns = bdev->bd_disk->private_data;
1407
32acab31
CH		 1408#ifdef CONFIG_NVME_MULTIPATH
1409 /* should never be called due to GENHD_FL_HIDDEN */
1410 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1411 goto fail;
32acab31 1412#endif
c6424a90 1413 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1414 goto fail;
1415 if (!try_module_get(ns->ctrl->ops->module))
1416 goto fail_put_ns;
1417
c6424a90 1418 return 0;
85088c4a
NC		 1419
1420fail_put_ns:
1421 nvme_put_ns(ns);
1422fail:
1423 return -ENXIO;
1673f1f0
CH		 1424}
1425
1426static void nvme_release(struct gendisk *disk, fmode_t mode)
1427{
85088c4a
NC		 1428 struct nvme_ns *ns = disk->private_data;
1429
1430 module_put(ns->ctrl->ops->module);
1431 nvme_put_ns(ns);
1673f1f0
CH		 1432}
1433
1434static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1435{
1436 /* some standard values */
1437 geo->heads = 1 << 6;
1438 geo->sectors = 1 << 5;
1439 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1440 return 0;
1441}
1442
1443#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1444static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1445{
1446 struct blk_integrity integrity;
1447
fa9a89fc 1448 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1449 switch (pi_type) {
1673f1f0
CH		 1450 case NVME_NS_DPS_PI_TYPE3:
1451 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1452 integrity.tag_size = sizeof(u16) + sizeof(u32);
1453 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1454 break;
1455 case NVME_NS_DPS_PI_TYPE1:
1456 case NVME_NS_DPS_PI_TYPE2:
1457 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1458 integrity.tag_size = sizeof(u16);
1459 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1460 break;
1461 default:
1462 integrity.profile = NULL;
1463 break;
1464 }
39b7baa4
CH		 1465 integrity.tuple_size = ms;
1466 blk_integrity_register(disk, &integrity);
1467 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1468}
1469#else
39b7baa4 1470static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1471{
1472}
1473#endif /* CONFIG_BLK_DEV_INTEGRITY */
1474
6b8190d6
SB		 1475static void nvme_set_chunk_size(struct nvme_ns *ns)
1476{
1477 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1478 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1479}
1480
3831761e 1481static void nvme_config_discard(struct nvme_ns *ns)
1673f1f0 1482{
3831761e
JA		 1483 struct nvme_ctrl *ctrl = ns->ctrl;
1484 struct request_queue *queue = ns->queue;
30e5e929
CH		 1485 u32 size = queue_logical_block_size(queue);
1486
3831761e
JA		 1487 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1488 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1489 return;
1490 }
1491
1492 if (ctrl->nr_streams && ns->sws && ns->sgs)
1493 size *= ns->sws * ns->sgs;
08095e70 1494
b35ba01e
CH		 1495 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1496 NVME_DSM_MAX_RANGES);
1497
b224f613 1498 queue->limits.discard_alignment = 0;
30e5e929 1499 queue->limits.discard_granularity = size;
f5d11840 1500
3831761e
JA		 1501 /* If discard is already enabled, don't reset queue limits */
1502 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1503 return;
1504
30e5e929
CH		 1505 blk_queue_max_discard_sectors(queue, UINT_MAX);
1506 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1507
1508 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1509 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1510}
1511
cdbff4f2 1512static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1513 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1514{
002fab04
CH		 1515 memset(ids, 0, sizeof(*ids));
1516
cdbff4f2 1517 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1518 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1519 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1520 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1521 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1522 /* Don't treat error as fatal we potentially
1523 * already have a NGUID or EUI-64
1524 */
002fab04 1525 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1526 dev_warn(ctrl->device,
3b22ba26
JT		 1527 "%s: Identify Descriptors failed\n", __func__);
1528 }
ac81bfa9
MB		 1529}
1530
ed754e5d
CH		 1531static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1532{
1533 return !uuid_is_null(&ids->uuid) ||
1534 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1535 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1536}
1537
002fab04
CH		 1538static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1539{
1540 return uuid_equal(&a->uuid, &b->uuid) &&
1541 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1542 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1543}
1544
24b0b58c
CH		 1545static void nvme_update_disk_info(struct gendisk *disk,
1546 struct nvme_ns *ns, struct nvme_id_ns *id)
1547{
1548 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1549 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1550
1551 blk_mq_freeze_queue(disk->queue);
1552 blk_integrity_unregister(disk);
1553
cee160fd
JL		 1554 blk_queue_logical_block_size(disk->queue, bs);
1555 blk_queue_physical_block_size(disk->queue, bs);
1556 blk_queue_io_min(disk->queue, bs);
1557
24b0b58c
CH		 1558 if (ns->ms && !ns->ext &&
1559 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1560 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1561 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c 1562 capacity = 0;
24b0b58c 1563
3831761e
JA		 1564 set_capacity(disk, capacity);
1565 nvme_config_discard(ns);
1293477f
CK		 1566
1567 if (id->nsattr & (1 << 0))
1568 set_disk_ro(disk, true);
1569 else
1570 set_disk_ro(disk, false);
1571
24b0b58c
CH		 1572 blk_mq_unfreeze_queue(disk->queue);
1573}
1574
ac81bfa9
MB		 1575static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1576{
1577 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1578
1579 /*
1580 * If identify namespace failed, use default 512 byte block size so
1581 * block layer can use before failing read/write for 0 capacity.
1582 */
c81bfba9 1583 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1584 if (ns->lba_shift == 0)
1585 ns->lba_shift = 9;
6b8190d6 1586 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1587 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1588 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1589 /* the PI implementation requires metadata equal t10 pi tuple size */
1590 if (ns->ms == sizeof(struct t10_pi_tuple))
1591 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1592 else
1593 ns->pi_type = 0;
1673f1f0 1594
6b8190d6
SB		 1595 if (ns->noiob)
1596 nvme_set_chunk_size(ns);
24b0b58c 1597 nvme_update_disk_info(disk, ns, id);
32acab31 1598#ifdef CONFIG_NVME_MULTIPATH
8f676b85 1599 if (ns->head->disk) {
32acab31 1600 nvme_update_disk_info(ns->head->disk, ns, id);
8f676b85
SG		 1601 blk_queue_stack_limits(ns->head->disk->queue, ns->queue);
1602 }
32acab31 1603#endif
ac81bfa9 1604}
1673f1f0 1605
ac81bfa9
MB		 1606static int nvme_revalidate_disk(struct gendisk *disk)
1607{
1608 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1609 struct nvme_ctrl *ctrl = ns->ctrl;
1610 struct nvme_id_ns *id;
002fab04 1611 struct nvme_ns_ids ids;
cdbff4f2 1612 int ret = 0;
ac81bfa9
MB		 1613
1614 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1615 set_capacity(disk, 0);
1616 return -ENODEV;
1617 }
1618
ed754e5d 1619 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1620 if (!id)
1621 return -ENODEV;
ac81bfa9 1622
cdbff4f2
CH		 1623 if (id->ncap == 0) {
1624 ret = -ENODEV;
1625 goto out;
1626 }
ac81bfa9 1627
5e0fab57 1628 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1629 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1630 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1631 dev_err(ctrl->device,
ed754e5d 1632 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1633 ret = -ENODEV;
1634 }
1635
cdbff4f2
CH		 1636out:
1637 kfree(id);
1638 return ret;
1673f1f0
CH		 1639}
1640
1641static char nvme_pr_type(enum pr_type type)
1642{
1643 switch (type) {
1644 case PR_WRITE_EXCLUSIVE:
1645 return 1;
1646 case PR_EXCLUSIVE_ACCESS:
1647 return 2;
1648 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1649 return 3;
1650 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1651 return 4;
1652 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1653 return 5;
1654 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1655 return 6;
1656 default:
1657 return 0;
1658 }
1659};
1660
1661static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1662 u64 key, u64 sa_key, u8 op)
1663{
32acab31
CH		 1664 struct nvme_ns_head *head = NULL;
1665 struct nvme_ns *ns;
1673f1f0 1666 struct nvme_command c;
32acab31 1667 int srcu_idx, ret;
1673f1f0
CH		 1668 u8 data[16] = { 0, };
1669
b0d61d58
KB		 1670 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1671 if (unlikely(!ns))
1672 return -EWOULDBLOCK;
1673
1673f1f0
CH		 1674 put_unaligned_le64(key, &data[0]);
1675 put_unaligned_le64(sa_key, &data[8]);
1676
1677 memset(&c, 0, sizeof(c));
1678 c.common.opcode = op;
b0d61d58 1679 c.common.nsid = cpu_to_le32(ns->head->ns_id);
b7c8f366 1680 c.common.cdw10 = cpu_to_le32(cdw10);
1673f1f0 1681
b0d61d58 1682 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1683 nvme_put_ns_from_disk(head, srcu_idx);
1684 return ret;
1673f1f0
CH		 1685}
1686
1687static int nvme_pr_register(struct block_device *bdev, u64 old,
1688 u64 new, unsigned flags)
1689{
1690 u32 cdw10;
1691
1692 if (flags & ~PR_FL_IGNORE_KEY)
1693 return -EOPNOTSUPP;
1694
1695 cdw10 = old ? 2 : 0;
1696 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1697 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1698 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1699}
1700
1701static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1702 enum pr_type type, unsigned flags)
1703{
1704 u32 cdw10;
1705
1706 if (flags & ~PR_FL_IGNORE_KEY)
1707 return -EOPNOTSUPP;
1708
1709 cdw10 = nvme_pr_type(type) << 8;
1710 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1711 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1712}
1713
1714static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1715 enum pr_type type, bool abort)
1716{
e9a9853c 1717 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1718 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1719}
1720
1721static int nvme_pr_clear(struct block_device *bdev, u64 key)
1722{
8c0b3915 1723 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1724 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1725}
1726
1727static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1728{
e9a9853c 1729 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1730 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1731}
1732
1733static const struct pr_ops nvme_pr_ops = {
1734 .pr_register = nvme_pr_register,
1735 .pr_reserve = nvme_pr_reserve,
1736 .pr_release = nvme_pr_release,
1737 .pr_preempt = nvme_pr_preempt,
1738 .pr_clear = nvme_pr_clear,
1739};
1740
a98e58e5 1741#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1742int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1743 bool send)
a98e58e5 1744{
4f1244c8 1745 struct nvme_ctrl *ctrl = data;
a98e58e5 1746 struct nvme_command cmd;
a98e58e5
SB		 1747
1748 memset(&cmd, 0, sizeof(cmd));
1749 if (send)
1750 cmd.common.opcode = nvme_admin_security_send;
1751 else
1752 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 1753 cmd.common.nsid = 0;
b7c8f366
CK		 1754 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1755 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5
SB		 1756
1757 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
6287b51c 1758 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0, false);
a98e58e5
SB		 1759}
1760EXPORT_SYMBOL_GPL(nvme_sec_submit);
1761#endif /* CONFIG_BLK_SED_OPAL */
1762
5bae7f73 1763static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1764 .owner = THIS_MODULE,
1765 .ioctl = nvme_ioctl,
761f2e1e 1766 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1767 .open = nvme_open,
1768 .release = nvme_release,
1769 .getgeo = nvme_getgeo,
1770 .revalidate_disk= nvme_revalidate_disk,
1771 .pr_ops = &nvme_pr_ops,
1772};
1773
32acab31
CH		 1774#ifdef CONFIG_NVME_MULTIPATH
1775static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1776{
1777 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1778
1779 if (!kref_get_unless_zero(&head->ref))
1780 return -ENXIO;
1781 return 0;
1782}
1783
1784static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1785{
1786 nvme_put_ns_head(disk->private_data);
1787}
1788
1789const struct block_device_operations nvme_ns_head_ops = {
1790 .owner = THIS_MODULE,
1791 .open = nvme_ns_head_open,
1792 .release = nvme_ns_head_release,
1793 .ioctl = nvme_ioctl,
1794 .compat_ioctl = nvme_ioctl,
1795 .getgeo = nvme_getgeo,
1796 .pr_ops = &nvme_pr_ops,
1797};
1798#endif /* CONFIG_NVME_MULTIPATH */
1799
5fd4ce1b
CH		 1800static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1801{
1802 unsigned long timeout =
1803 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1804 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1805 int ret;
1806
1807 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1808 if (csts == ~0)
1809 return -ENODEV;
5fd4ce1b
CH		 1810 if ((csts & NVME_CSTS_RDY) == bit)
1811 break;
1812
1813 msleep(100);
1814 if (fatal_signal_pending(current))
1815 return -EINTR;
1816 if (time_after(jiffies, timeout)) {
1b3c47c1 1817 dev_err(ctrl->device,
5fd4ce1b
CH		 1818 "Device not ready; aborting %s\n", enabled ?
1819 "initialisation" : "reset");
1820 return -ENODEV;
1821 }
1822 }
1823
1824 return ret;
1825}
1826
1827/*
1828 * If the device has been passed off to us in an enabled state, just clear
1829 * the enabled bit. The spec says we should set the 'shutdown notification
1830 * bits', but doing so may cause the device to complete commands to the
1831 * admin queue ... and we don't know what memory that might be pointing at!
1832 */
1833int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1834{
1835 int ret;
1836
1837 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1838 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1839
1840 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1841 if (ret)
1842 return ret;
54adc010 1843
b5a10c5f 1844 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1845 msleep(NVME_QUIRK_DELAY_AMOUNT);
1846
5fd4ce1b
CH		 1847 return nvme_wait_ready(ctrl, cap, false);
1848}
576d55d6 1849EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1850
1851int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1852{
1853 /*
1854 * Default to a 4K page size, with the intention to update this
1855 * path in the future to accomodate architectures with differing
1856 * kernel and IO page sizes.
1857 */
1858 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1859 int ret;
1860
1861 if (page_shift < dev_page_min) {
1b3c47c1 1862 dev_err(ctrl->device,
5fd4ce1b
CH		 1863 "Minimum device page size %u too large for host (%u)\n",
1864 1 << dev_page_min, 1 << page_shift);
1865 return -ENODEV;
1866 }
1867
1868 ctrl->page_size = 1 << page_shift;
1869
1870 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1871 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1872 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1873 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1874 ctrl->ctrl_config |= NVME_CC_ENABLE;
1875
1876 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1877 if (ret)
1878 return ret;
1879 return nvme_wait_ready(ctrl, cap, true);
1880}
576d55d6 1881EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1882
1883int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1884{
07fbd32a 1885 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1886 u32 csts;
1887 int ret;
1888
1889 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1890 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1891
1892 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1893 if (ret)
1894 return ret;
1895
1896 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1897 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1898 break;
1899
1900 msleep(100);
1901 if (fatal_signal_pending(current))
1902 return -EINTR;
1903 if (time_after(jiffies, timeout)) {
1b3c47c1 1904 dev_err(ctrl->device,
5fd4ce1b
CH		 1905 "Device shutdown incomplete; abort shutdown\n");
1906 return -ENODEV;
1907 }
1908 }
1909
1910 return ret;
1911}
576d55d6 1912EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1913
da35825d
CH		 1914static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1915 struct request_queue *q)
1916{
7c88cb00
JA		 1917 bool vwc = false;
1918
da35825d 1919 if (ctrl->max_hw_sectors) {
45686b61
CH		 1920 u32 max_segments =
1921 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1922
943e942e 1923 max_segments = min_not_zero(max_segments, ctrl->max_segments);
da35825d 1924 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1925 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1926 }
249159c5
KB		 1927 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1928 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1929 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1930 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1931 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1932 vwc = true;
1933 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1934}
1935
dbf86b39
JD		 1936static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1937{
1938 __le64 ts;
1939 int ret;
1940
1941 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1942 return 0;
1943
1944 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1945 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1946 NULL);
1947 if (ret)
1948 dev_warn_once(ctrl->device,
1949 "could not set timestamp (%d)\n", ret);
1950 return ret;
1951}
1952
49cd84b6
KB		 1953static int nvme_configure_acre(struct nvme_ctrl *ctrl)
1954{
1955 struct nvme_feat_host_behavior *host;
1956 int ret;
1957
1958 /* Don't bother enabling the feature if retry delay is not reported */
1959 if (!ctrl->crdt[0])
1960 return 0;
1961
1962 host = kzalloc(sizeof(*host), GFP_KERNEL);
1963 if (!host)
1964 return 0;
1965
1966 host->acre = NVME_ENABLE_ACRE;
1967 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
1968 host, sizeof(*host), NULL);
1969 kfree(host);
1970 return ret;
1971}
1972
634b8325 1973static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1974{
1975 /*
1976 * APST (Autonomous Power State Transition) lets us program a
1977 * table of power state transitions that the controller will
1978 * perform automatically. We configure it with a simple
1979 * heuristic: we are willing to spend at most 2% of the time
1980 * transitioning between power states. Therefore, when running
1981 * in any given state, we will enter the next lower-power
76e4ad09 1982 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1983 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1984 * the requested maximum latency.
1985 *
1986 * We will not autonomously enter any non-operational state for
1987 * which the total latency exceeds ps_max_latency_us. Users
1988 * can set ps_max_latency_us to zero to turn off APST.
1989 */
1990
1991 unsigned apste;
1992 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1993 u64 max_lat_us = 0;
1994 int max_ps = -1;
c5552fde
AL		 1995 int ret;
1996
1997 /*
1998 * If APST isn't supported or if we haven't been initialized yet,
1999 * then don't do anything.
2000 */
2001 if (!ctrl->apsta)
634b8325 2002 return 0;
c5552fde
AL		 2003
2004 if (ctrl->npss > 31) {
2005 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2006 return 0;
c5552fde
AL		 2007 }
2008
2009 table = kzalloc(sizeof(*table), GFP_KERNEL);
2010 if (!table)
634b8325 2011 return 0;
c5552fde 2012
76a5af84 2013 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 2014 /* Turn off APST. */
2015 apste = 0;
fb0dc399 2016 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 2017 } else {
2018 __le64 target = cpu_to_le64(0);
2019 int state;
2020
2021 /*
2022 * Walk through all states from lowest- to highest-power.
2023 * According to the spec, lower-numbered states use more
2024 * power. NPSS, despite the name, is the index of the
2025 * lowest-power state, not the number of states.
2026 */
2027 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 2028 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 2029
2030 if (target)
2031 table->entries[state] = target;
2032
ff5350a8
AL		 2033 /*
2034 * Don't allow transitions to the deepest state
2035 * if it's quirked off.
2036 */
2037 if (state == ctrl->npss &&
2038 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2039 continue;
2040
c5552fde
AL		 2041 /*
2042 * Is this state a useful non-operational state for
2043 * higher-power states to autonomously transition to?
2044 */
2045 if (!(ctrl->psd[state].flags &
2046 NVME_PS_FLAGS_NON_OP_STATE))
2047 continue;
2048
da87591b
KHF		 2049 exit_latency_us =
2050 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2051 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 2052 continue;
2053
da87591b
KHF		 2054 total_latency_us =
2055 exit_latency_us +
2056 le32_to_cpu(ctrl->psd[state].entry_lat);
2057
c5552fde
AL		 2058 /*
2059 * This state is good. Use it as the APST idle
2060 * target for higher power states.
2061 */
2062 transition_ms = total_latency_us + 19;
2063 do_div(transition_ms, 20);
2064 if (transition_ms > (1 << 24) - 1)
2065 transition_ms = (1 << 24) - 1;
2066
2067 target = cpu_to_le64((state << 3) |
2068 (transition_ms << 8));
fb0dc399
AL		 2069
2070 if (max_ps == -1)
2071 max_ps = state;
2072
2073 if (total_latency_us > max_lat_us)
2074 max_lat_us = total_latency_us;
c5552fde
AL		 2075 }
2076
2077 apste = 1;
fb0dc399
AL		 2078
2079 if (max_ps == -1) {
2080 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2081 } else {
2082 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2083 max_ps, max_lat_us, (int)sizeof(*table), table);
2084 }
c5552fde
AL		 2085 }
2086
2087 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2088 table, sizeof(*table), NULL);
2089 if (ret)
2090 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
2091
2092 kfree(table);
634b8325 2093 return ret;
c5552fde
AL		 2094}
2095
2096static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2097{
2098 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2099 u64 latency;
2100
2101 switch (val) {
2102 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2103 case PM_QOS_LATENCY_ANY:
2104 latency = U64_MAX;
2105 break;
2106
2107 default:
2108 latency = val;
2109 }
2110
2111 if (ctrl->ps_max_latency_us != latency) {
2112 ctrl->ps_max_latency_us = latency;
2113 nvme_configure_apst(ctrl);
2114 }
2115}
2116
bd4da3ab
AL		 2117struct nvme_core_quirk_entry {
2118 /*
2119 * NVMe model and firmware strings are padded with spaces. For
2120 * simplicity, strings in the quirk table are padded with NULLs
2121 * instead.
2122 */
2123 u16 vid;
2124 const char *mn;
2125 const char *fr;
2126 unsigned long quirks;
2127};
2128
2129static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2130 {
be56945c
AL		 2131 /*
2132 * This Toshiba device seems to die using any APST states. See:
2133 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2134 */
2135 .vid = 0x1179,
2136 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2137 .quirks = NVME_QUIRK_NO_APST,
be56945c 2138 }
bd4da3ab
AL		 2139};
2140
2141/* match is null-terminated but idstr is space-padded. */
2142static bool string_matches(const char *idstr, const char *match, size_t len)
2143{
2144 size_t matchlen;
2145
2146 if (!match)
2147 return true;
2148
2149 matchlen = strlen(match);
2150 WARN_ON_ONCE(matchlen > len);
2151
2152 if (memcmp(idstr, match, matchlen))
2153 return false;
2154
2155 for (; matchlen < len; matchlen++)
2156 if (idstr[matchlen] != ' ')
2157 return false;
2158
2159 return true;
2160}
2161
2162static bool quirk_matches(const struct nvme_id_ctrl *id,
2163 const struct nvme_core_quirk_entry *q)
2164{
2165 return q->vid == le16_to_cpu(id->vid) &&
2166 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2167 string_matches(id->fr, q->fr, sizeof(id->fr));
2168}
2169
ab9e00cc
CH		 2170static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2171 struct nvme_id_ctrl *id)
180de007
CH		 2172{
2173 size_t nqnlen;
2174 int off;
2175
6299358d
JD		 2176 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2177 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2178 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2179 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2180 return;
2181 }
180de007 2182
6299358d
JD		 2183 if (ctrl->vs >= NVME_VS(1, 2, 1))
2184 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2185 }
180de007
CH		 2186
2187 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2188 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2189 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2190 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2191 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2192 off += sizeof(id->sn);
ab9e00cc 2193 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2194 off += sizeof(id->mn);
ab9e00cc
CH		 2195 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2196}
2197
2198static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
2199{
2200 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
2201 kfree(subsys);
2202}
2203
2204static void nvme_release_subsystem(struct device *dev)
2205{
2206 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
2207}
2208
2209static void nvme_destroy_subsystem(struct kref *ref)
2210{
2211 struct nvme_subsystem *subsys =
2212 container_of(ref, struct nvme_subsystem, ref);
2213
2214 mutex_lock(&nvme_subsystems_lock);
2215 list_del(&subsys->entry);
2216 mutex_unlock(&nvme_subsystems_lock);
2217
ed754e5d 2218 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2219 device_del(&subsys->dev);
2220 put_device(&subsys->dev);
2221}
2222
2223static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2224{
2225 kref_put(&subsys->ref, nvme_destroy_subsystem);
2226}
2227
2228static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2229{
2230 struct nvme_subsystem *subsys;
2231
2232 lockdep_assert_held(&nvme_subsystems_lock);
2233
2234 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2235 if (strcmp(subsys->subnqn, subsysnqn))
2236 continue;
2237 if (!kref_get_unless_zero(&subsys->ref))
2238 continue;
2239 return subsys;
2240 }
2241
2242 return NULL;
2243}
2244
1e496938
HR		 2245#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2246 struct device_attribute subsys_attr_##_name = \
2247 __ATTR(_name, _mode, _show, NULL)
2248
2249static ssize_t nvme_subsys_show_nqn(struct device *dev,
2250 struct device_attribute *attr,
2251 char *buf)
2252{
2253 struct nvme_subsystem *subsys =
2254 container_of(dev, struct nvme_subsystem, dev);
2255
2256 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2257}
2258static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2259
2260#define nvme_subsys_show_str_function(field) \
2261static ssize_t subsys_##field##_show(struct device *dev, \
2262 struct device_attribute *attr, char *buf) \
2263{ \
2264 struct nvme_subsystem *subsys = \
2265 container_of(dev, struct nvme_subsystem, dev); \
2266 return sprintf(buf, "%.*s\n", \
2267 (int)sizeof(subsys->field), subsys->field); \
2268} \
2269static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2270
2271nvme_subsys_show_str_function(model);
2272nvme_subsys_show_str_function(serial);
2273nvme_subsys_show_str_function(firmware_rev);
2274
2275static struct attribute *nvme_subsys_attrs[] = {
2276 &subsys_attr_model.attr,
2277 &subsys_attr_serial.attr,
2278 &subsys_attr_firmware_rev.attr,
2279 &subsys_attr_subsysnqn.attr,
2280 NULL,
2281};
2282
2283static struct attribute_group nvme_subsys_attrs_group = {
2284 .attrs = nvme_subsys_attrs,
2285};
2286
2287static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2288 &nvme_subsys_attrs_group,
2289 NULL,
2290};
2291
b837b283
IR		 2292static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2293{
2294 int count = 0;
2295 struct nvme_ctrl *ctrl;
2296
2297 mutex_lock(&subsys->lock);
2298 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2299 if (ctrl->state != NVME_CTRL_DELETING &&
2300 ctrl->state != NVME_CTRL_DEAD)
2301 count++;
2302 }
2303 mutex_unlock(&subsys->lock);
2304
2305 return count;
2306}
2307
ab9e00cc
CH		 2308static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2309{
2310 struct nvme_subsystem *subsys, *found;
2311 int ret;
2312
2313 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2314 if (!subsys)
2315 return -ENOMEM;
2316 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2317 if (ret < 0) {
2318 kfree(subsys);
2319 return ret;
2320 }
2321 subsys->instance = ret;
2322 mutex_init(&subsys->lock);
2323 kref_init(&subsys->ref);
2324 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2325 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2326 nvme_init_subnqn(subsys, ctrl, id);
2327 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2328 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2329 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2330 subsys->vendor_id = le16_to_cpu(id->vid);
2331 subsys->cmic = id->cmic;
2332
2333 subsys->dev.class = nvme_subsys_class;
2334 subsys->dev.release = nvme_release_subsystem;
1e496938 2335 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2336 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2337 device_initialize(&subsys->dev);
2338
2339 mutex_lock(&nvme_subsystems_lock);
2340 found = __nvme_find_get_subsystem(subsys->subnqn);
2341 if (found) {
2342 /*
2343 * Verify that the subsystem actually supports multiple
2344 * controllers, else bail out.
2345 */
16001c10 2346 if (!(ctrl->opts && ctrl->opts->discovery_nqn) &&
181303d0 2347 nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2348 dev_err(ctrl->device,
2349 "ignoring ctrl due to duplicate subnqn (%s).\n",
2350 found->subnqn);
2351 nvme_put_subsystem(found);
2352 ret = -EINVAL;
2353 goto out_unlock;
2354 }
2355
2356 __nvme_release_subsystem(subsys);
2357 subsys = found;
2358 } else {
2359 ret = device_add(&subsys->dev);
2360 if (ret) {
2361 dev_err(ctrl->device,
2362 "failed to register subsystem device.\n");
2363 goto out_unlock;
2364 }
ed754e5d 2365 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2366 list_add_tail(&subsys->entry, &nvme_subsystems);
2367 }
2368
2369 ctrl->subsys = subsys;
2370 mutex_unlock(&nvme_subsystems_lock);
2371
2372 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2373 dev_name(ctrl->device))) {
2374 dev_err(ctrl->device,
2375 "failed to create sysfs link from subsystem.\n");
2376 /* the transport driver will eventually put the subsystem */
2377 return -EINVAL;
2378 }
2379
2380 mutex_lock(&subsys->lock);
2381 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2382 mutex_unlock(&subsys->lock);
2383
2384 return 0;
2385
2386out_unlock:
2387 mutex_unlock(&nvme_subsystems_lock);
2388 put_device(&subsys->dev);
2389 return ret;
180de007
CH		 2390}
2391
0e98719b
CH		 2392int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
2393 void *log, size_t size, u64 offset)
c627c487
KB		 2394{
2395 struct nvme_command c = { };
70da6094
MB		 2396 unsigned long dwlen = size / 4 - 1;
2397
2398 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2399 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2400 c.get_log_page.lid = log_page;
0e98719b 2401 c.get_log_page.lsp = lsp;
70da6094
MB		 2402 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2403 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2404 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2405 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2406
2407 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2408}
2409
84fef62d
KB		 2410static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2411{
2412 int ret;
2413
2414 if (!ctrl->effects)
2415 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2416
2417 if (!ctrl->effects)
2418 return 0;
2419
0e98719b
CH		 2420 ret = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CMD_EFFECTS, 0,
2421 ctrl->effects, sizeof(*ctrl->effects), 0);
84fef62d
KB		 2422 if (ret) {
2423 kfree(ctrl->effects);
2424 ctrl->effects = NULL;
2425 }
2426 return ret;
180de007
CH		 2427}
2428
7fd8930f
CH		 2429/*
2430 * Initialize the cached copies of the Identify data and various controller
2431 * register in our nvme_ctrl structure. This should be called as soon as
2432 * the admin queue is fully up and running.
2433 */
2434int nvme_init_identify(struct nvme_ctrl *ctrl)
2435{
2436 struct nvme_id_ctrl *id;
2437 u64 cap;
2438 int ret, page_shift;
a229dbf6 2439 u32 max_hw_sectors;
76a5af84 2440 bool prev_apst_enabled;
7fd8930f 2441
f3ca80fc
CH		 2442 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2443 if (ret) {
1b3c47c1 2444 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2445 return ret;
2446 }
2447
7fd8930f
CH		 2448 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2449 if (ret) {
1b3c47c1 2450 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2451 return ret;
2452 }
2453 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2454
8ef2074d 2455 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2456 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2457
7fd8930f
CH		 2458 ret = nvme_identify_ctrl(ctrl, &id);
2459 if (ret) {
1b3c47c1 2460 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2461 return -EIO;
2462 }
2463
84fef62d
KB		 2464 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2465 ret = nvme_get_effects_log(ctrl);
2466 if (ret < 0)
75c8b19a 2467 goto out_free;
84fef62d 2468 }
180de007 2469
bd4da3ab 2470 if (!ctrl->identified) {
ab9e00cc
CH		 2471 int i;
2472
2473 ret = nvme_init_subsystem(ctrl, id);
2474 if (ret)
2475 goto out_free;
2476
bd4da3ab
AL		 2477 /*
2478 * Check for quirks. Quirk can depend on firmware version,
2479 * so, in principle, the set of quirks present can change
2480 * across a reset. As a possible future enhancement, we
2481 * could re-scan for quirks every time we reinitialize
2482 * the device, but we'd have to make sure that the driver
2483 * behaves intelligently if the quirks change.
2484 */
bd4da3ab
AL		 2485 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2486 if (quirk_matches(id, &core_quirks[i]))
2487 ctrl->quirks |= core_quirks[i].quirks;
2488 }
2489 }
2490
c35e30b4 2491 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2492 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2493 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2494 }
2495
49cd84b6
KB		 2496 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
2497 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
2498 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
2499
8a9ae523 2500 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2501 ctrl->oncs = le16_to_cpup(&id->oncs);
c0561f82 2502 ctrl->oaes = le32_to_cpu(id->oaes);
6bf25d16 2503 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2504 ctrl->vwc = id->vwc;
7fd8930f 2505 if (id->mdts)
a229dbf6 2506 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2507 else
a229dbf6
CH		 2508 max_hw_sectors = UINT_MAX;
2509 ctrl->max_hw_sectors =
2510 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2511
da35825d 2512 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2513 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2514 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 2515 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 2516 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 2517
07fbd32a
MP		 2518 if (id->rtd3e) {
2519 /* us -> s */
2520 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2521
2522 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2523 shutdown_timeout, 60);
2524
2525 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2526 dev_info(ctrl->device,
07fbd32a
MP		 2527 "Shutdown timeout set to %u seconds\n",
2528 ctrl->shutdown_timeout);
2529 } else
2530 ctrl->shutdown_timeout = shutdown_timeout;
2531
c5552fde 2532 ctrl->npss = id->npss;
76a5af84
KHF		 2533 ctrl->apsta = id->apsta;
2534 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2535 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2536 if (force_apst && id->apsta) {
f0425db0 2537 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2538 ctrl->apst_enabled = true;
c35e30b4 2539 } else {
76a5af84 2540 ctrl->apst_enabled = false;
c35e30b4
AL		 2541 }
2542 } else {
76a5af84 2543 ctrl->apst_enabled = id->apsta;
c35e30b4 2544 }
c5552fde
AL		 2545 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2546
d3d5b87d 2547 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2548 ctrl->icdoff = le16_to_cpu(id->icdoff);
2549 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2550 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2551 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2552
2553 /*
2554 * In fabrics we need to verify the cntlid matches the
2555 * admin connect
2556 */
634b8325 2557 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2558 ret = -EINVAL;
634b8325
KB		 2559 goto out_free;
2560 }
038bd4cb
SG		 2561
2562 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2563 dev_err(ctrl->device,
038bd4cb
SG		 2564 "keep-alive support is mandatory for fabrics\n");
2565 ret = -EINVAL;
634b8325 2566 goto out_free;
038bd4cb 2567 }
07bfcd09
CH		 2568 } else {
2569 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2570 ctrl->hmpre = le32_to_cpu(id->hmpre);
2571 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2572 ctrl->hmminds = le32_to_cpu(id->hmminds);
2573 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2574 }
da35825d 2575
0d0b660f 2576 ret = nvme_mpath_init(ctrl, id);
7fd8930f 2577 kfree(id);
bd4da3ab 2578
0d0b660f
CH		 2579 if (ret < 0)
2580 return ret;
2581
76a5af84 2582 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2583 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2584 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2585 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2586
634b8325
KB		 2587 ret = nvme_configure_apst(ctrl);
2588 if (ret < 0)
2589 return ret;
dbf86b39
JD		 2590
2591 ret = nvme_configure_timestamp(ctrl);
2592 if (ret < 0)
2593 return ret;
634b8325
KB		 2594
2595 ret = nvme_configure_directives(ctrl);
2596 if (ret < 0)
2597 return ret;
c5552fde 2598
49cd84b6
KB		 2599 ret = nvme_configure_acre(ctrl);
2600 if (ret < 0)
2601 return ret;
2602
bd4da3ab 2603 ctrl->identified = true;
c5552fde 2604
634b8325
KB		 2605 return 0;
2606
2607out_free:
2608 kfree(id);
07bfcd09 2609 return ret;
7fd8930f 2610}
576d55d6 2611EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2612
f3ca80fc 2613static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2614{
a6a5149b
CH		 2615 struct nvme_ctrl *ctrl =
2616 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2617
2b1b7e78
JW		 2618 switch (ctrl->state) {
2619 case NVME_CTRL_LIVE:
2620 case NVME_CTRL_ADMIN_ONLY:
2621 break;
2622 default:
a6a5149b 2623 return -EWOULDBLOCK;
2b1b7e78
JW		 2624 }
2625
a6a5149b 2626 file->private_data = ctrl;
f3ca80fc
CH		 2627 return 0;
2628}
2629
bfd89471
CH		 2630static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2631{
2632 struct nvme_ns *ns;
2633 int ret;
2634
765cc031 2635 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2636 if (list_empty(&ctrl->namespaces)) {
2637 ret = -ENOTTY;
2638 goto out_unlock;
2639 }
2640
2641 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2642 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2643 dev_warn(ctrl->device,
bfd89471
CH		 2644 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2645 ret = -EINVAL;
2646 goto out_unlock;
2647 }
2648
1b3c47c1 2649 dev_warn(ctrl->device,
bfd89471
CH		 2650 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2651 kref_get(&ns->kref);
765cc031 2652 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2653
2654 ret = nvme_user_cmd(ctrl, ns, argp);
2655 nvme_put_ns(ns);
2656 return ret;
2657
2658out_unlock:
765cc031 2659 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2660 return ret;
2661}
2662
f3ca80fc
CH		 2663static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2664 unsigned long arg)
2665{
2666 struct nvme_ctrl *ctrl = file->private_data;
2667 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2668
2669 switch (cmd) {
2670 case NVME_IOCTL_ADMIN_CMD:
2671 return nvme_user_cmd(ctrl, NULL, argp);
2672 case NVME_IOCTL_IO_CMD:
bfd89471 2673 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2674 case NVME_IOCTL_RESET:
1b3c47c1 2675 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2676 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2677 case NVME_IOCTL_SUBSYS_RESET:
2678 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2679 case NVME_IOCTL_RESCAN:
2680 nvme_queue_scan(ctrl);
2681 return 0;
f3ca80fc
CH		 2682 default:
2683 return -ENOTTY;
2684 }
2685}
2686
2687static const struct file_operations nvme_dev_fops = {
2688 .owner = THIS_MODULE,
2689 .open = nvme_dev_open,
f3ca80fc
CH		 2690 .unlocked_ioctl = nvme_dev_ioctl,
2691 .compat_ioctl = nvme_dev_ioctl,
2692};
2693
2694static ssize_t nvme_sysfs_reset(struct device *dev,
2695 struct device_attribute *attr, const char *buf,
2696 size_t count)
2697{
2698 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2699 int ret;
2700
d86c4d8e 2701 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2702 if (ret < 0)
2703 return ret;
2704 return count;
1673f1f0 2705}
f3ca80fc 2706static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2707
9ec3bb2f
KB		 2708static ssize_t nvme_sysfs_rescan(struct device *dev,
2709 struct device_attribute *attr, const char *buf,
2710 size_t count)
2711{
2712 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2713
2714 nvme_queue_scan(ctrl);
2715 return count;
2716}
2717static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2718
5b85b826
CH		 2719static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2720{
2721 struct gendisk *disk = dev_to_disk(dev);
2722
2723 if (disk->fops == &nvme_fops)
2724 return nvme_get_ns_from_dev(dev)->head;
2725 else
2726 return disk->private_data;
2727}
2728
118472ab 2729static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2730 char *buf)
118472ab 2731{
5b85b826
CH		 2732 struct nvme_ns_head *head = dev_to_ns_head(dev);
2733 struct nvme_ns_ids *ids = &head->ids;
2734 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2735 int serial_len = sizeof(subsys->serial);
2736 int model_len = sizeof(subsys->model);
118472ab 2737
002fab04
CH		 2738 if (!uuid_is_null(&ids->uuid))
2739 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2740
002fab04
CH		 2741 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2742 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2743
002fab04
CH		 2744 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2745 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2746
ab9e00cc
CH		 2747 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2748 subsys->serial[serial_len - 1] == '\0'))
118472ab 2749 serial_len--;
ab9e00cc
CH		 2750 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2751 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2752 model_len--;
2753
ab9e00cc
CH		 2754 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2755 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2756 head->ns_id);
118472ab 2757}
c828a892 2758static DEVICE_ATTR_RO(wwid);
118472ab 2759
d934f984 2760static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2761 char *buf)
d934f984 2762{
5b85b826 2763 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2764}
c828a892 2765static DEVICE_ATTR_RO(nguid);
d934f984 2766
2b9b6e86 2767static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2768 char *buf)
2b9b6e86 2769{
5b85b826 2770 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2771
2772 /* For backward compatibility expose the NGUID to userspace if
2773 * we have no UUID set
2774 */
002fab04 2775 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2776 printk_ratelimited(KERN_WARNING
2777 "No UUID available providing old NGUID\n");
002fab04 2778 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2779 }
002fab04 2780 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2781}
c828a892 2782static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2783
2784static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2785 char *buf)
2b9b6e86 2786{
5b85b826 2787 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2788}
c828a892 2789static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2790
2791static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2792 char *buf)
2b9b6e86 2793{
5b85b826 2794 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2795}
c828a892 2796static DEVICE_ATTR_RO(nsid);
2b9b6e86 2797
5b85b826 2798static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2799 &dev_attr_wwid.attr,
2b9b6e86 2800 &dev_attr_uuid.attr,
d934f984 2801 &dev_attr_nguid.attr,
2b9b6e86
KB		 2802 &dev_attr_eui.attr,
2803 &dev_attr_nsid.attr,
0d0b660f
CH		 2804#ifdef CONFIG_NVME_MULTIPATH
2805 &dev_attr_ana_grpid.attr,
2806 &dev_attr_ana_state.attr,
2807#endif
2b9b6e86
KB		 2808 NULL,
2809};
2810
5b85b826 2811static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2812 struct attribute *a, int n)
2813{
2814 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2815 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2816
2817 if (a == &dev_attr_uuid.attr) {
a04b5de5 2818 if (uuid_is_null(&ids->uuid) &&
002fab04 2819 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2820 return 0;
2821 }
2822 if (a == &dev_attr_nguid.attr) {
002fab04 2823 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2824 return 0;
2825 }
2826 if (a == &dev_attr_eui.attr) {
002fab04 2827 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2828 return 0;
2829 }
0d0b660f
CH		 2830#ifdef CONFIG_NVME_MULTIPATH
2831 if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
2832 if (dev_to_disk(dev)->fops != &nvme_fops) /* per-path attr */
2833 return 0;
2834 if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
2835 return 0;
2836 }
2837#endif
2b9b6e86
KB		 2838 return a->mode;
2839}
2840
eb090c4c 2841static const struct attribute_group nvme_ns_id_attr_group = {
5b85b826
CH		 2842 .attrs = nvme_ns_id_attrs,
2843 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2844};
2845
33b14f67
HR		 2846const struct attribute_group *nvme_ns_id_attr_groups[] = {
2847 &nvme_ns_id_attr_group,
2848#ifdef CONFIG_NVM
2849 &nvme_nvm_attr_group,
2850#endif
2851 NULL,
2852};
2853
931e1c22 2854#define nvme_show_str_function(field) \
779ff756
KB		 2855static ssize_t field##_show(struct device *dev, \
2856 struct device_attribute *attr, char *buf) \
2857{ \
2858 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2859 return sprintf(buf, "%.*s\n", \
2860 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2861} \
2862static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2863
ab9e00cc
CH		 2864nvme_show_str_function(model);
2865nvme_show_str_function(serial);
2866nvme_show_str_function(firmware_rev);
2867
931e1c22
ML		 2868#define nvme_show_int_function(field) \
2869static ssize_t field##_show(struct device *dev, \
2870 struct device_attribute *attr, char *buf) \
2871{ \
2872 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2873 return sprintf(buf, "%d\n", ctrl->field); \
2874} \
2875static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2876
931e1c22 2877nvme_show_int_function(cntlid);
103e515e 2878nvme_show_int_function(numa_node);
779ff756 2879
1a353d85
ML		 2880static ssize_t nvme_sysfs_delete(struct device *dev,
2881 struct device_attribute *attr, const char *buf,
2882 size_t count)
2883{
2884 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2885
2886 if (device_remove_file_self(dev, attr))
c5017e85 2887 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2888 return count;
2889}
2890static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2891
2892static ssize_t nvme_sysfs_show_transport(struct device *dev,
2893 struct device_attribute *attr,
2894 char *buf)
2895{
2896 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2897
2898 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2899}
2900static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2901
8432bdb2
SG		 2902static ssize_t nvme_sysfs_show_state(struct device *dev,
2903 struct device_attribute *attr,
2904 char *buf)
2905{
2906 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2907 static const char *const state_name[] = {
2908 [NVME_CTRL_NEW] = "new",
2909 [NVME_CTRL_LIVE] = "live",
2b1b7e78 2910 [NVME_CTRL_ADMIN_ONLY] = "only-admin",
8432bdb2 2911 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 2912 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 2913 [NVME_CTRL_DELETING] = "deleting",
2914 [NVME_CTRL_DEAD] = "dead",
2915 };
2916
2917 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2918 state_name[ctrl->state])
2919 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2920
2921 return sprintf(buf, "unknown state\n");
2922}
2923
2924static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2925
1a353d85
ML		 2926static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2927 struct device_attribute *attr,
2928 char *buf)
2929{
2930 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2931
ab9e00cc 2932 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2933}
2934static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2935
2936static ssize_t nvme_sysfs_show_address(struct device *dev,
2937 struct device_attribute *attr,
2938 char *buf)
2939{
2940 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2941
2942 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2943}
2944static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2945
779ff756
KB		 2946static struct attribute *nvme_dev_attrs[] = {
2947 &dev_attr_reset_controller.attr,
9ec3bb2f 2948 &dev_attr_rescan_controller.attr,
779ff756
KB		 2949 &dev_attr_model.attr,
2950 &dev_attr_serial.attr,
2951 &dev_attr_firmware_rev.attr,
931e1c22 2952 &dev_attr_cntlid.attr,
1a353d85
ML		 2953 &dev_attr_delete_controller.attr,
2954 &dev_attr_transport.attr,
2955 &dev_attr_subsysnqn.attr,
2956 &dev_attr_address.attr,
8432bdb2 2957 &dev_attr_state.attr,
103e515e 2958 &dev_attr_numa_node.attr,
779ff756
KB		 2959 NULL
2960};
2961
1a353d85
ML		 2962static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2963 struct attribute *a, int n)
2964{
2965 struct device *dev = container_of(kobj, struct device, kobj);
2966 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2967
49d3d50b
CH		 2968 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2969 return 0;
2970 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2971 return 0;
1a353d85
ML		 2972
2973 return a->mode;
2974}
2975
779ff756 2976static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2977 .attrs = nvme_dev_attrs,
2978 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2979};
2980
2981static const struct attribute_group *nvme_dev_attr_groups[] = {
2982 &nvme_dev_attrs_group,
2983 NULL,
2984};
2985
ed754e5d
CH		 2986static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
2987 unsigned nsid)
2988{
2989 struct nvme_ns_head *h;
2990
2991 lockdep_assert_held(&subsys->lock);
2992
2993 list_for_each_entry(h, &subsys->nsheads, entry) {
2994 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
2995 return h;
2996 }
2997
2998 return NULL;
2999}
3000
3001static int __nvme_check_ids(struct nvme_subsystem *subsys,
3002 struct nvme_ns_head *new)
3003{
3004 struct nvme_ns_head *h;
3005
3006 lockdep_assert_held(&subsys->lock);
3007
3008 list_for_each_entry(h, &subsys->nsheads, entry) {
3009 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 3010 !list_empty(&h->list) &&
ed754e5d
CH		 3011 nvme_ns_ids_equal(&new->ids, &h->ids))
3012 return -EINVAL;
3013 }
3014
3015 return 0;
3016}
3017
3018static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
3019 unsigned nsid, struct nvme_id_ns *id)
3020{
3021 struct nvme_ns_head *head;
f3334447 3022 size_t size = sizeof(*head);
ed754e5d
CH		 3023 int ret = -ENOMEM;
3024
f3334447
CH		 3025#ifdef CONFIG_NVME_MULTIPATH
3026 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3027#endif
3028
3029 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3030 if (!head)
3031 goto out;
3032 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3033 if (ret < 0)
3034 goto out_free_head;
3035 head->instance = ret;
3036 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3037 ret = init_srcu_struct(&head->srcu);
3038 if (ret)
3039 goto out_ida_remove;
ed754e5d
CH		 3040 head->subsys = ctrl->subsys;
3041 head->ns_id = nsid;
3042 kref_init(&head->ref);
3043
3044 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
3045
3046 ret = __nvme_check_ids(ctrl->subsys, head);
3047 if (ret) {
3048 dev_err(ctrl->device,
3049 "duplicate IDs for nsid %d\n", nsid);
3050 goto out_cleanup_srcu;
3051 }
3052
32acab31
CH		 3053 ret = nvme_mpath_alloc_disk(ctrl, head);
3054 if (ret)
3055 goto out_cleanup_srcu;
3056
ed754e5d 3057 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3058
3059 kref_get(&ctrl->subsys->ref);
3060
ed754e5d
CH		 3061 return head;
3062out_cleanup_srcu:
3063 cleanup_srcu_struct(&head->srcu);
fd92c77f 3064out_ida_remove:
ed754e5d
CH		 3065 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3066out_free_head:
3067 kfree(head);
3068out:
3069 return ERR_PTR(ret);
3070}
3071
3072static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 3073 struct nvme_id_ns *id)
ed754e5d
CH		 3074{
3075 struct nvme_ctrl *ctrl = ns->ctrl;
3076 bool is_shared = id->nmic & (1 << 0);
3077 struct nvme_ns_head *head = NULL;
3078 int ret = 0;
3079
3080 mutex_lock(&ctrl->subsys->lock);
3081 if (is_shared)
3082 head = __nvme_find_ns_head(ctrl->subsys, nsid);
3083 if (!head) {
3084 head = nvme_alloc_ns_head(ctrl, nsid, id);
3085 if (IS_ERR(head)) {
3086 ret = PTR_ERR(head);
3087 goto out_unlock;
3088 }
ed754e5d
CH		 3089 } else {
3090 struct nvme_ns_ids ids;
3091
3092 nvme_report_ns_ids(ctrl, nsid, id, &ids);
3093 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
3094 dev_err(ctrl->device,
3095 "IDs don't match for shared namespace %d\n",
3096 nsid);
3097 ret = -EINVAL;
3098 goto out_unlock;
3099 }
ed754e5d
CH		 3100 }
3101
3102 list_add_tail(&ns->siblings, &head->list);
3103 ns->head = head;
3104
3105out_unlock:
3106 mutex_unlock(&ctrl->subsys->lock);
3107 return ret;
3108}
3109
5bae7f73
CH		 3110static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
3111{
3112 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
3113 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
3114
ed754e5d 3115 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 3116}
3117
32f0c4af 3118static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3119{
32f0c4af 3120 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3121
765cc031 3122 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3123 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3124 if (ns->head->ns_id == nsid) {
2dd41228
CH		 3125 if (!kref_get_unless_zero(&ns->kref))
3126 continue;
32f0c4af
KB		 3127 ret = ns;
3128 break;
3129 }
ed754e5d 3130 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3131 break;
3132 }
765cc031 3133 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3134 return ret;
5bae7f73
CH		 3135}
3136
f5d11840
JA		 3137static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
3138{
3139 struct streams_directive_params s;
3140 int ret;
3141
3142 if (!ctrl->nr_streams)
3143 return 0;
3144
ed754e5d 3145 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 3146 if (ret)
3147 return ret;
3148
3149 ns->sws = le32_to_cpu(s.sws);
3150 ns->sgs = le16_to_cpu(s.sgs);
3151
3152 if (ns->sws) {
3153 unsigned int bs = 1 << ns->lba_shift;
3154
3155 blk_queue_io_min(ns->queue, bs * ns->sws);
3156 if (ns->sgs)
3157 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
3158 }
3159
3160 return 0;
3161}
3162
5bae7f73
CH		 3163static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3164{
3165 struct nvme_ns *ns;
3166 struct gendisk *disk;
ac81bfa9
MB		 3167 struct nvme_id_ns *id;
3168 char disk_name[DISK_NAME_LEN];
103e515e 3169 int node = ctrl->numa_node, flags = GENHD_FL_EXT_DEVT;
5bae7f73
CH		 3170
3171 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3172 if (!ns)
3173 return;
3174
3175 ns->queue = blk_mq_init_queue(ctrl->tagset);
3176 if (IS_ERR(ns->queue))
ed754e5d 3177 goto out_free_ns;
e0596ab2 3178
8b904b5b 3179 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
e0596ab2
LG		 3180 if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3181 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3182
5bae7f73
CH		 3183 ns->queue->queuedata = ns;
3184 ns->ctrl = ctrl;
3185
5bae7f73 3186 kref_init(&ns->kref);
5bae7f73 3187 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3188
3189 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3190 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3191
cdbff4f2
CH		 3192 id = nvme_identify_ns(ctrl, nsid);
3193 if (!id)
ac81bfa9
MB		 3194 goto out_free_queue;
3195
cdbff4f2
CH		 3196 if (id->ncap == 0)
3197 goto out_free_id;
3198
9bd82b1a 3199 if (nvme_init_ns_head(ns, nsid, id))
ed754e5d 3200 goto out_free_id;
654b4a4a 3201 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3202 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3203
3dc87dd0
MB		 3204 disk = alloc_disk_node(0, node);
3205 if (!disk)
ed754e5d 3206 goto out_unlink_ns;
ac81bfa9 3207
3dc87dd0
MB		 3208 disk->fops = &nvme_fops;
3209 disk->private_data = ns;
3210 disk->queue = ns->queue;
32acab31 3211 disk->flags = flags;
3dc87dd0
MB		 3212 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3213 ns->disk = disk;
3214
3215 __nvme_revalidate_disk(disk, id);
5bae7f73 3216
85136c01
MB		 3217 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
3218 if (nvme_nvm_register(ns, disk_name, node)) {
3219 dev_warn(ctrl->device, "LightNVM init failure\n");
3220 goto out_put_disk;
3221 }
3222 }
3223
765cc031 3224 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3225 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3226 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3227
d22524a4 3228 nvme_get_ctrl(ctrl);
ac81bfa9 3229
33b14f67 3230 device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
32acab31 3231
0d0b660f 3232 nvme_mpath_add_disk(ns, id);
b9e03857 3233 nvme_fault_inject_init(ns);
0d0b660f
CH		 3234 kfree(id);
3235
5bae7f73 3236 return;
85136c01
MB		 3237 out_put_disk:
3238 put_disk(ns->disk);
ed754e5d
CH		 3239 out_unlink_ns:
3240 mutex_lock(&ctrl->subsys->lock);
3241 list_del_rcu(&ns->siblings);
3242 mutex_unlock(&ctrl->subsys->lock);
ac81bfa9
MB		 3243 out_free_id:
3244 kfree(id);
5bae7f73
CH		 3245 out_free_queue:
3246 blk_cleanup_queue(ns->queue);
3247 out_free_ns:
3248 kfree(ns);
3249}
3250
3251static void nvme_ns_remove(struct nvme_ns *ns)
3252{
646017a6
KB		 3253 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3254 return;
69d3b8ac 3255
b9e03857 3256 nvme_fault_inject_fini(ns);
b0b4e09c 3257 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73 3258 del_gendisk(ns->disk);
5bae7f73 3259 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3260 if (blk_get_integrity(ns->disk))
3261 blk_integrity_unregister(ns->disk);
5bae7f73 3262 }
32f0c4af 3263
ed754e5d 3264 mutex_lock(&ns->ctrl->subsys->lock);
9941a862 3265 list_del_rcu(&ns->siblings);
48f78be3 3266 nvme_mpath_clear_current_path(ns);
ed754e5d
CH		 3267 mutex_unlock(&ns->ctrl->subsys->lock);
3268
765cc031 3269 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3270 list_del_init(&ns->list);
765cc031 3271 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3272
9941a862 3273 synchronize_srcu(&ns->head->srcu);
479a322f 3274 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3275 nvme_put_ns(ns);
3276}
3277
540c801c
KB		 3278static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3279{
3280 struct nvme_ns *ns;
3281
32f0c4af 3282 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3283 if (ns) {
b0b4e09c 3284 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3285 nvme_ns_remove(ns);
32f0c4af 3286 nvme_put_ns(ns);
540c801c
KB		 3287 } else
3288 nvme_alloc_ns(ctrl, nsid);
3289}
3290
47b0e50a
SB		 3291static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3292 unsigned nsid)
3293{
3294 struct nvme_ns *ns, *next;
6f8e0d78 3295 LIST_HEAD(rm_list);
47b0e50a 3296
765cc031 3297 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3298 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
cf39a6bc 3299 if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
6f8e0d78 3300 list_move_tail(&ns->list, &rm_list);
47b0e50a 3301 }
765cc031 3302 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3303
3304 list_for_each_entry_safe(ns, next, &rm_list, list)
3305 nvme_ns_remove(ns);
3306
47b0e50a
SB		 3307}
3308
540c801c
KB		 3309static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3310{
3311 struct nvme_ns *ns;
3312 __le32 *ns_list;
3313 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3314 int ret = 0;
3315
42595eb7 3316 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3317 if (!ns_list)
3318 return -ENOMEM;
3319
3320 for (i = 0; i < num_lists; i++) {
3321 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3322 if (ret)
47b0e50a 3323 goto free;
540c801c
KB		 3324
3325 for (j = 0; j < min(nn, 1024U); j++) {
3326 nsid = le32_to_cpu(ns_list[j]);
3327 if (!nsid)
3328 goto out;
3329
3330 nvme_validate_ns(ctrl, nsid);
3331
3332 while (++prev < nsid) {
32f0c4af
KB		 3333 ns = nvme_find_get_ns(ctrl, prev);
3334 if (ns) {
540c801c 3335 nvme_ns_remove(ns);
32f0c4af
KB		 3336 nvme_put_ns(ns);
3337 }
540c801c
KB		 3338 }
3339 }
3340 nn -= j;
3341 }
3342 out:
47b0e50a
SB		 3343 nvme_remove_invalid_namespaces(ctrl, prev);
3344 free:
540c801c
KB		 3345 kfree(ns_list);
3346 return ret;
3347}
3348
5955be21 3349static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3350{
5bae7f73
CH		 3351 unsigned i;
3352
540c801c
KB		 3353 for (i = 1; i <= nn; i++)
3354 nvme_validate_ns(ctrl, i);
3355
47b0e50a 3356 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3357}
3358
f493af37 3359static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3360{
3361 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3362 __le32 *log;
f493af37 3363 int error;
30d90964
CH		 3364
3365 log = kzalloc(log_size, GFP_KERNEL);
3366 if (!log)
f493af37 3367 return;
30d90964 3368
f493af37
CH		 3369 /*
3370 * We need to read the log to clear the AEN, but we don't want to rely
3371 * on it for the changed namespace information as userspace could have
3372 * raced with us in reading the log page, which could cause us to miss
3373 * updates.
3374 */
0e98719b
CH		 3375 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, log,
3376 log_size, 0);
f493af37 3377 if (error)
30d90964
CH		 3378 dev_warn(ctrl->device,
3379 "reading changed ns log failed: %d\n", error);
30d90964 3380
30d90964 3381 kfree(log);
30d90964
CH		 3382}
3383
5955be21 3384static void nvme_scan_work(struct work_struct *work)
5bae7f73 3385{
5955be21
CH		 3386 struct nvme_ctrl *ctrl =
3387 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3388 struct nvme_id_ctrl *id;
540c801c 3389 unsigned nn;
5bae7f73 3390
5955be21
CH		 3391 if (ctrl->state != NVME_CTRL_LIVE)
3392 return;
3393
2b1b7e78
JW		 3394 WARN_ON_ONCE(!ctrl->tagset);
3395
77016199 3396 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 3397 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 3398 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 3399 }
3400
5bae7f73
CH		 3401 if (nvme_identify_ctrl(ctrl, &id))
3402 return;
540c801c
KB		 3403
3404 nn = le32_to_cpu(id->nn);
8ef2074d 3405 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3406 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3407 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3408 goto out_free_id;
540c801c 3409 }
5955be21 3410 nvme_scan_ns_sequential(ctrl, nn);
30d90964
CH		 3411out_free_id:
3412 kfree(id);
765cc031 3413 down_write(&ctrl->namespaces_rwsem);
540c801c 3414 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3415 up_write(&ctrl->namespaces_rwsem);
5955be21 3416}
5bae7f73 3417
32f0c4af
KB		 3418/*
3419 * This function iterates the namespace list unlocked to allow recovery from
3420 * controller failure. It is up to the caller to ensure the namespace list is
3421 * not modified by scan work while this function is executing.
3422 */
5bae7f73
CH		 3423void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3424{
3425 struct nvme_ns *ns, *next;
6f8e0d78 3426 LIST_HEAD(ns_list);
5bae7f73 3427
f6c8e432
SG		 3428 /* prevent racing with ns scanning */
3429 flush_work(&ctrl->scan_work);
3430
0ff9d4e1
KB		 3431 /*
3432 * The dead states indicates the controller was not gracefully
3433 * disconnected. In that case, we won't be able to flush any data while
3434 * removing the namespaces' disks; fail all the queues now to avoid
3435 * potentially having to clean up the failed sync later.
3436 */
3437 if (ctrl->state == NVME_CTRL_DEAD)
3438 nvme_kill_queues(ctrl);
3439
765cc031 3440 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3441 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3442 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3443
3444 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3445 nvme_ns_remove(ns);
3446}
576d55d6 3447EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3448
e3d7874d
KB		 3449static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3450{
3451 char *envp[2] = { NULL, NULL };
3452 u32 aen_result = ctrl->aen_result;
3453
3454 ctrl->aen_result = 0;
3455 if (!aen_result)
3456 return;
3457
3458 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3459 if (!envp[0])
3460 return;
3461 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3462 kfree(envp[0]);
3463}
3464
f866fc42
CH		 3465static void nvme_async_event_work(struct work_struct *work)
3466{
3467 struct nvme_ctrl *ctrl =
3468 container_of(work, struct nvme_ctrl, async_event_work);
3469
e3d7874d 3470 nvme_aen_uevent(ctrl);
ad22c355 3471 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3472}
3473
b6dccf7f
AD		 3474static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3475{
3476
3477 u32 csts;
3478
3479 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3480 return false;
3481
3482 if (csts == ~0)
3483 return false;
3484
3485 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3486}
3487
3488static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3489{
b6dccf7f
AD		 3490 struct nvme_fw_slot_info_log *log;
3491
3492 log = kmalloc(sizeof(*log), GFP_KERNEL);
3493 if (!log)
3494 return;
3495
0e98719b
CH		 3496 if (nvme_get_log(ctrl, NVME_NSID_ALL, 0, NVME_LOG_FW_SLOT, log,
3497 sizeof(*log), 0))
3498 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
b6dccf7f
AD		 3499 kfree(log);
3500}
3501
3502static void nvme_fw_act_work(struct work_struct *work)
3503{
3504 struct nvme_ctrl *ctrl = container_of(work,
3505 struct nvme_ctrl, fw_act_work);
3506 unsigned long fw_act_timeout;
3507
3508 if (ctrl->mtfa)
3509 fw_act_timeout = jiffies +
3510 msecs_to_jiffies(ctrl->mtfa * 100);
3511 else
3512 fw_act_timeout = jiffies +
3513 msecs_to_jiffies(admin_timeout * 1000);
3514
3515 nvme_stop_queues(ctrl);
3516 while (nvme_ctrl_pp_status(ctrl)) {
3517 if (time_after(jiffies, fw_act_timeout)) {
3518 dev_warn(ctrl->device,
3519 "Fw activation timeout, reset controller\n");
3520 nvme_reset_ctrl(ctrl);
3521 break;
3522 }
3523 msleep(100);
3524 }
3525
3526 if (ctrl->state != NVME_CTRL_LIVE)
3527 return;
3528
3529 nvme_start_queues(ctrl);
a806c6c8 3530 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3531 nvme_get_fw_slot_info(ctrl);
3532}
3533
868c2392
CH		 3534static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3535{
09bd1ff4
CK		 3536 u32 aer_notice_type = (result & 0xff00) >> 8;
3537
3538 switch (aer_notice_type) {
868c2392 3539 case NVME_AER_NOTICE_NS_CHANGED:
09bd1ff4 3540 trace_nvme_async_event(ctrl, aer_notice_type);
77016199 3541 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3542 nvme_queue_scan(ctrl);
3543 break;
3544 case NVME_AER_NOTICE_FW_ACT_STARTING:
09bd1ff4 3545 trace_nvme_async_event(ctrl, aer_notice_type);
868c2392
CH		 3546 queue_work(nvme_wq, &ctrl->fw_act_work);
3547 break;
0d0b660f
CH		 3548#ifdef CONFIG_NVME_MULTIPATH
3549 case NVME_AER_NOTICE_ANA:
09bd1ff4 3550 trace_nvme_async_event(ctrl, aer_notice_type);
0d0b660f
CH		 3551 if (!ctrl->ana_log_buf)
3552 break;
3553 queue_work(nvme_wq, &ctrl->ana_work);
3554 break;
3555#endif
868c2392
CH		 3556 default:
3557 dev_warn(ctrl->device, "async event result %08x\n", result);
3558 }
3559}
3560
7bf58533 3561void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3562 volatile union nvme_result *res)
f866fc42 3563{
7bf58533 3564 u32 result = le32_to_cpu(res->u32);
09bd1ff4 3565 u32 aer_type = result & 0x07;
f866fc42 3566
ad22c355 3567 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3568 return;
3569
09bd1ff4 3570 switch (aer_type) {
868c2392
CH		 3571 case NVME_AER_NOTICE:
3572 nvme_handle_aen_notice(ctrl, result);
3573 break;
e3d7874d
KB		 3574 case NVME_AER_ERROR:
3575 case NVME_AER_SMART:
3576 case NVME_AER_CSS:
3577 case NVME_AER_VS:
09bd1ff4 3578 trace_nvme_async_event(ctrl, aer_type);
e3d7874d 3579 ctrl->aen_result = result;
7bf58533
CH		 3580 break;
3581 default:
3582 break;
f866fc42 3583 }
c669ccdc 3584 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3585}
f866fc42 3586EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3587
d09f2b45 3588void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3589{
0d0b660f 3590 nvme_mpath_stop(ctrl);
d09f2b45 3591 nvme_stop_keep_alive(ctrl);
f866fc42 3592 flush_work(&ctrl->async_event_work);
b6dccf7f 3593 cancel_work_sync(&ctrl->fw_act_work);
b435ecea
NC		 3594 if (ctrl->ops->stop_ctrl)
3595 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 3596}
3597EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3598
3599void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3600{
3601 if (ctrl->kato)
3602 nvme_start_keep_alive(ctrl);
3603
3604 if (ctrl->queue_count > 1) {
3605 nvme_queue_scan(ctrl);
c0561f82 3606 nvme_enable_aen(ctrl);
d99ca609 3607 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3608 nvme_start_queues(ctrl);
3609 }
3610}
3611EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3612
d09f2b45
SG		 3613void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3614{
a6a5149b 3615 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3616}
576d55d6 3617EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3618
d22524a4 3619static void nvme_free_ctrl(struct device *dev)
53029b04 3620{
d22524a4
CH		 3621 struct nvme_ctrl *ctrl =
3622 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3623 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3624
9843f685 3625 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3626 kfree(ctrl->effects);
0d0b660f 3627 nvme_mpath_uninit(ctrl);
092ff052 3628 __free_page(ctrl->discard_page);
f3ca80fc 3629
ab9e00cc
CH		 3630 if (subsys) {
3631 mutex_lock(&subsys->lock);
3632 list_del(&ctrl->subsys_entry);
3633 mutex_unlock(&subsys->lock);
3634 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3635 }
f3ca80fc
CH		 3636
3637 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3638
ab9e00cc
CH		 3639 if (subsys)
3640 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3641}
3642
3643/*
3644 * Initialize a NVMe controller structures. This needs to be called during
3645 * earliest initialization so that we have the initialized structured around
3646 * during probing.
3647 */
3648int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3649 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3650{
3651 int ret;
3652
bb8d261e
CH		 3653 ctrl->state = NVME_CTRL_NEW;
3654 spin_lock_init(&ctrl->lock);
f3ca80fc 3655 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 3656 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 3657 ctrl->dev = dev;
3658 ctrl->ops = ops;
3659 ctrl->quirks = quirks;
5955be21 3660 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3661 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3662 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3663 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3664
230f1f9e
JS		 3665 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
3666 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
3667 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
3668
cb5b7262
JA		 3669 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
3670 PAGE_SIZE);
3671 ctrl->discard_page = alloc_page(GFP_KERNEL);
3672 if (!ctrl->discard_page) {
3673 ret = -ENOMEM;
3674 goto out;
3675 }
3676
9843f685
CH		 3677 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3678 if (ret < 0)
f3ca80fc 3679 goto out;
9843f685 3680 ctrl->instance = ret;
f3ca80fc 3681
d22524a4
CH		 3682 device_initialize(&ctrl->ctrl_device);
3683 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3684 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3685 ctrl->device->class = nvme_class;
3686 ctrl->device->parent = ctrl->dev;
3687 ctrl->device->groups = nvme_dev_attr_groups;
3688 ctrl->device->release = nvme_free_ctrl;
3689 dev_set_drvdata(ctrl->device, ctrl);
3690 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3691 if (ret)
f3ca80fc 3692 goto out_release_instance;
f3ca80fc 3693
a6a5149b
CH		 3694 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3695 ctrl->cdev.owner = ops->module;
3696 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3697 if (ret)
3698 goto out_free_name;
f3ca80fc 3699
c5552fde
AL		 3700 /*
3701 * Initialize latency tolerance controls. The sysfs files won't
3702 * be visible to userspace unless the device actually supports APST.
3703 */
3704 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3705 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3706 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3707
f3ca80fc 3708 return 0;
d22524a4 3709out_free_name:
d6a2b953 3710 kfree_const(ctrl->device->kobj.name);
f3ca80fc 3711out_release_instance:
9843f685 3712 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc 3713out:
cb5b7262
JA		 3714 if (ctrl->discard_page)
3715 __free_page(ctrl->discard_page);
f3ca80fc
CH		 3716 return ret;
3717}
576d55d6 3718EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3719
69d9a99c
KB		 3720/**
3721 * nvme_kill_queues(): Ends all namespace queues
3722 * @ctrl: the dead controller that needs to end
3723 *
3724 * Call this function when the driver determines it is unable to get the
3725 * controller in a state capable of servicing IO.
3726 */
3727void nvme_kill_queues(struct nvme_ctrl *ctrl)
3728{
3729 struct nvme_ns *ns;
3730
765cc031 3731 down_read(&ctrl->namespaces_rwsem);
82654b6b 3732
443bd90f 3733 /* Forcibly unquiesce queues to avoid blocking dispatch */
751a0cc0 3734 if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
7dd1ab16 3735 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3736
cf39a6bc
SB		 3737 list_for_each_entry(ns, &ctrl->namespaces, list)
3738 nvme_set_queue_dying(ns);
806f026f 3739
765cc031 3740 up_read(&ctrl->namespaces_rwsem);
69d9a99c 3741}
237045fc 3742EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3743
302ad8cc
KB		 3744void nvme_unfreeze(struct nvme_ctrl *ctrl)
3745{
3746 struct nvme_ns *ns;
3747
765cc031 3748 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3749 list_for_each_entry(ns, &ctrl->namespaces, list)
3750 blk_mq_unfreeze_queue(ns->queue);
765cc031 3751 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3752}
3753EXPORT_SYMBOL_GPL(nvme_unfreeze);
3754
3755void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3756{
3757 struct nvme_ns *ns;
3758
765cc031 3759 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3760 list_for_each_entry(ns, &ctrl->namespaces, list) {
3761 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3762 if (timeout <= 0)
3763 break;
3764 }
765cc031 3765 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3766}
3767EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3768
3769void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3770{
3771 struct nvme_ns *ns;
3772
765cc031 3773 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3774 list_for_each_entry(ns, &ctrl->namespaces, list)
3775 blk_mq_freeze_queue_wait(ns->queue);
765cc031 3776 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3777}
3778EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3779
3780void nvme_start_freeze(struct nvme_ctrl *ctrl)
3781{
3782 struct nvme_ns *ns;
3783
765cc031 3784 down_read(&ctrl->namespaces_rwsem);
302ad8cc 3785 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3786 blk_freeze_queue_start(ns->queue);
765cc031 3787 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3788}
3789EXPORT_SYMBOL_GPL(nvme_start_freeze);
3790
25646264 3791void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3792{
3793 struct nvme_ns *ns;
3794
765cc031 3795 down_read(&ctrl->namespaces_rwsem);
a6eaa884 3796 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3797 blk_mq_quiesce_queue(ns->queue);
765cc031 3798 up_read(&ctrl->namespaces_rwsem);
363c9aac 3799}
576d55d6 3800EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3801
25646264 3802void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3803{
3804 struct nvme_ns *ns;
3805
765cc031 3806 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 3807 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3808 blk_mq_unquiesce_queue(ns->queue);
765cc031 3809 up_read(&ctrl->namespaces_rwsem);
363c9aac 3810}
576d55d6 3811EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3812
5bae7f73
CH		 3813int __init nvme_core_init(void)
3814{
b227c59b 3815 int result = -ENOMEM;
5bae7f73 3816
9a6327d2
SG		 3817 nvme_wq = alloc_workqueue("nvme-wq",
3818 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3819 if (!nvme_wq)
b227c59b
RS		 3820 goto out;
3821
3822 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
3823 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3824 if (!nvme_reset_wq)
3825 goto destroy_wq;
3826
3827 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
3828 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3829 if (!nvme_delete_wq)
3830 goto destroy_reset_wq;
9a6327d2 3831
a6a5149b 3832 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3833 if (result < 0)
b227c59b 3834 goto destroy_delete_wq;
f3ca80fc
CH		 3835
3836 nvme_class = class_create(THIS_MODULE, "nvme");
3837 if (IS_ERR(nvme_class)) {
3838 result = PTR_ERR(nvme_class);
3839 goto unregister_chrdev;
3840 }
3841
ab9e00cc
CH		 3842 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3843 if (IS_ERR(nvme_subsys_class)) {
3844 result = PTR_ERR(nvme_subsys_class);
3845 goto destroy_class;
3846 }
5bae7f73 3847 return 0;
f3ca80fc 3848
ab9e00cc
CH		 3849destroy_class:
3850 class_destroy(nvme_class);
9a6327d2 3851unregister_chrdev:
a6a5149b 3852 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3853destroy_delete_wq:
3854 destroy_workqueue(nvme_delete_wq);
3855destroy_reset_wq:
3856 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 3857destroy_wq:
3858 destroy_workqueue(nvme_wq);
b227c59b 3859out:
f3ca80fc 3860 return result;
5bae7f73
CH		 3861}
3862
8eb5d89f 3863void __exit nvme_core_exit(void)
5bae7f73 3864{
ab9e00cc
CH		 3865 ida_destroy(&nvme_subsystems_ida);
3866 class_destroy(nvme_subsys_class);
f3ca80fc 3867 class_destroy(nvme_class);
a6a5149b 3868 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3869 destroy_workqueue(nvme_delete_wq);
3870 destroy_workqueue(nvme_reset_wq);
9a6327d2 3871 destroy_workqueue(nvme_wq);
5bae7f73 3872}
576d55d6
ML		 3873
3874MODULE_LICENSE("GPL");
3875MODULE_VERSION("1.0");
3876module_init(nvme_core_init);
3877module_exit(nvme_core_exit);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git