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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
a0a3408e 7#include <linux/aer.h>
18119775 8#include <linux/async.h>
b60503ba 9#include <linux/blkdev.h>
a4aea562 10#include <linux/blk-mq.h>
dca51e78 11#include <linux/blk-mq-pci.h>
ff5350a8 12#include <linux/dmi.h>
b60503ba
MW		 13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
b60503ba
MW		 16#include <linux/mm.h>
17#include <linux/module.h>
77bf25ea 18#include <linux/mutex.h>
d0877473 19#include <linux/once.h>
b60503ba 20#include <linux/pci.h>
d916b1be 21#include <linux/suspend.h>
e1e5e564 22#include <linux/t10-pi.h>
b60503ba 23#include <linux/types.h>
2f8e2c87 24#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 25#include <linux/sed-opal.h>
0f238ff5 26#include <linux/pci-p2pdma.h>
797a796a 27
604c01d5 28#include "trace.h"
f11bb3e2
CH		 29#include "nvme.h"
30
c1e0cc7e 31#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 32#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 33
a7a7cbe3 34#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 35
943e942e
JA		 36/*
37 * These can be higher, but we need to ensure that any command doesn't
38 * require an sg allocation that needs more than a page of data.
39 */
40#define NVME_MAX_KB_SZ 4096
41#define NVME_MAX_SEGS 127
42
58ffacb5
MW		 43static int use_threaded_interrupts;
44module_param(use_threaded_interrupts, int, 0);
45
8ffaadf7 46static bool use_cmb_sqes = true;
69f4eb9f 47module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 48MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49
87ad72a5
CH		 50static unsigned int max_host_mem_size_mb = 128;
51module_param(max_host_mem_size_mb, uint, 0444);
52MODULE_PARM_DESC(max_host_mem_size_mb,
53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 54
a7a7cbe3
CK		 55static unsigned int sgl_threshold = SZ_32K;
56module_param(sgl_threshold, uint, 0644);
57MODULE_PARM_DESC(sgl_threshold,
58 "Use SGLs when average request segment size is larger or equal to "
59 "this size. Use 0 to disable SGLs.");
60
b27c1e68 61static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62static const struct kernel_param_ops io_queue_depth_ops = {
63 .set = io_queue_depth_set,
64 .get = param_get_int,
65};
66
67static int io_queue_depth = 1024;
68module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70
3f68baf7
KB		 71static unsigned int write_queues;
72module_param(write_queues, uint, 0644);
3b6592f7
JA		 73MODULE_PARM_DESC(write_queues,
74 "Number of queues to use for writes. If not set, reads and writes "
75 "will share a queue set.");
76
3f68baf7
KB		 77static unsigned int poll_queues;
78module_param(poll_queues, uint, 0644);
4b04cc6a
JA		 79MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80
1c63dc66
CH		 81struct nvme_dev;
82struct nvme_queue;
b3fffdef 83
a5cdb68c 84static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 85static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 86
1c63dc66
CH		 87/*
88 * Represents an NVM Express device. Each nvme_dev is a PCI function.
89 */
90struct nvme_dev {
147b27e4 91 struct nvme_queue *queues;
1c63dc66
CH		 92 struct blk_mq_tag_set tagset;
93 struct blk_mq_tag_set admin_tagset;
94 u32 __iomem *dbs;
95 struct device *dev;
96 struct dma_pool *prp_page_pool;
97 struct dma_pool *prp_small_pool;
1c63dc66
CH		 98 unsigned online_queues;
99 unsigned max_qid;
e20ba6e1 100 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 101 unsigned int num_vecs;
1c63dc66 102 int q_depth;
c1e0cc7e 103 int io_sqes;
1c63dc66 104 u32 db_stride;
1c63dc66 105 void __iomem *bar;
97f6ef64 106 unsigned long bar_mapped_size;
5c8809e6 107 struct work_struct remove_work;
77bf25ea 108 struct mutex shutdown_lock;
1c63dc66 109 bool subsystem;
1c63dc66 110 u64 cmb_size;
0f238ff5 111 bool cmb_use_sqes;
1c63dc66 112 u32 cmbsz;
202021c1 113 u32 cmbloc;
1c63dc66 114 struct nvme_ctrl ctrl;
d916b1be 115 u32 last_ps;
87ad72a5 116
943e942e
JA		 117 mempool_t *iod_mempool;
118
87ad72a5 119 /* shadow doorbell buffer support: */
f9f38e33
HK		 120 u32 *dbbuf_dbs;
121 dma_addr_t dbbuf_dbs_dma_addr;
122 u32 *dbbuf_eis;
123 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 124
125 /* host memory buffer support: */
126 u64 host_mem_size;
127 u32 nr_host_mem_descs;
4033f35d 128 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 129 struct nvme_host_mem_buf_desc *host_mem_descs;
130 void **host_mem_desc_bufs;
4d115420 131};
1fa6aead 132
b27c1e68 133static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134{
135 int n = 0, ret;
136
137 ret = kstrtoint(val, 10, &n);
138 if (ret != 0 || n < 2)
139 return -EINVAL;
140
141 return param_set_int(val, kp);
142}
143
f9f38e33
HK		 144static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145{
146 return qid * 2 * stride;
147}
148
149static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150{
151 return (qid * 2 + 1) * stride;
152}
153
1c63dc66
CH		 154static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155{
156 return container_of(ctrl, struct nvme_dev, ctrl);
157}
158
b60503ba
MW		 159/*
160 * An NVM Express queue. Each device has at least two (one for admin
161 * commands and one for I/O commands).
162 */
163struct nvme_queue {
091b6092 164 struct nvme_dev *dev;
1ab0cd69 165 spinlock_t sq_lock;
c1e0cc7e 166 void *sq_cmds;
3a7afd8e
CH		 167 /* only used for poll queues: */
168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba
MW		 169 volatile struct nvme_completion *cqes;
170 dma_addr_t sq_dma_addr;
171 dma_addr_t cq_dma_addr;
b60503ba
MW		 172 u32 __iomem *q_db;
173 u16 q_depth;
7c349dde 174 u16 cq_vector;
b60503ba 175 u16 sq_tail;
04f3eafd 176 u16 last_sq_tail;
b60503ba 177 u16 cq_head;
c30341dc 178 u16 qid;
e9539f47 179 u8 cq_phase;
c1e0cc7e 180 u8 sqes;
4e224106
CH		 181 unsigned long flags;
182#define NVMEQ_ENABLED 0
63223078 183#define NVMEQ_SQ_CMB 1
d1ed6aa1 184#define NVMEQ_DELETE_ERROR 2
7c349dde 185#define NVMEQ_POLLED 3
f9f38e33
HK		 186 u32 *dbbuf_sq_db;
187 u32 *dbbuf_cq_db;
188 u32 *dbbuf_sq_ei;
189 u32 *dbbuf_cq_ei;
d1ed6aa1 190 struct completion delete_done;
b60503ba
MW		 191};
192
71bd150c 193/*
9b048119
CH		 194 * The nvme_iod describes the data in an I/O.
195 *
196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197 * to the actual struct scatterlist.
71bd150c
CH		 198 */
199struct nvme_iod {
d49187e9 200 struct nvme_request req;
f4800d6d 201 struct nvme_queue *nvmeq;
a7a7cbe3 202 bool use_sgl;
f4800d6d 203 int aborted;
71bd150c 204 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 205 int nents; /* Used in scatterlist */
71bd150c 206 dma_addr_t first_dma;
dff824b2 207 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 208 dma_addr_t meta_dma;
f4800d6d 209 struct scatterlist *sg;
b60503ba
MW		 210};
211
3b6592f7
JA		 212static unsigned int max_io_queues(void)
213{
4b04cc6a 214 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 215}
216
217static unsigned int max_queue_count(void)
218{
219 /* IO queues + admin queue */
220 return 1 + max_io_queues();
221}
222
f9f38e33
HK		 223static inline unsigned int nvme_dbbuf_size(u32 stride)
224{
3b6592f7 225 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 226}
227
228static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
229{
230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
231
232 if (dev->dbbuf_dbs)
233 return 0;
234
235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
236 &dev->dbbuf_dbs_dma_addr,
237 GFP_KERNEL);
238 if (!dev->dbbuf_dbs)
239 return -ENOMEM;
240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
241 &dev->dbbuf_eis_dma_addr,
242 GFP_KERNEL);
243 if (!dev->dbbuf_eis) {
244 dma_free_coherent(dev->dev, mem_size,
245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 dev->dbbuf_dbs = NULL;
247 return -ENOMEM;
248 }
249
250 return 0;
251}
252
253static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
254{
255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
256
257 if (dev->dbbuf_dbs) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
261 }
262 if (dev->dbbuf_eis) {
263 dma_free_coherent(dev->dev, mem_size,
264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
265 dev->dbbuf_eis = NULL;
266 }
267}
268
269static void nvme_dbbuf_init(struct nvme_dev *dev,
270 struct nvme_queue *nvmeq, int qid)
271{
272 if (!dev->dbbuf_dbs || !qid)
273 return;
274
275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
279}
280
281static void nvme_dbbuf_set(struct nvme_dev *dev)
282{
283 struct nvme_command c;
284
285 if (!dev->dbbuf_dbs)
286 return;
287
288 memset(&c, 0, sizeof(c));
289 c.dbbuf.opcode = nvme_admin_dbbuf;
290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
292
293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 295 /* Free memory and continue on */
296 nvme_dbbuf_dma_free(dev);
297 }
298}
299
300static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
301{
302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
303}
304
305/* Update dbbuf and return true if an MMIO is required */
306static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
307 volatile u32 *dbbuf_ei)
308{
309 if (dbbuf_db) {
310 u16 old_value;
311
312 /*
313 * Ensure that the queue is written before updating
314 * the doorbell in memory
315 */
316 wmb();
317
318 old_value = *dbbuf_db;
319 *dbbuf_db = value;
320
f1ed3df2
MW		 321 /*
322 * Ensure that the doorbell is updated before reading the event
323 * index from memory. The controller needs to provide similar
324 * ordering to ensure the envent index is updated before reading
325 * the doorbell.
326 */
327 mb();
328
f9f38e33
HK		 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
330 return false;
331 }
332
333 return true;
b60503ba
MW		 334}
335
ac3dd5bd
JA		 336/*
337 * Will slightly overestimate the number of pages needed. This is OK
338 * as it only leads to a small amount of wasted memory for the lifetime of
339 * the I/O.
340 */
341static int nvme_npages(unsigned size, struct nvme_dev *dev)
342{
5fd4ce1b
CH		 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
344 dev->ctrl.page_size);
ac3dd5bd
JA		 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
346}
347
a7a7cbe3
CK		 348/*
349 * Calculates the number of pages needed for the SGL segments. For example a 4k
350 * page can accommodate 256 SGL descriptors.
351 */
352static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 353{
a7a7cbe3 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 355}
ac3dd5bd 356
a7a7cbe3
CK		 357static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
358 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 359{
a7a7cbe3
CK		 360 size_t alloc_size;
361
362 if (use_sgl)
363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
364 else
365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
366
367 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 368}
ac3dd5bd 369
a4aea562
MB		 370static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
371 unsigned int hctx_idx)
e85248e5 372{
a4aea562 373 struct nvme_dev *dev = data;
147b27e4 374 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 375
42483228
KB		 376 WARN_ON(hctx_idx != 0);
377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 378
a4aea562
MB		 379 hctx->driver_data = nvmeq;
380 return 0;
e85248e5
MW		 381}
382
a4aea562
MB		 383static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384 unsigned int hctx_idx)
b60503ba 385{
a4aea562 386 struct nvme_dev *dev = data;
147b27e4 387 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 388
42483228 389 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 390 hctx->driver_data = nvmeq;
391 return 0;
b60503ba
MW		 392}
393
d6296d39
CH		 394static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
395 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 396{
d6296d39 397 struct nvme_dev *dev = set->driver_data;
f4800d6d 398 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 399 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 400 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 401
402 BUG_ON(!nvmeq);
f4800d6d 403 iod->nvmeq = nvmeq;
59e29ce6
SG		 404
405 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 406 return 0;
407}
408
3b6592f7
JA		 409static int queue_irq_offset(struct nvme_dev *dev)
410{
411 /* if we have more than 1 vec, admin queue offsets us by 1 */
412 if (dev->num_vecs > 1)
413 return 1;
414
415 return 0;
416}
417
dca51e78
CH		 418static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
419{
420 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 421 int i, qoff, offset;
422
423 offset = queue_irq_offset(dev);
424 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
425 struct blk_mq_queue_map *map = &set->map[i];
426
427 map->nr_queues = dev->io_queues[i];
428 if (!map->nr_queues) {
e20ba6e1 429 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 430 continue;
3b6592f7
JA		 431 }
432
4b04cc6a
JA		 433 /*
434 * The poll queue(s) doesn't have an IRQ (and hence IRQ
435 * affinity), so use the regular blk-mq cpu mapping
436 */
3b6592f7 437 map->queue_offset = qoff;
cb9e0e50 438 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 439 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
440 else
441 blk_mq_map_queues(map);
3b6592f7
JA		 442 qoff += map->nr_queues;
443 offset += map->nr_queues;
444 }
445
446 return 0;
dca51e78
CH		 447}
448
04f3eafd
JA		 449/*
450 * Write sq tail if we are asked to, or if the next command would wrap.
451 */
452static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
453{
454 if (!write_sq) {
455 u16 next_tail = nvmeq->sq_tail + 1;
456
457 if (next_tail == nvmeq->q_depth)
458 next_tail = 0;
459 if (next_tail != nvmeq->last_sq_tail)
460 return;
461 }
462
463 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
464 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
465 writel(nvmeq->sq_tail, nvmeq->q_db);
466 nvmeq->last_sq_tail = nvmeq->sq_tail;
467}
468
b60503ba 469/**
90ea5ca4 470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 471 * @nvmeq: The queue to use
472 * @cmd: The command to send
04f3eafd 473 * @write_sq: whether to write to the SQ doorbell
b60503ba 474 */
04f3eafd
JA		 475static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
476 bool write_sq)
b60503ba 477{
90ea5ca4 478 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 479 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
480 cmd, sizeof(*cmd));
90ea5ca4
CH		 481 if (++nvmeq->sq_tail == nvmeq->q_depth)
482 nvmeq->sq_tail = 0;
04f3eafd
JA		 483 nvme_write_sq_db(nvmeq, write_sq);
484 spin_unlock(&nvmeq->sq_lock);
485}
486
487static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
488{
489 struct nvme_queue *nvmeq = hctx->driver_data;
490
491 spin_lock(&nvmeq->sq_lock);
492 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
493 nvme_write_sq_db(nvmeq, true);
90ea5ca4 494 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 495}
496
a7a7cbe3 497static void **nvme_pci_iod_list(struct request *req)
b60503ba 498{
f4800d6d 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 500 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 501}
502
955b1b5a
MI		 503static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
504{
505 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 506 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 507 unsigned int avg_seg_size;
508
20469a37
KB		 509 if (nseg == 0)
510 return false;
511
512 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 513
514 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
515 return false;
516 if (!iod->nvmeq->qid)
517 return false;
518 if (!sgl_threshold || avg_seg_size < sgl_threshold)
519 return false;
520 return true;
521}
522
7fe07d14 523static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 524{
f4800d6d 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 526 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
527 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 528 int i;
eca18b23 529
dff824b2 530 if (iod->dma_len) {
f2fa006f
IR		 531 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
532 rq_dma_dir(req));
dff824b2 533 return;
7fe07d14
CH		 534 }
535
dff824b2
CH		 536 WARN_ON_ONCE(!iod->nents);
537
7f73eac3
LG		 538 if (is_pci_p2pdma_page(sg_page(iod->sg)))
539 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
540 rq_dma_dir(req));
541 else
dff824b2
CH		 542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
543
544
eca18b23 545 if (iod->npages == 0)
a7a7cbe3
CK		 546 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
547 dma_addr);
548
eca18b23 549 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 550 void *addr = nvme_pci_iod_list(req)[i];
551
552 if (iod->use_sgl) {
553 struct nvme_sgl_desc *sg_list = addr;
554
555 next_dma_addr =
556 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
557 } else {
558 __le64 *prp_list = addr;
559
560 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
561 }
562
563 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
564 dma_addr = next_dma_addr;
eca18b23 565 }
ac3dd5bd 566
d43f1ccf 567 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 568}
569
d0877473
KB		 570static void nvme_print_sgl(struct scatterlist *sgl, int nents)
571{
572 int i;
573 struct scatterlist *sg;
574
575 for_each_sg(sgl, sg, nents, i) {
576 dma_addr_t phys = sg_phys(sg);
577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
578 "dma_address:%pad dma_length:%d\n",
579 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
580 sg_dma_len(sg));
581 }
582}
583
a7a7cbe3
CK		 584static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
585 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 586{
f4800d6d 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 588 struct dma_pool *pool;
b131c61d 589 int length = blk_rq_payload_bytes(req);
eca18b23 590 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 591 int dma_len = sg_dma_len(sg);
592 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 593 u32 page_size = dev->ctrl.page_size;
f137e0f1 594 int offset = dma_addr & (page_size - 1);
e025344c 595 __le64 *prp_list;
a7a7cbe3 596 void **list = nvme_pci_iod_list(req);
e025344c 597 dma_addr_t prp_dma;
eca18b23 598 int nprps, i;
ff22b54f 599
1d090624 600 length -= (page_size - offset);
5228b328
JS		 601 if (length <= 0) {
602 iod->first_dma = 0;
a7a7cbe3 603 goto done;
5228b328 604 }
ff22b54f 605
1d090624 606 dma_len -= (page_size - offset);
ff22b54f 607 if (dma_len) {
1d090624 608 dma_addr += (page_size - offset);
ff22b54f
MW		 609 } else {
610 sg = sg_next(sg);
611 dma_addr = sg_dma_address(sg);
612 dma_len = sg_dma_len(sg);
613 }
614
1d090624 615 if (length <= page_size) {
edd10d33 616 iod->first_dma = dma_addr;
a7a7cbe3 617 goto done;
e025344c
SMM		 618 }
619
1d090624 620 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 621 if (nprps <= (256 / 8)) {
622 pool = dev->prp_small_pool;
eca18b23 623 iod->npages = 0;
99802a7a
MW		 624 } else {
625 pool = dev->prp_page_pool;
eca18b23 626 iod->npages = 1;
99802a7a
MW		 627 }
628
69d2b571 629 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 630 if (!prp_list) {
edd10d33 631 iod->first_dma = dma_addr;
eca18b23 632 iod->npages = -1;
86eea289 633 return BLK_STS_RESOURCE;
b77954cb 634 }
eca18b23
MW		 635 list[0] = prp_list;
636 iod->first_dma = prp_dma;
e025344c
SMM		 637 i = 0;
638 for (;;) {
1d090624 639 if (i == page_size >> 3) {
e025344c 640 __le64 *old_prp_list = prp_list;
69d2b571 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 642 if (!prp_list)
86eea289 643 return BLK_STS_RESOURCE;
eca18b23 644 list[iod->npages++] = prp_list;
7523d834
MW		 645 prp_list[0] = old_prp_list[i - 1];
646 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
647 i = 1;
e025344c
SMM		 648 }
649 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 650 dma_len -= page_size;
651 dma_addr += page_size;
652 length -= page_size;
e025344c
SMM		 653 if (length <= 0)
654 break;
655 if (dma_len > 0)
656 continue;
86eea289
KB		 657 if (unlikely(dma_len < 0))
658 goto bad_sgl;
e025344c
SMM		 659 sg = sg_next(sg);
660 dma_addr = sg_dma_address(sg);
661 dma_len = sg_dma_len(sg);
ff22b54f
MW		 662 }
663
a7a7cbe3
CK		 664done:
665 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
666 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
667
86eea289
KB		 668 return BLK_STS_OK;
669
670 bad_sgl:
d0877473
KB		 671 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
672 "Invalid SGL for payload:%d nents:%d\n",
673 blk_rq_payload_bytes(req), iod->nents);
86eea289 674 return BLK_STS_IOERR;
ff22b54f
MW		 675}
676
a7a7cbe3
CK		 677static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
678 struct scatterlist *sg)
679{
680 sge->addr = cpu_to_le64(sg_dma_address(sg));
681 sge->length = cpu_to_le32(sg_dma_len(sg));
682 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
683}
684
685static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
686 dma_addr_t dma_addr, int entries)
687{
688 sge->addr = cpu_to_le64(dma_addr);
689 if (entries < SGES_PER_PAGE) {
690 sge->length = cpu_to_le32(entries * sizeof(*sge));
691 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
692 } else {
693 sge->length = cpu_to_le32(PAGE_SIZE);
694 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
695 }
696}
697
698static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 699 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 700{
701 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 702 struct dma_pool *pool;
703 struct nvme_sgl_desc *sg_list;
704 struct scatterlist *sg = iod->sg;
a7a7cbe3 705 dma_addr_t sgl_dma;
b0f2853b 706 int i = 0;
a7a7cbe3 707
a7a7cbe3
CK		 708 /* setting the transfer type as SGL */
709 cmd->flags = NVME_CMD_SGL_METABUF;
710
b0f2853b 711 if (entries == 1) {
a7a7cbe3
CK		 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
713 return BLK_STS_OK;
714 }
715
716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
717 pool = dev->prp_small_pool;
718 iod->npages = 0;
719 } else {
720 pool = dev->prp_page_pool;
721 iod->npages = 1;
722 }
723
724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
725 if (!sg_list) {
726 iod->npages = -1;
727 return BLK_STS_RESOURCE;
728 }
729
730 nvme_pci_iod_list(req)[0] = sg_list;
731 iod->first_dma = sgl_dma;
732
733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
734
735 do {
736 if (i == SGES_PER_PAGE) {
737 struct nvme_sgl_desc *old_sg_desc = sg_list;
738 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
739
740 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
741 if (!sg_list)
742 return BLK_STS_RESOURCE;
743
744 i = 0;
745 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
746 sg_list[i++] = *link;
747 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
748 }
749
750 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 751 sg = sg_next(sg);
b0f2853b 752 } while (--entries > 0);
a7a7cbe3 753
a7a7cbe3
CK		 754 return BLK_STS_OK;
755}
756
dff824b2
CH		 757static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
758 struct request *req, struct nvme_rw_command *cmnd,
759 struct bio_vec *bv)
760{
761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4f40484
KH		 762 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
763 unsigned int first_prp_len = dev->ctrl.page_size - offset;
dff824b2
CH		 764
765 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
766 if (dma_mapping_error(dev->dev, iod->first_dma))
767 return BLK_STS_RESOURCE;
768 iod->dma_len = bv->bv_len;
769
770 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
771 if (bv->bv_len > first_prp_len)
772 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
773 return 0;
774}
775
29791057
CH		 776static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
777 struct request *req, struct nvme_rw_command *cmnd,
778 struct bio_vec *bv)
779{
780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
781
782 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
783 if (dma_mapping_error(dev->dev, iod->first_dma))
784 return BLK_STS_RESOURCE;
785 iod->dma_len = bv->bv_len;
786
049bf372 787 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 788 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
789 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
790 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
791 return 0;
792}
793
fc17b653 794static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 795 struct nvme_command *cmnd)
d29ec824 796{
f4800d6d 797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 798 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 799 int nr_mapped;
d29ec824 800
dff824b2
CH		 801 if (blk_rq_nr_phys_segments(req) == 1) {
802 struct bio_vec bv = req_bvec(req);
803
804 if (!is_pci_p2pdma_page(bv.bv_page)) {
805 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
806 return nvme_setup_prp_simple(dev, req,
807 &cmnd->rw, &bv);
29791057
CH		 808
809 if (iod->nvmeq->qid &&
810 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
811 return nvme_setup_sgl_simple(dev, req,
812 &cmnd->rw, &bv);
dff824b2
CH		 813 }
814 }
815
816 iod->dma_len = 0;
d43f1ccf
CH		 817 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
818 if (!iod->sg)
819 return BLK_STS_RESOURCE;
f9d03f96 820 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 821 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 822 if (!iod->nents)
823 goto out;
d29ec824 824
e0596ab2 825 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 826 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
827 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 828 else
829 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 830 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 831 if (!nr_mapped)
ba1ca37e 832 goto out;
d29ec824 833
70479b71 834 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 835 if (iod->use_sgl)
b0f2853b 836 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 837 else
838 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 839out:
86eea289 840 if (ret != BLK_STS_OK)
4aedb705
CH		 841 nvme_unmap_data(dev, req);
842 return ret;
843}
3045c0d0 844
4aedb705
CH		 845static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
846 struct nvme_command *cmnd)
847{
848 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 849
4aedb705
CH		 850 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
851 rq_dma_dir(req), 0);
852 if (dma_mapping_error(dev->dev, iod->meta_dma))
853 return BLK_STS_IOERR;
854 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
855 return 0;
00df5cb4
MW		 856}
857
d29ec824
CH		 858/*
859 * NOTE: ns is NULL when called on the admin queue.
860 */
fc17b653 861static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 862 const struct blk_mq_queue_data *bd)
edd10d33 863{
a4aea562
MB		 864 struct nvme_ns *ns = hctx->queue->queuedata;
865 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 866 struct nvme_dev *dev = nvmeq->dev;
a4aea562 867 struct request *req = bd->rq;
9b048119 868 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 869 struct nvme_command cmnd;
ebe6d874 870 blk_status_t ret;
e1e5e564 871
9b048119
CH		 872 iod->aborted = 0;
873 iod->npages = -1;
874 iod->nents = 0;
875
d1f06f4a
JA		 876 /*
877 * We should not need to do this, but we're still using this to
878 * ensure we can drain requests on a dying queue.
879 */
4e224106 880 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 881 return BLK_STS_IOERR;
882
f9d03f96 883 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 884 if (ret)
f4800d6d 885 return ret;
a4aea562 886
fc17b653 887 if (blk_rq_nr_phys_segments(req)) {
b131c61d 888 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 889 if (ret)
9b048119 890 goto out_free_cmd;
fc17b653 891 }
a4aea562 892
4aedb705
CH		 893 if (blk_integrity_rq(req)) {
894 ret = nvme_map_metadata(dev, req, &cmnd);
895 if (ret)
896 goto out_unmap_data;
897 }
898
aae239e1 899 blk_mq_start_request(req);
04f3eafd 900 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 901 return BLK_STS_OK;
4aedb705
CH		 902out_unmap_data:
903 nvme_unmap_data(dev, req);
f9d03f96
CH		 904out_free_cmd:
905 nvme_cleanup_cmd(req);
ba1ca37e 906 return ret;
b60503ba 907}
e1e5e564 908
77f02a7a 909static void nvme_pci_complete_rq(struct request *req)
eee417b0 910{
f4800d6d 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 912 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 913
4aedb705
CH		 914 if (blk_integrity_rq(req))
915 dma_unmap_page(dev->dev, iod->meta_dma,
916 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 917 if (blk_rq_nr_phys_segments(req))
4aedb705 918 nvme_unmap_data(dev, req);
77f02a7a 919 nvme_complete_rq(req);
b60503ba
MW		 920}
921
d783e0bd 922/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 923static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 924{
750dde44
CH		 925 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
926 nvmeq->cq_phase;
d783e0bd
MR		 927}
928
eb281c82 929static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 930{
eb281c82 931 u16 head = nvmeq->cq_head;
adf68f21 932
397c699f
KB		 933 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
934 nvmeq->dbbuf_cq_ei))
935 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 936}
aae239e1 937
cfa27356
CH		 938static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
939{
940 if (!nvmeq->qid)
941 return nvmeq->dev->admin_tagset.tags[0];
942 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
943}
944
5cb525c8 945static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 946{
5cb525c8 947 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 948 struct request *req;
adf68f21 949
83a12fb7
SG		 950 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
951 dev_warn(nvmeq->dev->ctrl.device,
952 "invalid id %d completed on queue %d\n",
953 cqe->command_id, le16_to_cpu(cqe->sq_id));
954 return;
b60503ba
MW		 955 }
956
83a12fb7
SG		 957 /*
958 * AEN requests are special as they don't time out and can
959 * survive any kind of queue freeze and often don't respond to
960 * aborts. We don't even bother to allocate a struct request
961 * for them but rather special case them here.
962 */
58a8df67 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 964 nvme_complete_async_event(&nvmeq->dev->ctrl,
965 cqe->status, &cqe->result);
a0fa9647 966 return;
83a12fb7 967 }
b60503ba 968
cfa27356 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
604c01d5 970 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 971 nvme_end_request(req, cqe->status, cqe->result);
972}
b60503ba 973
5cb525c8
JA		 974static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
975{
a8de6639
AD		 976 u16 tmp = nvmeq->cq_head + 1;
977
978 if (tmp == nvmeq->q_depth) {
5cb525c8 979 nvmeq->cq_head = 0;
e2a366a4 980 nvmeq->cq_phase ^= 1;
a8de6639
AD		 981 } else {
982 nvmeq->cq_head = tmp;
b60503ba 983 }
a0fa9647
JA		 984}
985
324b494c 986static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 987{
1052b8ac 988 int found = 0;
b60503ba 989
1052b8ac 990 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 991 found++;
b69e2ef2
KB		 992 /*
993 * load-load control dependency between phase and the rest of
994 * the cqe requires a full read memory barrier
995 */
996 dma_rmb();
324b494c 997 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 998 nvme_update_cq_head(nvmeq);
920d13a8 999 }
eb281c82 1000
324b494c 1001 if (found)
920d13a8 1002 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1003 return found;
b60503ba
MW		 1004}
1005
1006static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1007{
58ffacb5 1008 struct nvme_queue *nvmeq = data;
68fa9dbe 1009 irqreturn_t ret = IRQ_NONE;
5cb525c8 1010
3a7afd8e
CH		 1011 /*
1012 * The rmb/wmb pair ensures we see all updates from a previous run of
1013 * the irq handler, even if that was on another CPU.
1014 */
1015 rmb();
324b494c
KB		 1016 if (nvme_process_cq(nvmeq))
1017 ret = IRQ_HANDLED;
3a7afd8e 1018 wmb();
5cb525c8 1019
68fa9dbe 1020 return ret;
58ffacb5
MW		 1021}
1022
1023static irqreturn_t nvme_irq_check(int irq, void *data)
1024{
1025 struct nvme_queue *nvmeq = data;
750dde44 1026 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1027 return IRQ_WAKE_THREAD;
1028 return IRQ_NONE;
58ffacb5
MW		 1029}
1030
0b2a8a9f 1031/*
fa059b85 1032 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1033 * Can be called from any context.
1034 */
fa059b85 1035static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1036{
3a7afd8e 1037 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1038
fa059b85 1039 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1040
fa059b85
KB		 1041 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1042 nvme_process_cq(nvmeq);
1043 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1044}
1045
9743139c 1046static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1047{
1048 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1049 bool found;
1050
1051 if (!nvme_cqe_pending(nvmeq))
1052 return 0;
1053
3a7afd8e 1054 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1055 found = nvme_process_cq(nvmeq);
3a7afd8e 1056 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1057
dabcefab
JA		 1058 return found;
1059}
1060
ad22c355 1061static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1062{
f866fc42 1063 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1064 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1065 struct nvme_command c;
b60503ba 1066
a4aea562
MB		 1067 memset(&c, 0, sizeof(c));
1068 c.common.opcode = nvme_admin_async_event;
ad22c355 1069 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1070 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1071}
1072
b60503ba 1073static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1074{
b60503ba
MW		 1075 struct nvme_command c;
1076
1077 memset(&c, 0, sizeof(c));
1078 c.delete_queue.opcode = opcode;
1079 c.delete_queue.qid = cpu_to_le16(id);
1080
1c63dc66 1081 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1082}
1083
b60503ba 1084static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1085 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1086{
b60503ba 1087 struct nvme_command c;
4b04cc6a
JA		 1088 int flags = NVME_QUEUE_PHYS_CONTIG;
1089
7c349dde 1090 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1091 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1092
d29ec824 1093 /*
16772ae6 1094 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1095 * is attached to the request.
1096 */
b60503ba
MW		 1097 memset(&c, 0, sizeof(c));
1098 c.create_cq.opcode = nvme_admin_create_cq;
1099 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1100 c.create_cq.cqid = cpu_to_le16(qid);
1101 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1102 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1103 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1104
1c63dc66 1105 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1106}
1107
1108static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1109 struct nvme_queue *nvmeq)
1110{
9abd68ef 1111 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1112 struct nvme_command c;
81c1cd98 1113 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1114
9abd68ef
JA		 1115 /*
1116 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1117 * set. Since URGENT priority is zeroes, it makes all queues
1118 * URGENT.
1119 */
1120 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1121 flags |= NVME_SQ_PRIO_MEDIUM;
1122
d29ec824 1123 /*
16772ae6 1124 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1125 * is attached to the request.
1126 */
b60503ba
MW		 1127 memset(&c, 0, sizeof(c));
1128 c.create_sq.opcode = nvme_admin_create_sq;
1129 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1130 c.create_sq.sqid = cpu_to_le16(qid);
1131 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1132 c.create_sq.sq_flags = cpu_to_le16(flags);
1133 c.create_sq.cqid = cpu_to_le16(qid);
1134
1c63dc66 1135 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1136}
1137
1138static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1139{
1140 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1141}
1142
1143static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1144{
1145 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1146}
1147
2a842aca 1148static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1149{
f4800d6d
CH		 1150 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1151 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1152
27fa9bc5
CH		 1153 dev_warn(nvmeq->dev->ctrl.device,
1154 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1155 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1156 blk_mq_free_request(req);
bc5fc7e4
MW		 1157}
1158
b2a0eb1a
KB		 1159static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1160{
1161
1162 /* If true, indicates loss of adapter communication, possibly by a
1163 * NVMe Subsystem reset.
1164 */
1165 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1166
ad70062c
JW		 1167 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1168 switch (dev->ctrl.state) {
1169 case NVME_CTRL_RESETTING:
ad6a0a52 1170 case NVME_CTRL_CONNECTING:
b2a0eb1a 1171 return false;
ad70062c
JW		 1172 default:
1173 break;
1174 }
b2a0eb1a
KB		 1175
1176 /* We shouldn't reset unless the controller is on fatal error state
1177 * _or_ if we lost the communication with it.
1178 */
1179 if (!(csts & NVME_CSTS_CFS) && !nssro)
1180 return false;
1181
b2a0eb1a
KB		 1182 return true;
1183}
1184
1185static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1186{
1187 /* Read a config register to help see what died. */
1188 u16 pci_status;
1189 int result;
1190
1191 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1192 &pci_status);
1193 if (result == PCIBIOS_SUCCESSFUL)
1194 dev_warn(dev->ctrl.device,
1195 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1196 csts, pci_status);
1197 else
1198 dev_warn(dev->ctrl.device,
1199 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1200 csts, result);
1201}
1202
31c7c7d2 1203static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1204{
f4800d6d
CH		 1205 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1206 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1207 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1208 struct request *abort_req;
a4aea562 1209 struct nvme_command cmd;
b2a0eb1a
KB		 1210 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1211
651438bb
WX		 1212 /* If PCI error recovery process is happening, we cannot reset or
1213 * the recovery mechanism will surely fail.
1214 */
1215 mb();
1216 if (pci_channel_offline(to_pci_dev(dev->dev)))
1217 return BLK_EH_RESET_TIMER;
1218
b2a0eb1a
KB		 1219 /*
1220 * Reset immediately if the controller is failed
1221 */
1222 if (nvme_should_reset(dev, csts)) {
1223 nvme_warn_reset(dev, csts);
1224 nvme_dev_disable(dev, false);
d86c4d8e 1225 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1226 return BLK_EH_DONE;
b2a0eb1a 1227 }
c30341dc 1228
7776db1c
KB		 1229 /*
1230 * Did we miss an interrupt?
1231 */
fa059b85
KB		 1232 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1233 nvme_poll(req->mq_hctx);
1234 else
1235 nvme_poll_irqdisable(nvmeq);
1236
bf392a5d 1237 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1238 dev_warn(dev->ctrl.device,
1239 "I/O %d QID %d timeout, completion polled\n",
1240 req->tag, nvmeq->qid);
db8c48e4 1241 return BLK_EH_DONE;
7776db1c
KB		 1242 }
1243
31c7c7d2 1244 /*
fd634f41
CH		 1245 * Shutdown immediately if controller times out while starting. The
1246 * reset work will see the pci device disabled when it gets the forced
1247 * cancellation error. All outstanding requests are completed on
db8c48e4 1248 * shutdown, so we return BLK_EH_DONE.
fd634f41 1249 */
4244140d
KB		 1250 switch (dev->ctrl.state) {
1251 case NVME_CTRL_CONNECTING:
2036f726
KB		 1252 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1253 /* fall through */
1254 case NVME_CTRL_DELETING:
b9cac43c 1255 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1256 "I/O %d QID %d timeout, disable controller\n",
1257 req->tag, nvmeq->qid);
2036f726 1258 nvme_dev_disable(dev, true);
27fa9bc5 1259 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1260 return BLK_EH_DONE;
39a9dd81
KB		 1261 case NVME_CTRL_RESETTING:
1262 return BLK_EH_RESET_TIMER;
4244140d
KB		 1263 default:
1264 break;
c30341dc
KB		 1265 }
1266
fd634f41
CH		 1267 /*
1268 * Shutdown the controller immediately and schedule a reset if the
1269 * command was already aborted once before and still hasn't been
1270 * returned to the driver, or if this is the admin queue.
31c7c7d2 1271 */
f4800d6d 1272 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1273 dev_warn(dev->ctrl.device,
e1569a16
KB		 1274 "I/O %d QID %d timeout, reset controller\n",
1275 req->tag, nvmeq->qid);
a5cdb68c 1276 nvme_dev_disable(dev, false);
d86c4d8e 1277 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1278
27fa9bc5 1279 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1280 return BLK_EH_DONE;
c30341dc 1281 }
c30341dc 1282
e7a2a87d 1283 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1284 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1285 return BLK_EH_RESET_TIMER;
6bf25d16 1286 }
7bf7d778 1287 iod->aborted = 1;
a4aea562 1288
c30341dc
KB		 1289 memset(&cmd, 0, sizeof(cmd));
1290 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1291 cmd.abort.cid = req->tag;
c30341dc 1292 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1293
1b3c47c1
SG		 1294 dev_warn(nvmeq->dev->ctrl.device,
1295 "I/O %d QID %d timeout, aborting\n",
1296 req->tag, nvmeq->qid);
e7a2a87d
CH		 1297
1298 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1299 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1300 if (IS_ERR(abort_req)) {
1301 atomic_inc(&dev->ctrl.abort_limit);
1302 return BLK_EH_RESET_TIMER;
1303 }
1304
1305 abort_req->timeout = ADMIN_TIMEOUT;
1306 abort_req->end_io_data = NULL;
1307 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1308
31c7c7d2
CH		 1309 /*
1310 * The aborted req will be completed on receiving the abort req.
1311 * We enable the timer again. If hit twice, it'll cause a device reset,
1312 * as the device then is in a faulty state.
1313 */
1314 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1315}
1316
a4aea562
MB		 1317static void nvme_free_queue(struct nvme_queue *nvmeq)
1318{
8a1d09a6 1319 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1320 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1321 if (!nvmeq->sq_cmds)
1322 return;
0f238ff5 1323
63223078 1324 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1325 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1326 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1327 } else {
8a1d09a6 1328 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1329 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1330 }
9e866774
MW		 1331}
1332
a1a5ef99 1333static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1334{
1335 int i;
1336
d858e5f0 1337 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1338 dev->ctrl.queue_count--;
147b27e4 1339 nvme_free_queue(&dev->queues[i]);
121c7ad4 1340 }
22404274
KB		 1341}
1342
4d115420
KB		 1343/**
1344 * nvme_suspend_queue - put queue into suspended state
40581d1a 1345 * @nvmeq: queue to suspend
4d115420
KB		 1346 */
1347static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1348{
4e224106 1349 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1350 return 1;
a09115b2 1351
4e224106 1352 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1353 mb();
a09115b2 1354
4e224106 1355 nvmeq->dev->online_queues--;
1c63dc66 1356 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1357 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1358 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1359 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1360 return 0;
1361}
b60503ba 1362
8fae268b
KB		 1363static void nvme_suspend_io_queues(struct nvme_dev *dev)
1364{
1365 int i;
1366
1367 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1368 nvme_suspend_queue(&dev->queues[i]);
1369}
1370
a5cdb68c 1371static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1372{
147b27e4 1373 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1374
a5cdb68c
KB		 1375 if (shutdown)
1376 nvme_shutdown_ctrl(&dev->ctrl);
1377 else
b5b05048 1378 nvme_disable_ctrl(&dev->ctrl);
07836e65 1379
bf392a5d 1380 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1381}
1382
fa46c6fb
KB		 1383/*
1384 * Called only on a device that has been disabled and after all other threads
1385 * that can check this device's completion queues have synced. This is the
1386 * last chance for the driver to see a natural completion before
1387 * nvme_cancel_request() terminates all incomplete requests.
1388 */
1389static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1390{
fa46c6fb
KB		 1391 int i;
1392
324b494c
KB		 1393 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1394 nvme_process_cq(&dev->queues[i]);
fa46c6fb
KB		 1395}
1396
8ffaadf7
JD		 1397static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1398 int entry_size)
1399{
1400 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1401 unsigned q_size_aligned = roundup(q_depth * entry_size,
1402 dev->ctrl.page_size);
8ffaadf7
JD		 1403
1404 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1405 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1406 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1407 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1408
1409 /*
1410 * Ensure the reduced q_depth is above some threshold where it
1411 * would be better to map queues in system memory with the
1412 * original depth
1413 */
1414 if (q_depth < 64)
1415 return -ENOMEM;
1416 }
1417
1418 return q_depth;
1419}
1420
1421static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1422 int qid)
8ffaadf7 1423{
0f238ff5
LG		 1424 struct pci_dev *pdev = to_pci_dev(dev->dev);
1425
1426 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1427 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1428 if (nvmeq->sq_cmds) {
1429 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1430 nvmeq->sq_cmds);
1431 if (nvmeq->sq_dma_addr) {
1432 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1433 return 0;
1434 }
1435
8a1d09a6 1436 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1437 }
0f238ff5 1438 }
8ffaadf7 1439
8a1d09a6 1440 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1441 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1442 if (!nvmeq->sq_cmds)
1443 return -ENOMEM;
8ffaadf7
JD		 1444 return 0;
1445}
1446
a6ff7262 1447static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1448{
147b27e4 1449 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1450
62314e40
KB		 1451 if (dev->ctrl.queue_count > qid)
1452 return 0;
b60503ba 1453
c1e0cc7e 1454 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1455 nvmeq->q_depth = depth;
1456 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1457 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1458 if (!nvmeq->cqes)
1459 goto free_nvmeq;
b60503ba 1460
8a1d09a6 1461 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1462 goto free_cqdma;
1463
091b6092 1464 nvmeq->dev = dev;
1ab0cd69 1465 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1466 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1467 nvmeq->cq_head = 0;
82123460 1468 nvmeq->cq_phase = 1;
b80d5ccc 1469 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1470 nvmeq->qid = qid;
d858e5f0 1471 dev->ctrl.queue_count++;
36a7e993 1472
147b27e4 1473 return 0;
b60503ba
MW		 1474
1475 free_cqdma:
8a1d09a6
BH		 1476 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1477 nvmeq->cq_dma_addr);
b60503ba 1478 free_nvmeq:
147b27e4 1479 return -ENOMEM;
b60503ba
MW		 1480}
1481
dca51e78 1482static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1483{
0ff199cb
CH		 1484 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1485 int nr = nvmeq->dev->ctrl.instance;
1486
1487 if (use_threaded_interrupts) {
1488 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1489 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1490 } else {
1491 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1492 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1493 }
3001082c
MW		 1494}
1495
22404274 1496static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1497{
22404274 1498 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1499
22404274 1500 nvmeq->sq_tail = 0;
04f3eafd 1501 nvmeq->last_sq_tail = 0;
22404274
KB		 1502 nvmeq->cq_head = 0;
1503 nvmeq->cq_phase = 1;
b80d5ccc 1504 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1505 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1506 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1507 dev->online_queues++;
3a7afd8e 1508 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1509}
1510
4b04cc6a 1511static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1512{
1513 struct nvme_dev *dev = nvmeq->dev;
1514 int result;
7c349dde 1515 u16 vector = 0;
3f85d50b 1516
d1ed6aa1
CH		 1517 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1518
22b55601
KB		 1519 /*
1520 * A queue's vector matches the queue identifier unless the controller
1521 * has only one vector available.
1522 */
4b04cc6a
JA		 1523 if (!polled)
1524 vector = dev->num_vecs == 1 ? 0 : qid;
1525 else
7c349dde 1526 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1527
a8e3e0bb 1528 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1529 if (result)
1530 return result;
b60503ba
MW		 1531
1532 result = adapter_alloc_sq(dev, qid, nvmeq);
1533 if (result < 0)
ded45505 1534 return result;
c80b36cd 1535 if (result)
b60503ba
MW		 1536 goto release_cq;
1537
a8e3e0bb 1538 nvmeq->cq_vector = vector;
161b8be2 1539 nvme_init_queue(nvmeq, qid);
4b04cc6a 1540
7c349dde 1541 if (!polled) {
4b04cc6a
JA		 1542 result = queue_request_irq(nvmeq);
1543 if (result < 0)
1544 goto release_sq;
1545 }
b60503ba 1546
4e224106 1547 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1548 return result;
b60503ba 1549
a8e3e0bb 1550release_sq:
f25a2dfc 1551 dev->online_queues--;
b60503ba 1552 adapter_delete_sq(dev, qid);
a8e3e0bb 1553release_cq:
b60503ba 1554 adapter_delete_cq(dev, qid);
22404274 1555 return result;
b60503ba
MW		 1556}
1557
f363b089 1558static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1559 .queue_rq = nvme_queue_rq,
77f02a7a 1560 .complete = nvme_pci_complete_rq,
a4aea562 1561 .init_hctx = nvme_admin_init_hctx,
0350815a 1562 .init_request = nvme_init_request,
a4aea562
MB		 1563 .timeout = nvme_timeout,
1564};
1565
f363b089 1566static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1567 .queue_rq = nvme_queue_rq,
1568 .complete = nvme_pci_complete_rq,
1569 .commit_rqs = nvme_commit_rqs,
1570 .init_hctx = nvme_init_hctx,
1571 .init_request = nvme_init_request,
1572 .map_queues = nvme_pci_map_queues,
1573 .timeout = nvme_timeout,
1574 .poll = nvme_poll,
dabcefab
JA		 1575};
1576
ea191d2f
KB		 1577static void nvme_dev_remove_admin(struct nvme_dev *dev)
1578{
1c63dc66 1579 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1580 /*
1581 * If the controller was reset during removal, it's possible
1582 * user requests may be waiting on a stopped queue. Start the
1583 * queue to flush these to completion.
1584 */
c81545f9 1585 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1586 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1587 blk_mq_free_tag_set(&dev->admin_tagset);
1588 }
1589}
1590
a4aea562
MB		 1591static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1592{
1c63dc66 1593 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1594 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1595 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1596
38dabe21 1597 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1598 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1599 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
d43f1ccf 1600 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1601 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1602 dev->admin_tagset.driver_data = dev;
1603
1604 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1605 return -ENOMEM;
34b6c231 1606 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1607
1c63dc66
CH		 1608 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1609 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1610 blk_mq_free_tag_set(&dev->admin_tagset);
1611 return -ENOMEM;
1612 }
1c63dc66 1613 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1614 nvme_dev_remove_admin(dev);
1c63dc66 1615 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1616 return -ENODEV;
1617 }
0fb59cbc 1618 } else
c81545f9 1619 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1620
1621 return 0;
1622}
1623
97f6ef64
XY		 1624static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1625{
1626 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1627}
1628
1629static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1630{
1631 struct pci_dev *pdev = to_pci_dev(dev->dev);
1632
1633 if (size <= dev->bar_mapped_size)
1634 return 0;
1635 if (size > pci_resource_len(pdev, 0))
1636 return -ENOMEM;
1637 if (dev->bar)
1638 iounmap(dev->bar);
1639 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1640 if (!dev->bar) {
1641 dev->bar_mapped_size = 0;
1642 return -ENOMEM;
1643 }
1644 dev->bar_mapped_size = size;
1645 dev->dbs = dev->bar + NVME_REG_DBS;
1646
1647 return 0;
1648}
1649
01ad0990 1650static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1651{
ba47e386 1652 int result;
b60503ba
MW		 1653 u32 aqa;
1654 struct nvme_queue *nvmeq;
1655
97f6ef64
XY		 1656 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1657 if (result < 0)
1658 return result;
1659
8ef2074d 1660 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1661 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1662
7a67cbea
CH		 1663 if (dev->subsystem &&
1664 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1665 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1666
b5b05048 1667 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1668 if (result < 0)
1669 return result;
b60503ba 1670
a6ff7262 1671 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1672 if (result)
1673 return result;
b60503ba 1674
147b27e4 1675 nvmeq = &dev->queues[0];
b60503ba
MW		 1676 aqa = nvmeq->q_depth - 1;
1677 aqa |= aqa << 16;
1678
7a67cbea
CH		 1679 writel(aqa, dev->bar + NVME_REG_AQA);
1680 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1681 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1682
c0f2f45b 1683 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1684 if (result)
d4875622 1685 return result;
a4aea562 1686
2b25d981 1687 nvmeq->cq_vector = 0;
161b8be2 1688 nvme_init_queue(nvmeq, 0);
dca51e78 1689 result = queue_request_irq(nvmeq);
758dd7fd 1690 if (result) {
7c349dde 1691 dev->online_queues--;
d4875622 1692 return result;
758dd7fd 1693 }
025c557a 1694
4e224106 1695 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1696 return result;
1697}
1698
749941f2 1699static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1700{
4b04cc6a 1701 unsigned i, max, rw_queues;
749941f2 1702 int ret = 0;
42f61420 1703
d858e5f0 1704 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1705 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1706 ret = -ENOMEM;
42f61420 1707 break;
749941f2
CH		 1708 }
1709 }
42f61420 1710
d858e5f0 1711 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1712 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1713 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1714 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1715 } else {
1716 rw_queues = max;
1717 }
1718
949928c1 1719 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1720 bool polled = i > rw_queues;
1721
1722 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1723 if (ret)
42f61420 1724 break;
27e8166c 1725 }
749941f2
CH		 1726
1727 /*
1728 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1729 * than the desired amount of queues, and even a controller without
1730 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1731 * be useful to upgrade a buggy firmware for example.
1732 */
1733 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1734}
1735
202021c1
SB		 1736static ssize_t nvme_cmb_show(struct device *dev,
1737 struct device_attribute *attr,
1738 char *buf)
1739{
1740 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1741
c965809c 1742 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1743 ndev->cmbloc, ndev->cmbsz);
1744}
1745static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1746
88de4598 1747static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1748{
88de4598
CH		 1749 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1750
1751 return 1ULL << (12 + 4 * szu);
1752}
1753
1754static u32 nvme_cmb_size(struct nvme_dev *dev)
1755{
1756 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1757}
1758
f65efd6d 1759static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1760{
88de4598 1761 u64 size, offset;
8ffaadf7
JD		 1762 resource_size_t bar_size;
1763 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1764 int bar;
8ffaadf7 1765
9fe5c59f
KB		 1766 if (dev->cmb_size)
1767 return;
1768
7a67cbea 1769 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1770 if (!dev->cmbsz)
1771 return;
202021c1 1772 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1773
88de4598
CH		 1774 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1775 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1776 bar = NVME_CMB_BIR(dev->cmbloc);
1777 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1778
1779 if (offset > bar_size)
f65efd6d 1780 return;
8ffaadf7
JD		 1781
1782 /*
1783 * Controllers may support a CMB size larger than their BAR,
1784 * for example, due to being behind a bridge. Reduce the CMB to
1785 * the reported size of the BAR
1786 */
1787 if (size > bar_size - offset)
1788 size = bar_size - offset;
1789
0f238ff5
LG		 1790 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1791 dev_warn(dev->ctrl.device,
1792 "failed to register the CMB\n");
f65efd6d 1793 return;
0f238ff5
LG		 1794 }
1795
8ffaadf7 1796 dev->cmb_size = size;
0f238ff5
LG		 1797 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1798
1799 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1800 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1801 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1802
1803 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1804 &dev_attr_cmb.attr, NULL))
1805 dev_warn(dev->ctrl.device,
1806 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1807}
1808
1809static inline void nvme_release_cmb(struct nvme_dev *dev)
1810{
0f238ff5 1811 if (dev->cmb_size) {
1c78f773
MG		 1812 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1813 &dev_attr_cmb.attr, NULL);
0f238ff5 1814 dev->cmb_size = 0;
8ffaadf7
JD		 1815 }
1816}
1817
87ad72a5
CH		 1818static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1819{
4033f35d 1820 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1821 struct nvme_command c;
87ad72a5
CH		 1822 int ret;
1823
87ad72a5
CH		 1824 memset(&c, 0, sizeof(c));
1825 c.features.opcode = nvme_admin_set_features;
1826 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1827 c.features.dword11 = cpu_to_le32(bits);
1828 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1829 ilog2(dev->ctrl.page_size));
1830 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1831 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1832 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1833
1834 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1835 if (ret) {
1836 dev_warn(dev->ctrl.device,
1837 "failed to set host mem (err %d, flags %#x).\n",
1838 ret, bits);
1839 }
87ad72a5
CH		 1840 return ret;
1841}
1842
1843static void nvme_free_host_mem(struct nvme_dev *dev)
1844{
1845 int i;
1846
1847 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1848 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1849 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1850
cc667f6d
LD		 1851 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1852 le64_to_cpu(desc->addr),
1853 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1854 }
1855
1856 kfree(dev->host_mem_desc_bufs);
1857 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1858 dma_free_coherent(dev->dev,
1859 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1860 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1861 dev->host_mem_descs = NULL;
7e5dd57e 1862 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1863}
1864
92dc6895
CH		 1865static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1866 u32 chunk_size)
9d713c2b 1867{
87ad72a5 1868 struct nvme_host_mem_buf_desc *descs;
92dc6895 1869 u32 max_entries, len;
4033f35d 1870 dma_addr_t descs_dma;
2ee0e4ed 1871 int i = 0;
87ad72a5 1872 void **bufs;
6fbcde66 1873 u64 size, tmp;
87ad72a5 1874
87ad72a5
CH		 1875 tmp = (preferred + chunk_size - 1);
1876 do_div(tmp, chunk_size);
1877 max_entries = tmp;
044a9df1
CH		 1878
1879 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1880 max_entries = dev->ctrl.hmmaxd;
1881
750afb08
LC		 1882 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1883 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1884 if (!descs)
1885 goto out;
1886
1887 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1888 if (!bufs)
1889 goto out_free_descs;
1890
244a8fe4 1891 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1892 dma_addr_t dma_addr;
1893
50cdb7c6 1894 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1895 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1896 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1897 if (!bufs[i])
1898 break;
1899
1900 descs[i].addr = cpu_to_le64(dma_addr);
1901 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1902 i++;
1903 }
1904
92dc6895 1905 if (!size)
87ad72a5 1906 goto out_free_bufs;
87ad72a5 1907
87ad72a5
CH		 1908 dev->nr_host_mem_descs = i;
1909 dev->host_mem_size = size;
1910 dev->host_mem_descs = descs;
4033f35d 1911 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1912 dev->host_mem_desc_bufs = bufs;
1913 return 0;
1914
1915out_free_bufs:
1916 while (--i >= 0) {
1917 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1918
cc667f6d
LD		 1919 dma_free_attrs(dev->dev, size, bufs[i],
1920 le64_to_cpu(descs[i].addr),
1921 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1922 }
1923
1924 kfree(bufs);
1925out_free_descs:
4033f35d
CH		 1926 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1927 descs_dma);
87ad72a5 1928out:
87ad72a5
CH		 1929 dev->host_mem_descs = NULL;
1930 return -ENOMEM;
1931}
1932
92dc6895
CH		 1933static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1934{
1935 u32 chunk_size;
1936
1937 /* start big and work our way down */
30f92d62 1938 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1939 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1940 chunk_size /= 2) {
1941 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1942 if (!min || dev->host_mem_size >= min)
1943 return 0;
1944 nvme_free_host_mem(dev);
1945 }
1946 }
1947
1948 return -ENOMEM;
1949}
1950
9620cfba 1951static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1952{
1953 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1954 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1955 u64 min = (u64)dev->ctrl.hmmin * 4096;
1956 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1957 int ret;
87ad72a5
CH		 1958
1959 preferred = min(preferred, max);
1960 if (min > max) {
1961 dev_warn(dev->ctrl.device,
1962 "min host memory (%lld MiB) above limit (%d MiB).\n",
1963 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1964 nvme_free_host_mem(dev);
9620cfba 1965 return 0;
87ad72a5
CH		 1966 }
1967
1968 /*
1969 * If we already have a buffer allocated check if we can reuse it.
1970 */
1971 if (dev->host_mem_descs) {
1972 if (dev->host_mem_size >= min)
1973 enable_bits |= NVME_HOST_MEM_RETURN;
1974 else
1975 nvme_free_host_mem(dev);
1976 }
1977
1978 if (!dev->host_mem_descs) {
92dc6895
CH		 1979 if (nvme_alloc_host_mem(dev, min, preferred)) {
1980 dev_warn(dev->ctrl.device,
1981 "failed to allocate host memory buffer.\n");
9620cfba 1982 return 0; /* controller must work without HMB */
92dc6895
CH		 1983 }
1984
1985 dev_info(dev->ctrl.device,
1986 "allocated %lld MiB host memory buffer.\n",
1987 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 1988 }
1989
9620cfba
CH		 1990 ret = nvme_set_host_mem(dev, enable_bits);
1991 if (ret)
87ad72a5 1992 nvme_free_host_mem(dev);
9620cfba 1993 return ret;
9d713c2b
KB		 1994}
1995
612b7286
ML		 1996/*
1997 * nirqs is the number of interrupts available for write and read
1998 * queues. The core already reserved an interrupt for the admin queue.
1999 */
2000static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2001{
612b7286
ML		 2002 struct nvme_dev *dev = affd->priv;
2003 unsigned int nr_read_queues;
3b6592f7
JA		 2004
2005 /*
612b7286
ML		 2006 * If there is no interupt available for queues, ensure that
2007 * the default queue is set to 1. The affinity set size is
2008 * also set to one, but the irq core ignores it for this case.
2009 *
2010 * If only one interrupt is available or 'write_queue' == 0, combine
2011 * write and read queues.
2012 *
2013 * If 'write_queues' > 0, ensure it leaves room for at least one read
2014 * queue.
3b6592f7 2015 */
612b7286
ML		 2016 if (!nrirqs) {
2017 nrirqs = 1;
2018 nr_read_queues = 0;
2019 } else if (nrirqs == 1 || !write_queues) {
2020 nr_read_queues = 0;
2021 } else if (write_queues >= nrirqs) {
2022 nr_read_queues = 1;
3b6592f7 2023 } else {
612b7286 2024 nr_read_queues = nrirqs - write_queues;
3b6592f7 2025 }
612b7286
ML		 2026
2027 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2028 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2029 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2030 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2031 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2032}
2033
6451fe73 2034static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2035{
2036 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2037 struct irq_affinity affd = {
9cfef55b 2038 .pre_vectors = 1,
612b7286
ML		 2039 .calc_sets = nvme_calc_irq_sets,
2040 .priv = dev,
3b6592f7 2041 };
6451fe73
JA		 2042 unsigned int irq_queues, this_p_queues;
2043
2044 /*
2045 * Poll queues don't need interrupts, but we need at least one IO
2046 * queue left over for non-polled IO.
2047 */
2048 this_p_queues = poll_queues;
2049 if (this_p_queues >= nr_io_queues) {
2050 this_p_queues = nr_io_queues - 1;
2051 irq_queues = 1;
2052 } else {
7e4c6b9a 2053 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2054 }
2055 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7 2056
612b7286
ML		 2057 /* Initialize for the single interrupt case */
2058 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2059 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2060
66341331
BH		 2061 /*
2062 * Some Apple controllers require all queues to use the
2063 * first vector.
2064 */
2065 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2066 irq_queues = 1;
2067
612b7286
ML		 2068 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2069 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2070}
2071
8fae268b
KB		 2072static void nvme_disable_io_queues(struct nvme_dev *dev)
2073{
2074 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2075 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2076}
2077
8d85fce7 2078static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2079{
147b27e4 2080 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2081 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2082 int result, nr_io_queues;
2083 unsigned long size;
b60503ba 2084
3b6592f7 2085 nr_io_queues = max_io_queues();
d38e9f04
BH		 2086
2087 /*
2088 * If tags are shared with admin queue (Apple bug), then
2089 * make sure we only use one IO queue.
2090 */
2091 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2092 nr_io_queues = 1;
2093
9a0be7ab
CH		 2094 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2095 if (result < 0)
1b23484b 2096 return result;
9a0be7ab 2097
f5fa90dc 2098 if (nr_io_queues == 0)
a5229050 2099 return 0;
4e224106
CH		 2100
2101 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2102
0f238ff5 2103 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2104 result = nvme_cmb_qdepth(dev, nr_io_queues,
2105 sizeof(struct nvme_command));
2106 if (result > 0)
2107 dev->q_depth = result;
2108 else
0f238ff5 2109 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2110 }
2111
97f6ef64
XY		 2112 do {
2113 size = db_bar_size(dev, nr_io_queues);
2114 result = nvme_remap_bar(dev, size);
2115 if (!result)
2116 break;
2117 if (!--nr_io_queues)
2118 return -ENOMEM;
2119 } while (1);
2120 adminq->q_db = dev->dbs;
f1938f6e 2121
8fae268b 2122 retry:
9d713c2b 2123 /* Deregister the admin queue's interrupt */
0ff199cb 2124 pci_free_irq(pdev, 0, adminq);
9d713c2b 2125
e32efbfc
JA		 2126 /*
2127 * If we enable msix early due to not intx, disable it again before
2128 * setting up the full range we need.
2129 */
dca51e78 2130 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2131
2132 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2133 if (result <= 0)
dca51e78 2134 return -EIO;
3b6592f7 2135
22b55601 2136 dev->num_vecs = result;
4b04cc6a 2137 result = max(result - 1, 1);
e20ba6e1 2138 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2139
063a8096
MW		 2140 /*
2141 * Should investigate if there's a performance win from allocating
2142 * more queues than interrupt vectors; it might allow the submission
2143 * path to scale better, even if the receive path is limited by the
2144 * number of interrupts.
2145 */
dca51e78 2146 result = queue_request_irq(adminq);
7c349dde 2147 if (result)
d4875622 2148 return result;
4e224106 2149 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2150
2151 result = nvme_create_io_queues(dev);
2152 if (result || dev->online_queues < 2)
2153 return result;
2154
2155 if (dev->online_queues - 1 < dev->max_qid) {
2156 nr_io_queues = dev->online_queues - 1;
2157 nvme_disable_io_queues(dev);
2158 nvme_suspend_io_queues(dev);
2159 goto retry;
2160 }
2161 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2162 dev->io_queues[HCTX_TYPE_DEFAULT],
2163 dev->io_queues[HCTX_TYPE_READ],
2164 dev->io_queues[HCTX_TYPE_POLL]);
2165 return 0;
b60503ba
MW		 2166}
2167
2a842aca 2168static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2169{
db3cbfff 2170 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2171
db3cbfff 2172 blk_mq_free_request(req);
d1ed6aa1 2173 complete(&nvmeq->delete_done);
a5768aa8
KB		 2174}
2175
2a842aca 2176static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2177{
db3cbfff 2178 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2179
d1ed6aa1
CH		 2180 if (error)
2181 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2182
2183 nvme_del_queue_end(req, error);
a5768aa8
KB		 2184}
2185
db3cbfff 2186static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2187{
db3cbfff
KB		 2188 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2189 struct request *req;
2190 struct nvme_command cmd;
bda4e0fb 2191
db3cbfff
KB		 2192 memset(&cmd, 0, sizeof(cmd));
2193 cmd.delete_queue.opcode = opcode;
2194 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2195
eb71f435 2196 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2197 if (IS_ERR(req))
2198 return PTR_ERR(req);
bda4e0fb 2199
db3cbfff
KB		 2200 req->timeout = ADMIN_TIMEOUT;
2201 req->end_io_data = nvmeq;
2202
d1ed6aa1 2203 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2204 blk_execute_rq_nowait(q, NULL, req, false,
2205 opcode == nvme_admin_delete_cq ?
2206 nvme_del_cq_end : nvme_del_queue_end);
2207 return 0;
bda4e0fb
KB		 2208}
2209
8fae268b 2210static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2211{
5271edd4 2212 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2213 unsigned long timeout;
a5768aa8 2214
db3cbfff 2215 retry:
5271edd4
CH		 2216 timeout = ADMIN_TIMEOUT;
2217 while (nr_queues > 0) {
2218 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2219 break;
2220 nr_queues--;
2221 sent++;
db3cbfff 2222 }
d1ed6aa1
CH		 2223 while (sent) {
2224 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2225
2226 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2227 timeout);
2228 if (timeout == 0)
2229 return false;
d1ed6aa1 2230
d1ed6aa1 2231 sent--;
5271edd4
CH		 2232 if (nr_queues)
2233 goto retry;
2234 }
2235 return true;
a5768aa8
KB		 2236}
2237
5d02a5c1 2238static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2239{
2b1b7e78
JW		 2240 int ret;
2241
5bae7f73 2242 if (!dev->ctrl.tagset) {
376f7ef8 2243 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2244 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2245 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2246 if (dev->io_queues[HCTX_TYPE_POLL])
2247 dev->tagset.nr_maps++;
ffe7704d
KB		 2248 dev->tagset.timeout = NVME_IO_TIMEOUT;
2249 dev->tagset.numa_node = dev_to_node(dev->dev);
2250 dev->tagset.queue_depth =
a4aea562 2251 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2252 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2253 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2254 dev->tagset.driver_data = dev;
b60503ba 2255
d38e9f04
BH		 2256 /*
2257 * Some Apple controllers requires tags to be unique
2258 * across admin and IO queue, so reserve the first 32
2259 * tags of the IO queue.
2260 */
2261 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2262 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2263
2b1b7e78
JW		 2264 ret = blk_mq_alloc_tag_set(&dev->tagset);
2265 if (ret) {
2266 dev_warn(dev->ctrl.device,
2267 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2268 return;
2b1b7e78 2269 }
5bae7f73 2270 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2271 } else {
2272 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2273
2274 /* Free previously allocated queues that are no longer usable */
2275 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2276 }
949928c1 2277
e8fd41bb 2278 nvme_dbbuf_set(dev);
b60503ba
MW		 2279}
2280
b00a726a 2281static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2282{
b00a726a 2283 int result = -ENOMEM;
e75ec752 2284 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2285
2286 if (pci_enable_device_mem(pdev))
2287 return result;
2288
0877cb0d 2289 pci_set_master(pdev);
0877cb0d 2290
4fe06923 2291 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2292 goto disable;
0877cb0d 2293
7a67cbea 2294 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2295 result = -ENODEV;
b00a726a 2296 goto disable;
0e53d180 2297 }
e32efbfc
JA		 2298
2299 /*
a5229050
KB		 2300 * Some devices and/or platforms don't advertise or work with INTx
2301 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2302 * adjust this later.
e32efbfc 2303 */
dca51e78
CH		 2304 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2305 if (result < 0)
2306 return result;
e32efbfc 2307
20d0dfe6 2308 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2309
20d0dfe6 2310 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2311 io_queue_depth);
aa22c8e6 2312 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2313 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2314 dev->dbs = dev->bar + 4096;
1f390c1f 2315
66341331
BH		 2316 /*
2317 * Some Apple controllers require a non-standard SQE size.
2318 * Interestingly they also seem to ignore the CC:IOSQES register
2319 * so we don't bother updating it here.
2320 */
2321 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2322 dev->io_sqes = 7;
2323 else
2324 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2325
2326 /*
2327 * Temporary fix for the Apple controller found in the MacBook8,1 and
2328 * some MacBook7,1 to avoid controller resets and data loss.
2329 */
2330 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2331 dev->q_depth = 2;
9bdcfb10
CH		 2332 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2333 "set queue depth=%u to work around controller resets\n",
1f390c1f 2334 dev->q_depth);
d554b5e1
MP		 2335 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2336 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2337 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2338 dev->q_depth = 64;
2339 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2340 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2341 }
2342
d38e9f04
BH		 2343 /*
2344 * Controllers with the shared tags quirk need the IO queue to be
2345 * big enough so that we get 32 tags for the admin queue
2346 */
2347 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2348 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2349 dev->q_depth = NVME_AQ_DEPTH + 2;
2350 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2351 dev->q_depth);
2352 }
2353
2354
f65efd6d 2355 nvme_map_cmb(dev);
202021c1 2356
a0a3408e
KB		 2357 pci_enable_pcie_error_reporting(pdev);
2358 pci_save_state(pdev);
0877cb0d
KB		 2359 return 0;
2360
2361 disable:
0877cb0d
KB		 2362 pci_disable_device(pdev);
2363 return result;
2364}
2365
2366static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2367{
2368 if (dev->bar)
2369 iounmap(dev->bar);
a1f447b3 2370 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2371}
2372
2373static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2374{
e75ec752
CH		 2375 struct pci_dev *pdev = to_pci_dev(dev->dev);
2376
dca51e78 2377 pci_free_irq_vectors(pdev);
0877cb0d 2378
a0a3408e
KB		 2379 if (pci_is_enabled(pdev)) {
2380 pci_disable_pcie_error_reporting(pdev);
e75ec752 2381 pci_disable_device(pdev);
4d115420 2382 }
4d115420
KB		 2383}
2384
a5cdb68c 2385static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2386{
e43269e6 2387 bool dead = true, freeze = false;
302ad8cc 2388 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2389
77bf25ea 2390 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2391 if (pci_is_enabled(pdev)) {
2392 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2393
ebef7368 2394 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2395 dev->ctrl.state == NVME_CTRL_RESETTING) {
2396 freeze = true;
302ad8cc 2397 nvme_start_freeze(&dev->ctrl);
e43269e6 2398 }
302ad8cc
KB		 2399 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2400 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2401 }
c21377f8 2402
302ad8cc
KB		 2403 /*
2404 * Give the controller a chance to complete all entered requests if
2405 * doing a safe shutdown.
2406 */
e43269e6
KB		 2407 if (!dead && shutdown && freeze)
2408 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2409
2410 nvme_stop_queues(&dev->ctrl);
87ad72a5 2411
64ee0ac0 2412 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2413 nvme_disable_io_queues(dev);
a5cdb68c 2414 nvme_disable_admin_queue(dev, shutdown);
4d115420 2415 }
8fae268b
KB		 2416 nvme_suspend_io_queues(dev);
2417 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2418 nvme_pci_disable(dev);
fa46c6fb 2419 nvme_reap_pending_cqes(dev);
07836e65 2420
e1958e65
ML		 2421 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2422 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2423 blk_mq_tagset_wait_completed_request(&dev->tagset);
2424 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2425
2426 /*
2427 * The driver will not be starting up queues again if shutting down so
2428 * must flush all entered requests to their failed completion to avoid
2429 * deadlocking blk-mq hot-cpu notifier.
2430 */
c8e9e9b7 2431 if (shutdown) {
302ad8cc 2432 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2433 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2434 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2435 }
77bf25ea 2436 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2437}
2438
c1ac9a4b
KB		 2439static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2440{
2441 if (!nvme_wait_reset(&dev->ctrl))
2442 return -EBUSY;
2443 nvme_dev_disable(dev, shutdown);
2444 return 0;
2445}
2446
091b6092
MW		 2447static int nvme_setup_prp_pools(struct nvme_dev *dev)
2448{
e75ec752 2449 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2450 PAGE_SIZE, PAGE_SIZE, 0);
2451 if (!dev->prp_page_pool)
2452 return -ENOMEM;
2453
99802a7a 2454 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2455 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2456 256, 256, 0);
2457 if (!dev->prp_small_pool) {
2458 dma_pool_destroy(dev->prp_page_pool);
2459 return -ENOMEM;
2460 }
091b6092
MW		 2461 return 0;
2462}
2463
2464static void nvme_release_prp_pools(struct nvme_dev *dev)
2465{
2466 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2467 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2468}
2469
770597ec
KB		 2470static void nvme_free_tagset(struct nvme_dev *dev)
2471{
2472 if (dev->tagset.tags)
2473 blk_mq_free_tag_set(&dev->tagset);
2474 dev->ctrl.tagset = NULL;
2475}
2476
1673f1f0 2477static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2478{
1673f1f0 2479 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2480
f9f38e33 2481 nvme_dbbuf_dma_free(dev);
770597ec 2482 nvme_free_tagset(dev);
1c63dc66
CH		 2483 if (dev->ctrl.admin_q)
2484 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2485 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2486 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2487 put_device(dev->dev);
2488 kfree(dev->queues);
5e82e952
KB		 2489 kfree(dev);
2490}
2491
7c1ce408 2492static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2493{
c1ac9a4b
KB		 2494 /*
2495 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2496 * may be holding this pci_dev's device lock.
2497 */
2498 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2499 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2500 nvme_dev_disable(dev, false);
9f9cafc1 2501 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2502 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2503 nvme_put_ctrl(&dev->ctrl);
2504}
2505
fd634f41 2506static void nvme_reset_work(struct work_struct *work)
5e82e952 2507{
d86c4d8e
CH		 2508 struct nvme_dev *dev =
2509 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2510 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2511 int result;
5e82e952 2512
e71afda4
CK		 2513 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2514 result = -ENODEV;
fd634f41 2515 goto out;
e71afda4 2516 }
5e82e952 2517
fd634f41
CH		 2518 /*
2519 * If we're called to reset a live controller first shut it down before
2520 * moving on.
2521 */
b00a726a 2522 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2523 nvme_dev_disable(dev, false);
d6135c3a 2524 nvme_sync_queues(&dev->ctrl);
5e82e952 2525
5c959d73 2526 mutex_lock(&dev->shutdown_lock);
b00a726a 2527 result = nvme_pci_enable(dev);
f0b50732 2528 if (result)
4726bcf3 2529 goto out_unlock;
f0b50732 2530
01ad0990 2531 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2532 if (result)
4726bcf3 2533 goto out_unlock;
f0b50732 2534
0fb59cbc
KB		 2535 result = nvme_alloc_admin_tags(dev);
2536 if (result)
4726bcf3 2537 goto out_unlock;
b9afca3e 2538
943e942e
JA		 2539 /*
2540 * Limit the max command size to prevent iod->sg allocations going
2541 * over a single page.
2542 */
7637de31
CH		 2543 dev->ctrl.max_hw_sectors = min_t(u32,
2544 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2545 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2546
2547 /*
2548 * Don't limit the IOMMU merged segment size.
2549 */
2550 dma_set_max_seg_size(dev->dev, 0xffffffff);
2551
5c959d73
KB		 2552 mutex_unlock(&dev->shutdown_lock);
2553
2554 /*
2555 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2556 * initializing procedure here.
2557 */
2558 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2559 dev_warn(dev->ctrl.device,
2560 "failed to mark controller CONNECTING\n");
cee6c269 2561 result = -EBUSY;
5c959d73
KB		 2562 goto out;
2563 }
943e942e 2564
ce4541f4
CH		 2565 result = nvme_init_identify(&dev->ctrl);
2566 if (result)
f58944e2 2567 goto out;
ce4541f4 2568
e286bcfc
SB		 2569 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2570 if (!dev->ctrl.opal_dev)
2571 dev->ctrl.opal_dev =
2572 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2573 else if (was_suspend)
2574 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2575 } else {
2576 free_opal_dev(dev->ctrl.opal_dev);
2577 dev->ctrl.opal_dev = NULL;
4f1244c8 2578 }
a98e58e5 2579
f9f38e33
HK		 2580 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2581 result = nvme_dbbuf_dma_alloc(dev);
2582 if (result)
2583 dev_warn(dev->dev,
2584 "unable to allocate dma for dbbuf\n");
2585 }
2586
9620cfba
CH		 2587 if (dev->ctrl.hmpre) {
2588 result = nvme_setup_host_mem(dev);
2589 if (result < 0)
2590 goto out;
2591 }
87ad72a5 2592
f0b50732 2593 result = nvme_setup_io_queues(dev);
badc34d4 2594 if (result)
f58944e2 2595 goto out;
f0b50732 2596
2659e57b
CH		 2597 /*
2598 * Keep the controller around but remove all namespaces if we don't have
2599 * any working I/O queue.
2600 */
3cf519b5 2601 if (dev->online_queues < 2) {
1b3c47c1 2602 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2603 nvme_kill_queues(&dev->ctrl);
5bae7f73 2604 nvme_remove_namespaces(&dev->ctrl);
770597ec 2605 nvme_free_tagset(dev);
3cf519b5 2606 } else {
25646264 2607 nvme_start_queues(&dev->ctrl);
302ad8cc 2608 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2609 nvme_dev_add(dev);
302ad8cc 2610 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2611 }
2612
2b1b7e78
JW		 2613 /*
2614 * If only admin queue live, keep it to do further investigation or
2615 * recovery.
2616 */
5d02a5c1 2617 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2618 dev_warn(dev->ctrl.device,
5d02a5c1 2619 "failed to mark controller live state\n");
e71afda4 2620 result = -ENODEV;
bb8d261e
CH		 2621 goto out;
2622 }
92911a55 2623
d09f2b45 2624 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2625 return;
f0b50732 2626
4726bcf3
KB		 2627 out_unlock:
2628 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2629 out:
7c1ce408
CK		 2630 if (result)
2631 dev_warn(dev->ctrl.device,
2632 "Removing after probe failure status: %d\n", result);
2633 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2634}
2635
5c8809e6 2636static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2637{
5c8809e6 2638 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2639 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2640
2641 if (pci_get_drvdata(pdev))
921920ab 2642 device_release_driver(&pdev->dev);
1673f1f0 2643 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2644}
2645
1c63dc66 2646static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2647{
1c63dc66 2648 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2649 return 0;
9ca97374
TH		 2650}
2651
5fd4ce1b 2652static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2653{
5fd4ce1b
CH		 2654 writel(val, to_nvme_dev(ctrl)->bar + off);
2655 return 0;
2656}
4cc06521 2657
7fd8930f
CH		 2658static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2659{
3a8ecc93 2660 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2661 return 0;
4cc06521
KB		 2662}
2663
97c12223
KB		 2664static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2665{
2666 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2667
2db24e4a 2668 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2669}
2670
1c63dc66 2671static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2672 .name = "pcie",
e439bb12 2673 .module = THIS_MODULE,
e0596ab2
LG		 2674 .flags = NVME_F_METADATA_SUPPORTED |
2675 NVME_F_PCI_P2PDMA,
1c63dc66 2676 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2677 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2678 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2679 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2680 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2681 .get_address = nvme_pci_get_address,
1c63dc66 2682};
4cc06521 2683
b00a726a
KB		 2684static int nvme_dev_map(struct nvme_dev *dev)
2685{
b00a726a
KB		 2686 struct pci_dev *pdev = to_pci_dev(dev->dev);
2687
a1f447b3 2688 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2689 return -ENODEV;
2690
97f6ef64 2691 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2692 goto release;
2693
9fa196e7 2694 return 0;
b00a726a 2695 release:
9fa196e7
MG		 2696 pci_release_mem_regions(pdev);
2697 return -ENODEV;
b00a726a
KB		 2698}
2699
8427bbc2 2700static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2701{
2702 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2703 /*
2704 * Several Samsung devices seem to drop off the PCIe bus
2705 * randomly when APST is on and uses the deepest sleep state.
2706 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2707 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2708 * 950 PRO 256GB", but it seems to be restricted to two Dell
2709 * laptops.
2710 */
2711 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2712 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2713 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2714 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2715 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2716 /*
2717 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2718 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2719 * within few minutes after bootup on a Coffee Lake board -
2720 * ASUS PRIME Z370-A
8427bbc2
KHF		 2721 */
2722 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2723 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2724 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2725 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2726 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2727 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2728 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2729 /*
2730 * Forcing to use host managed nvme power settings for
2731 * lowest idle power with quick resume latency on
2732 * Samsung and Toshiba SSDs based on suspend behavior
2733 * on Coffee Lake board for LENOVO C640
2734 */
2735 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2736 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2737 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2738 }
2739
2740 return 0;
2741}
2742
18119775
KB		 2743static void nvme_async_probe(void *data, async_cookie_t cookie)
2744{
2745 struct nvme_dev *dev = data;
80f513b5 2746
bd46a906 2747 flush_work(&dev->ctrl.reset_work);
18119775 2748 flush_work(&dev->ctrl.scan_work);
80f513b5 2749 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2750}
2751
8d85fce7 2752static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2753{
a4aea562 2754 int node, result = -ENOMEM;
b60503ba 2755 struct nvme_dev *dev;
ff5350a8 2756 unsigned long quirks = id->driver_data;
943e942e 2757 size_t alloc_size;
b60503ba 2758
a4aea562
MB		 2759 node = dev_to_node(&pdev->dev);
2760 if (node == NUMA_NO_NODE)
2fa84351 2761 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2762
2763 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2764 if (!dev)
2765 return -ENOMEM;
147b27e4 2766
3b6592f7
JA		 2767 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2768 GFP_KERNEL, node);
b60503ba
MW		 2769 if (!dev->queues)
2770 goto free;
2771
e75ec752 2772 dev->dev = get_device(&pdev->dev);
9a6b9458 2773 pci_set_drvdata(pdev, dev);
1c63dc66 2774
b00a726a
KB		 2775 result = nvme_dev_map(dev);
2776 if (result)
b00c9b7a 2777 goto put_pci;
b00a726a 2778
d86c4d8e 2779 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2780 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2781 mutex_init(&dev->shutdown_lock);
b60503ba 2782
091b6092
MW		 2783 result = nvme_setup_prp_pools(dev);
2784 if (result)
b00c9b7a 2785 goto unmap;
4cc06521 2786
8427bbc2 2787 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2788
943e942e
JA		 2789 /*
2790 * Double check that our mempool alloc size will cover the biggest
2791 * command we support.
2792 */
2793 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2794 NVME_MAX_SEGS, true);
2795 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2796
2797 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2798 mempool_kfree,
2799 (void *) alloc_size,
2800 GFP_KERNEL, node);
2801 if (!dev->iod_mempool) {
2802 result = -ENOMEM;
2803 goto release_pools;
2804 }
2805
b6e44b4c
KB		 2806 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2807 quirks);
2808 if (result)
2809 goto release_mempool;
2810
1b3c47c1
SG		 2811 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2812
bd46a906 2813 nvme_reset_ctrl(&dev->ctrl);
18119775 2814 async_schedule(nvme_async_probe, dev);
4caff8fc 2815
b60503ba
MW		 2816 return 0;
2817
b6e44b4c
KB		 2818 release_mempool:
2819 mempool_destroy(dev->iod_mempool);
0877cb0d 2820 release_pools:
091b6092 2821 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2822 unmap:
2823 nvme_dev_unmap(dev);
a96d4f5c 2824 put_pci:
e75ec752 2825 put_device(dev->dev);
b60503ba
MW		 2826 free:
2827 kfree(dev->queues);
b60503ba
MW		 2828 kfree(dev);
2829 return result;
2830}
2831
775755ed 2832static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2833{
a6739479 2834 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2835
2836 /*
2837 * We don't need to check the return value from waiting for the reset
2838 * state as pci_dev device lock is held, making it impossible to race
2839 * with ->remove().
2840 */
2841 nvme_disable_prepare_reset(dev, false);
2842 nvme_sync_queues(&dev->ctrl);
775755ed 2843}
f0d54a54 2844
775755ed
CH		 2845static void nvme_reset_done(struct pci_dev *pdev)
2846{
f263fbb8 2847 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2848
2849 if (!nvme_try_sched_reset(&dev->ctrl))
2850 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2851}
2852
09ece142
KB		 2853static void nvme_shutdown(struct pci_dev *pdev)
2854{
2855 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b 2856 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2857}
2858
f58944e2
KB		 2859/*
2860 * The driver's remove may be called on a device in a partially initialized
2861 * state. This function must not have any dependencies on the device state in
2862 * order to proceed.
2863 */
8d85fce7 2864static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2865{
2866 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2867
bb8d261e 2868 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2869 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2870
6db28eda 2871 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2872 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2873 nvme_dev_disable(dev, true);
cb4bfda6 2874 nvme_dev_remove_admin(dev);
6db28eda 2875 }
0ff9d4e1 2876
d86c4d8e 2877 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2878 nvme_stop_ctrl(&dev->ctrl);
2879 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2880 nvme_dev_disable(dev, true);
9fe5c59f 2881 nvme_release_cmb(dev);
87ad72a5 2882 nvme_free_host_mem(dev);
a4aea562 2883 nvme_dev_remove_admin(dev);
a1a5ef99 2884 nvme_free_queues(dev, 0);
9a6b9458 2885 nvme_release_prp_pools(dev);
b00a726a 2886 nvme_dev_unmap(dev);
726612b6 2887 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2888}
2889
671a6018 2890#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2891static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2892{
2893 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2894}
2895
2896static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2897{
2898 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2899}
2900
2901static int nvme_resume(struct device *dev)
2902{
2903 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2904 struct nvme_ctrl *ctrl = &ndev->ctrl;
2905
4eaefe8c 2906 if (ndev->last_ps == U32_MAX ||
d916b1be 2907 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 2908 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 2909 return 0;
2910}
2911
cd638946
KB		 2912static int nvme_suspend(struct device *dev)
2913{
2914 struct pci_dev *pdev = to_pci_dev(dev);
2915 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 2916 struct nvme_ctrl *ctrl = &ndev->ctrl;
2917 int ret = -EBUSY;
2918
4eaefe8c
RW		 2919 ndev->last_ps = U32_MAX;
2920
d916b1be
KB		 2921 /*
2922 * The platform does not remove power for a kernel managed suspend so
2923 * use host managed nvme power settings for lowest idle power if
2924 * possible. This should have quicker resume latency than a full device
2925 * shutdown. But if the firmware is involved after the suspend or the
2926 * device does not support any non-default power states, shut down the
2927 * device fully.
4eaefe8c
RW		 2928 *
2929 * If ASPM is not enabled for the device, shut down the device and allow
2930 * the PCI bus layer to put it into D3 in order to take the PCIe link
2931 * down, so as to allow the platform to achieve its minimum low-power
2932 * state (which may not be possible if the link is up).
d916b1be 2933 */
4eaefe8c 2934 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 2935 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 2936 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2937 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 2938
2939 nvme_start_freeze(ctrl);
2940 nvme_wait_freeze(ctrl);
2941 nvme_sync_queues(ctrl);
2942
5d02a5c1 2943 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 2944 goto unfreeze;
2945
d916b1be
KB		 2946 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2947 if (ret < 0)
2948 goto unfreeze;
2949
7cbb5c6f
ML		 2950 /*
2951 * A saved state prevents pci pm from generically controlling the
2952 * device's power. If we're using protocol specific settings, we don't
2953 * want pci interfering.
2954 */
2955 pci_save_state(pdev);
2956
d916b1be
KB		 2957 ret = nvme_set_power_state(ctrl, ctrl->npss);
2958 if (ret < 0)
2959 goto unfreeze;
2960
2961 if (ret) {
7cbb5c6f
ML		 2962 /* discard the saved state */
2963 pci_load_saved_state(pdev, NULL);
2964
d916b1be
KB		 2965 /*
2966 * Clearing npss forces a controller reset on resume. The
05d3046f 2967 * correct value will be rediscovered then.
d916b1be 2968 */
c1ac9a4b 2969 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 2970 ctrl->npss = 0;
d916b1be 2971 }
d916b1be
KB		 2972unfreeze:
2973 nvme_unfreeze(ctrl);
2974 return ret;
2975}
2976
2977static int nvme_simple_suspend(struct device *dev)
2978{
2979 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
c1ac9a4b 2980 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 2981}
2982
d916b1be 2983static int nvme_simple_resume(struct device *dev)
cd638946
KB		 2984{
2985 struct pci_dev *pdev = to_pci_dev(dev);
2986 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2987
c1ac9a4b 2988 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 2989}
2990
21774222 2991static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 2992 .suspend = nvme_suspend,
2993 .resume = nvme_resume,
2994 .freeze = nvme_simple_suspend,
2995 .thaw = nvme_simple_resume,
2996 .poweroff = nvme_simple_suspend,
2997 .restore = nvme_simple_resume,
2998};
2999#endif /* CONFIG_PM_SLEEP */
b60503ba 3000
a0a3408e
KB		 3001static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3002 pci_channel_state_t state)
3003{
3004 struct nvme_dev *dev = pci_get_drvdata(pdev);
3005
3006 /*
3007 * A frozen channel requires a reset. When detected, this method will
3008 * shutdown the controller to quiesce. The controller will be restarted
3009 * after the slot reset through driver's slot_reset callback.
3010 */
a0a3408e
KB		 3011 switch (state) {
3012 case pci_channel_io_normal:
3013 return PCI_ERS_RESULT_CAN_RECOVER;
3014 case pci_channel_io_frozen:
d011fb31
KB		 3015 dev_warn(dev->ctrl.device,
3016 "frozen state error detected, reset controller\n");
a5cdb68c 3017 nvme_dev_disable(dev, false);
a0a3408e
KB		 3018 return PCI_ERS_RESULT_NEED_RESET;
3019 case pci_channel_io_perm_failure:
d011fb31
KB		 3020 dev_warn(dev->ctrl.device,
3021 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3022 return PCI_ERS_RESULT_DISCONNECT;
3023 }
3024 return PCI_ERS_RESULT_NEED_RESET;
3025}
3026
3027static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3028{
3029 struct nvme_dev *dev = pci_get_drvdata(pdev);
3030
1b3c47c1 3031 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3032 pci_restore_state(pdev);
d86c4d8e 3033 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3034 return PCI_ERS_RESULT_RECOVERED;
3035}
3036
3037static void nvme_error_resume(struct pci_dev *pdev)
3038{
72cd4cc2
KB		 3039 struct nvme_dev *dev = pci_get_drvdata(pdev);
3040
3041 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3042}
3043
1d352035 3044static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3045 .error_detected = nvme_error_detected,
b60503ba
MW		 3046 .slot_reset = nvme_slot_reset,
3047 .resume = nvme_error_resume,
775755ed
CH		 3048 .reset_prepare = nvme_reset_prepare,
3049 .reset_done = nvme_reset_done,
b60503ba
MW		 3050};
3051
6eb0d698 3052static const struct pci_device_id nvme_id_table[] = {
106198ed 3053 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 3054 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3055 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3056 { PCI_VDEVICE(INTEL, 0x0a53),
3057 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3058 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 3059 { PCI_VDEVICE(INTEL, 0x0a54),
3060 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3061 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 3062 { PCI_VDEVICE(INTEL, 0x0a55),
3063 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3064 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3065 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3066 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2
AM		 3067 NVME_QUIRK_MEDIUM_PRIO_SQ |
3068 NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
6299358d
JD		 3069 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3070 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3071 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3072 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3073 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
0302ae60
MP		 3074 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3075 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3076 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3077 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3078 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3079 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3080 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3081 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3082 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3083 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3084 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3085 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3086 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3087 .driver_data = NVME_QUIRK_LIGHTNVM, },
3088 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3089 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3090 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3091 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3092 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3093 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3094 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3095 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3096 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
b60503ba 3097 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
98f7b86a
AS		 3098 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3099 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3100 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3101 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3102 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3103 NVME_QUIRK_128_BYTES_SQES |
3104 NVME_QUIRK_SHARED_TAGS },
b60503ba
MW		 3105 { 0, }
3106};
3107MODULE_DEVICE_TABLE(pci, nvme_id_table);
3108
3109static struct pci_driver nvme_driver = {
3110 .name = "nvme",
3111 .id_table = nvme_id_table,
3112 .probe = nvme_probe,
8d85fce7 3113 .remove = nvme_remove,
09ece142 3114 .shutdown = nvme_shutdown,
d916b1be 3115#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3116 .driver = {
3117 .pm = &nvme_dev_pm_ops,
3118 },
d916b1be 3119#endif
74d986ab 3120 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3121 .err_handler = &nvme_err_handler,
3122};
3123
3124static int __init nvme_init(void)
3125{
81101540
CH		 3126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3129 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167
KB		 3130
3131 write_queues = min(write_queues, num_possible_cpus());
3132 poll_queues = min(poll_queues, num_possible_cpus());
9a6327d2 3133 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3134}
3135
3136static void __exit nvme_exit(void)
3137{
3138 pci_unregister_driver(&nvme_driver);
03e0f3a6 3139 flush_workqueue(nvme_wq);
b60503ba
MW		 3140}
3141
3142MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3143MODULE_LICENSE("GPL");
c78b4713 3144MODULE_VERSION("1.0");
b60503ba
MW		 3145module_init(nvme_init);
3146module_exit(nvme_exit);
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