]>
Commit | Line | Data |
---|---|---|
8cfab3cf | 1 | // SPDX-License-Identifier: GPL-2.0 |
47ff3de9 KVA |
2 | /* |
3 | * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs | |
4 | * | |
7ecd4a81 | 5 | * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com |
47ff3de9 KVA |
6 | * |
7 | * Authors: Kishon Vijay Abraham I <kishon@ti.com> | |
47ff3de9 KVA |
8 | */ |
9 | ||
5af94053 | 10 | #include <linux/clk.h> |
608793e2 | 11 | #include <linux/delay.h> |
7a4db656 | 12 | #include <linux/device.h> |
47ff3de9 KVA |
13 | #include <linux/err.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/irqdomain.h> | |
17 | #include <linux/kernel.h> | |
3b868d15 | 18 | #include <linux/module.h> |
c925cfaf | 19 | #include <linux/of.h> |
78bdcad0 | 20 | #include <linux/of_gpio.h> |
ab5fe4f4 | 21 | #include <linux/of_pci.h> |
47ff3de9 KVA |
22 | #include <linux/pci.h> |
23 | #include <linux/phy/phy.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/resource.h> | |
27 | #include <linux/types.h> | |
f7a2757f KVA |
28 | #include <linux/mfd/syscon.h> |
29 | #include <linux/regmap.h> | |
381ed79c | 30 | #include <linux/gpio/consumer.h> |
47ff3de9 | 31 | |
6e0832fa | 32 | #include "../../pci.h" |
47ff3de9 KVA |
33 | #include "pcie-designware.h" |
34 | ||
35 | /* PCIe controller wrapper DRA7XX configuration registers */ | |
36 | ||
37 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024 | |
38 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028 | |
39 | #define ERR_SYS BIT(0) | |
40 | #define ERR_FATAL BIT(1) | |
41 | #define ERR_NONFATAL BIT(2) | |
42 | #define ERR_COR BIT(3) | |
43 | #define ERR_AXI BIT(4) | |
44 | #define ERR_ECRC BIT(5) | |
45 | #define PME_TURN_OFF BIT(8) | |
46 | #define PME_TO_ACK BIT(9) | |
47 | #define PM_PME BIT(10) | |
48 | #define LINK_REQ_RST BIT(11) | |
49 | #define LINK_UP_EVT BIT(12) | |
50 | #define CFG_BME_EVT BIT(13) | |
51 | #define CFG_MSE_EVT BIT(14) | |
52 | #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \ | |
53 | ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \ | |
54 | LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT) | |
55 | ||
56 | #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034 | |
57 | #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038 | |
58 | #define INTA BIT(0) | |
59 | #define INTB BIT(1) | |
60 | #define INTC BIT(2) | |
61 | #define INTD BIT(3) | |
62 | #define MSI BIT(4) | |
63 | #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD) | |
64 | ||
608793e2 KVA |
65 | #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100 |
66 | #define DEVICE_TYPE_EP 0x0 | |
67 | #define DEVICE_TYPE_LEG_EP 0x1 | |
68 | #define DEVICE_TYPE_RC 0x4 | |
69 | ||
47ff3de9 KVA |
70 | #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104 |
71 | #define LTSSM_EN 0x1 | |
72 | ||
73 | #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C | |
74 | #define LINK_UP BIT(16) | |
883cc17c | 75 | #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF |
47ff3de9 | 76 | |
608793e2 KVA |
77 | #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 |
78 | #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 | |
79 | ||
80 | #define PCIECTRL_TI_CONF_MSI_XMT 0x012c | |
81 | #define MSI_REQ_GRANT BIT(0) | |
82 | #define MSI_VECTOR_SHIFT 7 | |
83 | ||
c232c0df KVA |
84 | #define PCIE_1LANE_2LANE_SELECTION BIT(13) |
85 | #define PCIE_B1C0_MODE_SEL BIT(2) | |
86 | #define PCIE_B0_B1_TSYNCEN BIT(0) | |
87 | ||
47ff3de9 | 88 | struct dra7xx_pcie { |
442ec4c0 | 89 | struct dw_pcie *pci; |
8e5ec414 BH |
90 | void __iomem *base; /* DT ti_conf */ |
91 | int phy_count; /* DT phy-names count */ | |
92 | struct phy **phy; | |
ebe85a44 | 93 | struct irq_domain *irq_domain; |
5af94053 | 94 | struct clk *clk; |
608793e2 KVA |
95 | enum dw_pcie_device_mode mode; |
96 | }; | |
97 | ||
98 | struct dra7xx_pcie_of_data { | |
99 | enum dw_pcie_device_mode mode; | |
c232c0df | 100 | u32 b1co_mode_sel_mask; |
47ff3de9 KVA |
101 | }; |
102 | ||
442ec4c0 | 103 | #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) |
47ff3de9 KVA |
104 | |
105 | static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) | |
106 | { | |
107 | return readl(pcie->base + offset); | |
108 | } | |
109 | ||
110 | static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, | |
111 | u32 value) | |
112 | { | |
113 | writel(value, pcie->base + offset); | |
114 | } | |
115 | ||
b6900aeb | 116 | static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr) |
2ed6cc71 KVA |
117 | { |
118 | return pci_addr & DRA7XX_CPU_TO_BUS_ADDR; | |
119 | } | |
120 | ||
442ec4c0 | 121 | static int dra7xx_pcie_link_up(struct dw_pcie *pci) |
47ff3de9 | 122 | { |
442ec4c0 | 123 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); |
47ff3de9 KVA |
124 | u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); |
125 | ||
126 | return !!(reg & LINK_UP); | |
127 | } | |
128 | ||
608793e2 | 129 | static void dra7xx_pcie_stop_link(struct dw_pcie *pci) |
47ff3de9 | 130 | { |
608793e2 KVA |
131 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); |
132 | u32 reg; | |
133 | ||
134 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
135 | reg &= ~LTSSM_EN; | |
136 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
137 | } | |
138 | ||
139 | static int dra7xx_pcie_establish_link(struct dw_pcie *pci) | |
140 | { | |
141 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
442ec4c0 | 142 | struct device *dev = pci->dev; |
6cbb247e | 143 | u32 reg; |
47ff3de9 | 144 | |
442ec4c0 | 145 | if (dw_pcie_link_up(pci)) { |
c7f8146b | 146 | dev_err(dev, "link is already up\n"); |
47ff3de9 KVA |
147 | return 0; |
148 | } | |
149 | ||
150 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
151 | reg |= LTSSM_EN; | |
152 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
153 | ||
608793e2 | 154 | return 0; |
47ff3de9 KVA |
155 | } |
156 | ||
5ffd90a0 | 157 | static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) |
47ff3de9 | 158 | { |
47ff3de9 | 159 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, |
40aa52c4 | 160 | LEG_EP_INTERRUPTS | MSI); |
5ffd90a0 KVA |
161 | |
162 | dra7xx_pcie_writel(dra7xx, | |
163 | PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, | |
ebe85a44 | 164 | MSI | LEG_EP_INTERRUPTS); |
47ff3de9 KVA |
165 | } |
166 | ||
5ffd90a0 KVA |
167 | static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) |
168 | { | |
169 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, | |
40aa52c4 | 170 | INTERRUPTS); |
5ffd90a0 KVA |
171 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, |
172 | INTERRUPTS); | |
173 | } | |
174 | ||
175 | static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) | |
176 | { | |
177 | dra7xx_pcie_enable_wrapper_interrupts(dra7xx); | |
178 | dra7xx_pcie_enable_msi_interrupts(dra7xx); | |
179 | } | |
180 | ||
60b3c27f | 181 | static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp) |
47ff3de9 | 182 | { |
442ec4c0 KVA |
183 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
184 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
21baa1c4 | 185 | |
21baa1c4 | 186 | dra7xx_pcie_enable_interrupts(dra7xx); |
4a301766 BA |
187 | |
188 | return 0; | |
47ff3de9 KVA |
189 | } |
190 | ||
47ff3de9 KVA |
191 | static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
192 | irq_hw_number_t hwirq) | |
193 | { | |
194 | irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); | |
195 | irq_set_chip_data(irq, domain->host_data); | |
47ff3de9 KVA |
196 | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static const struct irq_domain_ops intx_domain_ops = { | |
201 | .map = dra7xx_pcie_intx_map, | |
524d59f6 | 202 | .xlate = pci_irqd_intx_xlate, |
47ff3de9 KVA |
203 | }; |
204 | ||
60b3c27f | 205 | static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index) |
47ff3de9 | 206 | { |
442ec4c0 | 207 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
9a5595ab | 208 | unsigned long val; |
d21faba1 | 209 | int pos; |
47ff3de9 | 210 | |
9a5595ab VR |
211 | val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + |
212 | (index * MSI_REG_CTRL_BLOCK_SIZE)); | |
213 | if (!val) | |
214 | return 0; | |
47ff3de9 | 215 | |
b5c7e7ec | 216 | pos = find_first_bit(&val, MAX_MSI_IRQS_PER_CTRL); |
9a5595ab | 217 | while (pos != MAX_MSI_IRQS_PER_CTRL) { |
d21faba1 MZ |
218 | generic_handle_domain_irq(pp->irq_domain, |
219 | (index * MAX_MSI_IRQS_PER_CTRL) + pos); | |
9a5595ab VR |
220 | pos++; |
221 | pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos); | |
47ff3de9 KVA |
222 | } |
223 | ||
9a5595ab | 224 | return 1; |
47ff3de9 KVA |
225 | } |
226 | ||
60b3c27f | 227 | static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp) |
47ff3de9 | 228 | { |
9a5595ab VR |
229 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
230 | int ret, i, count, num_ctrls; | |
231 | ||
232 | num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; | |
233 | ||
234 | /** | |
235 | * Need to make sure all MSI status bits read 0 before exiting. | |
236 | * Else, new MSI IRQs are not registered by the wrapper. Have an | |
237 | * upperbound for the loop and exit the IRQ in case of IRQ flood | |
238 | * to avoid locking up system in interrupt context. | |
239 | */ | |
240 | count = 0; | |
241 | do { | |
242 | ret = 0; | |
243 | ||
244 | for (i = 0; i < num_ctrls; i++) | |
245 | ret |= dra7xx_pcie_handle_msi(pp, i); | |
246 | count++; | |
247 | } while (ret && count <= 1000); | |
248 | ||
249 | if (count > 1000) | |
250 | dev_warn_ratelimited(pci->dev, | |
251 | "Too many MSI IRQs to handle\n"); | |
252 | } | |
253 | ||
254 | static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc) | |
255 | { | |
256 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
257 | struct dra7xx_pcie *dra7xx; | |
60b3c27f | 258 | struct dw_pcie_rp *pp; |
9a5595ab | 259 | struct dw_pcie *pci; |
09b2d203 | 260 | unsigned long reg; |
d21faba1 | 261 | u32 bit; |
47ff3de9 | 262 | |
9a5595ab VR |
263 | chained_irq_enter(chip, desc); |
264 | ||
265 | pp = irq_desc_get_handler_data(desc); | |
266 | pci = to_dw_pcie_from_pp(pp); | |
267 | dra7xx = to_dra7xx_pcie(pci); | |
268 | ||
47ff3de9 | 269 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); |
9a5595ab | 270 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); |
47ff3de9 KVA |
271 | |
272 | switch (reg) { | |
273 | case MSI: | |
9a5595ab | 274 | dra7xx_pcie_handle_msi_irq(pp); |
47ff3de9 KVA |
275 | break; |
276 | case INTA: | |
277 | case INTB: | |
278 | case INTC: | |
279 | case INTD: | |
d21faba1 MZ |
280 | for_each_set_bit(bit, ®, PCI_NUM_INTX) |
281 | generic_handle_domain_irq(dra7xx->irq_domain, bit); | |
47ff3de9 KVA |
282 | break; |
283 | } | |
284 | ||
9a5595ab | 285 | chained_irq_exit(chip, desc); |
47ff3de9 KVA |
286 | } |
287 | ||
47ff3de9 KVA |
288 | static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) |
289 | { | |
290 | struct dra7xx_pcie *dra7xx = arg; | |
442ec4c0 KVA |
291 | struct dw_pcie *pci = dra7xx->pci; |
292 | struct device *dev = pci->dev; | |
608793e2 | 293 | struct dw_pcie_ep *ep = &pci->ep; |
47ff3de9 KVA |
294 | u32 reg; |
295 | ||
296 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); | |
297 | ||
298 | if (reg & ERR_SYS) | |
c7f8146b | 299 | dev_dbg(dev, "System Error\n"); |
47ff3de9 KVA |
300 | |
301 | if (reg & ERR_FATAL) | |
c7f8146b | 302 | dev_dbg(dev, "Fatal Error\n"); |
47ff3de9 KVA |
303 | |
304 | if (reg & ERR_NONFATAL) | |
c7f8146b | 305 | dev_dbg(dev, "Non Fatal Error\n"); |
47ff3de9 KVA |
306 | |
307 | if (reg & ERR_COR) | |
c7f8146b | 308 | dev_dbg(dev, "Correctable Error\n"); |
47ff3de9 KVA |
309 | |
310 | if (reg & ERR_AXI) | |
c7f8146b | 311 | dev_dbg(dev, "AXI tag lookup fatal Error\n"); |
47ff3de9 KVA |
312 | |
313 | if (reg & ERR_ECRC) | |
c7f8146b | 314 | dev_dbg(dev, "ECRC Error\n"); |
47ff3de9 KVA |
315 | |
316 | if (reg & PME_TURN_OFF) | |
c7f8146b | 317 | dev_dbg(dev, |
47ff3de9 KVA |
318 | "Power Management Event Turn-Off message received\n"); |
319 | ||
320 | if (reg & PME_TO_ACK) | |
c7f8146b | 321 | dev_dbg(dev, |
47ff3de9 KVA |
322 | "Power Management Turn-Off Ack message received\n"); |
323 | ||
324 | if (reg & PM_PME) | |
c7f8146b | 325 | dev_dbg(dev, "PM Power Management Event message received\n"); |
47ff3de9 KVA |
326 | |
327 | if (reg & LINK_REQ_RST) | |
c7f8146b | 328 | dev_dbg(dev, "Link Request Reset\n"); |
47ff3de9 | 329 | |
608793e2 KVA |
330 | if (reg & LINK_UP_EVT) { |
331 | if (dra7xx->mode == DW_PCIE_EP_TYPE) | |
332 | dw_pcie_ep_linkup(ep); | |
c7f8146b | 333 | dev_dbg(dev, "Link-up state change\n"); |
608793e2 | 334 | } |
47ff3de9 KVA |
335 | |
336 | if (reg & CFG_BME_EVT) | |
c7f8146b | 337 | dev_dbg(dev, "CFG 'Bus Master Enable' change\n"); |
47ff3de9 KVA |
338 | |
339 | if (reg & CFG_MSE_EVT) | |
c7f8146b | 340 | dev_dbg(dev, "CFG 'Memory Space Enable' change\n"); |
47ff3de9 KVA |
341 | |
342 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); | |
343 | ||
344 | return IRQ_HANDLED; | |
345 | } | |
346 | ||
60b3c27f | 347 | static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp) |
9a5595ab VR |
348 | { |
349 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); | |
350 | struct device *dev = pci->dev; | |
351 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
352 | struct device_node *node = dev->of_node; | |
353 | struct device_node *pcie_intc_node = of_get_next_child(node, NULL); | |
354 | ||
355 | if (!pcie_intc_node) { | |
356 | dev_err(dev, "No PCIe Intc node found\n"); | |
357 | return -ENODEV; | |
358 | } | |
359 | ||
360 | irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler, | |
361 | pp); | |
362 | dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, | |
363 | &intx_domain_ops, pp); | |
364 | of_node_put(pcie_intc_node); | |
365 | if (!dra7xx->irq_domain) { | |
366 | dev_err(dev, "Failed to get a INTx IRQ domain\n"); | |
367 | return -ENODEV; | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
9a5595ab VR |
373 | static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = { |
374 | .host_init = dra7xx_pcie_host_init, | |
9a5595ab VR |
375 | }; |
376 | ||
608793e2 KVA |
377 | static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) |
378 | { | |
379 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); | |
380 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
85aa1399 KVA |
381 | enum pci_barno bar; |
382 | ||
c9c13ba4 | 383 | for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) |
85aa1399 | 384 | dw_pcie_ep_reset_bar(pci, bar); |
608793e2 KVA |
385 | |
386 | dra7xx_pcie_enable_wrapper_interrupts(dra7xx); | |
387 | } | |
388 | ||
c5d973a0 | 389 | static void dra7xx_pcie_raise_intx_irq(struct dra7xx_pcie *dra7xx) |
608793e2 KVA |
390 | { |
391 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1); | |
392 | mdelay(1); | |
393 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1); | |
394 | } | |
395 | ||
396 | static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, | |
397 | u8 interrupt_num) | |
398 | { | |
399 | u32 reg; | |
400 | ||
401 | reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; | |
402 | reg |= MSI_REQ_GRANT; | |
403 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); | |
404 | } | |
405 | ||
16093362 | 406 | static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, |
74955cb8 | 407 | unsigned int type, u16 interrupt_num) |
608793e2 KVA |
408 | { |
409 | struct dw_pcie *pci = to_dw_pcie_from_ep(ep); | |
410 | struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); | |
411 | ||
412 | switch (type) { | |
74955cb8 | 413 | case PCI_IRQ_INTX: |
c5d973a0 | 414 | dra7xx_pcie_raise_intx_irq(dra7xx); |
608793e2 | 415 | break; |
74955cb8 | 416 | case PCI_IRQ_MSI: |
608793e2 KVA |
417 | dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num); |
418 | break; | |
419 | default: | |
420 | dev_err(pci->dev, "UNKNOWN IRQ type\n"); | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
4894467e KVA |
426 | static const struct pci_epc_features dra7xx_pcie_epc_features = { |
427 | .linkup_notifier = true, | |
428 | .msi_capable = true, | |
429 | .msix_capable = false, | |
430 | }; | |
431 | ||
432 | static const struct pci_epc_features* | |
433 | dra7xx_pcie_get_features(struct dw_pcie_ep *ep) | |
434 | { | |
435 | return &dra7xx_pcie_epc_features; | |
436 | } | |
437 | ||
626961dd | 438 | static const struct dw_pcie_ep_ops pcie_ep_ops = { |
608793e2 KVA |
439 | .ep_init = dra7xx_pcie_ep_init, |
440 | .raise_irq = dra7xx_pcie_raise_irq, | |
4894467e | 441 | .get_features = dra7xx_pcie_get_features, |
608793e2 KVA |
442 | }; |
443 | ||
e259c292 TL |
444 | static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, |
445 | struct platform_device *pdev) | |
608793e2 KVA |
446 | { |
447 | int ret; | |
448 | struct dw_pcie_ep *ep; | |
608793e2 KVA |
449 | struct device *dev = &pdev->dev; |
450 | struct dw_pcie *pci = dra7xx->pci; | |
451 | ||
452 | ep = &pci->ep; | |
453 | ep->ops = &pcie_ep_ops; | |
454 | ||
936fa5cd | 455 | pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics"); |
011cb23c GP |
456 | if (IS_ERR(pci->dbi_base)) |
457 | return PTR_ERR(pci->dbi_base); | |
608793e2 | 458 | |
936fa5cd DZ |
459 | pci->dbi_base2 = |
460 | devm_platform_ioremap_resource_byname(pdev, "ep_dbics2"); | |
011cb23c GP |
461 | if (IS_ERR(pci->dbi_base2)) |
462 | return PTR_ERR(pci->dbi_base2); | |
608793e2 | 463 | |
608793e2 KVA |
464 | ret = dw_pcie_ep_init(ep); |
465 | if (ret) { | |
466 | dev_err(dev, "failed to initialize endpoint\n"); | |
467 | return ret; | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
e259c292 TL |
473 | static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, |
474 | struct platform_device *pdev) | |
47ff3de9 KVA |
475 | { |
476 | int ret; | |
442ec4c0 | 477 | struct dw_pcie *pci = dra7xx->pci; |
60b3c27f | 478 | struct dw_pcie_rp *pp = &pci->pp; |
442ec4c0 | 479 | struct device *dev = pci->dev; |
47ff3de9 KVA |
480 | |
481 | pp->irq = platform_get_irq(pdev, 1); | |
caecb05c | 482 | if (pp->irq < 0) |
2f3ec752 | 483 | return pp->irq; |
47ff3de9 | 484 | |
5bcb1757 | 485 | /* MSI IRQ is muxed */ |
db388348 | 486 | pp->msi_irq[0] = -ENODEV; |
5bcb1757 | 487 | |
ebe85a44 KVA |
488 | ret = dra7xx_pcie_init_irq_domain(pp); |
489 | if (ret < 0) | |
490 | return ret; | |
47ff3de9 | 491 | |
936fa5cd | 492 | pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics"); |
011cb23c GP |
493 | if (IS_ERR(pci->dbi_base)) |
494 | return PTR_ERR(pci->dbi_base); | |
47ff3de9 | 495 | |
71890ea0 NC |
496 | pp->ops = &dra7xx_pcie_host_ops; |
497 | ||
47ff3de9 KVA |
498 | ret = dw_pcie_host_init(pp); |
499 | if (ret) { | |
c7f8146b | 500 | dev_err(dev, "failed to initialize host\n"); |
47ff3de9 KVA |
501 | return ret; |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
442ec4c0 | 507 | static const struct dw_pcie_ops dw_pcie_ops = { |
2ed6cc71 | 508 | .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup, |
608793e2 KVA |
509 | .start_link = dra7xx_pcie_establish_link, |
510 | .stop_link = dra7xx_pcie_stop_link, | |
442ec4c0 KVA |
511 | .link_up = dra7xx_pcie_link_up, |
512 | }; | |
513 | ||
1f6c4501 KVA |
514 | static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) |
515 | { | |
516 | int phy_count = dra7xx->phy_count; | |
517 | ||
518 | while (phy_count--) { | |
519 | phy_power_off(dra7xx->phy[phy_count]); | |
520 | phy_exit(dra7xx->phy[phy_count]); | |
521 | } | |
522 | } | |
523 | ||
524 | static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx) | |
525 | { | |
526 | int phy_count = dra7xx->phy_count; | |
527 | int ret; | |
528 | int i; | |
529 | ||
530 | for (i = 0; i < phy_count; i++) { | |
65c839a1 KVA |
531 | ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE); |
532 | if (ret < 0) | |
533 | goto err_phy; | |
534 | ||
1f6c4501 KVA |
535 | ret = phy_init(dra7xx->phy[i]); |
536 | if (ret < 0) | |
537 | goto err_phy; | |
538 | ||
539 | ret = phy_power_on(dra7xx->phy[i]); | |
540 | if (ret < 0) { | |
541 | phy_exit(dra7xx->phy[i]); | |
542 | goto err_phy; | |
543 | } | |
544 | } | |
545 | ||
546 | return 0; | |
547 | ||
548 | err_phy: | |
549 | while (--i >= 0) { | |
550 | phy_power_off(dra7xx->phy[i]); | |
551 | phy_exit(dra7xx->phy[i]); | |
552 | } | |
553 | ||
554 | return ret; | |
555 | } | |
556 | ||
608793e2 KVA |
557 | static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = { |
558 | .mode = DW_PCIE_RC_TYPE, | |
559 | }; | |
560 | ||
561 | static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { | |
562 | .mode = DW_PCIE_EP_TYPE, | |
563 | }; | |
564 | ||
c232c0df KVA |
565 | static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { |
566 | .b1co_mode_sel_mask = BIT(2), | |
567 | .mode = DW_PCIE_RC_TYPE, | |
568 | }; | |
569 | ||
570 | static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = { | |
571 | .b1co_mode_sel_mask = GENMASK(3, 2), | |
572 | .mode = DW_PCIE_RC_TYPE, | |
573 | }; | |
574 | ||
575 | static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { | |
576 | .b1co_mode_sel_mask = BIT(2), | |
577 | .mode = DW_PCIE_EP_TYPE, | |
578 | }; | |
579 | ||
580 | static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = { | |
581 | .b1co_mode_sel_mask = GENMASK(3, 2), | |
582 | .mode = DW_PCIE_EP_TYPE, | |
583 | }; | |
584 | ||
608793e2 KVA |
585 | static const struct of_device_id of_dra7xx_pcie_match[] = { |
586 | { | |
587 | .compatible = "ti,dra7-pcie", | |
588 | .data = &dra7xx_pcie_rc_of_data, | |
589 | }, | |
590 | { | |
591 | .compatible = "ti,dra7-pcie-ep", | |
592 | .data = &dra7xx_pcie_ep_of_data, | |
593 | }, | |
c232c0df KVA |
594 | { |
595 | .compatible = "ti,dra746-pcie-rc", | |
596 | .data = &dra746_pcie_rc_of_data, | |
597 | }, | |
598 | { | |
599 | .compatible = "ti,dra726-pcie-rc", | |
600 | .data = &dra726_pcie_rc_of_data, | |
601 | }, | |
602 | { | |
603 | .compatible = "ti,dra746-pcie-ep", | |
604 | .data = &dra746_pcie_ep_of_data, | |
605 | }, | |
606 | { | |
607 | .compatible = "ti,dra726-pcie-ep", | |
608 | .data = &dra726_pcie_ep_of_data, | |
609 | }, | |
608793e2 KVA |
610 | {}, |
611 | }; | |
3b868d15 | 612 | MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match); |
608793e2 | 613 | |
f7a2757f | 614 | /* |
726d75a6 | 615 | * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 |
f7a2757f KVA |
616 | * @dra7xx: the dra7xx device where the workaround should be applied |
617 | * | |
618 | * Access to the PCIe slave port that are not 32-bit aligned will result | |
619 | * in incorrect mapping to TLP Address and Byte enable fields. Therefore, | |
620 | * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or | |
621 | * 0x3. | |
622 | * | |
623 | * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. | |
624 | */ | |
726d75a6 | 625 | static int dra7xx_pcie_unaligned_memaccess(struct device *dev) |
f7a2757f KVA |
626 | { |
627 | int ret; | |
628 | struct device_node *np = dev->of_node; | |
629 | struct of_phandle_args args; | |
630 | struct regmap *regmap; | |
631 | ||
632 | regmap = syscon_regmap_lookup_by_phandle(np, | |
633 | "ti,syscon-unaligned-access"); | |
634 | if (IS_ERR(regmap)) { | |
635 | dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
639 | ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access", | |
640 | 2, 0, &args); | |
641 | if (ret) { | |
642 | dev_err(dev, "failed to parse ti,syscon-unaligned-access\n"); | |
643 | return ret; | |
644 | } | |
645 | ||
646 | ret = regmap_update_bits(regmap, args.args[0], args.args[1], | |
647 | args.args[1]); | |
648 | if (ret) | |
649 | dev_err(dev, "failed to enable unaligned access\n"); | |
650 | ||
651 | of_node_put(args.np); | |
652 | ||
653 | return ret; | |
654 | } | |
655 | ||
c232c0df KVA |
656 | static int dra7xx_pcie_configure_two_lane(struct device *dev, |
657 | u32 b1co_mode_sel_mask) | |
658 | { | |
659 | struct device_node *np = dev->of_node; | |
660 | struct regmap *pcie_syscon; | |
661 | unsigned int pcie_reg; | |
662 | u32 mask; | |
663 | u32 val; | |
664 | ||
665 | pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel"); | |
666 | if (IS_ERR(pcie_syscon)) { | |
667 | dev_err(dev, "unable to get ti,syscon-lane-sel\n"); | |
668 | return -EINVAL; | |
669 | } | |
670 | ||
671 | if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1, | |
672 | &pcie_reg)) { | |
673 | dev_err(dev, "couldn't get lane selection reg offset\n"); | |
674 | return -EINVAL; | |
675 | } | |
676 | ||
677 | mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN; | |
678 | val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN; | |
679 | regmap_update_bits(pcie_syscon, pcie_reg, mask, val); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
e259c292 | 684 | static int dra7xx_pcie_probe(struct platform_device *pdev) |
47ff3de9 KVA |
685 | { |
686 | u32 reg; | |
687 | int ret; | |
688 | int irq; | |
689 | int i; | |
690 | int phy_count; | |
691 | struct phy **phy; | |
7a4db656 | 692 | struct device_link **link; |
47ff3de9 | 693 | void __iomem *base; |
442ec4c0 | 694 | struct dw_pcie *pci; |
442ec4c0 | 695 | struct dra7xx_pcie *dra7xx; |
47ff3de9 KVA |
696 | struct device *dev = &pdev->dev; |
697 | struct device_node *np = dev->of_node; | |
698 | char name[10]; | |
602d38bc | 699 | struct gpio_desc *reset; |
608793e2 KVA |
700 | const struct dra7xx_pcie_of_data *data; |
701 | enum dw_pcie_device_mode mode; | |
c232c0df | 702 | u32 b1co_mode_sel_mask; |
608793e2 | 703 | |
dc078f15 FF |
704 | data = of_device_get_match_data(dev); |
705 | if (!data) | |
608793e2 KVA |
706 | return -EINVAL; |
707 | ||
608793e2 | 708 | mode = (enum dw_pcie_device_mode)data->mode; |
c232c0df | 709 | b1co_mode_sel_mask = data->b1co_mode_sel_mask; |
47ff3de9 KVA |
710 | |
711 | dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); | |
712 | if (!dra7xx) | |
713 | return -ENOMEM; | |
714 | ||
442ec4c0 KVA |
715 | pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); |
716 | if (!pci) | |
717 | return -ENOMEM; | |
718 | ||
719 | pci->dev = dev; | |
720 | pci->ops = &dw_pcie_ops; | |
721 | ||
47ff3de9 | 722 | irq = platform_get_irq(pdev, 0); |
caecb05c | 723 | if (irq < 0) |
a0d21ba1 | 724 | return irq; |
47ff3de9 | 725 | |
c8a11977 WY |
726 | base = devm_platform_ioremap_resource_byname(pdev, "ti_conf"); |
727 | if (IS_ERR(base)) | |
728 | return PTR_ERR(base); | |
47ff3de9 KVA |
729 | |
730 | phy_count = of_property_count_strings(np, "phy-names"); | |
731 | if (phy_count < 0) { | |
732 | dev_err(dev, "unable to find the strings\n"); | |
733 | return phy_count; | |
734 | } | |
735 | ||
a86854d0 | 736 | phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); |
47ff3de9 KVA |
737 | if (!phy) |
738 | return -ENOMEM; | |
739 | ||
a86854d0 | 740 | link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); |
7a4db656 KVA |
741 | if (!link) |
742 | return -ENOMEM; | |
743 | ||
5af94053 LC |
744 | dra7xx->clk = devm_clk_get_optional(dev, NULL); |
745 | if (IS_ERR(dra7xx->clk)) | |
746 | return dev_err_probe(dev, PTR_ERR(dra7xx->clk), | |
747 | "clock request failed"); | |
748 | ||
749 | ret = clk_prepare_enable(dra7xx->clk); | |
750 | if (ret) | |
751 | return ret; | |
752 | ||
47ff3de9 KVA |
753 | for (i = 0; i < phy_count; i++) { |
754 | snprintf(name, sizeof(name), "pcie-phy%d", i); | |
755 | phy[i] = devm_phy_get(dev, name); | |
756 | if (IS_ERR(phy[i])) | |
757 | return PTR_ERR(phy[i]); | |
7a4db656 KVA |
758 | |
759 | link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); | |
760 | if (!link[i]) { | |
761 | ret = -EINVAL; | |
762 | goto err_link; | |
763 | } | |
47ff3de9 KVA |
764 | } |
765 | ||
766 | dra7xx->base = base; | |
767 | dra7xx->phy = phy; | |
442ec4c0 | 768 | dra7xx->pci = pci; |
47ff3de9 KVA |
769 | dra7xx->phy_count = phy_count; |
770 | ||
c232c0df KVA |
771 | if (phy_count == 2) { |
772 | ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); | |
773 | if (ret < 0) | |
774 | dra7xx->phy_count = 1; /* Fallback to x1 lane mode */ | |
775 | } | |
776 | ||
1f6c4501 KVA |
777 | ret = dra7xx_pcie_enable_phy(dra7xx); |
778 | if (ret) { | |
779 | dev_err(dev, "failed to enable phy\n"); | |
780 | return ret; | |
781 | } | |
782 | ||
9bcf0a6f KVA |
783 | platform_set_drvdata(pdev, dra7xx); |
784 | ||
47ff3de9 KVA |
785 | pm_runtime_enable(dev); |
786 | ret = pm_runtime_get_sync(dev); | |
d3f4caa3 | 787 | if (ret < 0) { |
47ff3de9 | 788 | dev_err(dev, "pm_runtime_get_sync failed\n"); |
0e2bdb0e | 789 | goto err_get_sync; |
47ff3de9 KVA |
790 | } |
791 | ||
602d38bc KVA |
792 | reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); |
793 | if (IS_ERR(reset)) { | |
794 | ret = PTR_ERR(reset); | |
795 | dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); | |
78bdcad0 | 796 | goto err_gpio; |
47ff3de9 KVA |
797 | } |
798 | ||
799 | reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); | |
800 | reg &= ~LTSSM_EN; | |
801 | dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); | |
802 | ||
608793e2 KVA |
803 | switch (mode) { |
804 | case DW_PCIE_RC_TYPE: | |
f1aba0a0 NC |
805 | if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) { |
806 | ret = -ENODEV; | |
807 | goto err_gpio; | |
808 | } | |
809 | ||
608793e2 KVA |
810 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, |
811 | DEVICE_TYPE_RC); | |
726d75a6 V |
812 | |
813 | ret = dra7xx_pcie_unaligned_memaccess(dev); | |
814 | if (ret) | |
815 | dev_err(dev, "WA for Errata i870 not applied\n"); | |
816 | ||
608793e2 KVA |
817 | ret = dra7xx_add_pcie_port(dra7xx, pdev); |
818 | if (ret < 0) | |
819 | goto err_gpio; | |
820 | break; | |
821 | case DW_PCIE_EP_TYPE: | |
f1aba0a0 NC |
822 | if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) { |
823 | ret = -ENODEV; | |
824 | goto err_gpio; | |
825 | } | |
826 | ||
608793e2 KVA |
827 | dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, |
828 | DEVICE_TYPE_EP); | |
f7a2757f | 829 | |
726d75a6 | 830 | ret = dra7xx_pcie_unaligned_memaccess(dev); |
f7a2757f KVA |
831 | if (ret) |
832 | goto err_gpio; | |
833 | ||
608793e2 KVA |
834 | ret = dra7xx_add_pcie_ep(dra7xx, pdev); |
835 | if (ret < 0) | |
836 | goto err_gpio; | |
837 | break; | |
838 | default: | |
839 | dev_err(dev, "INVALID device type %d\n", mode); | |
840 | } | |
841 | dra7xx->mode = mode; | |
47ff3de9 | 842 | |
da87d35a | 843 | ret = devm_request_threaded_irq(dev, irq, NULL, dra7xx_pcie_irq_handler, |
d4c7d1a0 K |
844 | IRQF_SHARED, "dra7xx-pcie-main", dra7xx); |
845 | if (ret) { | |
846 | dev_err(dev, "failed to request irq\n"); | |
847 | goto err_gpio; | |
848 | } | |
849 | ||
47ff3de9 KVA |
850 | return 0; |
851 | ||
78bdcad0 | 852 | err_gpio: |
0e2bdb0e | 853 | err_get_sync: |
c2615d62 | 854 | pm_runtime_put(dev); |
47ff3de9 | 855 | pm_runtime_disable(dev); |
1f6c4501 | 856 | dra7xx_pcie_disable_phy(dra7xx); |
47ff3de9 | 857 | |
7a4db656 KVA |
858 | err_link: |
859 | while (--i >= 0) | |
860 | device_link_del(link[i]); | |
861 | ||
47ff3de9 KVA |
862 | return ret; |
863 | } | |
864 | ||
389c7094 KVA |
865 | static int dra7xx_pcie_suspend(struct device *dev) |
866 | { | |
867 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
442ec4c0 | 868 | struct dw_pcie *pci = dra7xx->pci; |
389c7094 KVA |
869 | u32 val; |
870 | ||
608793e2 KVA |
871 | if (dra7xx->mode != DW_PCIE_RC_TYPE) |
872 | return 0; | |
873 | ||
389c7094 | 874 | /* clear MSE */ |
442ec4c0 | 875 | val = dw_pcie_readl_dbi(pci, PCI_COMMAND); |
389c7094 | 876 | val &= ~PCI_COMMAND_MEMORY; |
442ec4c0 | 877 | dw_pcie_writel_dbi(pci, PCI_COMMAND, val); |
389c7094 KVA |
878 | |
879 | return 0; | |
880 | } | |
881 | ||
882 | static int dra7xx_pcie_resume(struct device *dev) | |
883 | { | |
884 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
442ec4c0 | 885 | struct dw_pcie *pci = dra7xx->pci; |
389c7094 KVA |
886 | u32 val; |
887 | ||
608793e2 KVA |
888 | if (dra7xx->mode != DW_PCIE_RC_TYPE) |
889 | return 0; | |
890 | ||
389c7094 | 891 | /* set MSE */ |
442ec4c0 | 892 | val = dw_pcie_readl_dbi(pci, PCI_COMMAND); |
389c7094 | 893 | val |= PCI_COMMAND_MEMORY; |
442ec4c0 | 894 | dw_pcie_writel_dbi(pci, PCI_COMMAND, val); |
389c7094 KVA |
895 | |
896 | return 0; | |
897 | } | |
898 | ||
e52eb445 KVA |
899 | static int dra7xx_pcie_suspend_noirq(struct device *dev) |
900 | { | |
901 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
e52eb445 | 902 | |
1f6c4501 | 903 | dra7xx_pcie_disable_phy(dra7xx); |
e52eb445 KVA |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static int dra7xx_pcie_resume_noirq(struct device *dev) | |
909 | { | |
910 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
e52eb445 | 911 | int ret; |
e52eb445 | 912 | |
1f6c4501 KVA |
913 | ret = dra7xx_pcie_enable_phy(dra7xx); |
914 | if (ret) { | |
915 | dev_err(dev, "failed to enable phy\n"); | |
916 | return ret; | |
e52eb445 KVA |
917 | } |
918 | ||
919 | return 0; | |
e52eb445 | 920 | } |
e52eb445 | 921 | |
4751fac7 | 922 | static void dra7xx_pcie_shutdown(struct platform_device *pdev) |
9c049bea K |
923 | { |
924 | struct device *dev = &pdev->dev; | |
925 | struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); | |
926 | int ret; | |
927 | ||
928 | dra7xx_pcie_stop_link(dra7xx->pci); | |
929 | ||
930 | ret = pm_runtime_put_sync(dev); | |
931 | if (ret < 0) | |
932 | dev_dbg(dev, "pm_runtime_put_sync failed\n"); | |
933 | ||
934 | pm_runtime_disable(dev); | |
935 | dra7xx_pcie_disable_phy(dra7xx); | |
5af94053 LC |
936 | |
937 | clk_disable_unprepare(dra7xx->clk); | |
9c049bea K |
938 | } |
939 | ||
e52eb445 | 940 | static const struct dev_pm_ops dra7xx_pcie_pm_ops = { |
19b7858c BH |
941 | SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume) |
942 | NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq, | |
943 | dra7xx_pcie_resume_noirq) | |
e52eb445 KVA |
944 | }; |
945 | ||
47ff3de9 | 946 | static struct platform_driver dra7xx_pcie_driver = { |
e259c292 | 947 | .probe = dra7xx_pcie_probe, |
47ff3de9 KVA |
948 | .driver = { |
949 | .name = "dra7-pcie", | |
47ff3de9 | 950 | .of_match_table = of_dra7xx_pcie_match, |
d29438d6 | 951 | .suppress_bind_attrs = true, |
e52eb445 | 952 | .pm = &dra7xx_pcie_pm_ops, |
47ff3de9 | 953 | }, |
9c049bea | 954 | .shutdown = dra7xx_pcie_shutdown, |
47ff3de9 | 955 | }; |
3b868d15 LC |
956 | module_platform_driver(dra7xx_pcie_driver); |
957 | ||
958 | MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); | |
959 | MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs"); | |
960 | MODULE_LICENSE("GPL v2"); |