[people/ms/u-boot.git] / drivers / pci / fsl_pci_init.c

/*
 * Copyright 2007-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
 *
 * Initialize controller and call the common driver/pci pci_hose_scan to
 * scan for bridges and devices.
 *
 * Hose fields which need to be pre-initialized by board specific code:
 *   regions[]
 *   first_busno
 *
 * Fields updated:
 *   last_busno
 */

#include <pci.h>
#include <asm/io.h>
#include <asm/fsl_pci.h>

/* Freescale-specific PCI config registers */
#define FSL_PCI_PBFR		0x44
#define FSL_PCIE_CAP_ID		0x4c
#define FSL_PCIE_CFG_RDY	0x4b0
#define FSL_PROG_IF_AGENT	0x1

void pciauto_prescan_setup_bridge(struct pci_controller *hose,
				pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
				pci_dev_t dev, int sub_bus);
void pciauto_config_init(struct pci_controller *hose);

#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif

#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
#define CONFIG_SYS_PCI_MEMORY_PHYS 0
#endif

#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
#endif

/* Setup one inbound ATMU window.
 *
 * We let the caller decide what the window size should be
 */
static void set_inbound_window(volatile pit_t *pi,
				struct pci_region *r,
				u64 size)
{
	u32 sz = (__ilog2_u64(size) - 1);
	u32 flag = PIWAR_EN | PIWAR_LOCAL |
			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;

	out_be32(&pi->pitar, r->phys_start >> 12);
	out_be32(&pi->piwbar, r->bus_start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&pi->piwbear, r->bus_start >> 44);
#else
	out_be32(&pi->piwbear, 0);
#endif
	if (r->flags & PCI_REGION_PREFETCH)
		flag |= PIWAR_PF;
	out_be32(&pi->piwar, flag | sz);
}

int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;

	pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

	return fsl_is_pci_agent(hose);
}

static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
					 u64 out_lo, u8 pcie_cap,
					 volatile pit_t *pi)
{
	struct pci_region *r = hose->regions + hose->region_count;
	u64 sz = min((u64)gd->ram_size, (1ull << 32));

	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	pci_size_t pci_sz;

	/* we have no space available for inbound memory mapping */
	if (bus_start > out_lo) {
		printf ("no space for inbound mapping of memory\n");
		return 0;
	}

	/* limit size */
	if ((bus_start + sz) > out_lo) {
		sz = out_lo - bus_start;
		debug ("limiting size to %llx\n", sz);
	}

	pci_sz = 1ull << __ilog2_u64(sz);
	/*
	 * we can overlap inbound/outbound windows on PCI-E since RX & TX
	 * links a separate
	 */
	if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
		debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
			(u64)bus_start, (u64)phys_start, (u64)sz);
		pci_set_region(r, bus_start, phys_start, sz,
				PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
				PCI_REGION_PREFETCH);

		/* if we aren't an exact power of two match, pci_sz is smaller
		 * round it up to the next power of two.  We report the actual
		 * size to pci region tracking.
		 */
		if (pci_sz != sz)
			sz = 2ull << __ilog2_u64(sz);

		set_inbound_window(pi--, r++, sz);
		sz = 0; /* make sure we dont set the R2 window */
	} else {
		debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
		pci_set_region(r, bus_start, phys_start, pci_sz,
				PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
				PCI_REGION_PREFETCH);
		set_inbound_window(pi--, r++, pci_sz);

		sz -= pci_sz;
		bus_start += pci_sz;
		phys_start += pci_sz;

		pci_sz = 1ull << __ilog2_u64(sz);
		if (sz) {
			debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
				(u64)bus_start, (u64)phys_start, (u64)pci_sz);
			pci_set_region(r, bus_start, phys_start, pci_sz,
					PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
					PCI_REGION_PREFETCH);
			set_inbound_window(pi--, r++, pci_sz);
			sz -= pci_sz;
			bus_start += pci_sz;
			phys_start += pci_sz;
		}
	}

#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	/*
	 * On 64-bit capable systems, set up a mapping for all of DRAM
	 * in high pci address space.
	 */
	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
	/* round up to the next largest power of two */
	if (gd->ram_size > pci_sz)
		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
	debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
		(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
		(u64)pci_sz);
	pci_set_region(r,
			CONFIG_SYS_PCI64_MEMORY_BUS,
			CONFIG_SYS_PCI_MEMORY_PHYS,
			pci_sz,
			PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
			PCI_REGION_PREFETCH);
	set_inbound_window(pi--, r++, pci_sz);
#else
	pci_sz = 1ull << __ilog2_u64(sz);
	if (sz) {
		debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
			(u64)bus_start, (u64)phys_start, (u64)pci_sz);
		pci_set_region(r, bus_start, phys_start, pci_sz,
				PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
				PCI_REGION_PREFETCH);
		sz -= pci_sz;
		bus_start += pci_sz;
		phys_start += pci_sz;
		set_inbound_window(pi--, r++, pci_sz);
	}
#endif

#ifdef CONFIG_PHYS_64BIT
	if (sz && (((u64)gd->ram_size) < (1ull << 32)))
		printf("Was not able to map all of memory via "
			"inbound windows -- %lld remaining\n", sz);
#endif

	hose->region_count = r - hose->regions;

	return 1;
}

void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
{
	u16 temp16;
	u32 temp32;
	int enabled, r, inbound = 0;
	u16 ltssm;
	u8 temp8, pcie_cap;
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
	struct pci_region *reg = hose->regions + hose->region_count;
	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);

	/* Initialize ATMU registers based on hose regions and flags */
	volatile pot_t *po = &pci->pot[1];	/* skip 0 */
	volatile pit_t *pi = &pci->pit[2];	/* ranges from: 3 to 1 */

	u64 out_hi = 0, out_lo = -1ULL;
	u32 pcicsrbar, pcicsrbar_sz;

#ifdef DEBUG
	int neg_link_w;
#endif

	pci_setup_indirect(hose, cfg_addr, cfg_data);

	/* Handle setup of outbound windows first */
	for (r = 0; r < hose->region_count; r++) {
		unsigned long flags = hose->regions[r].flags;
		u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);

		flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
		if (flags != PCI_REGION_SYS_MEMORY) {
			u64 start = hose->regions[r].bus_start;
			u64 end = start + hose->regions[r].size;

			out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
			out_be32(&po->potar, start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
			out_be32(&po->potear, start >> 44);
#else
			out_be32(&po->potear, 0);
#endif
			if (hose->regions[r].flags & PCI_REGION_IO) {
				out_be32(&po->powar, POWAR_EN | sz |
					POWAR_IO_READ | POWAR_IO_WRITE);
			} else {
				out_be32(&po->powar, POWAR_EN | sz |
					POWAR_MEM_READ | POWAR_MEM_WRITE);
				out_lo = min(start, out_lo);
				out_hi = max(end, out_hi);
			}
			po++;
		}
	}
	debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);

	/* setup PCSRBAR/PEXCSRBAR */
	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
	pcicsrbar_sz = ~pcicsrbar_sz + 1;

	if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
		(out_lo > 0x100000000ull))
		pcicsrbar = 0x100000000ull - pcicsrbar_sz;
	else
		pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);

	out_lo = min(out_lo, (u64)pcicsrbar);

	debug("PCICSRBAR @ 0x%x\n", pcicsrbar);

	pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
			pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
	hose->region_count++;

	/* see if we are a PCIe or PCI controller */
	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);

	/* inbound */
	inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);

	for (r = 0; r < hose->region_count; r++)
		debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
			(u64)hose->regions[r].phys_start,
			hose->regions[r].bus_start,
			hose->regions[r].size,
			hose->regions[r].flags);

	pci_register_hose(hose);
	pciauto_config_init(hose);	/* grab pci_{mem,prefetch,io} */
	hose->current_busno = hose->first_busno;

	out_be32(&pci->pedr, 0xffffffff);	/* Clear any errors */
	out_be32(&pci->peer, ~0x20140);	/* Enable All Error Interupts except
					 * - Master abort (pci)
					 * - Master PERR (pci)
					 * - ICCA (PCIe)
					 */
	pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
	temp32 |= 0xf000e;		/* set URR, FER, NFER (but not CER) */
	pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);

	if (pcie_cap == PCI_CAP_ID_EXP) {
		pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
		enabled = ltssm >= PCI_LTSSM_L0;

#ifdef CONFIG_FSL_PCIE_RESET
		if (ltssm == 1) {
			int i;
			debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
			/* assert PCIe reset */
			setbits_be32(&pci->pdb_stat, 0x08000000);
			(void) in_be32(&pci->pdb_stat);
			udelay(100);
			debug("  Asserting PCIe reset @%x = %x\n",
			      &pci->pdb_stat, in_be32(&pci->pdb_stat));
			/* clear PCIe reset */
			clrbits_be32(&pci->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
				pci_hose_read_config_word(hose, dev, PCI_LTSSM,
							&ltssm);
				udelay(1000);
				debug("....PCIe link error. "
				      "LTSSM=0x%02x.\n", ltssm);
			}
			enabled = ltssm >= PCI_LTSSM_L0;

			/* we need to re-write the bar0 since a reset will
			 * clear it
			 */
			pci_hose_write_config_dword(hose, dev,
					PCI_BASE_ADDRESS_0, pcicsrbar);
		}
#endif

		if (!enabled) {
			debug("....PCIE link error.  Skipping scan."
			      "LTSSM=0x%02x\n", ltssm);
			hose->last_busno = hose->first_busno;
			return;
		}

		out_be32(&pci->pme_msg_det, 0xffffffff);
		out_be32(&pci->pme_msg_int_en, 0xffffffff);
#ifdef DEBUG
		pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
		neg_link_w = (temp16 & 0x3f0 ) >> 4;
		printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
		      ltssm, neg_link_w);
#endif
		hose->current_busno++; /* Start scan with secondary */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
	}

	/* Use generic setup_device to initialize standard pci regs,
	 * but do not allocate any windows since any BAR found (such
	 * as PCSRBAR) is not in this cpu's memory space.
	 */
	pciauto_setup_device(hose, dev, 0, hose->pci_mem,
			     hose->pci_prefetch, hose->pci_io);

	if (inbound) {
		pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
		pci_hose_write_config_word(hose, dev, PCI_COMMAND,
					   temp16 | PCI_COMMAND_MEMORY);
	}

#ifndef CONFIG_PCI_NOSCAN
	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);

	/* Programming Interface (PCI_CLASS_PROG)
	 * 0 == pci host or pcie root-complex,
	 * 1 == pci agent or pcie end-point
	 */
	if (!temp8) {
		printf("               Scanning PCI bus %02x\n",
			hose->current_busno);
		hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
	} else {
		debug("               Not scanning PCI bus %02x. PI=%x\n",
			hose->current_busno, temp8);
		hose->last_busno = hose->current_busno;
	}

	/* if we are PCIe - update limit regs and subordinate busno
	 * for the virtual P2P bridge
	 */
	if (pcie_cap == PCI_CAP_ID_EXP) {
		pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
	}
#else
	hose->last_busno = hose->current_busno;
#endif

	/* Clear all error indications */
	if (pcie_cap == PCI_CAP_ID_EXP)
		out_be32(&pci->pme_msg_det, 0xffffffff);
	out_be32(&pci->pedr, 0xffffffff);

	pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
	if (temp16) {
		pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
	}

	pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
	if (temp16) {
		pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
	}
}

int fsl_is_pci_agent(struct pci_controller *hose)
{
	u8 prog_if;
	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);

	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);

	return (prog_if == FSL_PROG_IF_AGENT);
}

int fsl_pci_init_port(struct fsl_pci_info *pci_info,
			struct pci_controller *hose, int busno)
{
	volatile ccsr_fsl_pci_t *pci;
	struct pci_region *r;

	pci = (ccsr_fsl_pci_t *) pci_info->regs;

	/* on non-PCIe controllers we don't have pme_msg_det so this code
	 * should do nothing since the read will return 0
	 */
	if (in_be32(&pci->pme_msg_det)) {
		out_be32(&pci->pme_msg_det, 0xffffffff);
		debug (" with errors.  Clearing.  Now 0x%08x",
			pci->pme_msg_det);
	}

	r = hose->regions + hose->region_count;

	/* outbound memory */
	pci_set_region(r++,
			pci_info->mem_bus,
			pci_info->mem_phys,
			pci_info->mem_size,
			PCI_REGION_MEM);

	/* outbound io */
	pci_set_region(r++,
			pci_info->io_bus,
			pci_info->io_phys,
			pci_info->io_size,
			PCI_REGION_IO);

	hose->region_count = r - hose->regions;
	hose->first_busno = busno;

	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

	if (fsl_is_pci_agent(hose)) {
		fsl_pci_config_unlock(hose);
		hose->last_busno = hose->first_busno;
	}

	printf("    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
			hose->first_busno, hose->last_busno);

	return(hose->last_busno + 1);
}

/* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose)
{
	pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
	u8 agent;
	u8 pcie_cap;
	u16 pbfr;

	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
	if (!agent)
		return;

	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
	if (pcie_cap != 0x0) {
		/* PCIe - set CFG_READY bit of Configuration Ready Register */
		pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
	} else {
		/* PCI - clear ACL bit of PBFR */
		pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
		pbfr &= ~0x20;
		pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
	}
}

#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>

void ft_fsl_pci_setup(void *blob, const char *pci_alias,
			struct pci_controller *hose)
{
	int off = fdt_path_offset(blob, pci_alias);

	if (off >= 0) {
		u32 bus_range[2];

		bus_range[0] = 0;
		bus_range[1] = hose->last_busno - hose->first_busno;
		fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
		fdt_pci_dma_ranges(blob, off, hose);
	}
}
#endif
Commit	Line	Data
63cec581	1	/*
715d8f76	2	* Copyright 2007-2009 Freescale Semiconductor, Inc.
63cec581 ES	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	16	* MA 02111-1307 USA
	17	*/
2e4d94f1	18
63cec581 ES	19	#include <common.h>
63cec581 ES	20
b9a1fa97 KG	21	DECLARE_GLOBAL_DATA_PTR;
b9a1fa97 KG	22
63cec581 ES	23	/*
	24	* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
	25	*
	26	* Initialize controller and call the common driver/pci pci_hose_scan to
	27	* scan for bridges and devices.
	28	*
	29	* Hose fields which need to be pre-initialized by board specific code:
	30	* regions[]
	31	* first_busno
	32	*
	33	* Fields updated:
	34	* last_busno
	35	*/
	36
	37	#include <pci.h>
ad19e7a5	38	#include <asm/io.h>
c8514622	39	#include <asm/fsl_pci.h>
63cec581	40
7a897959 PT	41	/* Freescale-specific PCI config registers */
	42	#define FSL_PCI_PBFR 0x44
	43	#define FSL_PCIE_CAP_ID 0x4c
	44	#define FSL_PCIE_CFG_RDY 0x4b0
715d8f76	45	#define FSL_PROG_IF_AGENT 0x1
7a897959	46
63cec581 ES	47	void pciauto_prescan_setup_bridge(struct pci_controller *hose,
	48	pci_dev_t dev, int sub_bus);
	49	void pciauto_postscan_setup_bridge(struct pci_controller *hose,
	50	pci_dev_t dev, int sub_bus);
63cec581	51	void pciauto_config_init(struct pci_controller *hose);
612ea010	52
b9a1fa97 KG	53	#ifndef CONFIG_SYS_PCI_MEMORY_BUS
	54	#define CONFIG_SYS_PCI_MEMORY_BUS 0
	55	#endif
	56
	57	#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
	58	#define CONFIG_SYS_PCI_MEMORY_PHYS 0
	59	#endif
	60
	61	#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
	62	#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull10241024*1024)
	63	#endif
	64
ad19e7a5 KG	65	/* Setup one inbound ATMU window.
	66	*
	67	* We let the caller decide what the window size should be
	68	*/
	69	static void set_inbound_window(volatile pit_t *pi,
	70	struct pci_region *r,
	71	u64 size)
b9a1fa97	72	{
ad19e7a5 KG	73	u32 sz = (__ilog2_u64(size) - 1);
	74	u32 flag = PIWAR_EN \| PIWAR_LOCAL \|
	75	PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP;
	76
	77	out_be32(&pi->pitar, r->phys_start >> 12);
	78	out_be32(&pi->piwbar, r->bus_start >> 12);
	79	#ifdef CONFIG_SYS_PCI_64BIT
	80	out_be32(&pi->piwbear, r->bus_start >> 44);
	81	#else
	82	out_be32(&pi->piwbear, 0);
	83	#endif
	84	if (r->flags & PCI_REGION_PREFETCH)
	85	flag \|= PIWAR_PF;
	86	out_be32(&pi->piwar, flag \| sz);
	87	}
	88
ee53650d KG	89	int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
	90	{
	91	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) addr;
	92
	93	pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
	94
	95	return fsl_is_pci_agent(hose);
	96	}
	97
ad19e7a5 KG	98	static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
	99	u64 out_lo, u8 pcie_cap,
	100	volatile pit_t *pi)
	101	{
	102	struct pci_region *r = hose->regions + hose->region_count;
	103	u64 sz = min((u64)gd->ram_size, (1ull << 32));
b9a1fa97 KG	104
	105	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	106	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
ad19e7a5	107	pci_size_t pci_sz;
b9a1fa97	108
ad19e7a5 KG	109	/* we have no space available for inbound memory mapping */
	110	if (bus_start > out_lo) {
	111	printf ("no space for inbound mapping of memory\n");
	112	return 0;
	113	}
b9a1fa97	114
ad19e7a5 KG	115	/* limit size */
	116	if ((bus_start + sz) > out_lo) {
	117	sz = out_lo - bus_start;
	118	debug ("limiting size to %llx\n", sz);
	119	}
b9a1fa97 KG	120
b9a1fa97 KG	121	pci_sz = 1ull << __ilog2_u64(sz);
ad19e7a5 KG	122	/*
	123	* we can overlap inbound/outbound windows on PCI-E since RX & TX
	124	* links a separate
	125	*/
	126	if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
	127	debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
	128	(u64)bus_start, (u64)phys_start, (u64)sz);
	129	pci_set_region(r, bus_start, phys_start, sz,
	130	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY \|
	131	PCI_REGION_PREFETCH);
	132
	133	/* if we aren't an exact power of two match, pci_sz is smaller
	134	* round it up to the next power of two. We report the actual
	135	* size to pci region tracking.
	136	*/
	137	if (pci_sz != sz)
	138	sz = 2ull << __ilog2_u64(sz);
	139
	140	set_inbound_window(pi--, r++, sz);
	141	sz = 0; /* make sure we dont set the R2 window */
	142	} else {
	143	debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
b9a1fa97	144	(u64)bus_start, (u64)phys_start, (u64)pci_sz);
ad19e7a5	145	pci_set_region(r, bus_start, phys_start, pci_sz,
ff4e66e9	146	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY \|
b9a1fa97	147	PCI_REGION_PREFETCH);
ad19e7a5 KG	148	set_inbound_window(pi--, r++, pci_sz);
ad19e7a5 KG	149
b9a1fa97 KG	150	sz -= pci_sz;
	151	bus_start += pci_sz;
	152	phys_start += pci_sz;
ad19e7a5 KG	153
	154	pci_sz = 1ull << __ilog2_u64(sz);
	155	if (sz) {
	156	debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
	157	(u64)bus_start, (u64)phys_start, (u64)pci_sz);
	158	pci_set_region(r, bus_start, phys_start, pci_sz,
	159	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY \|
	160	PCI_REGION_PREFETCH);
	161	set_inbound_window(pi--, r++, pci_sz);
	162	sz -= pci_sz;
	163	bus_start += pci_sz;
	164	phys_start += pci_sz;
	165	}
b9a1fa97 KG	166	}
	167
	168	#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
cd425162 BB	169	/*
	170	* On 64-bit capable systems, set up a mapping for all of DRAM
	171	* in high pci address space.
	172	*/
b9a1fa97 KG	173	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
	174	/* round up to the next largest power of two */
	175	if (gd->ram_size > pci_sz)
cd425162	176	pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
b9a1fa97	177	debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
cd425162	178	(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
b9a1fa97 KG	179	(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
b9a1fa97 KG	180	(u64)pci_sz);
ad19e7a5	181	pci_set_region(r,
cd425162	182	CONFIG_SYS_PCI64_MEMORY_BUS,
b9a1fa97 KG	183	CONFIG_SYS_PCI_MEMORY_PHYS,
b9a1fa97 KG	184	pci_sz,
ff4e66e9	185	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY \|
b9a1fa97	186	PCI_REGION_PREFETCH);
ad19e7a5	187	set_inbound_window(pi--, r++, pci_sz);
b9a1fa97 KG	188	#else
	189	pci_sz = 1ull << __ilog2_u64(sz);
	190	if (sz) {
	191	debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
	192	(u64)bus_start, (u64)phys_start, (u64)pci_sz);
ad19e7a5	193	pci_set_region(r, bus_start, phys_start, pci_sz,
ff4e66e9	194	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY \|
b9a1fa97 KG	195	PCI_REGION_PREFETCH);
	196	sz -= pci_sz;
	197	bus_start += pci_sz;
	198	phys_start += pci_sz;
ad19e7a5	199	set_inbound_window(pi--, r++, pci_sz);
b9a1fa97 KG	200	}
	201	#endif
	202
4c253fdb	203	#ifdef CONFIG_PHYS_64BIT
b9a1fa97 KG	204	if (sz && (((u64)gd->ram_size) < (1ull << 32)))
	205	printf("Was not able to map all of memory via "
	206	"inbound windows -- %lld remaining\n", sz);
4c253fdb	207	#endif
b9a1fa97	208
ad19e7a5 KG	209	hose->region_count = r - hose->regions;
	210
	211	return 1;
b9a1fa97 KG	212	}
b9a1fa97 KG	213
fb3143b3	214	void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
63cec581 ES	215	{
	216	u16 temp16;
	217	u32 temp32;
8295b944	218	int enabled, r, inbound = 0;
63cec581	219	u16 ltssm;
8295b944	220	u8 temp8, pcie_cap;
fb3143b3	221	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t )cfg_addr;
cb151aa2	222	struct pci_region *reg = hose->regions + hose->region_count;
8295b944	223	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
63cec581 ES	224
63cec581 ES	225	/* Initialize ATMU registers based on hose regions and flags */
d0ff51ba	226	volatile pot_t po = &pci->pot[1]; / skip 0 */
ad19e7a5 KG	227	volatile pit_t pi = &pci->pit[2]; / ranges from: 3 to 1 */
	228
	229	u64 out_hi = 0, out_lo = -1ULL;
	230	u32 pcicsrbar, pcicsrbar_sz;
63cec581 ES	231
	232	#ifdef DEBUG
	233	int neg_link_w;
	234	#endif
	235
fb3143b3 KG	236	pci_setup_indirect(hose, cfg_addr, cfg_data);
fb3143b3 KG	237
ad19e7a5 KG	238	/* Handle setup of outbound windows first */
	239	for (r = 0; r < hose->region_count; r++) {
	240	unsigned long flags = hose->regions[r].flags;
	241	u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
cb151aa2	242
ad19e7a5 KG	243	flags &= PCI_REGION_SYS_MEMORY\|PCI_REGION_TYPE;
	244	if (flags != PCI_REGION_SYS_MEMORY) {
	245	u64 start = hose->regions[r].bus_start;
	246	u64 end = start + hose->regions[r].size;
cb151aa2	247
ad19e7a5 KG	248	out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
ad19e7a5 KG	249	out_be32(&po->potar, start >> 12);
612ea010	250	#ifdef CONFIG_SYS_PCI_64BIT
ad19e7a5	251	out_be32(&po->potear, start >> 44);
612ea010	252	#else
ad19e7a5	253	out_be32(&po->potear, 0);
612ea010	254	#endif
ad19e7a5 KG	255	if (hose->regions[r].flags & PCI_REGION_IO) {
	256	out_be32(&po->powar, POWAR_EN \| sz \|
	257	POWAR_IO_READ \| POWAR_IO_WRITE);
	258	} else {
	259	out_be32(&po->powar, POWAR_EN \| sz \|
	260	POWAR_MEM_READ \| POWAR_MEM_WRITE);
	261	out_lo = min(start, out_lo);
	262	out_hi = max(end, out_hi);
	263	}
63cec581 ES	264	po++;
	265	}
	266	}
ad19e7a5 KG	267	debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
	268
	269	/* setup PCSRBAR/PEXCSRBAR */
	270	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
	271	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
	272	pcicsrbar_sz = ~pcicsrbar_sz + 1;
	273
	274	if (out_hi < (0x100000000ull - pcicsrbar_sz) \|\|
	275	(out_lo > 0x100000000ull))
	276	pcicsrbar = 0x100000000ull - pcicsrbar_sz;
	277	else
	278	pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
	279	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
	280
	281	out_lo = min(out_lo, (u64)pcicsrbar);
	282
	283	debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
	284
	285	pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
	286	pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
	287	hose->region_count++;
63cec581	288
8295b944 KG	289	/* see if we are a PCIe or PCI controller */
	290	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
	291
ad19e7a5 KG	292	/* inbound */
	293	inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
	294
	295	for (r = 0; r < hose->region_count; r++)
	296	debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
	297	(u64)hose->regions[r].phys_start,
	298	hose->regions[r].bus_start,
	299	hose->regions[r].size,
	300	hose->regions[r].flags);
	301
63cec581 ES	302	pci_register_hose(hose);
	303	pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
	304	hose->current_busno = hose->first_busno;
	305
ad19e7a5 KG	306	out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
ad19e7a5 KG	307	out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
2e4d94f1 ES	308	* - Master abort (pci)
	309	* - Master PERR (pci)
	310	* - ICCA (PCIe)
	311	*/
ad19e7a5	312	pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
63cec581 ES	313	temp32 \|= 0xf000e; /* set URR, FER, NFER (but not CER) */
	314	pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
	315
8295b944	316	if (pcie_cap == PCI_CAP_ID_EXP) {
63cec581 ES	317	pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
	318	enabled = ltssm >= PCI_LTSSM_L0;
	319
8ff3de61 KG	320	#ifdef CONFIG_FSL_PCIE_RESET
	321	if (ltssm == 1) {
	322	int i;
ad19e7a5 KG	323	debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
	324	/* assert PCIe reset */
	325	setbits_be32(&pci->pdb_stat, 0x08000000);
	326	(void) in_be32(&pci->pdb_stat);
8ff3de61 KG	327	udelay(100);
8ff3de61 KG	328	debug(" Asserting PCIe reset @%x = %x\n",
ad19e7a5 KG	329	&pci->pdb_stat, in_be32(&pci->pdb_stat));
	330	/* clear PCIe reset */
	331	clrbits_be32(&pci->pdb_stat, 0x08000000);
8ff3de61 KG	332	asm("sync;isync");
	333	for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
	334	pci_hose_read_config_word(hose, dev, PCI_LTSSM,
	335	&ltssm);
	336	udelay(1000);
	337	debug("....PCIe link error. "
	338	"LTSSM=0x%02x.\n", ltssm);
	339	}
	340	enabled = ltssm >= PCI_LTSSM_L0;
ad19e7a5 KG	341
	342	/* we need to re-write the bar0 since a reset will
	343	* clear it
	344	*/
	345	pci_hose_write_config_dword(hose, dev,
	346	PCI_BASE_ADDRESS_0, pcicsrbar);
8ff3de61 KG	347	}
	348	#endif
	349
63cec581 ES	350	if (!enabled) {
63cec581 ES	351	debug("....PCIE link error. Skipping scan."
2e4d94f1	352	"LTSSM=0x%02x\n", ltssm);
63cec581 ES	353	hose->last_busno = hose->first_busno;
	354	return;
	355	}
	356
ad19e7a5 KG	357	out_be32(&pci->pme_msg_det, 0xffffffff);
ad19e7a5 KG	358	out_be32(&pci->pme_msg_int_en, 0xffffffff);
63cec581 ES	359	#ifdef DEBUG
	360	pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
	361	neg_link_w = (temp16 & 0x3f0 ) >> 4;
2e4d94f1	362	printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
63cec581 ES	363	ltssm, neg_link_w);
	364	#endif
	365	hose->current_busno++; /* Start scan with secondary */
	366	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
63cec581 ES	367	}
63cec581 ES	368
16e23c3f ES	369	/* Use generic setup_device to initialize standard pci regs,
	370	* but do not allocate any windows since any BAR found (such
	371	* as PCSRBAR) is not in this cpu's memory space.
	372	*/
16e23c3f	373	pciauto_setup_device(hose, dev, 0, hose->pci_mem,
63cec581	374	hose->pci_prefetch, hose->pci_io);
16e23c3f	375
cb8250fe ES	376	if (inbound) {
	377	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
	378	pci_hose_write_config_word(hose, dev, PCI_COMMAND,
	379	temp16 \| PCI_COMMAND_MEMORY);
	380	}
	381
2e4d94f1	382	#ifndef CONFIG_PCI_NOSCAN
6df0efd5 ES	383	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
	384
	385	/* Programming Interface (PCI_CLASS_PROG)
	386	* 0 == pci host or pcie root-complex,
	387	* 1 == pci agent or pcie end-point
	388	*/
	389	if (!temp8) {
	390	printf(" Scanning PCI bus %02x\n",
	391	hose->current_busno);
	392	hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
	393	} else {
	394	debug(" Not scanning PCI bus %02x. PI=%x\n",
	395	hose->current_busno, temp8);
	396	hose->last_busno = hose->current_busno;
	397	}
63cec581	398
8295b944 KG	399	/* if we are PCIe - update limit regs and subordinate busno
	400	* for the virtual P2P bridge
	401	*/
	402	if (pcie_cap == PCI_CAP_ID_EXP) {
63cec581 ES	403	pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
63cec581 ES	404	}
2e4d94f1 ES	405	#else
	406	hose->last_busno = hose->current_busno;
	407	#endif
63cec581 ES	408
63cec581 ES	409	/* Clear all error indications */
8295b944	410	if (pcie_cap == PCI_CAP_ID_EXP)
ad19e7a5 KG	411	out_be32(&pci->pme_msg_det, 0xffffffff);
ad19e7a5 KG	412	out_be32(&pci->pedr, 0xffffffff);
63cec581 ES	413
	414	pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
	415	if (temp16) {
8295b944	416	pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
63cec581 ES	417	}
	418
	419	pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
	420	if (temp16) {
63cec581 ES	421	pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
	422	}
	423	}
a2aab460	424
715d8f76 ES	425	int fsl_is_pci_agent(struct pci_controller *hose)
	426	{
	427	u8 prog_if;
	428	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
	429
	430	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
	431
	432	return (prog_if == FSL_PROG_IF_AGENT);
	433	}
	434
0d3d68b2	435	int fsl_pci_init_port(struct fsl_pci_info *pci_info,
01471d53	436	struct pci_controller *hose, int busno)
0d3d68b2 PA	437	{
	438	volatile ccsr_fsl_pci_t *pci;
	439	struct pci_region *r;
	440
	441	pci = (ccsr_fsl_pci_t *) pci_info->regs;
	442
	443	/* on non-PCIe controllers we don't have pme_msg_det so this code
	444	* should do nothing since the read will return 0
	445	*/
	446	if (in_be32(&pci->pme_msg_det)) {
	447	out_be32(&pci->pme_msg_det, 0xffffffff);
	448	debug (" with errors. Clearing. Now 0x%08x",
	449	pci->pme_msg_det);
	450	}
	451
	452	r = hose->regions + hose->region_count;
	453
	454	/* outbound memory */
	455	pci_set_region(r++,
	456	pci_info->mem_bus,
	457	pci_info->mem_phys,
	458	pci_info->mem_size,
	459	PCI_REGION_MEM);
	460
	461	/* outbound io */
	462	pci_set_region(r++,
	463	pci_info->io_bus,
	464	pci_info->io_phys,
	465	pci_info->io_size,
	466	PCI_REGION_IO);
	467
	468	hose->region_count = r - hose->regions;
	469	hose->first_busno = busno;
	470
	471	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
	472
715d8f76 ES	473	if (fsl_is_pci_agent(hose)) {
	474	fsl_pci_config_unlock(hose);
	475	hose->last_busno = hose->first_busno;
	476	}
	477
93a83872	478	printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
0d3d68b2 PA	479	hose->first_busno, hose->last_busno);
	480
	481	return(hose->last_busno + 1);
	482	}
	483
7a897959 PT	484	/* Enable inbound PCI config cycles for agent/endpoint interface */
	485	void fsl_pci_config_unlock(struct pci_controller *hose)
	486	{
	487	pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
	488	u8 agent;
	489	u8 pcie_cap;
	490	u16 pbfr;
	491
	492	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
	493	if (!agent)
	494	return;
	495
	496	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
	497	if (pcie_cap != 0x0) {
	498	/* PCIe - set CFG_READY bit of Configuration Ready Register */
	499	pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
	500	} else {
	501	/* PCI - clear ACL bit of PBFR */
	502	pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
	503	pbfr &= ~0x20;
	504	pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
	505	}
	506	}
	507
a2aab460 KG	508	#ifdef CONFIG_OF_BOARD_SETUP
	509	#include <libfdt.h>
	510	#include <fdt_support.h>
	511
	512	void ft_fsl_pci_setup(void blob, const char pci_alias,
	513	struct pci_controller *hose)
	514	{
	515	int off = fdt_path_offset(blob, pci_alias);
	516
	517	if (off >= 0) {
	518	u32 bus_range[2];
	519
	520	bus_range[0] = 0;
	521	bus_range[1] = hose->last_busno - hose->first_busno;
	522	fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
	523	fdt_pci_dma_ranges(blob, off, hose);
	524	}
	525	}
	526	#endif