[thirdparty/kernel/stable.git] / drivers / pci / pci-bridge-emul.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __PCI_BRIDGE_EMUL_H__
#define __PCI_BRIDGE_EMUL_H__

#include <linux/kernel.h>

/* PCI configuration space of a PCI-to-PCI bridge. */
struct pci_bridge_emul_conf {
	u16 vendor;
	u16 device;
	u16 command;
	u16 status;
	u32 class_revision;
	u8 cache_line_size;
	u8 latency_timer;
	u8 header_type;
	u8 bist;
	u32 bar[2];
	u8 primary_bus;
	u8 secondary_bus;
	u8 subordinate_bus;
	u8 secondary_latency_timer;
	u8 iobase;
	u8 iolimit;
	u16 secondary_status;
	u16 membase;
	u16 memlimit;
	u16 pref_mem_base;
	u16 pref_mem_limit;
	u32 prefbaseupper;
	u32 preflimitupper;
	u16 iobaseupper;
	u16 iolimitupper;
	u8 capabilities_pointer;
	u8 reserve[3];
	u32 romaddr;
	u8 intline;
	u8 intpin;
	u16 bridgectrl;
};

/* PCI configuration space of the PCIe capabilities */
struct pci_bridge_emul_pcie_conf {
	u8 cap_id;
	u8 next;
	u16 cap;
	u32 devcap;
	u16 devctl;
	u16 devsta;
	u32 lnkcap;
	u16 lnkctl;
	u16 lnksta;
	u32 slotcap;
	u16 slotctl;
	u16 slotsta;
	u16 rootctl;
	u16 rsvd;
	u32 rootsta;
	u32 devcap2;
	u16 devctl2;
	u16 devsta2;
	u32 lnkcap2;
	u16 lnkctl2;
	u16 lnksta2;
	u32 slotcap2;
	u16 slotctl2;
	u16 slotsta2;
};

struct pci_bridge_emul;

typedef enum { PCI_BRIDGE_EMUL_HANDLED,
	       PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;

struct pci_bridge_emul_ops {
	/*
	 * Called when reading from the regular PCI bridge
	 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
	 * operation has handled the read operation and filled in the
	 * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
	 * be emulated by the common code by reading from the
	 * in-memory copy of the configuration space.
	 */
	pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
						   int reg, u32 *value);

	/*
	 * Same as ->read_base(), except it is for reading from the
	 * PCIe capability configuration space.
	 */
	pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
						   int reg, u32 *value);
	/*
	 * Called when writing to the regular PCI bridge configuration
	 * space. old is the current value, new is the new value being
	 * written, and mask indicates which parts of the value are
	 * being changed.
	 */
	void (*write_base)(struct pci_bridge_emul *bridge, int reg,
			   u32 old, u32 new, u32 mask);

	/*
	 * Same as ->write_base(), except it is for writing from the
	 * PCIe capability configuration space.
	 */
	void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
			   u32 old, u32 new, u32 mask);
};

struct pci_bridge_reg_behavior;

struct pci_bridge_emul {
	struct pci_bridge_emul_conf conf;
	struct pci_bridge_emul_pcie_conf pcie_conf;
	struct pci_bridge_emul_ops *ops;
	struct pci_bridge_reg_behavior *pci_regs_behavior;
	struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
	void *data;
	bool has_pcie;
};

enum {
	PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0),
};

int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
			 unsigned int flags);
void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);

int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
			      int size, u32 *value);
int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
			       int size, u32 value);

#endif /* __PCI_BRIDGE_EMUL_H__ */
Commit	Line	Data
23a5fba4 TP	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	#ifndef __PCI_BRIDGE_EMUL_H__
	3	#define __PCI_BRIDGE_EMUL_H__
	4
	5	#include <linux/kernel.h>
	6
	7	/* PCI configuration space of a PCI-to-PCI bridge. */
	8	struct pci_bridge_emul_conf {
	9	u16 vendor;
	10	u16 device;
	11	u16 command;
	12	u16 status;
	13	u32 class_revision;
	14	u8 cache_line_size;
	15	u8 latency_timer;
	16	u8 header_type;
	17	u8 bist;
	18	u32 bar[2];
	19	u8 primary_bus;
	20	u8 secondary_bus;
	21	u8 subordinate_bus;
	22	u8 secondary_latency_timer;
	23	u8 iobase;
	24	u8 iolimit;
	25	u16 secondary_status;
	26	u16 membase;
	27	u16 memlimit;
	28	u16 pref_mem_base;
	29	u16 pref_mem_limit;
	30	u32 prefbaseupper;
	31	u32 preflimitupper;
	32	u16 iobaseupper;
	33	u16 iolimitupper;
	34	u8 capabilities_pointer;
	35	u8 reserve[3];
	36	u32 romaddr;
	37	u8 intline;
	38	u8 intpin;
	39	u16 bridgectrl;
	40	};
	41
	42	/* PCI configuration space of the PCIe capabilities */
	43	struct pci_bridge_emul_pcie_conf {
	44	u8 cap_id;
	45	u8 next;
	46	u16 cap;
	47	u32 devcap;
	48	u16 devctl;
	49	u16 devsta;
	50	u32 lnkcap;
	51	u16 lnkctl;
	52	u16 lnksta;
	53	u32 slotcap;
	54	u16 slotctl;
	55	u16 slotsta;
	56	u16 rootctl;
	57	u16 rsvd;
	58	u32 rootsta;
	59	u32 devcap2;
	60	u16 devctl2;
	61	u16 devsta2;
	62	u32 lnkcap2;
	63	u16 lnkctl2;
	64	u16 lnksta2;
65	u32 slotcap2;
66	u16 slotctl2;
67	u16 slotsta2;
68	};
69
70	struct pci_bridge_emul;
71
72	typedef enum { PCI_BRIDGE_EMUL_HANDLED,
73	PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
74
75	struct pci_bridge_emul_ops {
76	/*
77	* Called when reading from the regular PCI bridge
78	* configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
79	* operation has handled the read operation and filled in the
80	* *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
81	* be emulated by the common code by reading from the
82	* in-memory copy of the configuration space.
83	*/
84	pci_bridge_emul_read_status_t (read_base)(struct pci_bridge_emul bridge,
85	int reg, u32 *value);
86
87	/*
88	* Same as ->read_base(), except it is for reading from the
89	* PCIe capability configuration space.
90	*/
91	pci_bridge_emul_read_status_t (read_pcie)(struct pci_bridge_emul bridge,
92	int reg, u32 *value);
93	/*
94	* Called when writing to the regular PCI bridge configuration
95	* space. old is the current value, new is the new value being
96	* written, and mask indicates which parts of the value are
97	* being changed.
98	*/
99	void (write_base)(struct pci_bridge_emul bridge, int reg,
100	u32 old, u32 new, u32 mask);
101
102	/*
103	* Same as ->write_base(), except it is for writing from the
104	* PCIe capability configuration space.
105	*/
106	void (write_pcie)(struct pci_bridge_emul bridge, int reg,
107	u32 old, u32 new, u32 mask);
108	};
109
59f81c35 TP	110	struct pci_bridge_reg_behavior;
59f81c35 TP	111
23a5fba4 TP	112	struct pci_bridge_emul {
	113	struct pci_bridge_emul_conf conf;
	114	struct pci_bridge_emul_pcie_conf pcie_conf;
	115	struct pci_bridge_emul_ops *ops;
59f81c35 TP	116	struct pci_bridge_reg_behavior *pci_regs_behavior;
59f81c35 TP	117	struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
23a5fba4 TP	118	void *data;
	119	bool has_pcie;
	120	};
	121
33776d05 TP	122	enum {
	123	PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0),
	124	};
	125
	126	int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
	127	unsigned int flags);
59f81c35 TP	128	void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);
59f81c35 TP	129
23a5fba4 TP	130	int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
	131	int size, u32 *value);
	132	int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
	133	int size, u32 value);
	134
	135	#endif /* __PCI_BRIDGE_EMUL_H__ */