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Commit | Line | Data |
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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
2 | /* |
3 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Andreas Heppel <aheppel@sysgo.de> | |
5 | * | |
f07771cc | 6 | * (C) Copyright 2002, 2003 |
c609719b | 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
c609719b WD |
8 | */ |
9 | ||
10 | /* | |
2b81e8a3 SG |
11 | * Old PCI routines |
12 | * | |
13 | * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI | |
14 | * and change pci-uclass.c. | |
c609719b WD |
15 | */ |
16 | ||
17 | #include <common.h> | |
18 | ||
c609719b | 19 | #include <command.h> |
250e039d | 20 | #include <errno.h> |
c609719b WD |
21 | #include <asm/processor.h> |
22 | #include <asm/io.h> | |
23 | #include <pci.h> | |
24 | ||
8f9052fd BM |
25 | DECLARE_GLOBAL_DATA_PTR; |
26 | ||
f07771cc | 27 | #define PCI_HOSE_OP(rw, size, type) \ |
53677ef1 WD |
28 | int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ |
29 | pci_dev_t dev, \ | |
f07771cc WD |
30 | int offset, type value) \ |
31 | { \ | |
32 | return hose->rw##_##size(hose, dev, offset, value); \ | |
c609719b WD |
33 | } |
34 | ||
35 | PCI_HOSE_OP(read, byte, u8 *) | |
36 | PCI_HOSE_OP(read, word, u16 *) | |
37 | PCI_HOSE_OP(read, dword, u32 *) | |
38 | PCI_HOSE_OP(write, byte, u8) | |
39 | PCI_HOSE_OP(write, word, u16) | |
40 | PCI_HOSE_OP(write, dword, u32) | |
41 | ||
f07771cc WD |
42 | #define PCI_OP(rw, size, type, error_code) \ |
43 | int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ | |
44 | { \ | |
45 | struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ | |
46 | \ | |
47 | if (!hose) \ | |
48 | { \ | |
49 | error_code; \ | |
50 | return -1; \ | |
51 | } \ | |
52 | \ | |
53 | return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ | |
c609719b WD |
54 | } |
55 | ||
56 | PCI_OP(read, byte, u8 *, *value = 0xff) | |
57 | PCI_OP(read, word, u16 *, *value = 0xffff) | |
58 | PCI_OP(read, dword, u32 *, *value = 0xffffffff) | |
59 | PCI_OP(write, byte, u8, ) | |
60 | PCI_OP(write, word, u16, ) | |
61 | PCI_OP(write, dword, u32, ) | |
62 | ||
f07771cc WD |
63 | #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ |
64 | int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ | |
53677ef1 | 65 | pci_dev_t dev, \ |
f07771cc WD |
66 | int offset, type val) \ |
67 | { \ | |
68 | u32 val32; \ | |
69 | \ | |
815b5bd5 SK |
70 | if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ |
71 | *val = -1; \ | |
f07771cc | 72 | return -1; \ |
815b5bd5 | 73 | } \ |
f07771cc WD |
74 | \ |
75 | *val = (val32 >> ((offset & (int)off_mask) * 8)); \ | |
76 | \ | |
77 | return 0; \ | |
c609719b WD |
78 | } |
79 | ||
f07771cc WD |
80 | #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ |
81 | int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ | |
53677ef1 | 82 | pci_dev_t dev, \ |
f07771cc WD |
83 | int offset, type val) \ |
84 | { \ | |
498b8db7 | 85 | u32 val32, mask, ldata, shift; \ |
f07771cc WD |
86 | \ |
87 | if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ | |
88 | return -1; \ | |
89 | \ | |
498b8db7 WD |
90 | shift = ((offset & (int)off_mask) * 8); \ |
91 | ldata = (((unsigned long)val) & val_mask) << shift; \ | |
92 | mask = val_mask << shift; \ | |
f07771cc WD |
93 | val32 = (val32 & ~mask) | ldata; \ |
94 | \ | |
95 | if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ | |
96 | return -1; \ | |
97 | \ | |
98 | return 0; \ | |
c609719b WD |
99 | } |
100 | ||
101 | PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) | |
102 | PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) | |
103 | PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) | |
104 | PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) | |
105 | ||
106 | /* | |
107 | * | |
108 | */ | |
109 | ||
96d61603 | 110 | static struct pci_controller* hose_head; |
c609719b | 111 | |
8f9052fd BM |
112 | struct pci_controller *pci_get_hose_head(void) |
113 | { | |
114 | if (gd->hose) | |
115 | return gd->hose; | |
116 | ||
117 | return hose_head; | |
118 | } | |
119 | ||
c609719b WD |
120 | void pci_register_hose(struct pci_controller* hose) |
121 | { | |
122 | struct pci_controller **phose = &hose_head; | |
123 | ||
124 | while(*phose) | |
125 | phose = &(*phose)->next; | |
126 | ||
127 | hose->next = NULL; | |
128 | ||
129 | *phose = hose; | |
130 | } | |
131 | ||
cb2bf931 | 132 | struct pci_controller *pci_bus_to_hose(int bus) |
c609719b WD |
133 | { |
134 | struct pci_controller *hose; | |
135 | ||
8f9052fd | 136 | for (hose = pci_get_hose_head(); hose; hose = hose->next) { |
f07771cc | 137 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
c609719b | 138 | return hose; |
cb2bf931 | 139 | } |
c609719b | 140 | |
6902df56 | 141 | printf("pci_bus_to_hose() failed\n"); |
c609719b WD |
142 | return NULL; |
143 | } | |
144 | ||
3a0e3c27 KG |
145 | struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) |
146 | { | |
147 | struct pci_controller *hose; | |
148 | ||
8f9052fd | 149 | for (hose = pci_get_hose_head(); hose; hose = hose->next) { |
3a0e3c27 KG |
150 | if (hose->cfg_addr == cfg_addr) |
151 | return hose; | |
152 | } | |
153 | ||
154 | return NULL; | |
155 | } | |
156 | ||
cc2a8c77 AV |
157 | int pci_last_busno(void) |
158 | { | |
8f9052fd | 159 | struct pci_controller *hose = pci_get_hose_head(); |
cc2a8c77 AV |
160 | |
161 | if (!hose) | |
162 | return -1; | |
163 | ||
164 | while (hose->next) | |
165 | hose = hose->next; | |
166 | ||
167 | return hose->last_busno; | |
168 | } | |
169 | ||
c609719b WD |
170 | pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) |
171 | { | |
172 | struct pci_controller * hose; | |
c609719b | 173 | pci_dev_t bdf; |
aab6724c | 174 | int bus; |
c609719b | 175 | |
8f9052fd | 176 | for (hose = pci_get_hose_head(); hose; hose = hose->next) { |
aab6724c | 177 | for (bus = hose->first_busno; bus <= hose->last_busno; bus++) { |
aab6724c SG |
178 | bdf = pci_hose_find_devices(hose, bus, ids, &index); |
179 | if (bdf != -1) | |
250e039d | 180 | return bdf; |
250e039d SG |
181 | } |
182 | } | |
183 | ||
aab6724c | 184 | return -1; |
c609719b WD |
185 | } |
186 | ||
11503be4 SG |
187 | static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev, |
188 | ulong io, pci_addr_t mem, ulong command) | |
c609719b | 189 | { |
cf5787f2 | 190 | u32 bar_response; |
af778c6d | 191 | unsigned int old_command; |
30e76d5e KG |
192 | pci_addr_t bar_value; |
193 | pci_size_t bar_size; | |
c609719b WD |
194 | unsigned char pin; |
195 | int bar, found_mem64; | |
196 | ||
cb2bf931 AS |
197 | debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, |
198 | (u64)mem, command); | |
c609719b | 199 | |
cb2bf931 | 200 | pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); |
c609719b | 201 | |
252b404d | 202 | for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { |
cb2bf931 AS |
203 | pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); |
204 | pci_hose_read_config_dword(hose, dev, bar, &bar_response); | |
c609719b WD |
205 | |
206 | if (!bar_response) | |
207 | continue; | |
208 | ||
209 | found_mem64 = 0; | |
210 | ||
211 | /* Check the BAR type and set our address mask */ | |
f07771cc | 212 | if (bar_response & PCI_BASE_ADDRESS_SPACE) { |
c609719b | 213 | bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; |
f07771cc | 214 | /* round up region base address to a multiple of size */ |
c609719b | 215 | io = ((io - 1) | (bar_size - 1)) + 1; |
f07771cc WD |
216 | bar_value = io; |
217 | /* compute new region base address */ | |
218 | io = io + bar_size; | |
219 | } else { | |
220 | if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == | |
30e76d5e KG |
221 | PCI_BASE_ADDRESS_MEM_TYPE_64) { |
222 | u32 bar_response_upper; | |
223 | u64 bar64; | |
cb2bf931 AS |
224 | pci_hose_write_config_dword(hose, dev, bar + 4, |
225 | 0xffffffff); | |
226 | pci_hose_read_config_dword(hose, dev, bar + 4, | |
227 | &bar_response_upper); | |
30e76d5e KG |
228 | |
229 | bar64 = ((u64)bar_response_upper << 32) | bar_response; | |
c609719b | 230 | |
30e76d5e KG |
231 | bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; |
232 | found_mem64 = 1; | |
233 | } else { | |
234 | bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); | |
235 | } | |
c609719b | 236 | |
f07771cc | 237 | /* round up region base address to multiple of size */ |
c609719b | 238 | mem = ((mem - 1) | (bar_size - 1)) + 1; |
f07771cc WD |
239 | bar_value = mem; |
240 | /* compute new region base address */ | |
241 | mem = mem + bar_size; | |
c609719b WD |
242 | } |
243 | ||
244 | /* Write it out and update our limit */ | |
30e76d5e | 245 | pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); |
c609719b | 246 | |
f07771cc | 247 | if (found_mem64) { |
c609719b | 248 | bar += 4; |
30e76d5e | 249 | #ifdef CONFIG_SYS_PCI_64BIT |
cb2bf931 AS |
250 | pci_hose_write_config_dword(hose, dev, bar, |
251 | (u32)(bar_value >> 32)); | |
30e76d5e | 252 | #else |
cb2bf931 | 253 | pci_hose_write_config_dword(hose, dev, bar, 0x00000000); |
30e76d5e | 254 | #endif |
c609719b WD |
255 | } |
256 | } | |
257 | ||
258 | /* Configure Cache Line Size Register */ | |
cb2bf931 | 259 | pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
c609719b WD |
260 | |
261 | /* Configure Latency Timer */ | |
cb2bf931 | 262 | pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
c609719b WD |
263 | |
264 | /* Disable interrupt line, if device says it wants to use interrupts */ | |
cb2bf931 | 265 | pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); |
f07771cc | 266 | if (pin != 0) { |
5f48d798 SG |
267 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, |
268 | PCI_INTERRUPT_LINE_DISABLE); | |
c609719b WD |
269 | } |
270 | ||
cb2bf931 AS |
271 | pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); |
272 | pci_hose_write_config_dword(hose, dev, PCI_COMMAND, | |
f07771cc | 273 | (old_command & 0xffff0000) | command); |
c609719b WD |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
278 | /* | |
279 | * | |
280 | */ | |
281 | ||
282 | struct pci_config_table *pci_find_config(struct pci_controller *hose, | |
283 | unsigned short class, | |
284 | unsigned int vendor, | |
285 | unsigned int device, | |
286 | unsigned int bus, | |
287 | unsigned int dev, | |
288 | unsigned int func) | |
289 | { | |
290 | struct pci_config_table *table; | |
291 | ||
f07771cc | 292 | for (table = hose->config_table; table && table->vendor; table++) { |
c609719b WD |
293 | if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && |
294 | (table->device == PCI_ANY_ID || table->device == device) && | |
295 | (table->class == PCI_ANY_ID || table->class == class) && | |
296 | (table->bus == PCI_ANY_ID || table->bus == bus) && | |
297 | (table->dev == PCI_ANY_ID || table->dev == dev) && | |
f07771cc | 298 | (table->func == PCI_ANY_ID || table->func == func)) { |
c609719b WD |
299 | return table; |
300 | } | |
301 | } | |
302 | ||
303 | return NULL; | |
304 | } | |
305 | ||
306 | void pci_cfgfunc_config_device(struct pci_controller *hose, | |
307 | pci_dev_t dev, | |
308 | struct pci_config_table *entry) | |
309 | { | |
cb2bf931 AS |
310 | pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], |
311 | entry->priv[2]); | |
c609719b WD |
312 | } |
313 | ||
314 | void pci_cfgfunc_do_nothing(struct pci_controller *hose, | |
315 | pci_dev_t dev, struct pci_config_table *entry) | |
316 | { | |
317 | } | |
318 | ||
319 | /* | |
cb2bf931 | 320 | * HJF: Changed this to return int. I think this is required |
c7de829c WD |
321 | * to get the correct result when scanning bridges |
322 | */ | |
323 | extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); | |
c609719b | 324 | |
dc1da42f | 325 | #ifdef CONFIG_PCI_SCAN_SHOW |
7b19fd6d | 326 | __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) |
dc1da42f SR |
327 | { |
328 | if (dev == PCI_BDF(hose->first_busno, 0, 0)) | |
329 | return 0; | |
330 | ||
331 | return 1; | |
332 | } | |
dc1da42f SR |
333 | #endif /* CONFIG_PCI_SCAN_SHOW */ |
334 | ||
c609719b WD |
335 | int pci_hose_scan_bus(struct pci_controller *hose, int bus) |
336 | { | |
cb2bf931 | 337 | unsigned int sub_bus, found_multi = 0; |
c609719b WD |
338 | unsigned short vendor, device, class; |
339 | unsigned char header_type; | |
03992ac2 | 340 | #ifndef CONFIG_PCI_PNP |
c609719b | 341 | struct pci_config_table *cfg; |
03992ac2 | 342 | #endif |
c609719b | 343 | pci_dev_t dev; |
009884ae PT |
344 | #ifdef CONFIG_PCI_SCAN_SHOW |
345 | static int indent = 0; | |
346 | #endif | |
c609719b WD |
347 | |
348 | sub_bus = bus; | |
349 | ||
350 | for (dev = PCI_BDF(bus,0,0); | |
cb2bf931 AS |
351 | dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, |
352 | PCI_MAX_PCI_FUNCTIONS - 1); | |
353 | dev += PCI_BDF(0, 0, 1)) { | |
dc1da42f SR |
354 | |
355 | if (pci_skip_dev(hose, dev)) | |
356 | continue; | |
c609719b WD |
357 | |
358 | if (PCI_FUNC(dev) && !found_multi) | |
359 | continue; | |
360 | ||
361 | pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); | |
362 | ||
363 | pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); | |
364 | ||
983eb9d1 PT |
365 | if (vendor == 0xffff || vendor == 0x0000) |
366 | continue; | |
c609719b | 367 | |
983eb9d1 PT |
368 | if (!PCI_FUNC(dev)) |
369 | found_multi = header_type & 0x80; | |
c609719b | 370 | |
cb2bf931 AS |
371 | debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", |
372 | PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); | |
c609719b | 373 | |
983eb9d1 PT |
374 | pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); |
375 | pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); | |
c609719b | 376 | |
0991866c TH |
377 | #ifdef CONFIG_PCI_FIXUP_DEV |
378 | board_pci_fixup_dev(hose, dev, vendor, device, class); | |
379 | #endif | |
380 | ||
a38d216e | 381 | #ifdef CONFIG_PCI_SCAN_SHOW |
009884ae PT |
382 | indent++; |
383 | ||
384 | /* Print leading space, including bus indentation */ | |
385 | printf("%*c", indent + 1, ' '); | |
386 | ||
a38d216e | 387 | if (pci_print_dev(hose, dev)) { |
009884ae PT |
388 | printf("%02x:%02x.%-*x - %04x:%04x - %s\n", |
389 | PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), | |
a38d216e PT |
390 | vendor, device, pci_class_str(class >> 8)); |
391 | } | |
392 | #endif | |
393 | ||
03992ac2 | 394 | #ifdef CONFIG_PCI_PNP |
b4141195 MY |
395 | sub_bus = max((unsigned int)pciauto_config_device(hose, dev), |
396 | sub_bus); | |
03992ac2 | 397 | #else |
983eb9d1 PT |
398 | cfg = pci_find_config(hose, class, vendor, device, |
399 | PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); | |
400 | if (cfg) { | |
401 | cfg->config_device(hose, dev, cfg); | |
b4141195 MY |
402 | sub_bus = max(sub_bus, |
403 | (unsigned int)hose->current_busno); | |
983eb9d1 | 404 | } |
03992ac2 | 405 | #endif |
a38d216e | 406 | |
009884ae PT |
407 | #ifdef CONFIG_PCI_SCAN_SHOW |
408 | indent--; | |
409 | #endif | |
410 | ||
983eb9d1 PT |
411 | if (hose->fixup_irq) |
412 | hose->fixup_irq(hose, dev); | |
c609719b WD |
413 | } |
414 | ||
415 | return sub_bus; | |
416 | } | |
417 | ||
418 | int pci_hose_scan(struct pci_controller *hose) | |
419 | { | |
0da1fb03 | 420 | #if defined(CONFIG_PCI_BOOTDELAY) |
0da1fb03 AG |
421 | char *s; |
422 | int i; | |
423 | ||
8f9052fd | 424 | if (!gd->pcidelay_done) { |
0da1fb03 | 425 | /* wait "pcidelay" ms (if defined)... */ |
00caae6d | 426 | s = env_get("pcidelay"); |
0da1fb03 AG |
427 | if (s) { |
428 | int val = simple_strtoul(s, NULL, 10); | |
429 | for (i = 0; i < val; i++) | |
430 | udelay(1000); | |
431 | } | |
8f9052fd | 432 | gd->pcidelay_done = 1; |
0da1fb03 AG |
433 | } |
434 | #endif /* CONFIG_PCI_BOOTDELAY */ | |
435 | ||
0373a7e9 TH |
436 | #ifdef CONFIG_PCI_SCAN_SHOW |
437 | puts("PCI:\n"); | |
438 | #endif | |
439 | ||
cb2bf931 AS |
440 | /* |
441 | * Start scan at current_busno. | |
40e81add ES |
442 | * PCIe will start scan at first_busno+1. |
443 | */ | |
cb2bf931 | 444 | /* For legacy support, ensure current >= first */ |
40e81add ES |
445 | if (hose->first_busno > hose->current_busno) |
446 | hose->current_busno = hose->first_busno; | |
c609719b WD |
447 | #ifdef CONFIG_PCI_PNP |
448 | pciauto_config_init(hose); | |
449 | #endif | |
40e81add | 450 | return pci_hose_scan_bus(hose, hose->current_busno); |
c609719b WD |
451 | } |
452 | ||
ad10dd9a SR |
453 | void pci_init(void) |
454 | { | |
96d61603 JS |
455 | hose_head = NULL; |
456 | ||
ec21aee6 | 457 | /* allow env to disable pci init/enum */ |
00caae6d | 458 | if (env_get("pcidisable") != NULL) |
ec21aee6 TH |
459 | return; |
460 | ||
ad10dd9a SR |
461 | /* now call board specific pci_init()... */ |
462 | pci_init_board(); | |
463 | } | |
287df01e ZQ |
464 | |
465 | /* Returns the address of the requested capability structure within the | |
466 | * device's PCI configuration space or 0 in case the device does not | |
467 | * support it. | |
468 | * */ | |
469 | int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, | |
470 | int cap) | |
471 | { | |
472 | int pos; | |
473 | u8 hdr_type; | |
474 | ||
475 | pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); | |
476 | ||
477 | pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); | |
478 | ||
479 | if (pos) | |
480 | pos = pci_find_cap(hose, dev, pos, cap); | |
481 | ||
482 | return pos; | |
483 | } | |
484 | ||
485 | /* Find the header pointer to the Capabilities*/ | |
486 | int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, | |
487 | u8 hdr_type) | |
488 | { | |
489 | u16 status; | |
490 | ||
491 | pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); | |
492 | ||
493 | if (!(status & PCI_STATUS_CAP_LIST)) | |
494 | return 0; | |
495 | ||
496 | switch (hdr_type) { | |
497 | case PCI_HEADER_TYPE_NORMAL: | |
498 | case PCI_HEADER_TYPE_BRIDGE: | |
499 | return PCI_CAPABILITY_LIST; | |
500 | case PCI_HEADER_TYPE_CARDBUS: | |
501 | return PCI_CB_CAPABILITY_LIST; | |
502 | default: | |
503 | return 0; | |
504 | } | |
505 | } | |
506 | ||
507 | int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) | |
508 | { | |
509 | int ttl = PCI_FIND_CAP_TTL; | |
510 | u8 id; | |
511 | u8 next_pos; | |
512 | ||
513 | while (ttl--) { | |
514 | pci_hose_read_config_byte(hose, dev, pos, &next_pos); | |
515 | if (next_pos < CAP_START_POS) | |
516 | break; | |
517 | next_pos &= ~3; | |
518 | pos = (int) next_pos; | |
519 | pci_hose_read_config_byte(hose, dev, | |
520 | pos + PCI_CAP_LIST_ID, &id); | |
521 | if (id == 0xff) | |
522 | break; | |
523 | if (id == cap) | |
524 | return pos; | |
525 | pos += PCI_CAP_LIST_NEXT; | |
526 | } | |
527 | return 0; | |
528 | } | |
ed5b580b ML |
529 | |
530 | /** | |
531 | * pci_find_next_ext_capability - Find an extended capability | |
532 | * | |
533 | * Returns the address of the next matching extended capability structure | |
534 | * within the device's PCI configuration space or 0 if the device does | |
535 | * not support it. Some capabilities can occur several times, e.g., the | |
536 | * vendor-specific capability, and this provides a way to find them all. | |
537 | */ | |
538 | int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev, | |
539 | int start, int cap) | |
540 | { | |
541 | u32 header; | |
542 | int ttl, pos = PCI_CFG_SPACE_SIZE; | |
543 | ||
544 | /* minimum 8 bytes per capability */ | |
545 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
546 | ||
547 | if (start) | |
548 | pos = start; | |
549 | ||
550 | pci_hose_read_config_dword(hose, dev, pos, &header); | |
551 | if (header == 0xffffffff || header == 0) | |
552 | return 0; | |
553 | ||
554 | while (ttl-- > 0) { | |
555 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) | |
556 | return pos; | |
557 | ||
558 | pos = PCI_EXT_CAP_NEXT(header); | |
559 | if (pos < PCI_CFG_SPACE_SIZE) | |
560 | break; | |
561 | ||
562 | pci_hose_read_config_dword(hose, dev, pos, &header); | |
563 | if (header == 0xffffffff || header == 0) | |
564 | break; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /** | |
571 | * pci_hose_find_ext_capability - Find an extended capability | |
572 | * | |
573 | * Returns the address of the requested extended capability structure | |
574 | * within the device's PCI configuration space or 0 if the device does | |
575 | * not support it. | |
576 | */ | |
577 | int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev, | |
578 | int cap) | |
579 | { | |
580 | return pci_find_next_ext_capability(hose, dev, 0, cap); | |
581 | } |