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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * | |
f07771cc | 5 | * (C) Copyright 2002, 2003 |
c609719b WD |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
9 | */ |
10 | ||
11 | /* | |
12 | * PCI routines | |
13 | */ | |
14 | ||
15 | #include <common.h> | |
16 | ||
c609719b | 17 | #include <command.h> |
c609719b WD |
18 | #include <asm/processor.h> |
19 | #include <asm/io.h> | |
20 | #include <pci.h> | |
21 | ||
f07771cc | 22 | #define PCI_HOSE_OP(rw, size, type) \ |
53677ef1 WD |
23 | int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ |
24 | pci_dev_t dev, \ | |
f07771cc WD |
25 | int offset, type value) \ |
26 | { \ | |
27 | return hose->rw##_##size(hose, dev, offset, value); \ | |
c609719b WD |
28 | } |
29 | ||
30 | PCI_HOSE_OP(read, byte, u8 *) | |
31 | PCI_HOSE_OP(read, word, u16 *) | |
32 | PCI_HOSE_OP(read, dword, u32 *) | |
33 | PCI_HOSE_OP(write, byte, u8) | |
34 | PCI_HOSE_OP(write, word, u16) | |
35 | PCI_HOSE_OP(write, dword, u32) | |
36 | ||
f07771cc WD |
37 | #define PCI_OP(rw, size, type, error_code) \ |
38 | int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ | |
39 | { \ | |
40 | struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ | |
41 | \ | |
42 | if (!hose) \ | |
43 | { \ | |
44 | error_code; \ | |
45 | return -1; \ | |
46 | } \ | |
47 | \ | |
48 | return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ | |
c609719b WD |
49 | } |
50 | ||
51 | PCI_OP(read, byte, u8 *, *value = 0xff) | |
52 | PCI_OP(read, word, u16 *, *value = 0xffff) | |
53 | PCI_OP(read, dword, u32 *, *value = 0xffffffff) | |
54 | PCI_OP(write, byte, u8, ) | |
55 | PCI_OP(write, word, u16, ) | |
56 | PCI_OP(write, dword, u32, ) | |
57 | ||
f07771cc WD |
58 | #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ |
59 | int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ | |
53677ef1 | 60 | pci_dev_t dev, \ |
f07771cc WD |
61 | int offset, type val) \ |
62 | { \ | |
63 | u32 val32; \ | |
64 | \ | |
815b5bd5 SK |
65 | if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \ |
66 | *val = -1; \ | |
f07771cc | 67 | return -1; \ |
815b5bd5 | 68 | } \ |
f07771cc WD |
69 | \ |
70 | *val = (val32 >> ((offset & (int)off_mask) * 8)); \ | |
71 | \ | |
72 | return 0; \ | |
c609719b WD |
73 | } |
74 | ||
f07771cc WD |
75 | #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ |
76 | int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ | |
53677ef1 | 77 | pci_dev_t dev, \ |
f07771cc WD |
78 | int offset, type val) \ |
79 | { \ | |
498b8db7 | 80 | u32 val32, mask, ldata, shift; \ |
f07771cc WD |
81 | \ |
82 | if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ | |
83 | return -1; \ | |
84 | \ | |
498b8db7 WD |
85 | shift = ((offset & (int)off_mask) * 8); \ |
86 | ldata = (((unsigned long)val) & val_mask) << shift; \ | |
87 | mask = val_mask << shift; \ | |
f07771cc WD |
88 | val32 = (val32 & ~mask) | ldata; \ |
89 | \ | |
90 | if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ | |
91 | return -1; \ | |
92 | \ | |
93 | return 0; \ | |
c609719b WD |
94 | } |
95 | ||
96 | PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) | |
97 | PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) | |
98 | PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) | |
99 | PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) | |
100 | ||
6e61fae4 BB |
101 | /* Get a virtual address associated with a BAR region */ |
102 | void *pci_map_bar(pci_dev_t pdev, int bar, int flags) | |
103 | { | |
104 | pci_addr_t pci_bus_addr; | |
cf5787f2 | 105 | u32 bar_response; |
6e61fae4 BB |
106 | |
107 | /* read BAR address */ | |
108 | pci_read_config_dword(pdev, bar, &bar_response); | |
cf5787f2 | 109 | pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); |
6e61fae4 BB |
110 | |
111 | /* | |
112 | * Pass "0" as the length argument to pci_bus_to_virt. The arg | |
113 | * isn't actualy used on any platform because u-boot assumes a static | |
114 | * linear mapping. In the future, this could read the BAR size | |
115 | * and pass that as the size if needed. | |
116 | */ | |
117 | return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE); | |
118 | } | |
119 | ||
c609719b WD |
120 | /* |
121 | * | |
122 | */ | |
123 | ||
96d61603 | 124 | static struct pci_controller* hose_head; |
c609719b WD |
125 | |
126 | void pci_register_hose(struct pci_controller* hose) | |
127 | { | |
128 | struct pci_controller **phose = &hose_head; | |
129 | ||
130 | while(*phose) | |
131 | phose = &(*phose)->next; | |
132 | ||
133 | hose->next = NULL; | |
134 | ||
135 | *phose = hose; | |
136 | } | |
137 | ||
cb2bf931 | 138 | struct pci_controller *pci_bus_to_hose(int bus) |
c609719b WD |
139 | { |
140 | struct pci_controller *hose; | |
141 | ||
cb2bf931 | 142 | for (hose = hose_head; hose; hose = hose->next) { |
f07771cc | 143 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
c609719b | 144 | return hose; |
cb2bf931 | 145 | } |
c609719b | 146 | |
6902df56 | 147 | printf("pci_bus_to_hose() failed\n"); |
c609719b WD |
148 | return NULL; |
149 | } | |
150 | ||
3a0e3c27 KG |
151 | struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) |
152 | { | |
153 | struct pci_controller *hose; | |
154 | ||
155 | for (hose = hose_head; hose; hose = hose->next) { | |
156 | if (hose->cfg_addr == cfg_addr) | |
157 | return hose; | |
158 | } | |
159 | ||
160 | return NULL; | |
161 | } | |
162 | ||
cc2a8c77 AV |
163 | int pci_last_busno(void) |
164 | { | |
165 | struct pci_controller *hose = hose_head; | |
166 | ||
167 | if (!hose) | |
168 | return -1; | |
169 | ||
170 | while (hose->next) | |
171 | hose = hose->next; | |
172 | ||
173 | return hose->last_busno; | |
174 | } | |
175 | ||
c609719b WD |
176 | pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) |
177 | { | |
178 | struct pci_controller * hose; | |
179 | u16 vendor, device; | |
180 | u8 header_type; | |
181 | pci_dev_t bdf; | |
182 | int i, bus, found_multi = 0; | |
183 | ||
cb2bf931 | 184 | for (hose = hose_head; hose; hose = hose->next) { |
6d0f6bcf | 185 | #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
c609719b WD |
186 | for (bus = hose->last_busno; bus >= hose->first_busno; bus--) |
187 | #else | |
188 | for (bus = hose->first_busno; bus <= hose->last_busno; bus++) | |
189 | #endif | |
cb2bf931 | 190 | for (bdf = PCI_BDF(bus, 0, 0); |
f5e0d039 | 191 | #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) |
cb2bf931 AS |
192 | bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, |
193 | PCI_MAX_PCI_FUNCTIONS - 1); | |
c609719b | 194 | #else |
cb2bf931 | 195 | bdf < PCI_BDF(bus + 1, 0, 0); |
c609719b | 196 | #endif |
cb2bf931 | 197 | bdf += PCI_BDF(0, 0, 1)) { |
f07771cc | 198 | if (!PCI_FUNC(bdf)) { |
c609719b WD |
199 | pci_read_config_byte(bdf, |
200 | PCI_HEADER_TYPE, | |
201 | &header_type); | |
202 | ||
203 | found_multi = header_type & 0x80; | |
f07771cc | 204 | } else { |
c609719b WD |
205 | if (!found_multi) |
206 | continue; | |
207 | } | |
208 | ||
209 | pci_read_config_word(bdf, | |
210 | PCI_VENDOR_ID, | |
211 | &vendor); | |
212 | pci_read_config_word(bdf, | |
213 | PCI_DEVICE_ID, | |
214 | &device); | |
215 | ||
cb2bf931 | 216 | for (i = 0; ids[i].vendor != 0; i++) { |
c609719b | 217 | if (vendor == ids[i].vendor && |
cb2bf931 | 218 | device == ids[i].device) { |
c609719b WD |
219 | if (index <= 0) |
220 | return bdf; | |
221 | ||
222 | index--; | |
223 | } | |
cb2bf931 | 224 | } |
c609719b WD |
225 | } |
226 | } | |
227 | ||
cb2bf931 | 228 | return -1; |
c609719b WD |
229 | } |
230 | ||
231 | pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) | |
232 | { | |
233 | static struct pci_device_id ids[2] = {{}, {0, 0}}; | |
234 | ||
235 | ids[0].vendor = vendor; | |
236 | ids[0].device = device; | |
237 | ||
238 | return pci_find_devices(ids, index); | |
239 | } | |
240 | ||
241 | /* | |
242 | * | |
243 | */ | |
244 | ||
cb2bf931 | 245 | int __pci_hose_phys_to_bus(struct pci_controller *hose, |
2d43e873 KG |
246 | phys_addr_t phys_addr, |
247 | unsigned long flags, | |
248 | unsigned long skip_mask, | |
249 | pci_addr_t *ba) | |
c609719b WD |
250 | { |
251 | struct pci_region *res; | |
30e76d5e | 252 | pci_addr_t bus_addr; |
c609719b WD |
253 | int i; |
254 | ||
f07771cc | 255 | for (i = 0; i < hose->region_count; i++) { |
c609719b WD |
256 | res = &hose->regions[i]; |
257 | ||
258 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) | |
259 | continue; | |
260 | ||
2d43e873 KG |
261 | if (res->flags & skip_mask) |
262 | continue; | |
263 | ||
c609719b WD |
264 | bus_addr = phys_addr - res->phys_start + res->bus_start; |
265 | ||
266 | if (bus_addr >= res->bus_start && | |
f07771cc | 267 | bus_addr < res->bus_start + res->size) { |
2d43e873 KG |
268 | *ba = bus_addr; |
269 | return 0; | |
c609719b WD |
270 | } |
271 | } | |
272 | ||
2d43e873 | 273 | return 1; |
c609719b WD |
274 | } |
275 | ||
2d43e873 KG |
276 | pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose, |
277 | phys_addr_t phys_addr, | |
278 | unsigned long flags) | |
c609719b | 279 | { |
2d43e873 KG |
280 | pci_addr_t bus_addr = 0; |
281 | int ret; | |
c609719b | 282 | |
f07771cc | 283 | if (!hose) { |
cb2bf931 | 284 | puts("pci_hose_phys_to_bus: invalid hose\n"); |
2d43e873 | 285 | return bus_addr; |
c609719b WD |
286 | } |
287 | ||
cb2bf931 AS |
288 | /* |
289 | * if PCI_REGION_MEM is set we do a two pass search with preference | |
290 | * on matches that don't have PCI_REGION_SYS_MEMORY set | |
291 | */ | |
2d43e873 KG |
292 | if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { |
293 | ret = __pci_hose_phys_to_bus(hose, phys_addr, | |
294 | flags, PCI_REGION_SYS_MEMORY, &bus_addr); | |
295 | if (!ret) | |
296 | return bus_addr; | |
297 | } | |
298 | ||
299 | ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr); | |
300 | ||
301 | if (ret) | |
cb2bf931 | 302 | puts("pci_hose_phys_to_bus: invalid physical address\n"); |
2d43e873 KG |
303 | |
304 | return bus_addr; | |
305 | } | |
306 | ||
cb2bf931 | 307 | int __pci_hose_bus_to_phys(struct pci_controller *hose, |
2d43e873 KG |
308 | pci_addr_t bus_addr, |
309 | unsigned long flags, | |
310 | unsigned long skip_mask, | |
311 | phys_addr_t *pa) | |
312 | { | |
313 | struct pci_region *res; | |
314 | int i; | |
315 | ||
f07771cc | 316 | for (i = 0; i < hose->region_count; i++) { |
c609719b WD |
317 | res = &hose->regions[i]; |
318 | ||
319 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) | |
320 | continue; | |
321 | ||
2d43e873 KG |
322 | if (res->flags & skip_mask) |
323 | continue; | |
324 | ||
c609719b | 325 | if (bus_addr >= res->bus_start && |
d878c9a9 | 326 | (bus_addr - res->bus_start) < res->size) { |
2d43e873 KG |
327 | *pa = (bus_addr - res->bus_start + res->phys_start); |
328 | return 0; | |
c609719b WD |
329 | } |
330 | } | |
331 | ||
2d43e873 KG |
332 | return 1; |
333 | } | |
334 | ||
335 | phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, | |
336 | pci_addr_t bus_addr, | |
337 | unsigned long flags) | |
338 | { | |
339 | phys_addr_t phys_addr = 0; | |
340 | int ret; | |
341 | ||
342 | if (!hose) { | |
cb2bf931 | 343 | puts("pci_hose_bus_to_phys: invalid hose\n"); |
2d43e873 KG |
344 | return phys_addr; |
345 | } | |
346 | ||
cb2bf931 AS |
347 | /* |
348 | * if PCI_REGION_MEM is set we do a two pass search with preference | |
349 | * on matches that don't have PCI_REGION_SYS_MEMORY set | |
350 | */ | |
2d43e873 KG |
351 | if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) { |
352 | ret = __pci_hose_bus_to_phys(hose, bus_addr, | |
353 | flags, PCI_REGION_SYS_MEMORY, &phys_addr); | |
354 | if (!ret) | |
355 | return phys_addr; | |
356 | } | |
357 | ||
358 | ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr); | |
359 | ||
360 | if (ret) | |
cb2bf931 | 361 | puts("pci_hose_bus_to_phys: invalid physical address\n"); |
c609719b | 362 | |
2d43e873 | 363 | return phys_addr; |
c609719b WD |
364 | } |
365 | ||
366 | /* | |
367 | * | |
368 | */ | |
369 | ||
370 | int pci_hose_config_device(struct pci_controller *hose, | |
371 | pci_dev_t dev, | |
372 | unsigned long io, | |
30e76d5e | 373 | pci_addr_t mem, |
c609719b WD |
374 | unsigned long command) |
375 | { | |
cf5787f2 | 376 | u32 bar_response; |
af778c6d | 377 | unsigned int old_command; |
30e76d5e KG |
378 | pci_addr_t bar_value; |
379 | pci_size_t bar_size; | |
c609719b WD |
380 | unsigned char pin; |
381 | int bar, found_mem64; | |
382 | ||
cb2bf931 AS |
383 | debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io, |
384 | (u64)mem, command); | |
c609719b | 385 | |
cb2bf931 | 386 | pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0); |
c609719b | 387 | |
252b404d | 388 | for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { |
cb2bf931 AS |
389 | pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); |
390 | pci_hose_read_config_dword(hose, dev, bar, &bar_response); | |
c609719b WD |
391 | |
392 | if (!bar_response) | |
393 | continue; | |
394 | ||
395 | found_mem64 = 0; | |
396 | ||
397 | /* Check the BAR type and set our address mask */ | |
f07771cc | 398 | if (bar_response & PCI_BASE_ADDRESS_SPACE) { |
c609719b | 399 | bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; |
f07771cc | 400 | /* round up region base address to a multiple of size */ |
c609719b | 401 | io = ((io - 1) | (bar_size - 1)) + 1; |
f07771cc WD |
402 | bar_value = io; |
403 | /* compute new region base address */ | |
404 | io = io + bar_size; | |
405 | } else { | |
406 | if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == | |
30e76d5e KG |
407 | PCI_BASE_ADDRESS_MEM_TYPE_64) { |
408 | u32 bar_response_upper; | |
409 | u64 bar64; | |
cb2bf931 AS |
410 | pci_hose_write_config_dword(hose, dev, bar + 4, |
411 | 0xffffffff); | |
412 | pci_hose_read_config_dword(hose, dev, bar + 4, | |
413 | &bar_response_upper); | |
30e76d5e KG |
414 | |
415 | bar64 = ((u64)bar_response_upper << 32) | bar_response; | |
c609719b | 416 | |
30e76d5e KG |
417 | bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1; |
418 | found_mem64 = 1; | |
419 | } else { | |
420 | bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1); | |
421 | } | |
c609719b | 422 | |
f07771cc | 423 | /* round up region base address to multiple of size */ |
c609719b | 424 | mem = ((mem - 1) | (bar_size - 1)) + 1; |
f07771cc WD |
425 | bar_value = mem; |
426 | /* compute new region base address */ | |
427 | mem = mem + bar_size; | |
c609719b WD |
428 | } |
429 | ||
430 | /* Write it out and update our limit */ | |
30e76d5e | 431 | pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); |
c609719b | 432 | |
f07771cc | 433 | if (found_mem64) { |
c609719b | 434 | bar += 4; |
30e76d5e | 435 | #ifdef CONFIG_SYS_PCI_64BIT |
cb2bf931 AS |
436 | pci_hose_write_config_dword(hose, dev, bar, |
437 | (u32)(bar_value >> 32)); | |
30e76d5e | 438 | #else |
cb2bf931 | 439 | pci_hose_write_config_dword(hose, dev, bar, 0x00000000); |
30e76d5e | 440 | #endif |
c609719b WD |
441 | } |
442 | } | |
443 | ||
444 | /* Configure Cache Line Size Register */ | |
cb2bf931 | 445 | pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
c609719b WD |
446 | |
447 | /* Configure Latency Timer */ | |
cb2bf931 | 448 | pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
c609719b WD |
449 | |
450 | /* Disable interrupt line, if device says it wants to use interrupts */ | |
cb2bf931 | 451 | pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); |
f07771cc | 452 | if (pin != 0) { |
cb2bf931 | 453 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff); |
c609719b WD |
454 | } |
455 | ||
cb2bf931 AS |
456 | pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command); |
457 | pci_hose_write_config_dword(hose, dev, PCI_COMMAND, | |
f07771cc | 458 | (old_command & 0xffff0000) | command); |
c609719b WD |
459 | |
460 | return 0; | |
461 | } | |
462 | ||
463 | /* | |
464 | * | |
465 | */ | |
466 | ||
467 | struct pci_config_table *pci_find_config(struct pci_controller *hose, | |
468 | unsigned short class, | |
469 | unsigned int vendor, | |
470 | unsigned int device, | |
471 | unsigned int bus, | |
472 | unsigned int dev, | |
473 | unsigned int func) | |
474 | { | |
475 | struct pci_config_table *table; | |
476 | ||
f07771cc | 477 | for (table = hose->config_table; table && table->vendor; table++) { |
c609719b WD |
478 | if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && |
479 | (table->device == PCI_ANY_ID || table->device == device) && | |
480 | (table->class == PCI_ANY_ID || table->class == class) && | |
481 | (table->bus == PCI_ANY_ID || table->bus == bus) && | |
482 | (table->dev == PCI_ANY_ID || table->dev == dev) && | |
f07771cc | 483 | (table->func == PCI_ANY_ID || table->func == func)) { |
c609719b WD |
484 | return table; |
485 | } | |
486 | } | |
487 | ||
488 | return NULL; | |
489 | } | |
490 | ||
491 | void pci_cfgfunc_config_device(struct pci_controller *hose, | |
492 | pci_dev_t dev, | |
493 | struct pci_config_table *entry) | |
494 | { | |
cb2bf931 AS |
495 | pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], |
496 | entry->priv[2]); | |
c609719b WD |
497 | } |
498 | ||
499 | void pci_cfgfunc_do_nothing(struct pci_controller *hose, | |
500 | pci_dev_t dev, struct pci_config_table *entry) | |
501 | { | |
502 | } | |
503 | ||
504 | /* | |
cb2bf931 | 505 | * HJF: Changed this to return int. I think this is required |
c7de829c WD |
506 | * to get the correct result when scanning bridges |
507 | */ | |
508 | extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); | |
c609719b | 509 | |
983eb9d1 PT |
510 | #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) |
511 | const char * pci_class_str(u8 class) | |
512 | { | |
513 | switch (class) { | |
514 | case PCI_CLASS_NOT_DEFINED: | |
515 | return "Build before PCI Rev2.0"; | |
516 | break; | |
517 | case PCI_BASE_CLASS_STORAGE: | |
518 | return "Mass storage controller"; | |
519 | break; | |
520 | case PCI_BASE_CLASS_NETWORK: | |
521 | return "Network controller"; | |
522 | break; | |
523 | case PCI_BASE_CLASS_DISPLAY: | |
524 | return "Display controller"; | |
525 | break; | |
526 | case PCI_BASE_CLASS_MULTIMEDIA: | |
527 | return "Multimedia device"; | |
528 | break; | |
529 | case PCI_BASE_CLASS_MEMORY: | |
530 | return "Memory controller"; | |
531 | break; | |
532 | case PCI_BASE_CLASS_BRIDGE: | |
533 | return "Bridge device"; | |
534 | break; | |
535 | case PCI_BASE_CLASS_COMMUNICATION: | |
536 | return "Simple comm. controller"; | |
537 | break; | |
538 | case PCI_BASE_CLASS_SYSTEM: | |
539 | return "Base system peripheral"; | |
540 | break; | |
541 | case PCI_BASE_CLASS_INPUT: | |
542 | return "Input device"; | |
543 | break; | |
544 | case PCI_BASE_CLASS_DOCKING: | |
545 | return "Docking station"; | |
546 | break; | |
547 | case PCI_BASE_CLASS_PROCESSOR: | |
548 | return "Processor"; | |
549 | break; | |
550 | case PCI_BASE_CLASS_SERIAL: | |
551 | return "Serial bus controller"; | |
552 | break; | |
553 | case PCI_BASE_CLASS_INTELLIGENT: | |
554 | return "Intelligent controller"; | |
555 | break; | |
556 | case PCI_BASE_CLASS_SATELLITE: | |
557 | return "Satellite controller"; | |
558 | break; | |
559 | case PCI_BASE_CLASS_CRYPT: | |
560 | return "Cryptographic device"; | |
561 | break; | |
562 | case PCI_BASE_CLASS_SIGNAL_PROCESSING: | |
563 | return "DSP"; | |
564 | break; | |
565 | case PCI_CLASS_OTHERS: | |
566 | return "Does not fit any class"; | |
567 | break; | |
568 | default: | |
569 | return "???"; | |
570 | break; | |
571 | }; | |
572 | } | |
573 | #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ | |
574 | ||
7b19fd6d | 575 | __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) |
dc1da42f SR |
576 | { |
577 | /* | |
578 | * Check if pci device should be skipped in configuration | |
579 | */ | |
580 | if (dev == PCI_BDF(hose->first_busno, 0, 0)) { | |
581 | #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ | |
582 | /* | |
583 | * Only skip configuration if "pciconfighost" is not set | |
584 | */ | |
585 | if (getenv("pciconfighost") == NULL) | |
586 | return 1; | |
587 | #else | |
588 | return 1; | |
589 | #endif | |
590 | } | |
591 | ||
592 | return 0; | |
593 | } | |
dc1da42f SR |
594 | |
595 | #ifdef CONFIG_PCI_SCAN_SHOW | |
7b19fd6d | 596 | __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) |
dc1da42f SR |
597 | { |
598 | if (dev == PCI_BDF(hose->first_busno, 0, 0)) | |
599 | return 0; | |
600 | ||
601 | return 1; | |
602 | } | |
dc1da42f SR |
603 | #endif /* CONFIG_PCI_SCAN_SHOW */ |
604 | ||
c609719b WD |
605 | int pci_hose_scan_bus(struct pci_controller *hose, int bus) |
606 | { | |
cb2bf931 | 607 | unsigned int sub_bus, found_multi = 0; |
c609719b WD |
608 | unsigned short vendor, device, class; |
609 | unsigned char header_type; | |
03992ac2 | 610 | #ifndef CONFIG_PCI_PNP |
c609719b | 611 | struct pci_config_table *cfg; |
03992ac2 | 612 | #endif |
c609719b | 613 | pci_dev_t dev; |
009884ae PT |
614 | #ifdef CONFIG_PCI_SCAN_SHOW |
615 | static int indent = 0; | |
616 | #endif | |
c609719b WD |
617 | |
618 | sub_bus = bus; | |
619 | ||
620 | for (dev = PCI_BDF(bus,0,0); | |
cb2bf931 AS |
621 | dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1, |
622 | PCI_MAX_PCI_FUNCTIONS - 1); | |
623 | dev += PCI_BDF(0, 0, 1)) { | |
dc1da42f SR |
624 | |
625 | if (pci_skip_dev(hose, dev)) | |
626 | continue; | |
c609719b WD |
627 | |
628 | if (PCI_FUNC(dev) && !found_multi) | |
629 | continue; | |
630 | ||
631 | pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); | |
632 | ||
633 | pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); | |
634 | ||
983eb9d1 PT |
635 | if (vendor == 0xffff || vendor == 0x0000) |
636 | continue; | |
c609719b | 637 | |
983eb9d1 PT |
638 | if (!PCI_FUNC(dev)) |
639 | found_multi = header_type & 0x80; | |
c609719b | 640 | |
cb2bf931 AS |
641 | debug("PCI Scan: Found Bus %d, Device %d, Function %d\n", |
642 | PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); | |
c609719b | 643 | |
983eb9d1 PT |
644 | pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); |
645 | pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); | |
c609719b | 646 | |
0991866c TH |
647 | #ifdef CONFIG_PCI_FIXUP_DEV |
648 | board_pci_fixup_dev(hose, dev, vendor, device, class); | |
649 | #endif | |
650 | ||
a38d216e | 651 | #ifdef CONFIG_PCI_SCAN_SHOW |
009884ae PT |
652 | indent++; |
653 | ||
654 | /* Print leading space, including bus indentation */ | |
655 | printf("%*c", indent + 1, ' '); | |
656 | ||
a38d216e | 657 | if (pci_print_dev(hose, dev)) { |
009884ae PT |
658 | printf("%02x:%02x.%-*x - %04x:%04x - %s\n", |
659 | PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), | |
a38d216e PT |
660 | vendor, device, pci_class_str(class >> 8)); |
661 | } | |
662 | #endif | |
663 | ||
03992ac2 AS |
664 | #ifdef CONFIG_PCI_PNP |
665 | sub_bus = max(pciauto_config_device(hose, dev), sub_bus); | |
666 | #else | |
983eb9d1 PT |
667 | cfg = pci_find_config(hose, class, vendor, device, |
668 | PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); | |
669 | if (cfg) { | |
670 | cfg->config_device(hose, dev, cfg); | |
671 | sub_bus = max(sub_bus, hose->current_busno); | |
983eb9d1 | 672 | } |
03992ac2 | 673 | #endif |
a38d216e | 674 | |
009884ae PT |
675 | #ifdef CONFIG_PCI_SCAN_SHOW |
676 | indent--; | |
677 | #endif | |
678 | ||
983eb9d1 PT |
679 | if (hose->fixup_irq) |
680 | hose->fixup_irq(hose, dev); | |
c609719b WD |
681 | } |
682 | ||
683 | return sub_bus; | |
684 | } | |
685 | ||
686 | int pci_hose_scan(struct pci_controller *hose) | |
687 | { | |
0da1fb03 AG |
688 | #if defined(CONFIG_PCI_BOOTDELAY) |
689 | static int pcidelay_done; | |
690 | char *s; | |
691 | int i; | |
692 | ||
693 | if (!pcidelay_done) { | |
694 | /* wait "pcidelay" ms (if defined)... */ | |
695 | s = getenv("pcidelay"); | |
696 | if (s) { | |
697 | int val = simple_strtoul(s, NULL, 10); | |
698 | for (i = 0; i < val; i++) | |
699 | udelay(1000); | |
700 | } | |
701 | pcidelay_done = 1; | |
702 | } | |
703 | #endif /* CONFIG_PCI_BOOTDELAY */ | |
704 | ||
cb2bf931 AS |
705 | /* |
706 | * Start scan at current_busno. | |
40e81add ES |
707 | * PCIe will start scan at first_busno+1. |
708 | */ | |
cb2bf931 | 709 | /* For legacy support, ensure current >= first */ |
40e81add ES |
710 | if (hose->first_busno > hose->current_busno) |
711 | hose->current_busno = hose->first_busno; | |
c609719b WD |
712 | #ifdef CONFIG_PCI_PNP |
713 | pciauto_config_init(hose); | |
714 | #endif | |
40e81add | 715 | return pci_hose_scan_bus(hose, hose->current_busno); |
c609719b WD |
716 | } |
717 | ||
ad10dd9a SR |
718 | void pci_init(void) |
719 | { | |
96d61603 JS |
720 | hose_head = NULL; |
721 | ||
ad10dd9a SR |
722 | /* now call board specific pci_init()... */ |
723 | pci_init_board(); | |
724 | } | |
287df01e ZQ |
725 | |
726 | /* Returns the address of the requested capability structure within the | |
727 | * device's PCI configuration space or 0 in case the device does not | |
728 | * support it. | |
729 | * */ | |
730 | int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, | |
731 | int cap) | |
732 | { | |
733 | int pos; | |
734 | u8 hdr_type; | |
735 | ||
736 | pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); | |
737 | ||
738 | pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); | |
739 | ||
740 | if (pos) | |
741 | pos = pci_find_cap(hose, dev, pos, cap); | |
742 | ||
743 | return pos; | |
744 | } | |
745 | ||
746 | /* Find the header pointer to the Capabilities*/ | |
747 | int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, | |
748 | u8 hdr_type) | |
749 | { | |
750 | u16 status; | |
751 | ||
752 | pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); | |
753 | ||
754 | if (!(status & PCI_STATUS_CAP_LIST)) | |
755 | return 0; | |
756 | ||
757 | switch (hdr_type) { | |
758 | case PCI_HEADER_TYPE_NORMAL: | |
759 | case PCI_HEADER_TYPE_BRIDGE: | |
760 | return PCI_CAPABILITY_LIST; | |
761 | case PCI_HEADER_TYPE_CARDBUS: | |
762 | return PCI_CB_CAPABILITY_LIST; | |
763 | default: | |
764 | return 0; | |
765 | } | |
766 | } | |
767 | ||
768 | int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) | |
769 | { | |
770 | int ttl = PCI_FIND_CAP_TTL; | |
771 | u8 id; | |
772 | u8 next_pos; | |
773 | ||
774 | while (ttl--) { | |
775 | pci_hose_read_config_byte(hose, dev, pos, &next_pos); | |
776 | if (next_pos < CAP_START_POS) | |
777 | break; | |
778 | next_pos &= ~3; | |
779 | pos = (int) next_pos; | |
780 | pci_hose_read_config_byte(hose, dev, | |
781 | pos + PCI_CAP_LIST_ID, &id); | |
782 | if (id == 0xff) | |
783 | break; | |
784 | if (id == cap) | |
785 | return pos; | |
786 | pos += PCI_CAP_LIST_NEXT; | |
787 | } | |
788 | return 0; | |
789 | } |