[people/ms/u-boot.git] / drivers / pci / pci_indirect.c

/*
 * Support for indirect PCI bridges.
 *
 * Copyright (C) 1998 Gabriel Paubert.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#if !defined(__I386__)

#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

#define cfg_read(val, addr, type, op)	*val = op((type)(addr))
#define cfg_write(val, addr, type, op)	op((type *)(addr), (val))

#if defined(CONFIG_MPC8260)
#define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
static int								 \
indirect_##rw##_config_##size(struct pci_controller *hose,		 \
			      pci_dev_t dev, int offset, type val)	 \
{									 \
	u32 b, d,f;							 \
	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
	b = b - hose->first_busno;					 \
	dev = PCI_BDF(b, d, f);						 \
	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
	sync();								 \
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
	return 0;							 \
}
#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define INDIRECT_PCI_OP(rw, size, type, op, mask)                        \
static int                                                               \
indirect_##rw##_config_##size(struct pci_controller *hose,               \
			      pci_dev_t dev, int offset, type val)       \
{                                                                        \
	u32 b, d,f;							 \
	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
	b = b - hose->first_busno;					 \
	dev = PCI_BDF(b, d, f);						 \
	*(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
	sync();                                                          \
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);       \
	return 0;                                                        \
}
#elif defined(CONFIG_440GX)  || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
      defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
static int								 \
indirect_##rw##_config_##size(struct pci_controller *hose,		 \
			      pci_dev_t dev, int offset, type val)	 \
{									 \
	u32 b, d,f;							 \
	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
	b = b - hose->first_busno;					 \
	dev = PCI_BDF(b, d, f);						 \
	if (PCI_BUS(dev) > 0)                                            \
		out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
	else                                                             \
		out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
	return 0;							 \
}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask)			 \
static int								 \
indirect_##rw##_config_##size(struct pci_controller *hose,		 \
			      pci_dev_t dev, int offset, type val)	 \
{									 \
	u32 b, d,f;							 \
	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev);		 \
	b = b - hose->first_busno;					 \
	dev = PCI_BDF(b, d, f);						 \
	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
	return 0;							 \
}
#endif

#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask)		 \
static int								 \
indirect_##rw##_config_##size(struct pci_controller *hose,		 \
			      pci_dev_t dev, int offset, type val)	 \
{									 \
	unsigned int msr = mfmsr();					 \
	mtmsr(msr & ~(MSR_EE | MSR_CE));				 \
	out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);	 \
	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);	 \
	out_le32(hose->cfg_addr, 0x00000000);				 \
	mtmsr(msr);							 \
	return 0;							 \
}

INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
#ifdef CONFIG_405GP
INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
#else
INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
#endif

void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
{
	pci_set_ops(hose,
		    indirect_read_config_byte,
		    indirect_read_config_word,
		    indirect_read_config_dword,
		    indirect_write_config_byte,
		    indirect_write_config_word,
		    indirect_write_config_dword);

	hose->cfg_addr = (unsigned int *) cfg_addr;
	hose->cfg_data = (unsigned char *) cfg_data;
}

#endif	/* !__I386__ */
Commit	Line	Data
affae2bf WD	1	/*
	2	* Support for indirect PCI bridges.
	3	*
	4	* Copyright (C) 1998 Gabriel Paubert.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
affae2bf WD	7	*/
	8
	9	#include <common.h>
	10
29161f47	11	#if !defined(__I386__)
affae2bf WD	12
	13	#include <asm/processor.h>
	14	#include <asm/io.h>
	15	#include <pci.h>
	16
	17	#define cfg_read(val, addr, type, op) *val = op((type)(addr))
	18	#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
	19
5d232d0e	20	#if defined(CONFIG_MPC8260)
affae2bf WD	21	#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
affae2bf WD	22	static int \
53677ef1	23	indirect_##rw##_config_##size(struct pci_controller *hose, \
affae2bf WD	24	pci_dev_t dev, int offset, type val) \
affae2bf WD	25	{ \
dffb70f3 KG	26	u32 b, d,f; \
	27	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
	28	b = b - hose->first_busno; \
	29	dev = PCI_BDF(b, d, f); \
53677ef1	30	out_le32(hose->cfg_addr, dev \| (offset & 0xfc) \| 0x80000000); \
4d75a504	31	sync(); \
affae2bf	32	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
53677ef1	33	return 0; \
affae2bf	34	}
571f49fa	35	#elif defined(CONFIG_E500) \|\| defined(CONFIG_MPC86xx)
42d1f039 WD	36	#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
	37	static int \
	38	indirect_##rw##_config_##size(struct pci_controller *hose, \
	39	pci_dev_t dev, int offset, type val) \
	40	{ \
dffb70f3 KG	41	u32 b, d,f; \
	42	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
	43	b = b - hose->first_busno; \
	44	dev = PCI_BDF(b, d, f); \
571f49fa	45	*(hose->cfg_addr) = dev \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000; \
42d1f039 WD	46	sync(); \
	47	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
	48	return 0; \
	49	}
97c9f290 FR	50	#elif defined(CONFIG_440GX) \|\| defined(CONFIG_440GP) \|\| defined(CONFIG_440SP) \|\| \
97c9f290 FR	51	defined(CONFIG_440SPE) \|\| defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
3c74e32a WD	52	#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
3c74e32a WD	53	static int \
53677ef1	54	indirect_##rw##_config_##size(struct pci_controller *hose, \
3c74e32a WD	55	pci_dev_t dev, int offset, type val) \
3c74e32a WD	56	{ \
dffb70f3 KG	57	u32 b, d,f; \
	58	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
	59	b = b - hose->first_busno; \
	60	dev = PCI_BDF(b, d, f); \
3c74e32a WD	61	if (PCI_BUS(dev) > 0) \
	62	out_le32(hose->cfg_addr, dev \| (offset & 0xfc) \| 0x80000001); \
	63	else \
	64	out_le32(hose->cfg_addr, dev \| (offset & 0xfc) \| 0x80000000); \
	65	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
53677ef1	66	return 0; \
3c74e32a	67	}
4d75a504 WD	68	#else
	69	#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
	70	static int \
53677ef1	71	indirect_##rw##_config_##size(struct pci_controller *hose, \
4d75a504 WD	72	pci_dev_t dev, int offset, type val) \
4d75a504 WD	73	{ \
dffb70f3 KG	74	u32 b, d,f; \
	75	b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
	76	b = b - hose->first_busno; \
	77	dev = PCI_BDF(b, d, f); \
53677ef1	78	out_le32(hose->cfg_addr, dev \| (offset & 0xfc) \| 0x80000000); \
4d75a504	79	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
53677ef1	80	return 0; \
4d75a504 WD	81	}
4d75a504 WD	82	#endif
affae2bf WD	83
	84	#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \
	85	static int \
53677ef1	86	indirect_##rw##_config_##size(struct pci_controller *hose, \
affae2bf WD	87	pci_dev_t dev, int offset, type val) \
	88	{ \
	89	unsigned int msr = mfmsr(); \
	90	mtmsr(msr & ~(MSR_EE \| MSR_CE)); \
53677ef1	91	out_le32(hose->cfg_addr, dev \| (offset & 0xfc) \| 0x80000000); \
affae2bf	92	cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
53677ef1	93	out_le32(hose->cfg_addr, 0x00000000); \
affae2bf	94	mtmsr(msr); \
53677ef1	95	return 0; \
affae2bf WD	96	}
	97
	98	INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
	99	INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
	100	INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
	101	#ifdef CONFIG_405GP
	102	INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
	103	INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
	104	INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
	105	#else
	106	INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
	107	INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
	108	INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
	109	#endif
	110
	111	void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
	112	{
	113	pci_set_ops(hose,
	114	indirect_read_config_byte,
	115	indirect_read_config_word,
	116	indirect_read_config_dword,
	117	indirect_write_config_byte,
	118	indirect_write_config_word,
	119	indirect_write_config_dword);
	120
	121	hose->cfg_addr = (unsigned int *) cfg_addr;
	122	hose->cfg_data = (unsigned char *) cfg_data;
	123	}
	124
29161f47	125	#endif /* !__I386__ */