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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9c28d61c AS |
2 | /* |
3 | * PCIe driver for Marvell MVEBU SoCs | |
4 | * | |
5 | * Based on Barebox drivers/pci/pci-mvebu.c | |
6 | * | |
7 | * Ported to U-Boot by: | |
8 | * Anton Schubert <anton.schubert@gmx.de> | |
9 | * Stefan Roese <sr@denx.de> | |
9c28d61c AS |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <pci.h> | |
1221ce45 | 14 | #include <linux/errno.h> |
9c28d61c AS |
15 | #include <asm/io.h> |
16 | #include <asm/arch/cpu.h> | |
17 | #include <asm/arch/soc.h> | |
18 | #include <linux/mbus.h> | |
19 | ||
20 | DECLARE_GLOBAL_DATA_PTR; | |
21 | ||
22 | /* PCIe unit register offsets */ | |
23 | #define SELECT(x, n) ((x >> n) & 1UL) | |
24 | ||
25 | #define PCIE_DEV_ID_OFF 0x0000 | |
26 | #define PCIE_CMD_OFF 0x0004 | |
27 | #define PCIE_DEV_REV_OFF 0x0008 | |
28 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
29 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
30 | #define PCIE_CAPAB_OFF 0x0060 | |
31 | #define PCIE_CTRL_STAT_OFF 0x0068 | |
32 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | |
33 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) | |
34 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
35 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
36 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
37 | #define PCIE_WIN5_CTRL_OFF 0x1880 | |
38 | #define PCIE_WIN5_BASE_OFF 0x1884 | |
39 | #define PCIE_WIN5_REMAP_OFF 0x188c | |
40 | #define PCIE_CONF_ADDR_OFF 0x18f8 | |
41 | #define PCIE_CONF_ADDR_EN BIT(31) | |
42 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | |
43 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | |
44 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | |
45 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) | |
46 | #define PCIE_CONF_ADDR(dev, reg) \ | |
47 | (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \ | |
48 | PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \ | |
49 | PCIE_CONF_ADDR_EN) | |
50 | #define PCIE_CONF_DATA_OFF 0x18fc | |
51 | #define PCIE_MASK_OFF 0x1910 | |
52 | #define PCIE_MASK_ENABLE_INTS (0xf << 24) | |
53 | #define PCIE_CTRL_OFF 0x1a00 | |
54 | #define PCIE_CTRL_X1_MODE BIT(0) | |
55 | #define PCIE_STAT_OFF 0x1a04 | |
56 | #define PCIE_STAT_BUS (0xff << 8) | |
57 | #define PCIE_STAT_DEV (0x1f << 16) | |
58 | #define PCIE_STAT_LINK_DOWN BIT(0) | |
59 | #define PCIE_DEBUG_CTRL 0x1a60 | |
60 | #define PCIE_DEBUG_SOFT_RESET BIT(20) | |
61 | ||
62 | struct resource { | |
63 | u32 start; | |
64 | u32 end; | |
65 | }; | |
66 | ||
67 | struct mvebu_pcie { | |
68 | struct pci_controller hose; | |
69 | char *name; | |
70 | void __iomem *base; | |
71 | void __iomem *membase; | |
72 | struct resource mem; | |
73 | void __iomem *iobase; | |
74 | u32 port; | |
75 | u32 lane; | |
76 | u32 lane_mask; | |
77 | pci_dev_t dev; | |
78 | }; | |
79 | ||
80 | #define to_pcie(_hc) container_of(_hc, struct mvebu_pcie, pci) | |
81 | ||
82 | /* | |
83 | * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped | |
49b23e03 | 84 | * into SoCs address space. Each controller will map 128M of MEM |
9c28d61c AS |
85 | * and 64K of I/O space when registered. |
86 | */ | |
87 | static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE; | |
49b23e03 | 88 | #define PCIE_MEM_SIZE (128 << 20) |
9c28d61c AS |
89 | |
90 | #if defined(CONFIG_ARMADA_38X) | |
91 | #define PCIE_BASE(if) \ | |
92 | ((if) == 0 ? \ | |
882d3fa6 DE |
93 | MVEBU_REG_PCIE0_BASE : \ |
94 | (MVEBU_REG_PCIE_BASE + 0x4000 * (if - 1))) | |
9c28d61c AS |
95 | |
96 | /* | |
97 | * On A38x MV6820 these PEX ports are supported: | |
98 | * 0 - Port 0.0 | |
882d3fa6 DE |
99 | * 1 - Port 1.0 |
100 | * 2 - Port 2.0 | |
101 | * 3 - Port 3.0 | |
9c28d61c | 102 | */ |
882d3fa6 | 103 | #define MAX_PEX 4 |
9c28d61c AS |
104 | static struct mvebu_pcie pcie_bus[MAX_PEX]; |
105 | ||
106 | static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, | |
107 | int *mem_target, int *mem_attr) | |
108 | { | |
882d3fa6 DE |
109 | u8 port[] = { 0, 1, 2, 3 }; |
110 | u8 lane[] = { 0, 0, 0, 0 }; | |
111 | u8 target[] = { 8, 4, 4, 4 }; | |
112 | u8 attr[] = { 0xe8, 0xe8, 0xd8, 0xb8 }; | |
9c28d61c AS |
113 | |
114 | pcie->port = port[pex_idx]; | |
115 | pcie->lane = lane[pex_idx]; | |
116 | *mem_target = target[pex_idx]; | |
117 | *mem_attr = attr[pex_idx]; | |
118 | } | |
119 | #else | |
120 | #define PCIE_BASE(if) \ | |
121 | ((if) < 8 ? \ | |
122 | (MVEBU_REG_PCIE_BASE + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) : \ | |
123 | (MVEBU_REG_PCIE_BASE + 0x2000 + ((if) % 8) * 0x40000)) | |
124 | ||
125 | /* | |
126 | * On AXP MV78460 these PEX ports are supported: | |
127 | * 0 - Port 0.0 | |
128 | * 1 - Port 0.1 | |
129 | * 2 - Port 0.2 | |
130 | * 3 - Port 0.3 | |
131 | * 4 - Port 1.0 | |
132 | * 5 - Port 1.1 | |
133 | * 6 - Port 1.2 | |
134 | * 7 - Port 1.3 | |
135 | * 8 - Port 2.0 | |
136 | * 9 - Port 3.0 | |
137 | */ | |
138 | #define MAX_PEX 10 | |
139 | static struct mvebu_pcie pcie_bus[MAX_PEX]; | |
140 | ||
141 | static void mvebu_get_port_lane(struct mvebu_pcie *pcie, int pex_idx, | |
142 | int *mem_target, int *mem_attr) | |
143 | { | |
144 | u8 port[] = { 0, 0, 0, 0, 1, 1, 1, 1, 2, 3 }; | |
145 | u8 lane[] = { 0, 1, 2, 3, 0, 1, 2, 3, 0, 0 }; | |
146 | u8 target[] = { 4, 4, 4, 4, 8, 8, 8, 8, 4, 8 }; | |
147 | u8 attr[] = { 0xe8, 0xd8, 0xb8, 0x78, | |
148 | 0xe8, 0xd8, 0xb8, 0x78, | |
149 | 0xf8, 0xf8 }; | |
150 | ||
151 | pcie->port = port[pex_idx]; | |
152 | pcie->lane = lane[pex_idx]; | |
153 | *mem_target = target[pex_idx]; | |
154 | *mem_attr = attr[pex_idx]; | |
155 | } | |
156 | #endif | |
157 | ||
9a045278 PS |
158 | static int mvebu_pex_unit_is_x4(int pex_idx) |
159 | { | |
160 | int pex_unit = pex_idx < 9 ? pex_idx >> 2 : 3; | |
161 | u32 mask = (0x0f << (pex_unit * 8)); | |
162 | ||
163 | return (readl(COMPHY_REFCLK_ALIGNMENT) & mask) == mask; | |
164 | } | |
165 | ||
9c28d61c AS |
166 | static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) |
167 | { | |
168 | u32 val; | |
169 | val = readl(pcie->base + PCIE_STAT_OFF); | |
170 | return !(val & PCIE_STAT_LINK_DOWN); | |
171 | } | |
172 | ||
173 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) | |
174 | { | |
175 | u32 stat; | |
176 | ||
177 | stat = readl(pcie->base + PCIE_STAT_OFF); | |
178 | stat &= ~PCIE_STAT_BUS; | |
179 | stat |= busno << 8; | |
180 | writel(stat, pcie->base + PCIE_STAT_OFF); | |
181 | } | |
182 | ||
183 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) | |
184 | { | |
185 | u32 stat; | |
186 | ||
187 | stat = readl(pcie->base + PCIE_STAT_OFF); | |
188 | stat &= ~PCIE_STAT_DEV; | |
189 | stat |= devno << 16; | |
190 | writel(stat, pcie->base + PCIE_STAT_OFF); | |
191 | } | |
192 | ||
193 | static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie) | |
194 | { | |
195 | u32 stat; | |
196 | ||
197 | stat = readl(pcie->base + PCIE_STAT_OFF); | |
198 | return (stat & PCIE_STAT_BUS) >> 8; | |
199 | } | |
200 | ||
201 | static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie) | |
202 | { | |
203 | u32 stat; | |
204 | ||
205 | stat = readl(pcie->base + PCIE_STAT_OFF); | |
206 | return (stat & PCIE_STAT_DEV) >> 16; | |
207 | } | |
208 | ||
209 | static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) | |
210 | { | |
211 | return container_of(hose, struct mvebu_pcie, hose); | |
212 | } | |
213 | ||
214 | static int mvebu_pcie_read_config_dword(struct pci_controller *hose, | |
215 | pci_dev_t dev, int offset, u32 *val) | |
216 | { | |
217 | struct mvebu_pcie *pcie = hose_to_pcie(hose); | |
218 | int local_bus = PCI_BUS(pcie->dev); | |
219 | int local_dev = PCI_DEV(pcie->dev); | |
220 | u32 reg; | |
221 | ||
222 | /* Only allow one other device besides the local one on the local bus */ | |
223 | if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) { | |
224 | if (local_dev == 0 && PCI_DEV(dev) != 1) { | |
225 | /* | |
226 | * If local dev is 0, the first other dev can | |
227 | * only be 1 | |
228 | */ | |
229 | *val = 0xffffffff; | |
230 | return 1; | |
231 | } else if (local_dev != 0 && PCI_DEV(dev) != 0) { | |
232 | /* | |
233 | * If local dev is not 0, the first other dev can | |
234 | * only be 0 | |
235 | */ | |
236 | *val = 0xffffffff; | |
237 | return 1; | |
238 | } | |
239 | } | |
240 | ||
241 | /* write address */ | |
242 | reg = PCIE_CONF_ADDR(dev, offset); | |
243 | writel(reg, pcie->base + PCIE_CONF_ADDR_OFF); | |
244 | *val = readl(pcie->base + PCIE_CONF_DATA_OFF); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static int mvebu_pcie_write_config_dword(struct pci_controller *hose, | |
250 | pci_dev_t dev, int offset, u32 val) | |
251 | { | |
252 | struct mvebu_pcie *pcie = hose_to_pcie(hose); | |
253 | int local_bus = PCI_BUS(pcie->dev); | |
254 | int local_dev = PCI_DEV(pcie->dev); | |
255 | ||
256 | /* Only allow one other device besides the local one on the local bus */ | |
257 | if (PCI_BUS(dev) == local_bus && PCI_DEV(dev) != local_dev) { | |
258 | if (local_dev == 0 && PCI_DEV(dev) != 1) { | |
259 | /* | |
260 | * If local dev is 0, the first other dev can | |
261 | * only be 1 | |
262 | */ | |
263 | return 1; | |
264 | } else if (local_dev != 0 && PCI_DEV(dev) != 0) { | |
265 | /* | |
266 | * If local dev is not 0, the first other dev can | |
267 | * only be 0 | |
268 | */ | |
269 | return 1; | |
270 | } | |
271 | } | |
272 | ||
273 | writel(PCIE_CONF_ADDR(dev, offset), pcie->base + PCIE_CONF_ADDR_OFF); | |
274 | writel(val, pcie->base + PCIE_CONF_DATA_OFF); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Setup PCIE BARs and Address Decode Wins: | |
281 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
282 | * WIN[0-3] -> DRAM bank[0-3] | |
283 | */ | |
284 | static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) | |
285 | { | |
286 | const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); | |
287 | u32 size; | |
288 | int i; | |
289 | ||
290 | /* First, disable and clear BARs and windows. */ | |
291 | for (i = 1; i < 3; i++) { | |
292 | writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i)); | |
293 | writel(0, pcie->base + PCIE_BAR_LO_OFF(i)); | |
294 | writel(0, pcie->base + PCIE_BAR_HI_OFF(i)); | |
295 | } | |
296 | ||
297 | for (i = 0; i < 5; i++) { | |
298 | writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i)); | |
299 | writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i)); | |
300 | writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); | |
301 | } | |
302 | ||
303 | writel(0, pcie->base + PCIE_WIN5_CTRL_OFF); | |
304 | writel(0, pcie->base + PCIE_WIN5_BASE_OFF); | |
305 | writel(0, pcie->base + PCIE_WIN5_REMAP_OFF); | |
306 | ||
307 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ | |
308 | size = 0; | |
309 | for (i = 0; i < dram->num_cs; i++) { | |
310 | const struct mbus_dram_window *cs = dram->cs + i; | |
311 | ||
312 | writel(cs->base & 0xffff0000, | |
313 | pcie->base + PCIE_WIN04_BASE_OFF(i)); | |
314 | writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i)); | |
315 | writel(((cs->size - 1) & 0xffff0000) | | |
316 | (cs->mbus_attr << 8) | | |
317 | (dram->mbus_dram_target_id << 4) | 1, | |
318 | pcie->base + PCIE_WIN04_CTRL_OFF(i)); | |
319 | ||
320 | size += cs->size; | |
321 | } | |
322 | ||
323 | /* Round up 'size' to the nearest power of two. */ | |
324 | if ((size & (size - 1)) != 0) | |
325 | size = 1 << fls(size); | |
326 | ||
327 | /* Setup BAR[1] to all DRAM banks. */ | |
328 | writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1)); | |
329 | writel(0, pcie->base + PCIE_BAR_HI_OFF(1)); | |
330 | writel(((size - 1) & 0xffff0000) | 0x1, | |
331 | pcie->base + PCIE_BAR_CTRL_OFF(1)); | |
332 | } | |
333 | ||
334 | void pci_init_board(void) | |
335 | { | |
336 | int mem_target, mem_attr, i; | |
337 | int bus = 0; | |
338 | u32 reg; | |
339 | u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4); | |
340 | ||
341 | /* Check SoC Control Power State */ | |
342 | debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n", | |
343 | __func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1), | |
344 | SELECT(soc_ctrl, 2)); | |
345 | ||
346 | for (i = 0; i < MAX_PEX; i++) { | |
347 | struct mvebu_pcie *pcie = &pcie_bus[i]; | |
348 | struct pci_controller *hose = &pcie->hose; | |
349 | ||
350 | /* Get port number, lane number and memory target / attr */ | |
351 | mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr); | |
352 | ||
353 | /* Don't read at all from pci registers if port power is down */ | |
882d3fa6 DE |
354 | if (SELECT(soc_ctrl, pcie->port) == 0) { |
355 | if (pcie->lane == 0) | |
356 | debug("%s: skipping port %d\n", __func__, pcie->port); | |
9c28d61c AS |
357 | continue; |
358 | } | |
359 | ||
360 | pcie->base = (void __iomem *)PCIE_BASE(i); | |
361 | ||
362 | /* Check link and skip ports that have no link */ | |
363 | if (!mvebu_pcie_link_up(pcie)) { | |
364 | debug("%s: PCIe %d.%d - down\n", __func__, | |
365 | pcie->port, pcie->lane); | |
366 | continue; | |
367 | } | |
368 | debug("%s: PCIe %d.%d - up, base %08x\n", __func__, | |
369 | pcie->port, pcie->lane, (u32)pcie->base); | |
370 | ||
371 | /* Read Id info and local bus/dev */ | |
372 | debug("direct conf read %08x, local bus %d, local dev %d\n", | |
373 | readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie), | |
374 | mvebu_pcie_get_local_dev_nr(pcie)); | |
375 | ||
376 | mvebu_pcie_set_local_bus_nr(pcie, bus); | |
377 | mvebu_pcie_set_local_dev_nr(pcie, 0); | |
378 | pcie->dev = PCI_BDF(bus, 0, 0); | |
379 | ||
380 | pcie->mem.start = (u32)mvebu_pcie_membase; | |
381 | pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1; | |
382 | mvebu_pcie_membase += PCIE_MEM_SIZE; | |
383 | ||
384 | if (mvebu_mbus_add_window_by_id(mem_target, mem_attr, | |
385 | (phys_addr_t)pcie->mem.start, | |
386 | PCIE_MEM_SIZE)) { | |
387 | printf("PCIe unable to add mbus window for mem at %08x+%08x\n", | |
388 | (u32)pcie->mem.start, PCIE_MEM_SIZE); | |
389 | } | |
390 | ||
391 | /* Setup windows and configure host bridge */ | |
392 | mvebu_pcie_setup_wins(pcie); | |
393 | ||
394 | /* Master + slave enable. */ | |
395 | reg = readl(pcie->base + PCIE_CMD_OFF); | |
396 | reg |= PCI_COMMAND_MEMORY; | |
397 | reg |= PCI_COMMAND_MASTER; | |
398 | reg |= BIT(10); /* disable interrupts */ | |
399 | writel(reg, pcie->base + PCIE_CMD_OFF); | |
400 | ||
401 | /* Setup U-Boot PCI Controller */ | |
402 | hose->first_busno = 0; | |
403 | hose->current_busno = bus; | |
404 | ||
405 | /* PCI memory space */ | |
406 | pci_set_region(hose->regions + 0, pcie->mem.start, | |
407 | pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); | |
408 | pci_set_region(hose->regions + 1, | |
409 | 0, 0, | |
410 | gd->ram_size, | |
411 | PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); | |
412 | hose->region_count = 2; | |
413 | ||
414 | pci_set_ops(hose, | |
415 | pci_hose_read_config_byte_via_dword, | |
416 | pci_hose_read_config_word_via_dword, | |
417 | mvebu_pcie_read_config_dword, | |
418 | pci_hose_write_config_byte_via_dword, | |
419 | pci_hose_write_config_word_via_dword, | |
420 | mvebu_pcie_write_config_dword); | |
421 | pci_register_hose(hose); | |
422 | ||
423 | hose->last_busno = pci_hose_scan(hose); | |
424 | ||
425 | /* Set BAR0 to internal registers */ | |
426 | writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); | |
427 | writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); | |
428 | ||
429 | bus = hose->last_busno + 1; | |
9a045278 PS |
430 | |
431 | /* need to skip more for X4 links, otherwise scan will hang */ | |
432 | if (mvebu_soc_family() == MVEBU_SOC_AXP) { | |
433 | if (mvebu_pex_unit_is_x4(i)) | |
434 | i += 3; | |
435 | } | |
9c28d61c AS |
436 | } |
437 | } |