projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 1a2334a4 YG |
2 | /* |
| 3 | * SH4 PCI Controller (PCIC) for U-Boot. | |
| 4 | * (C) Dustin McIntire (dustin@sensoria.com) | |
| ab8f4d40 | 5 | * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 1a2334a4 YG |
6 | * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
| 7 | * | |
| 8f0fec74 | 8 | * u-boot/arch/sh/cpu/sh4/pci-sh4.c |
| 1a2334a4 YG |
9 | */ |
| 10 | ||
| 11 | #include <common.h> | |
| 12 | ||
| 1a2334a4 YG |
13 | #include <asm/processor.h> |
| 14 | #include <asm/io.h> | |
| 15 | #include <asm/pci.h> | |
| 16 | #include <pci.h> | |
| 17 | ||
| 18 | int pci_sh4_init(struct pci_controller *hose) | |
| 19 | { | |
| 20 | hose->first_busno = 0; | |
| 21 | hose->region_count = 0; | |
| 22 | hose->last_busno = 0xff; | |
| 23 | ||
| 24 | /* PCI memory space */ | |
| 25 | pci_set_region(hose->regions + 0, | |
| 26 | CONFIG_PCI_MEM_BUS, | |
| 27 | CONFIG_PCI_MEM_PHYS, | |
| 28 | CONFIG_PCI_MEM_SIZE, | |
| 29 | PCI_REGION_MEM); | |
| 30 | hose->region_count++; | |
| 31 | ||
| 32 | /* PCI IO space */ | |
| 33 | pci_set_region(hose->regions + 1, | |
| 34 | CONFIG_PCI_IO_BUS, | |
| 35 | CONFIG_PCI_IO_PHYS, | |
| 36 | CONFIG_PCI_IO_SIZE, | |
| 37 | PCI_REGION_IO); | |
| 38 | hose->region_count++; | |
| 39 | ||
| 06e2735e YS |
40 | #if defined(CONFIG_PCI_SYS_BUS) |
| 41 | /* PCI System Memory space */ | |
| 42 | pci_set_region(hose->regions + 2, | |
| 43 | CONFIG_PCI_SYS_BUS, | |
| 44 | CONFIG_PCI_SYS_PHYS, | |
| 45 | CONFIG_PCI_SYS_SIZE, | |
| 46 | PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); | |
| 47 | hose->region_count++; | |
| 48 | #endif | |
| 49 | ||
| 1a2334a4 YG |
50 | udelay(1000); |
| 51 | ||
| 52 | pci_set_ops(hose, | |
| 53 | pci_hose_read_config_byte_via_dword, | |
| 54 | pci_hose_read_config_word_via_dword, | |
| 55 | pci_sh4_read_config_dword, | |
| 56 | pci_hose_write_config_byte_via_dword, | |
| 57 | pci_hose_write_config_word_via_dword, | |
| 58 | pci_sh4_write_config_dword); | |
| 59 | ||
| 60 | pci_register_hose(hose); | |
| 61 | ||
| 62 | udelay(1000); | |
| 63 | ||
| 64 | #ifdef CONFIG_PCI_SCAN_SHOW | |
| 65 | printf("PCI: Bus Dev VenId DevId Class Int\n"); | |
| 66 | #endif | |
| 67 | hose->last_busno = pci_hose_scan(hose); | |
| 68 | return 0; | |
| 69 | } | |
| d85f46a2 NI |
70 | |
| 71 | int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) | |
| 72 | { | |
| 73 | return 0; | |
| 74 | } | |
| 75 | ||
| 76 | #ifdef CONFIG_PCI_SCAN_SHOW | |
| 77 | int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) | |
| 78 | { | |
| 79 | return 1; | |
| 80 | } | |
| 81 | #endif /* CONFIG_PCI_SCAN_SHOW */ |