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ddr: altera: Remove unnecessary update of the SCC
[people/ms/u-boot.git] / drivers / pci / pci_sh7751.c
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28e5efde
NI		 1/*
2 * SH7751 PCI Controller (PCIC) for U-Boot.
3 * (C) Dustin McIntire (dustin@sensoria.com)
4 * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
28e5efde
NI		 7 */
8
9#include <common.h>
b5d10a13 10#include <pci.h>
28e5efde
NI		 11#include <asm/processor.h>
12#include <asm/io.h>
b5d10a13 13#include <asm/pci.h>
28e5efde
NI		 14
15/* Register addresses and such */
16#define SH7751_BCR1 (vu_long *)0xFF800000
b5d10a13 17#define SH7751_BCR2 (vu_short *)0xFF800004
28e5efde
NI		 18#define SH7751_WCR1 (vu_long *)0xFF800008
19#define SH7751_WCR2 (vu_long *)0xFF80000C
20#define SH7751_WCR3 (vu_long *)0xFF800010
21#define SH7751_MCR (vu_long *)0xFF800014
b5d10a13 22#define SH7751_BCR3 (vu_short *)0xFF800050
28e5efde
NI		 23#define SH7751_PCICONF0 (vu_long *)0xFE200000
24#define SH7751_PCICONF1 (vu_long *)0xFE200004
25#define SH7751_PCICONF2 (vu_long *)0xFE200008
26#define SH7751_PCICONF3 (vu_long *)0xFE20000C
27#define SH7751_PCICONF4 (vu_long *)0xFE200010
28#define SH7751_PCICONF5 (vu_long *)0xFE200014
29#define SH7751_PCICONF6 (vu_long *)0xFE200018
30#define SH7751_PCICR (vu_long *)0xFE200100
31#define SH7751_PCILSR0 (vu_long *)0xFE200104
32#define SH7751_PCILSR1 (vu_long *)0xFE200108
33#define SH7751_PCILAR0 (vu_long *)0xFE20010C
34#define SH7751_PCILAR1 (vu_long *)0xFE200110
35#define SH7751_PCIMBR (vu_long *)0xFE2001C4
36#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
37#define SH7751_PCIPINT (vu_long *)0xFE2001CC
38#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
39#define SH7751_PCICLKR (vu_long *)0xFE2001D4
40#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
41#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
42#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
43#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
44#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
45#define SH7751_PCIMCR (vu_long *)0xFE2001F4
46#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
47
48#define BCR1_BREQEN 0x00080000
49#define PCI_SH7751_ID 0x35051054
50#define PCI_SH7751R_ID 0x350E1054
51#define SH7751_PCICONF1_WCC 0x00000080
52#define SH7751_PCICONF1_PER 0x00000040
53#define SH7751_PCICONF1_BUM 0x00000004
54#define SH7751_PCICONF1_MES 0x00000002
55#define SH7751_PCICONF1_CMDS 0x000000C6
56#define SH7751_PCI_HOST_BRIDGE 0x6
57#define SH7751_PCICR_PREFIX 0xa5000000
58#define SH7751_PCICR_PRST 0x00000002
59#define SH7751_PCICR_CFIN 0x00000001
60#define SH7751_PCIPINT_D3 0x00000002
61#define SH7751_PCIPINT_D0 0x00000001
62#define SH7751_PCICLKR_PREFIX 0xa5000000
63
64#define SH7751_PCI_MEM_BASE 0xFD000000
65#define SH7751_PCI_MEM_SIZE 0x01000000
66#define SH7751_PCI_IO_BASE 0xFE240000
67#define SH7751_PCI_IO_SIZE 0x00040000
68
69#define SH7751_CS3_BASE_ADDR 0x0C000000
70#define SH7751_P2CS3_BASE_ADDR 0xAC000000
71
72#define SH7751_PCIPAR (vu_long *)0xFE2001C0
73#define SH7751_PCIPDR (vu_long *)0xFE200220
74
b5d10a13
NI		 75#define p4_in(addr) (*addr)
76#define p4_out(data, addr) (*addr) = (data)
28e5efde
NI		 77
78/* Double word */
79int pci_sh4_read_config_dword(struct pci_controller *hose,
b5d10a13 80 pci_dev_t dev, int offset, u32 *value)
28e5efde
NI		 81{
82 u32 par_data = 0x80000000 | dev;
83
84 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
85 *value = p4_in(SH7751_PCIPDR);
86
87 return 0;
88}
89
90int pci_sh4_write_config_dword(struct pci_controller *hose,
b5d10a13 91 pci_dev_t dev, int offset, u32 value)
28e5efde
NI		 92{
93 u32 par_data = 0x80000000 | dev;
94
95 p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
96 p4_out(value, SH7751_PCIPDR);
97
98 return 0;
99}
100
101int pci_sh7751_init(struct pci_controller *hose)
102{
103 /* Double-check that we're a 7751 or 7751R chip */
104 if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
105 && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
106 printf("PCI: Unknown PCI host bridge.\n");
107 return 1;
108 }
109 printf("PCI: SH7751 PCI host bridge found.\n");
110
111 /* Double-check some BSC config settings */
112 /* (Area 3 non-MPX 32-bit, PCI bus pins) */
113 if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
b5d10a13
NI		 114 printf("SH7751_BCR1 value is wrong(0x%08X)\n",
115 (unsigned int)p4_in(SH7751_BCR1));
28e5efde
NI		 116 return 2;
117 }
118 if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
b5d10a13
NI		 119 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
120 (unsigned int)p4_in(SH7751_BCR2));
28e5efde
NI		 121 return 3;
122 }
123 if (p4_in(SH7751_BCR2) & 0x01) {
b5d10a13
NI		 124 printf("SH7751_BCR2 value is wrong(0x%08X)\n",
125 (unsigned int)p4_in(SH7751_BCR2));
28e5efde
NI		 126 return 4;
127 }
128
129 /* Force BREQEN in BCR1 to allow PCIC access */
130 p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
131
132 /* Toggle PCI reset pin */
133 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
134 udelay(32);
135 p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
136
137 /* Set cmd bits: WCC, PER, BUM, MES */
138 /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
139 p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
140
141 /* Define this host as the host bridge */
142 p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
143
144 /* Force PCI clock(s) on */
145 p4_out(0, SH7751_PCICLKR);
146 p4_out(0x03, SH7751_PCICLKR);
147
148 /* Clear powerdown IRQs, also mask them (unused) */
149 p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
150 p4_out(0, SH7751_PCIPINTM);
151
152 p4_out(0xab000001, SH7751_PCICONF4);
153
154 /* Set up target memory mappings (for external DMA access) */
155 /* Map both P0 and P2 range to Area 3 RAM for ease of use */
156 p4_out((64 - 1) << 20, SH7751_PCILSR0);
157 p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
158 p4_out(0, SH7751_PCILSR1);
159 p4_out(0, SH7751_PCILAR1);
160 p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
161 p4_out(0xd0000000, SH7751_PCICONF6);
162
163 /* Map memory window to same address on PCI bus */
164 p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
165
166 /* Map IO window to same address on PCI bus */
167 p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
168
169 /* set BREQEN */
170 p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
171
172 /* Copy BSC registers into PCI BSC */
173 p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
a319f149
JCPV		 174 p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
175 p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
28e5efde
NI		 176 p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
177 p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
178 p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
179 p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
180
181 /* Finally, set central function init complete */
182 p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
183
184 pci_sh4_init(hose);
185
186 return 0;
187}
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