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f315828b TR |
1 | /* |
2 | * Copyright (c) 2010, CompuLab, Ltd. | |
3 | * Author: Mike Rapoport <mike@compulab.co.il> | |
4 | * | |
5 | * Based on NVIDIA PCIe driver | |
6 | * Copyright (c) 2008-2009, NVIDIA Corporation. | |
7 | * | |
8 | * Copyright (c) 2013-2014, NVIDIA Corporation. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0 | |
11 | */ | |
12 | ||
13 | #define DEBUG | |
14 | #define pr_fmt(fmt) "tegra-pcie: " fmt | |
15 | ||
16 | #include <common.h> | |
17 | #include <errno.h> | |
18 | #include <fdtdec.h> | |
19 | #include <malloc.h> | |
20 | #include <pci.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/gpio.h> | |
24 | ||
25 | #include <asm/arch/clock.h> | |
26 | #include <asm/arch/powergate.h> | |
27 | #include <asm/arch-tegra/xusb-padctl.h> | |
28 | ||
29 | #include <linux/list.h> | |
30 | ||
31 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> | |
32 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | #define AFI_AXI_BAR0_SZ 0x00 | |
36 | #define AFI_AXI_BAR1_SZ 0x04 | |
37 | #define AFI_AXI_BAR2_SZ 0x08 | |
38 | #define AFI_AXI_BAR3_SZ 0x0c | |
39 | #define AFI_AXI_BAR4_SZ 0x10 | |
40 | #define AFI_AXI_BAR5_SZ 0x14 | |
41 | ||
42 | #define AFI_AXI_BAR0_START 0x18 | |
43 | #define AFI_AXI_BAR1_START 0x1c | |
44 | #define AFI_AXI_BAR2_START 0x20 | |
45 | #define AFI_AXI_BAR3_START 0x24 | |
46 | #define AFI_AXI_BAR4_START 0x28 | |
47 | #define AFI_AXI_BAR5_START 0x2c | |
48 | ||
49 | #define AFI_FPCI_BAR0 0x30 | |
50 | #define AFI_FPCI_BAR1 0x34 | |
51 | #define AFI_FPCI_BAR2 0x38 | |
52 | #define AFI_FPCI_BAR3 0x3c | |
53 | #define AFI_FPCI_BAR4 0x40 | |
54 | #define AFI_FPCI_BAR5 0x44 | |
55 | ||
56 | #define AFI_CACHE_BAR0_SZ 0x48 | |
57 | #define AFI_CACHE_BAR0_ST 0x4c | |
58 | #define AFI_CACHE_BAR1_SZ 0x50 | |
59 | #define AFI_CACHE_BAR1_ST 0x54 | |
60 | ||
61 | #define AFI_MSI_BAR_SZ 0x60 | |
62 | #define AFI_MSI_FPCI_BAR_ST 0x64 | |
63 | #define AFI_MSI_AXI_BAR_ST 0x68 | |
64 | ||
65 | #define AFI_CONFIGURATION 0xac | |
66 | #define AFI_CONFIGURATION_EN_FPCI (1 << 0) | |
67 | ||
68 | #define AFI_FPCI_ERROR_MASKS 0xb0 | |
69 | ||
70 | #define AFI_INTR_MASK 0xb4 | |
71 | #define AFI_INTR_MASK_INT_MASK (1 << 0) | |
72 | #define AFI_INTR_MASK_MSI_MASK (1 << 8) | |
73 | ||
74 | #define AFI_SM_INTR_ENABLE 0xc4 | |
75 | #define AFI_SM_INTR_INTA_ASSERT (1 << 0) | |
76 | #define AFI_SM_INTR_INTB_ASSERT (1 << 1) | |
77 | #define AFI_SM_INTR_INTC_ASSERT (1 << 2) | |
78 | #define AFI_SM_INTR_INTD_ASSERT (1 << 3) | |
79 | #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) | |
80 | #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) | |
81 | #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) | |
82 | #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) | |
83 | ||
84 | #define AFI_AFI_INTR_ENABLE 0xc8 | |
85 | #define AFI_INTR_EN_INI_SLVERR (1 << 0) | |
86 | #define AFI_INTR_EN_INI_DECERR (1 << 1) | |
87 | #define AFI_INTR_EN_TGT_SLVERR (1 << 2) | |
88 | #define AFI_INTR_EN_TGT_DECERR (1 << 3) | |
89 | #define AFI_INTR_EN_TGT_WRERR (1 << 4) | |
90 | #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) | |
91 | #define AFI_INTR_EN_AXI_DECERR (1 << 6) | |
92 | #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) | |
93 | #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) | |
94 | ||
95 | #define AFI_PCIE_CONFIG 0x0f8 | |
96 | #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) | |
97 | #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe | |
98 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) | |
99 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20) | |
100 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) | |
101 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20) | |
102 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20) | |
103 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) | |
104 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) | |
105 | #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) | |
106 | ||
107 | #define AFI_FUSE 0x104 | |
108 | #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) | |
109 | ||
110 | #define AFI_PEX0_CTRL 0x110 | |
111 | #define AFI_PEX1_CTRL 0x118 | |
112 | #define AFI_PEX2_CTRL 0x128 | |
113 | #define AFI_PEX_CTRL_RST (1 << 0) | |
114 | #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) | |
115 | #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) | |
116 | #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) | |
117 | ||
118 | #define AFI_PLLE_CONTROL 0x160 | |
119 | #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) | |
120 | #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) | |
121 | ||
122 | #define AFI_PEXBIAS_CTRL_0 0x168 | |
123 | ||
124 | #define PADS_CTL_SEL 0x0000009C | |
125 | ||
126 | #define PADS_CTL 0x000000A0 | |
127 | #define PADS_CTL_IDDQ_1L (1 << 0) | |
128 | #define PADS_CTL_TX_DATA_EN_1L (1 << 6) | |
129 | #define PADS_CTL_RX_DATA_EN_1L (1 << 10) | |
130 | ||
131 | #define PADS_PLL_CTL_TEGRA20 0x000000B8 | |
132 | #define PADS_PLL_CTL_TEGRA30 0x000000B4 | |
133 | #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) | |
134 | #define PADS_PLL_CTL_LOCKDET (0x1 << 8) | |
135 | #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) | |
136 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16) | |
137 | #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16) | |
138 | #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16) | |
139 | #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) | |
140 | #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20) | |
141 | #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20) | |
142 | #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22) | |
143 | ||
144 | #define PADS_REFCLK_CFG0 0x000000C8 | |
145 | #define PADS_REFCLK_CFG1 0x000000CC | |
146 | ||
147 | /* | |
148 | * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit | |
149 | * entries, one entry per PCIe port. These field definitions and desired | |
150 | * values aren't in the TRM, but do come from NVIDIA. | |
151 | */ | |
152 | #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ | |
153 | #define PADS_REFCLK_CFG_E_TERM_SHIFT 7 | |
154 | #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ | |
155 | #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ | |
156 | ||
157 | /* Default value provided by HW engineering is 0xfa5c */ | |
158 | #define PADS_REFCLK_CFG_VALUE \ | |
159 | ( \ | |
160 | (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ | |
161 | (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ | |
162 | (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ | |
163 | (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ | |
164 | ) | |
165 | ||
166 | #define RP_VEND_XP 0x00000F00 | |
167 | #define RP_VEND_XP_DL_UP (1 << 30) | |
168 | ||
169 | #define RP_PRIV_MISC 0x00000FE0 | |
170 | #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) | |
171 | #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) | |
172 | ||
173 | #define RP_LINK_CONTROL_STATUS 0x00000090 | |
174 | #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 | |
175 | #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 | |
176 | ||
177 | struct tegra_pcie; | |
178 | ||
179 | struct tegra_pcie_port { | |
180 | struct tegra_pcie *pcie; | |
181 | ||
182 | struct fdt_resource regs; | |
183 | unsigned int num_lanes; | |
184 | unsigned int index; | |
185 | ||
186 | struct list_head list; | |
187 | }; | |
188 | ||
189 | struct tegra_pcie_soc { | |
190 | unsigned int num_ports; | |
191 | unsigned long pads_pll_ctl; | |
192 | unsigned long tx_ref_sel; | |
193 | bool has_pex_clkreq_en; | |
194 | bool has_pex_bias_ctrl; | |
195 | bool has_cml_clk; | |
196 | bool has_gen2; | |
197 | }; | |
198 | ||
199 | struct tegra_pcie { | |
200 | struct pci_controller hose; | |
201 | ||
202 | struct fdt_resource pads; | |
203 | struct fdt_resource afi; | |
204 | struct fdt_resource cs; | |
205 | ||
206 | struct fdt_resource prefetch; | |
207 | struct fdt_resource mem; | |
208 | struct fdt_resource io; | |
209 | ||
210 | struct list_head ports; | |
211 | unsigned long xbar; | |
212 | ||
213 | const struct tegra_pcie_soc *soc; | |
214 | struct tegra_xusb_phy *phy; | |
215 | }; | |
216 | ||
217 | static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose) | |
218 | { | |
219 | return container_of(hose, struct tegra_pcie, hose); | |
220 | } | |
221 | ||
222 | static void afi_writel(struct tegra_pcie *pcie, unsigned long value, | |
223 | unsigned long offset) | |
224 | { | |
225 | writel(value, pcie->afi.start + offset); | |
226 | } | |
227 | ||
228 | static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) | |
229 | { | |
230 | return readl(pcie->afi.start + offset); | |
231 | } | |
232 | ||
233 | static void pads_writel(struct tegra_pcie *pcie, unsigned long value, | |
234 | unsigned long offset) | |
235 | { | |
236 | writel(value, pcie->pads.start + offset); | |
237 | } | |
238 | ||
239 | static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) | |
240 | { | |
241 | return readl(pcie->pads.start + offset); | |
242 | } | |
243 | ||
244 | static unsigned long rp_readl(struct tegra_pcie_port *port, | |
245 | unsigned long offset) | |
246 | { | |
247 | return readl(port->regs.start + offset); | |
248 | } | |
249 | ||
250 | static void rp_writel(struct tegra_pcie_port *port, unsigned long value, | |
251 | unsigned long offset) | |
252 | { | |
253 | writel(value, port->regs.start + offset); | |
254 | } | |
255 | ||
256 | static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) | |
257 | { | |
258 | return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | | |
259 | (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | | |
260 | (where & 0xfc); | |
261 | } | |
262 | ||
263 | static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, | |
264 | int where, unsigned long *address) | |
265 | { | |
266 | unsigned int bus = PCI_BUS(bdf); | |
267 | ||
268 | if (bus == 0) { | |
269 | unsigned int dev = PCI_DEV(bdf); | |
270 | struct tegra_pcie_port *port; | |
271 | ||
272 | list_for_each_entry(port, &pcie->ports, list) { | |
273 | if (port->index + 1 == dev) { | |
274 | *address = port->regs.start + (where & ~3); | |
275 | return 0; | |
276 | } | |
277 | } | |
278 | } else { | |
279 | *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); | |
280 | return 0; | |
281 | } | |
282 | ||
283 | return -1; | |
284 | } | |
285 | ||
286 | static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf, | |
287 | int where, u32 *value) | |
288 | { | |
289 | struct tegra_pcie *pcie = to_tegra_pcie(hose); | |
290 | unsigned long address; | |
291 | int err; | |
292 | ||
293 | err = tegra_pcie_conf_address(pcie, bdf, where, &address); | |
294 | if (err < 0) { | |
295 | *value = 0xffffffff; | |
296 | return 1; | |
297 | } | |
298 | ||
299 | *value = readl(address); | |
300 | ||
301 | /* fixup root port class */ | |
302 | if (PCI_BUS(bdf) == 0) { | |
303 | if (where == PCI_CLASS_REVISION) { | |
304 | *value &= ~0x00ff0000; | |
305 | *value |= PCI_CLASS_BRIDGE_PCI << 16; | |
306 | } | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf, | |
313 | int where, u32 value) | |
314 | { | |
315 | struct tegra_pcie *pcie = to_tegra_pcie(hose); | |
316 | unsigned long address; | |
317 | int err; | |
318 | ||
319 | err = tegra_pcie_conf_address(pcie, bdf, where, &address); | |
320 | if (err < 0) | |
321 | return 1; | |
322 | ||
323 | writel(value, address); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int tegra_pcie_port_parse_dt(const void *fdt, int node, | |
329 | struct tegra_pcie_port *port) | |
330 | { | |
331 | const u32 *addr; | |
332 | int len; | |
333 | ||
334 | addr = fdt_getprop(fdt, node, "assigned-addresses", &len); | |
335 | if (!addr) { | |
336 | error("property \"assigned-addresses\" not found"); | |
337 | return -FDT_ERR_NOTFOUND; | |
338 | } | |
339 | ||
340 | port->regs.start = fdt32_to_cpu(addr[2]); | |
341 | port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, | |
347 | unsigned long *xbar) | |
348 | { | |
349 | enum fdt_compat_id id = fdtdec_lookup(fdt, node); | |
350 | ||
351 | switch (id) { | |
352 | case COMPAT_NVIDIA_TEGRA20_PCIE: | |
353 | switch (lanes) { | |
354 | case 0x00000004: | |
355 | debug("single-mode configuration\n"); | |
356 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE; | |
357 | return 0; | |
358 | ||
359 | case 0x00000202: | |
360 | debug("dual-mode configuration\n"); | |
361 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL; | |
362 | return 0; | |
363 | } | |
364 | break; | |
365 | ||
366 | case COMPAT_NVIDIA_TEGRA30_PCIE: | |
367 | switch (lanes) { | |
368 | case 0x00000204: | |
369 | debug("4x1, 2x1 configuration\n"); | |
370 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420; | |
371 | return 0; | |
372 | ||
373 | case 0x00020202: | |
374 | debug("2x3 configuration\n"); | |
375 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222; | |
376 | return 0; | |
377 | ||
378 | case 0x00010104: | |
379 | debug("4x1, 1x2 configuration\n"); | |
380 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411; | |
381 | return 0; | |
382 | } | |
383 | break; | |
384 | ||
385 | case COMPAT_NVIDIA_TEGRA124_PCIE: | |
386 | switch (lanes) { | |
387 | case 0x0000104: | |
388 | debug("4x1, 1x1 configuration\n"); | |
389 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; | |
390 | return 0; | |
391 | ||
392 | case 0x0000102: | |
393 | debug("2x1, 1x1 configuration\n"); | |
394 | *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; | |
395 | return 0; | |
396 | } | |
397 | break; | |
398 | ||
399 | default: | |
400 | break; | |
401 | } | |
402 | ||
403 | return -FDT_ERR_NOTFOUND; | |
404 | } | |
405 | ||
406 | static int tegra_pcie_parse_dt_ranges(const void *fdt, int node, | |
407 | struct tegra_pcie *pcie) | |
408 | { | |
409 | const u32 *ptr, *end; | |
410 | int len; | |
411 | ||
412 | ptr = fdt_getprop(fdt, node, "ranges", &len); | |
413 | if (!ptr) { | |
414 | error("missing \"ranges\" property"); | |
415 | return -FDT_ERR_NOTFOUND; | |
416 | } | |
417 | ||
418 | end = ptr + len / 4; | |
419 | ||
420 | while (ptr < end) { | |
421 | struct fdt_resource *res = NULL; | |
422 | u32 space = fdt32_to_cpu(*ptr); | |
423 | ||
424 | switch ((space >> 24) & 0x3) { | |
425 | case 0x01: | |
426 | res = &pcie->io; | |
427 | break; | |
428 | ||
429 | case 0x02: /* 32 bit */ | |
430 | case 0x03: /* 64 bit */ | |
431 | if (space & (1 << 30)) | |
432 | res = &pcie->prefetch; | |
433 | else | |
434 | res = &pcie->mem; | |
435 | ||
436 | break; | |
437 | } | |
438 | ||
439 | if (res) { | |
440 | res->start = fdt32_to_cpu(ptr[3]); | |
441 | res->end = res->start + fdt32_to_cpu(ptr[5]); | |
442 | } | |
443 | ||
444 | ptr += 3 + 1 + 2; | |
445 | } | |
446 | ||
447 | debug("PCI regions:\n"); | |
448 | debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end); | |
449 | debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start, | |
450 | pcie->mem.end); | |
451 | debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start, | |
452 | pcie->prefetch.end); | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static int tegra_pcie_parse_port_info(const void *fdt, int node, | |
458 | unsigned int *index, | |
459 | unsigned int *lanes) | |
460 | { | |
a62e84d7 | 461 | struct fdt_pci_addr addr; |
f315828b TR |
462 | int err; |
463 | ||
464 | err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0); | |
465 | if (err < 0) { | |
466 | error("failed to parse \"nvidia,num-lanes\" property"); | |
467 | return err; | |
468 | } | |
469 | ||
470 | *lanes = err; | |
471 | ||
053b86e6 | 472 | err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr); |
f315828b TR |
473 | if (err < 0) { |
474 | error("failed to parse \"reg\" property"); | |
475 | return err; | |
476 | } | |
477 | ||
053b86e6 | 478 | *index = PCI_DEV(addr.phys_hi) - 1; |
f315828b TR |
479 | |
480 | return 0; | |
481 | } | |
482 | ||
483 | static int tegra_pcie_parse_dt(const void *fdt, int node, | |
484 | struct tegra_pcie *pcie) | |
485 | { | |
486 | int err, subnode; | |
487 | u32 lanes = 0; | |
488 | ||
489 | err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads", | |
490 | &pcie->pads); | |
491 | if (err < 0) { | |
492 | error("resource \"pads\" not found"); | |
493 | return err; | |
494 | } | |
495 | ||
496 | err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi", | |
497 | &pcie->afi); | |
498 | if (err < 0) { | |
499 | error("resource \"afi\" not found"); | |
500 | return err; | |
501 | } | |
502 | ||
503 | err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs", | |
504 | &pcie->cs); | |
505 | if (err < 0) { | |
506 | error("resource \"cs\" not found"); | |
507 | return err; | |
508 | } | |
509 | ||
510 | pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); | |
511 | if (pcie->phy) { | |
512 | err = tegra_xusb_phy_prepare(pcie->phy); | |
513 | if (err < 0) { | |
514 | error("failed to prepare PHY: %d", err); | |
515 | return err; | |
516 | } | |
517 | } | |
518 | ||
519 | err = tegra_pcie_parse_dt_ranges(fdt, node, pcie); | |
520 | if (err < 0) { | |
521 | error("failed to parse \"ranges\" property"); | |
522 | return err; | |
523 | } | |
524 | ||
525 | fdt_for_each_subnode(fdt, subnode, node) { | |
526 | unsigned int index = 0, num_lanes = 0; | |
527 | struct tegra_pcie_port *port; | |
528 | ||
529 | err = tegra_pcie_parse_port_info(fdt, subnode, &index, | |
530 | &num_lanes); | |
531 | if (err < 0) { | |
532 | error("failed to obtain root port info"); | |
533 | continue; | |
534 | } | |
535 | ||
536 | lanes |= num_lanes << (index << 3); | |
537 | ||
538 | if (!fdtdec_get_is_enabled(fdt, subnode)) | |
539 | continue; | |
540 | ||
541 | port = malloc(sizeof(*port)); | |
542 | if (!port) | |
543 | continue; | |
544 | ||
545 | memset(port, 0, sizeof(*port)); | |
546 | port->num_lanes = num_lanes; | |
547 | port->index = index; | |
548 | ||
549 | err = tegra_pcie_port_parse_dt(fdt, subnode, port); | |
550 | if (err < 0) { | |
551 | free(port); | |
552 | continue; | |
553 | } | |
554 | ||
555 | list_add_tail(&port->list, &pcie->ports); | |
556 | port->pcie = pcie; | |
557 | } | |
558 | ||
559 | err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar); | |
560 | if (err < 0) { | |
561 | error("invalid lane configuration"); | |
562 | return err; | |
563 | } | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | int __weak tegra_pcie_board_init(void) | |
569 | { | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static int tegra_pcie_power_on(struct tegra_pcie *pcie) | |
574 | { | |
575 | const struct tegra_pcie_soc *soc = pcie->soc; | |
576 | unsigned long value; | |
577 | int err; | |
578 | ||
579 | /* reset PCIEXCLK logic, AFI controller and PCIe controller */ | |
580 | reset_set_enable(PERIPH_ID_PCIEXCLK, 1); | |
581 | reset_set_enable(PERIPH_ID_AFI, 1); | |
582 | reset_set_enable(PERIPH_ID_PCIE, 1); | |
583 | ||
584 | err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); | |
585 | if (err < 0) { | |
586 | error("failed to power off PCIe partition: %d", err); | |
587 | return err; | |
588 | } | |
589 | ||
590 | tegra_pcie_board_init(); | |
591 | ||
592 | err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, | |
593 | PERIPH_ID_PCIE); | |
594 | if (err < 0) { | |
595 | error("failed to power up PCIe partition: %d", err); | |
596 | return err; | |
597 | } | |
598 | ||
599 | /* take AFI controller out of reset */ | |
600 | reset_set_enable(PERIPH_ID_AFI, 0); | |
601 | ||
602 | /* enable AFI clock */ | |
603 | clock_enable(PERIPH_ID_AFI); | |
604 | ||
605 | if (soc->has_cml_clk) { | |
606 | /* enable CML clock */ | |
607 | value = readl(NV_PA_CLK_RST_BASE + 0x48c); | |
608 | value |= (1 << 0); | |
609 | value &= ~(1 << 1); | |
610 | writel(value, NV_PA_CLK_RST_BASE + 0x48c); | |
611 | } | |
612 | ||
613 | err = tegra_plle_enable(); | |
614 | if (err < 0) { | |
615 | error("failed to enable PLLE: %d\n", err); | |
616 | return err; | |
617 | } | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) | |
623 | { | |
624 | const struct tegra_pcie_soc *soc = pcie->soc; | |
625 | unsigned long start = get_timer(0); | |
626 | u32 value; | |
627 | ||
628 | while (get_timer(start) < timeout) { | |
629 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
630 | if (value & PADS_PLL_CTL_LOCKDET) | |
631 | return 0; | |
632 | } | |
633 | ||
634 | return -ETIMEDOUT; | |
635 | } | |
636 | ||
637 | static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) | |
638 | { | |
639 | const struct tegra_pcie_soc *soc = pcie->soc; | |
640 | u32 value; | |
641 | int err; | |
642 | ||
643 | /* initialize internal PHY, enable up to 16 PCIe lanes */ | |
644 | pads_writel(pcie, 0, PADS_CTL_SEL); | |
645 | ||
646 | /* override IDDQ to 1 on all 4 lanes */ | |
647 | value = pads_readl(pcie, PADS_CTL); | |
648 | value |= PADS_CTL_IDDQ_1L; | |
649 | pads_writel(pcie, value, PADS_CTL); | |
650 | ||
651 | /* | |
652 | * Set up PHY PLL inputs select PLLE output as refclock, set TX | |
653 | * ref sel to div10 (not div5). | |
654 | */ | |
655 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
656 | value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); | |
657 | value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; | |
658 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
659 | ||
660 | /* reset PLL */ | |
661 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
662 | value &= ~PADS_PLL_CTL_RST_B4SM; | |
663 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
664 | ||
665 | udelay(20); | |
666 | ||
667 | /* take PLL out of reset */ | |
668 | value = pads_readl(pcie, soc->pads_pll_ctl); | |
669 | value |= PADS_PLL_CTL_RST_B4SM; | |
670 | pads_writel(pcie, value, soc->pads_pll_ctl); | |
671 | ||
672 | /* configure the reference clock driver */ | |
673 | value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); | |
674 | pads_writel(pcie, value, PADS_REFCLK_CFG0); | |
675 | ||
676 | if (soc->num_ports > 2) | |
677 | pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); | |
678 | ||
679 | /* wait for the PLL to lock */ | |
680 | err = tegra_pcie_pll_wait(pcie, 500); | |
681 | if (err < 0) { | |
682 | error("PLL failed to lock: %d", err); | |
683 | return err; | |
684 | } | |
685 | ||
686 | /* turn off IDDQ override */ | |
687 | value = pads_readl(pcie, PADS_CTL); | |
688 | value &= ~PADS_CTL_IDDQ_1L; | |
689 | pads_writel(pcie, value, PADS_CTL); | |
690 | ||
691 | /* enable TX/RX data */ | |
692 | value = pads_readl(pcie, PADS_CTL); | |
693 | value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L; | |
694 | pads_writel(pcie, value, PADS_CTL); | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) | |
700 | { | |
701 | const struct tegra_pcie_soc *soc = pcie->soc; | |
702 | struct tegra_pcie_port *port; | |
703 | u32 value; | |
704 | int err; | |
705 | ||
706 | if (pcie->phy) { | |
707 | value = afi_readl(pcie, AFI_PLLE_CONTROL); | |
708 | value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; | |
709 | value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; | |
710 | afi_writel(pcie, value, AFI_PLLE_CONTROL); | |
711 | } | |
712 | ||
713 | if (soc->has_pex_bias_ctrl) | |
714 | afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0); | |
715 | ||
716 | value = afi_readl(pcie, AFI_PCIE_CONFIG); | |
717 | value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; | |
718 | value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar; | |
719 | ||
720 | list_for_each_entry(port, &pcie->ports, list) | |
721 | value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index); | |
722 | ||
723 | afi_writel(pcie, value, AFI_PCIE_CONFIG); | |
724 | ||
725 | value = afi_readl(pcie, AFI_FUSE); | |
726 | ||
727 | if (soc->has_gen2) | |
728 | value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; | |
729 | else | |
730 | value |= AFI_FUSE_PCIE_T0_GEN2_DIS; | |
731 | ||
732 | afi_writel(pcie, value, AFI_FUSE); | |
733 | ||
734 | if (pcie->phy) | |
735 | err = tegra_xusb_phy_enable(pcie->phy); | |
736 | else | |
737 | err = tegra_pcie_phy_enable(pcie); | |
738 | ||
739 | if (err < 0) { | |
740 | error("failed to power on PHY: %d\n", err); | |
741 | return err; | |
742 | } | |
743 | ||
744 | /* take the PCIEXCLK logic out of reset */ | |
745 | reset_set_enable(PERIPH_ID_PCIEXCLK, 0); | |
746 | ||
747 | /* finally enable PCIe */ | |
748 | value = afi_readl(pcie, AFI_CONFIGURATION); | |
749 | value |= AFI_CONFIGURATION_EN_FPCI; | |
750 | afi_writel(pcie, value, AFI_CONFIGURATION); | |
751 | ||
752 | /* disable all interrupts */ | |
753 | afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE); | |
754 | afi_writel(pcie, 0, AFI_SM_INTR_ENABLE); | |
755 | afi_writel(pcie, 0, AFI_INTR_MASK); | |
756 | afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) | |
762 | { | |
763 | unsigned long fpci, axi, size; | |
764 | ||
765 | /* BAR 0: type 1 extended configuration space */ | |
766 | fpci = 0xfe100000; | |
767 | size = fdt_resource_size(&pcie->cs); | |
768 | axi = pcie->cs.start; | |
769 | ||
770 | afi_writel(pcie, axi, AFI_AXI_BAR0_START); | |
771 | afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); | |
772 | afi_writel(pcie, fpci, AFI_FPCI_BAR0); | |
773 | ||
774 | /* BAR 1: downstream I/O */ | |
775 | fpci = 0xfdfc0000; | |
776 | size = fdt_resource_size(&pcie->io); | |
777 | axi = pcie->io.start; | |
778 | ||
779 | afi_writel(pcie, axi, AFI_AXI_BAR1_START); | |
780 | afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ); | |
781 | afi_writel(pcie, fpci, AFI_FPCI_BAR1); | |
782 | ||
783 | /* BAR 2: prefetchable memory */ | |
784 | fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
785 | size = fdt_resource_size(&pcie->prefetch); | |
786 | axi = pcie->prefetch.start; | |
787 | ||
788 | afi_writel(pcie, axi, AFI_AXI_BAR2_START); | |
789 | afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ); | |
790 | afi_writel(pcie, fpci, AFI_FPCI_BAR2); | |
791 | ||
792 | /* BAR 3: non-prefetchable memory */ | |
793 | fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1; | |
794 | size = fdt_resource_size(&pcie->mem); | |
795 | axi = pcie->mem.start; | |
796 | ||
797 | afi_writel(pcie, axi, AFI_AXI_BAR3_START); | |
798 | afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ); | |
799 | afi_writel(pcie, fpci, AFI_FPCI_BAR3); | |
800 | ||
801 | /* NULL out the remaining BARs as they are not used */ | |
802 | afi_writel(pcie, 0, AFI_AXI_BAR4_START); | |
803 | afi_writel(pcie, 0, AFI_AXI_BAR4_SZ); | |
804 | afi_writel(pcie, 0, AFI_FPCI_BAR4); | |
805 | ||
806 | afi_writel(pcie, 0, AFI_AXI_BAR5_START); | |
807 | afi_writel(pcie, 0, AFI_AXI_BAR5_SZ); | |
808 | afi_writel(pcie, 0, AFI_FPCI_BAR5); | |
809 | ||
810 | /* map all upstream transactions as uncached */ | |
811 | afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST); | |
812 | afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ); | |
813 | afi_writel(pcie, 0, AFI_CACHE_BAR1_ST); | |
814 | afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ); | |
815 | ||
816 | /* MSI translations are setup only when needed */ | |
817 | afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST); | |
818 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
819 | afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST); | |
820 | afi_writel(pcie, 0, AFI_MSI_BAR_SZ); | |
821 | } | |
822 | ||
823 | static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) | |
824 | { | |
825 | unsigned long ret = 0; | |
826 | ||
827 | switch (port->index) { | |
828 | case 0: | |
829 | ret = AFI_PEX0_CTRL; | |
830 | break; | |
831 | ||
832 | case 1: | |
833 | ret = AFI_PEX1_CTRL; | |
834 | break; | |
835 | ||
836 | case 2: | |
837 | ret = AFI_PEX2_CTRL; | |
838 | break; | |
839 | } | |
840 | ||
841 | return ret; | |
842 | } | |
843 | ||
844 | static void tegra_pcie_port_reset(struct tegra_pcie_port *port) | |
845 | { | |
846 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
847 | unsigned long value; | |
848 | ||
849 | /* pulse reset signel */ | |
850 | value = afi_readl(port->pcie, ctrl); | |
851 | value &= ~AFI_PEX_CTRL_RST; | |
852 | afi_writel(port->pcie, value, ctrl); | |
853 | ||
854 | udelay(2000); | |
855 | ||
856 | value = afi_readl(port->pcie, ctrl); | |
857 | value |= AFI_PEX_CTRL_RST; | |
858 | afi_writel(port->pcie, value, ctrl); | |
859 | } | |
860 | ||
861 | static void tegra_pcie_port_enable(struct tegra_pcie_port *port) | |
862 | { | |
863 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
864 | unsigned long value; | |
865 | ||
866 | /* enable reference clock */ | |
867 | value = afi_readl(port->pcie, ctrl); | |
868 | value |= AFI_PEX_CTRL_REFCLK_EN; | |
869 | ||
870 | if (port->pcie->soc->has_pex_clkreq_en) | |
871 | value |= AFI_PEX_CTRL_CLKREQ_EN; | |
872 | ||
873 | value |= AFI_PEX_CTRL_OVERRIDE_EN; | |
874 | ||
875 | afi_writel(port->pcie, value, ctrl); | |
876 | ||
877 | tegra_pcie_port_reset(port); | |
878 | } | |
879 | ||
880 | static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) | |
881 | { | |
882 | unsigned int retries = 3; | |
883 | unsigned long value; | |
884 | ||
885 | value = rp_readl(port, RP_PRIV_MISC); | |
886 | value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; | |
887 | value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; | |
888 | rp_writel(port, value, RP_PRIV_MISC); | |
889 | ||
890 | do { | |
891 | unsigned int timeout = 200; | |
892 | ||
893 | do { | |
894 | value = rp_readl(port, RP_VEND_XP); | |
895 | if (value & RP_VEND_XP_DL_UP) | |
896 | break; | |
897 | ||
898 | udelay(2000); | |
899 | } while (--timeout); | |
900 | ||
901 | if (!timeout) { | |
902 | debug("link %u down, retrying\n", port->index); | |
903 | goto retry; | |
904 | } | |
905 | ||
906 | timeout = 200; | |
907 | ||
908 | do { | |
909 | value = rp_readl(port, RP_LINK_CONTROL_STATUS); | |
910 | if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) | |
911 | return true; | |
912 | ||
913 | udelay(2000); | |
914 | } while (--timeout); | |
915 | ||
916 | retry: | |
917 | tegra_pcie_port_reset(port); | |
918 | } while (--retries); | |
919 | ||
920 | return false; | |
921 | } | |
922 | ||
923 | static void tegra_pcie_port_disable(struct tegra_pcie_port *port) | |
924 | { | |
925 | unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); | |
926 | unsigned long value; | |
927 | ||
928 | /* assert port reset */ | |
929 | value = afi_readl(port->pcie, ctrl); | |
930 | value &= ~AFI_PEX_CTRL_RST; | |
931 | afi_writel(port->pcie, value, ctrl); | |
932 | ||
933 | /* disable reference clock */ | |
934 | value = afi_readl(port->pcie, ctrl); | |
935 | value &= ~AFI_PEX_CTRL_REFCLK_EN; | |
936 | afi_writel(port->pcie, value, ctrl); | |
937 | } | |
938 | ||
939 | static void tegra_pcie_port_free(struct tegra_pcie_port *port) | |
940 | { | |
941 | list_del(&port->list); | |
942 | free(port); | |
943 | } | |
944 | ||
945 | static int tegra_pcie_enable(struct tegra_pcie *pcie) | |
946 | { | |
947 | struct tegra_pcie_port *port, *tmp; | |
948 | ||
949 | list_for_each_entry_safe(port, tmp, &pcie->ports, list) { | |
950 | debug("probing port %u, using %u lanes\n", port->index, | |
951 | port->num_lanes); | |
952 | ||
953 | tegra_pcie_port_enable(port); | |
954 | ||
955 | if (tegra_pcie_port_check_link(port)) | |
956 | continue; | |
957 | ||
958 | debug("link %u down, ignoring\n", port->index); | |
959 | ||
960 | tegra_pcie_port_disable(port); | |
961 | tegra_pcie_port_free(port); | |
962 | } | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | static const struct tegra_pcie_soc tegra20_pcie_soc = { | |
968 | .num_ports = 2, | |
969 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, | |
970 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, | |
971 | .has_pex_clkreq_en = false, | |
972 | .has_pex_bias_ctrl = false, | |
973 | .has_cml_clk = false, | |
974 | .has_gen2 = false, | |
975 | }; | |
976 | ||
977 | static const struct tegra_pcie_soc tegra30_pcie_soc = { | |
978 | .num_ports = 3, | |
979 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
980 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
981 | .has_pex_clkreq_en = true, | |
982 | .has_pex_bias_ctrl = true, | |
983 | .has_cml_clk = true, | |
984 | .has_gen2 = false, | |
985 | }; | |
986 | ||
987 | static const struct tegra_pcie_soc tegra124_pcie_soc = { | |
988 | .num_ports = 2, | |
989 | .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, | |
990 | .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, | |
991 | .has_pex_clkreq_en = true, | |
992 | .has_pex_bias_ctrl = true, | |
993 | .has_cml_clk = true, | |
994 | .has_gen2 = true, | |
995 | }; | |
996 | ||
997 | static int process_nodes(const void *fdt, int nodes[], unsigned int count) | |
998 | { | |
999 | unsigned int i; | |
1000 | ||
1001 | for (i = 0; i < count; i++) { | |
1002 | const struct tegra_pcie_soc *soc; | |
1003 | struct tegra_pcie *pcie; | |
1004 | enum fdt_compat_id id; | |
1005 | int err; | |
1006 | ||
1007 | if (!fdtdec_get_is_enabled(fdt, nodes[i])) | |
1008 | continue; | |
1009 | ||
1010 | id = fdtdec_lookup(fdt, nodes[i]); | |
1011 | switch (id) { | |
1012 | case COMPAT_NVIDIA_TEGRA20_PCIE: | |
1013 | soc = &tegra20_pcie_soc; | |
1014 | break; | |
1015 | ||
1016 | case COMPAT_NVIDIA_TEGRA30_PCIE: | |
1017 | soc = &tegra30_pcie_soc; | |
1018 | break; | |
1019 | ||
1020 | case COMPAT_NVIDIA_TEGRA124_PCIE: | |
1021 | soc = &tegra124_pcie_soc; | |
1022 | break; | |
1023 | ||
1024 | default: | |
1025 | error("unsupported compatible: %s", | |
1026 | fdtdec_get_compatible(id)); | |
1027 | continue; | |
1028 | } | |
1029 | ||
1030 | pcie = malloc(sizeof(*pcie)); | |
1031 | if (!pcie) { | |
1032 | error("failed to allocate controller"); | |
1033 | continue; | |
1034 | } | |
1035 | ||
1036 | memset(pcie, 0, sizeof(*pcie)); | |
1037 | pcie->soc = soc; | |
1038 | ||
1039 | INIT_LIST_HEAD(&pcie->ports); | |
1040 | ||
1041 | err = tegra_pcie_parse_dt(fdt, nodes[i], pcie); | |
1042 | if (err < 0) { | |
1043 | free(pcie); | |
1044 | continue; | |
1045 | } | |
1046 | ||
1047 | err = tegra_pcie_power_on(pcie); | |
1048 | if (err < 0) { | |
1049 | error("failed to power on"); | |
1050 | continue; | |
1051 | } | |
1052 | ||
1053 | err = tegra_pcie_enable_controller(pcie); | |
1054 | if (err < 0) { | |
1055 | error("failed to enable controller"); | |
1056 | continue; | |
1057 | } | |
1058 | ||
1059 | tegra_pcie_setup_translations(pcie); | |
1060 | ||
1061 | err = tegra_pcie_enable(pcie); | |
1062 | if (err < 0) { | |
1063 | error("failed to enable PCIe"); | |
1064 | continue; | |
1065 | } | |
1066 | ||
1067 | pcie->hose.first_busno = 0; | |
1068 | pcie->hose.current_busno = 0; | |
1069 | pcie->hose.last_busno = 0; | |
1070 | ||
1071 | pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE, | |
1072 | NV_PA_SDRAM_BASE, gd->ram_size, | |
1073 | PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); | |
1074 | ||
1075 | pci_set_region(&pcie->hose.regions[1], pcie->io.start, | |
1076 | pcie->io.start, fdt_resource_size(&pcie->io), | |
1077 | PCI_REGION_IO); | |
1078 | ||
1079 | pci_set_region(&pcie->hose.regions[2], pcie->mem.start, | |
1080 | pcie->mem.start, fdt_resource_size(&pcie->mem), | |
1081 | PCI_REGION_MEM); | |
1082 | ||
1083 | pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start, | |
1084 | pcie->prefetch.start, | |
1085 | fdt_resource_size(&pcie->prefetch), | |
1086 | PCI_REGION_MEM | PCI_REGION_PREFETCH); | |
1087 | ||
1088 | pcie->hose.region_count = 4; | |
1089 | ||
1090 | pci_set_ops(&pcie->hose, | |
1091 | pci_hose_read_config_byte_via_dword, | |
1092 | pci_hose_read_config_word_via_dword, | |
1093 | tegra_pcie_read_conf, | |
1094 | pci_hose_write_config_byte_via_dword, | |
1095 | pci_hose_write_config_word_via_dword, | |
1096 | tegra_pcie_write_conf); | |
1097 | ||
1098 | pci_register_hose(&pcie->hose); | |
1099 | ||
1100 | #ifdef CONFIG_PCI_SCAN_SHOW | |
1101 | printf("PCI: Enumerating devices...\n"); | |
1102 | printf("---------------------------------------\n"); | |
1103 | printf(" Device ID Description\n"); | |
1104 | printf(" ------ -- -----------\n"); | |
1105 | #endif | |
1106 | ||
1107 | pcie->hose.last_busno = pci_hose_scan(&pcie->hose); | |
1108 | } | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | void pci_init_board(void) | |
1114 | { | |
1115 | const void *fdt = gd->fdt_blob; | |
1116 | int count, nodes[1]; | |
1117 | ||
1118 | count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", | |
1119 | COMPAT_NVIDIA_TEGRA124_PCIE, | |
1120 | nodes, ARRAY_SIZE(nodes)); | |
1121 | if (process_nodes(fdt, nodes, count)) | |
1122 | return; | |
1123 | ||
1124 | count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", | |
1125 | COMPAT_NVIDIA_TEGRA30_PCIE, | |
1126 | nodes, ARRAY_SIZE(nodes)); | |
1127 | if (process_nodes(fdt, nodes, count)) | |
1128 | return; | |
1129 | ||
1130 | count = fdtdec_find_aliases_for_id(fdt, "pcie-controller", | |
1131 | COMPAT_NVIDIA_TEGRA20_PCIE, | |
1132 | nodes, ARRAY_SIZE(nodes)); | |
1133 | if (process_nodes(fdt, nodes, count)) | |
1134 | return; | |
1135 | } | |
1136 | ||
1137 | int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) | |
1138 | { | |
1139 | if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0) | |
1140 | return 1; | |
1141 | ||
1142 | return 0; | |
1143 | } |