[thirdparty/u-boot.git] / drivers / pci / pcie_fsl.c

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2019 NXP
 *
 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include "pcie_fsl.h"
#include <dm/device_compat.h>

LIST_HEAD(fsl_pcie_list);

static int fsl_pcie_link_up(struct fsl_pcie *pcie);

static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
{
	struct udevice *bus = pcie->bus;

	if (!pcie->enabled)
		return -ENXIO;

	if (PCI_BUS(bdf) < bus->seq)
		return -EINVAL;

	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
		return -EINVAL;

	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
		return -EINVAL;

	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
		return -EINVAL;

	return 0;
}

static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
				uint offset, ulong *valuep,
				enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;

	if (fsl_pcie_addr_valid(pcie, bdf)) {
		*valuep = pci_get_ff(size);
		return 0;
	}

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		*valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
		break;
	case PCI_SIZE_16:
		*valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
			  (offset & 2)));
		break;
	case PCI_SIZE_32:
		*valuep = in_le32(&regs->cfg_data);
		break;
	}

	return 0;
}

static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
				 uint offset, ulong value,
				 enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;
	u8 val_8;
	u16 val_16;
	u32 val_32;

	if (fsl_pcie_addr_valid(pcie, bdf))
		return 0;

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		val_8 = value;
		out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
		break;
	case PCI_SIZE_16:
		val_16 = value;
		out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
		break;
	case PCI_SIZE_32:
		val_32 = value;
		out_le32(&regs->cfg_data, val_32);
		break;
	}

	return 0;
}

static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
				     ulong *valuep, enum pci_size_t size)
{
	int ret;
	struct udevice *bus = pcie->bus;

	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
				   offset, valuep, size);

	return ret;
}

static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
				      ulong value, enum pci_size_t size)
{
	struct udevice *bus = pcie->bus;

	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
				     offset, value, size);
}

static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
					  u8 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
					  u16 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
					   u32 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
					   u8 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
}

static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
					   u16 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
}

static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
					    u32 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
}

static int fsl_pcie_link_up(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 ltssm;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		ltssm = (in_be32(&regs->pex_csr0)
			& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
		return ltssm == LTSSM_L0_REV3;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);

	return ltssm == LTSSM_L0;
}

static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
{
	u8 header_type;

	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);

	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
}

static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (mem)
		set_next_law(mem->phys_start,
			     law_size_bits(mem->size),
			     pcie->law_trgt_if);

	if (io)
		set_next_law(io->phys_start,
			     law_size_bits(io->size),
			     pcie->law_trgt_if);

	return 0;
}

static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
		return;
	}

	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
}

static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
				       int type, u64 phys, u64 bus_addr,
				       pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pot_t *po = &regs->pot[idx];
	u32 war, sz;

	if (idx < 0)
		return -EINVAL;

	out_be32(&po->powbar, phys >> 12);
	out_be32(&po->potar, bus_addr >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&po->potear, bus_addr >> 44);
#else
	out_be32(&po->potear, 0);
#endif

	sz = (__ilog2_u64((u64)size) - 1);
	war = POWAR_EN | sz;

	if (type == PCI_REGION_IO)
		war |= POWAR_IO_READ | POWAR_IO_WRITE;
	else
		war |= POWAR_MEM_READ | POWAR_MEM_WRITE;

	out_be32(&po->powar, war);

	return 0;
}

static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
				      bool pf, u64 phys, u64 bus_addr,
				      pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pit_t *pi = &regs->pit[idx];
	u32 sz = (__ilog2_u64(size) - 1);
	u32 flag = PIWAR_LOCAL;

	if (idx < 0)
		return -EINVAL;

	out_be32(&pi->pitar, phys >> 12);
	out_be32(&pi->piwbar, bus_addr >> 12);

#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&pi->piwbear, bus_addr >> 44);
#else
	out_be32(&pi->piwbear, 0);
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	flag = 0;
#endif

	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
	if (pf)
		flag |= PIWAR_PF;
	out_be32(&pi->piwar, flag | sz);

	return 0;
}

static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;
	int idx = 1; /* skip 0 */

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (io)
		/* ATU : OUTBOUND : IO */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_IO,
					    io->phys_start,
					    io->bus_start,
					    io->size);

	if (mem)
		/* ATU : OUTBOUND : MEM */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_MEM,
					    mem->phys_start,
					    mem->bus_start,
					    mem->size);
	return 0;
}

static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
{
	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	pci_size_t pci_sz;
	int idx;

	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
		idx = 2;
	else
		idx = 3;

	pci_sz = 1ull << __ilog2_u64(sz);

	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)bus_start, (u64)phys_start, (u64)sz);

	/* if we aren't an exact power of two match, pci_sz is smaller
	 * round it up to the next power of two.  We report the actual
	 * size to pci region tracking.
	 */
	if (pci_sz != sz)
		sz = 2ull << __ilog2_u64(sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI_MEMORY_BUS, sz);
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	/*
	 * On 64-bit capable systems, set up a mapping for all of DRAM
	 * in high pci address space.
	 */
	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
	/* round up to the next largest power of two */
	if (gd->ram_size > pci_sz)
		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);

	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
		(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
#endif

	return 0;
}

static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
{
	fsl_pcie_setup_outbound_wins(pcie);
	fsl_pcie_setup_inbound_wins(pcie);

	return 0;
}

static int fsl_pcie_init_port(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val_32;
	u16 val_16;

	fsl_pcie_init_atmu(pcie);

#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	val_32 = 0;
	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	val_32 &= ~0x03;
	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	udelay(1);
#endif

#ifdef CONFIG_FSL_PCIE_RESET
	u16 ltssm;
	int i;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		/* assert PCIe reset */
		setbits_be32(&regs->pdb_stat, 0x08000000);
		(void)in_be32(&regs->pdb_stat);
		udelay(1000);
		/* clear PCIe reset */
		clrbits_be32(&regs->pdb_stat, 0x08000000);
		asm("sync;isync");
		for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
			udelay(1000);
	} else {
		fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
		if (ltssm == 1) {
			/* assert PCIe reset */
			setbits_be32(&regs->pdb_stat, 0x08000000);
			(void)in_be32(&regs->pdb_stat);
			udelay(100);
			/* clear PCIe reset */
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 &&
			     !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
	if (!fsl_pcie_link_up(pcie)) {
		serdes_corenet_t *srds_regs;

		srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
		val_32 = in_be32(&srds_regs->srdspccr0);

		if ((val_32 >> 28) == 3) {
			int i;

			out_be32(&srds_regs->srdspccr0, 2 << 28);
			setbits_be32(&regs->pdb_stat, 0x08000000);
			in_be32(&regs->pdb_stat);
			udelay(100);
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

	/*
	 * The Read-Only Write Enable bit defaults to 1 instead of 0.
	 * Set to 0 to protect the read-only registers.
	 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
#endif

	/*
	 * Enable All Error Interrupts except
	 * - Master abort (pci)
	 * - Master PERR (pci)
	 * - ICCA (PCIe)
	 */
	out_be32(&regs->peer, ~0x20140);

	/* set URR, FER, NFER (but not CER) */
	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	val_32 |= 0xf000e;
	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);

	/* Clear all error indications */
	out_be32(&regs->pme_msg_det, 0xffffffff);
	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	out_be32(&regs->pedr, 0xffffffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);

	return 0;
}

static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 classcode_reg;
	u32 val;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		classcode_reg = PCI_CLASS_REVISION;
		setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	} else {
		classcode_reg = CSR_CLASSCODE;
	}

	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
	val &= 0xff;
	val |= PCI_CLASS_BRIDGE_PCI << 16;
	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);

	return 0;
}

static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
{
	return fsl_pcie_fixup_classcode(pcie);
}

static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
{
	fsl_pcie_config_ready(pcie);

	return 0;
}

static int fsl_pcie_probe(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 val_16;

	pcie->bus = dev;
	pcie->block_rev = in_be32(&regs->block_rev1);

	list_add(&pcie->list, &fsl_pcie_list);
	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	if (!pcie->enabled) {
		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
		return 0;
	}

	fsl_pcie_setup_law(pcie);

	pcie->mode = fsl_pcie_is_agent(pcie);

	fsl_pcie_init_port(pcie);

	printf("PCIe%d: %s ", pcie->idx, dev->name);

	if (pcie->mode) {
		printf("Endpoint");
		fsl_pcie_init_ep(pcie);
	} else {
		printf("Root Complex");
		fsl_pcie_init_rc(pcie);
	}

	if (!fsl_pcie_link_up(pcie)) {
		printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
		return 0;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));

	return 0;
}

static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	struct fsl_pcie_data *info;
	int ret;

	pcie->regs = dev_remap_addr(dev);
	if (!pcie->regs) {
		pr_err("\"reg\" resource not found\n");
		return -EINVAL;
	}

	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	if (ret < 0) {
		pr_err("\"law_trgt_if\" not found\n");
		return ret;
	}

	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	pcie->info = info;
	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
		    info->block_offset) / info->stride;

	return 0;
}

static const struct dm_pci_ops fsl_pcie_ops = {
	.read_config	= fsl_pcie_read_config,
	.write_config	= fsl_pcie_write_config,
};

static struct fsl_pcie_data p1_p2_data = {
	.block_offset = 0xa000,
	.block_offset_mask = 0xffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data p2041_data = {
	.block_offset = 0x200000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data t2080_data = {
	.block_offset = 0x240000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x10000,
};

static const struct udevice_id fsl_pcie_ids[] = {
	{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
	{ }
};

U_BOOT_DRIVER(fsl_pcie) = {
	.name = "fsl_pcie",
	.id = UCLASS_PCI,
	.of_match = fsl_pcie_ids,
	.ops = &fsl_pcie_ops,
	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	.probe = fsl_pcie_probe,
	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
};
Commit	Line	Data
b89e3d92 HZ	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
	2	/*
	3	* Copyright 2019 NXP
	4	*
	5	* PCIe DM U-Boot driver for Freescale PowerPC SoCs
	6	* Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
	11	#include <malloc.h>
	12	#include <mapmem.h>
	13	#include <pci.h>
	14	#include <asm/fsl_pci.h>
	15	#include <asm/fsl_serdes.h>
	16	#include <asm/io.h>
	17	#include "pcie_fsl.h"
336d4615	18	#include <dm/device_compat.h>
b89e3d92 HZ	19
	20	LIST_HEAD(fsl_pcie_list);
	21
	22	static int fsl_pcie_link_up(struct fsl_pcie *pcie);
	23
	24	static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
	25	{
	26	struct udevice *bus = pcie->bus;
	27
	28	if (!pcie->enabled)
	29	return -ENXIO;
	30
	31	if (PCI_BUS(bdf) < bus->seq)
	32	return -EINVAL;
	33
	34	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) \|\| pcie->mode))
	35	return -EINVAL;
	36
	37	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 \|\| PCI_FUNC(bdf) > 0))
	38	return -EINVAL;
	39
	40	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
	41	return -EINVAL;
	42
	43	return 0;
	44	}
	45
c4e72c4a	46	static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
b89e3d92 HZ	47	uint offset, ulong *valuep,
	48	enum pci_size_t size)
	49	{
	50	struct fsl_pcie *pcie = dev_get_priv(bus);
	51	ccsr_fsl_pci_t *regs = pcie->regs;
	52	u32 val;
	53
	54	if (fsl_pcie_addr_valid(pcie, bdf)) {
	55	*valuep = pci_get_ff(size);
	56	return 0;
	57	}
	58
	59	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	60	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
	61	out_be32(&regs->cfg_addr, val);
	62
	63	sync();
	64
	65	switch (size) {
	66	case PCI_SIZE_8:
	67	valuep = in_8((u8 )&regs->cfg_data + (offset & 3));
	68	break;
	69	case PCI_SIZE_16:
	70	valuep = in_le16((u16 )((u8 *)&regs->cfg_data +
	71	(offset & 2)));
	72	break;
	73	case PCI_SIZE_32:
	74	*valuep = in_le32(&regs->cfg_data);
	75	break;
	76	}
	77
	78	return 0;
	79	}
	80
	81	static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
	82	uint offset, ulong value,
	83	enum pci_size_t size)
	84	{
	85	struct fsl_pcie *pcie = dev_get_priv(bus);
	86	ccsr_fsl_pci_t *regs = pcie->regs;
	87	u32 val;
	88	u8 val_8;
	89	u16 val_16;
	90	u32 val_32;
	91
	92	if (fsl_pcie_addr_valid(pcie, bdf))
	93	return 0;
	94
	95	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	96	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
	97	out_be32(&regs->cfg_addr, val);
	98
	99	sync();
	100
	101	switch (size) {
	102	case PCI_SIZE_8:
	103	val_8 = value;
	104	out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
	105	break;
	106	case PCI_SIZE_16:
	107	val_16 = value;
	108	out_le16((u16 )((u8 )&regs->cfg_data + (offset & 2)), val_16);
	109	break;
	110	case PCI_SIZE_32:
111	val_32 = value;
112	out_le32(&regs->cfg_data, val_32);
113	break;
114	}
115
116	return 0;
117	}
118
119	static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
120	ulong *valuep, enum pci_size_t size)
121	{
122	int ret;
123	struct udevice *bus = pcie->bus;
124
125	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
126	offset, valuep, size);
127
128	return ret;
129	}
130
131	static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
132	ulong value, enum pci_size_t size)
133	{
134	struct udevice *bus = pcie->bus;
135
136	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
137	offset, value, size);
138	}
139
140	static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
141	u8 *valuep)
142	{
143	ulong val;
144	int ret;
145
146	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
147	*valuep = val;
148
149	return ret;
150	}
151
152	static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
153	u16 *valuep)
154	{
155	ulong val;
156	int ret;
157
158	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
159	*valuep = val;
160
161	return ret;
162	}
163
164	static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
165	u32 *valuep)
166	{
167	ulong val;
168	int ret;
169
170	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
171	*valuep = val;
172
173	return ret;
174	}
175
176	static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
177	u8 value)
178	{
179	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
180	}
181
182	static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
183	u16 value)
184	{
185	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
186	}
187
188	static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
189	u32 value)
190	{
191	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
192	}
193
194	static int fsl_pcie_link_up(struct fsl_pcie *pcie)
195	{
196	ccsr_fsl_pci_t *regs = pcie->regs;
197	u16 ltssm;
198
199	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
200	ltssm = (in_be32(&regs->pex_csr0)
201	& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
202	return ltssm == LTSSM_L0_REV3;
203	}
204
205	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
206
207	return ltssm == LTSSM_L0;
208	}
209
210	static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
211	{
212	u8 header_type;
213
214	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
215
216	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
217	}
218
219	static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
220	{
221	struct pci_region io, mem, *pref;
222
223	pci_get_regions(pcie->bus, &io, &mem, &pref);
224
225	if (mem)
226	set_next_law(mem->phys_start,
227	law_size_bits(mem->size),
228	pcie->law_trgt_if);
229
230	if (io)
231	set_next_law(io->phys_start,
232	law_size_bits(io->size),
233	pcie->law_trgt_if);
234
235	return 0;
236	}
237
238	static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
239	{
240	ccsr_fsl_pci_t *regs = pcie->regs;
241
242	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
243	setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
244	return;
245	}
246
247	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
248	}
249
250	static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
251	int type, u64 phys, u64 bus_addr,
252	pci_size_t size)
253	{
254	ccsr_fsl_pci_t *regs = pcie->regs;
255	pot_t *po = &regs->pot[idx];
256	u32 war, sz;
257
258	if (idx < 0)
259	return -EINVAL;
260
261	out_be32(&po->powbar, phys >> 12);
262	out_be32(&po->potar, bus_addr >> 12);
263	#ifdef CONFIG_SYS_PCI_64BIT
264	out_be32(&po->potear, bus_addr >> 44);
265	#else
266	out_be32(&po->potear, 0);
267	#endif
268
269	sz = (__ilog2_u64((u64)size) - 1);
270	war = POWAR_EN \| sz;
271
272	if (type == PCI_REGION_IO)
273	war \|= POWAR_IO_READ \| POWAR_IO_WRITE;
274	else
275	war \|= POWAR_MEM_READ \| POWAR_MEM_WRITE;
276
277	out_be32(&po->powar, war);
278
279	return 0;
280	}
281
282	static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
283	bool pf, u64 phys, u64 bus_addr,
284	pci_size_t size)
285	{
286	ccsr_fsl_pci_t *regs = pcie->regs;
287	pit_t *pi = &regs->pit[idx];
288	u32 sz = (__ilog2_u64(size) - 1);
289	u32 flag = PIWAR_LOCAL;
290
291	if (idx < 0)
292	return -EINVAL;
293
294	out_be32(&pi->pitar, phys >> 12);
295	out_be32(&pi->piwbar, bus_addr >> 12);
296
297	#ifdef CONFIG_SYS_PCI_64BIT
298	out_be32(&pi->piwbear, bus_addr >> 44);
299	#else
300	out_be32(&pi->piwbear, 0);
301	#endif
302
adc983b4 HZ	303	#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	304	flag = 0;
	305	#endif
b89e3d92 HZ	306
	307	flag \|= PIWAR_EN \| PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP;
	308	if (pf)
	309	flag \|= PIWAR_PF;
	310	out_be32(&pi->piwar, flag \| sz);
	311
	312	return 0;
	313	}
	314
	315	static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
	316	{
	317	struct pci_region io, mem, *pref;
	318	int idx = 1; /* skip 0 */
	319
	320	pci_get_regions(pcie->bus, &io, &mem, &pref);
	321
	322	if (io)
	323	/* ATU : OUTBOUND : IO */
	324	fsl_pcie_setup_outbound_win(pcie, idx++,
	325	PCI_REGION_IO,
	326	io->phys_start,
	327	io->bus_start,
	328	io->size);
	329
	330	if (mem)
	331	/* ATU : OUTBOUND : MEM */
	332	fsl_pcie_setup_outbound_win(pcie, idx++,
	333	PCI_REGION_MEM,
	334	mem->phys_start,
	335	mem->bus_start,
	336	mem->size);
	337	return 0;
	338	}
	339
	340	static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
	341	{
	342	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	343	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	344	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	345	pci_size_t pci_sz;
	346	int idx;
	347
	348	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
	349	idx = 2;
	350	else
	351	idx = 3;
	352
	353	pci_sz = 1ull << __ilog2_u64(sz);
	354
	355	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
	356	(u64)bus_start, (u64)phys_start, (u64)sz);
	357
	358	/* if we aren't an exact power of two match, pci_sz is smaller
	359	* round it up to the next power of two. We report the actual
	360	* size to pci region tracking.
	361	*/
	362	if (pci_sz != sz)
	363	sz = 2ull << __ilog2_u64(sz);
	364
	365	fsl_pcie_setup_inbound_win(pcie, idx--, true,
	366	CONFIG_SYS_PCI_MEMORY_PHYS,
	367	CONFIG_SYS_PCI_MEMORY_BUS, sz);
	368	#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	369	/*
370	* On 64-bit capable systems, set up a mapping for all of DRAM
371	* in high pci address space.
372	*/
373	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
374	/* round up to the next largest power of two */
375	if (gd->ram_size > pci_sz)
376	pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
377
378	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
379	(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
380	(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
381
382	fsl_pcie_setup_inbound_win(pcie, idx--, true,
383	CONFIG_SYS_PCI_MEMORY_PHYS,
384	CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
385	#endif
386
387	return 0;
388	}
389
390	static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
391	{
392	fsl_pcie_setup_outbound_wins(pcie);
393	fsl_pcie_setup_inbound_wins(pcie);
394
395	return 0;
396	}
397
398	static int fsl_pcie_init_port(struct fsl_pcie *pcie)
399	{
400	ccsr_fsl_pci_t *regs = pcie->regs;
401	u32 val_32;
402	u16 val_16;
403
404	fsl_pcie_init_atmu(pcie);
405
adc983b4 HZ	406	#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	407	val_32 = 0;
	408	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	409	val_32 &= ~0x03;
	410	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	411	udelay(1);
	412	#endif
b89e3d92	413
adc983b4 HZ	414	#ifdef CONFIG_FSL_PCIE_RESET
	415	u16 ltssm;
	416	int i;
b89e3d92	417
adc983b4 HZ	418	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	419	/* assert PCIe reset */
	420	setbits_be32(&regs->pdb_stat, 0x08000000);
	421	(void)in_be32(&regs->pdb_stat);
	422	udelay(1000);
	423	/* clear PCIe reset */
	424	clrbits_be32(&regs->pdb_stat, 0x08000000);
	425	asm("sync;isync");
	426	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	427	udelay(1000);
	428	} else {
	429	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
	430	if (ltssm == 1) {
b89e3d92 HZ	431	/* assert PCIe reset */
	432	setbits_be32(&regs->pdb_stat, 0x08000000);
	433	(void)in_be32(&regs->pdb_stat);
adc983b4	434	udelay(100);
b89e3d92 HZ	435	/* clear PCIe reset */
	436	clrbits_be32(&regs->pdb_stat, 0x08000000);
	437	asm("sync;isync");
adc983b4 HZ	438	for (i = 0; i < 100 &&
adc983b4 HZ	439	!fsl_pcie_link_up(pcie); i++)
b89e3d92	440	udelay(1000);
b89e3d92 HZ	441	}
b89e3d92 HZ	442	}
adc983b4	443	#endif
b89e3d92	444
adc983b4 HZ	445	#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
adc983b4 HZ	446	if (!fsl_pcie_link_up(pcie)) {
b89e3d92 HZ	447	serdes_corenet_t *srds_regs;
	448
	449	srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
	450	val_32 = in_be32(&srds_regs->srdspccr0);
	451
	452	if ((val_32 >> 28) == 3) {
	453	int i;
	454
	455	out_be32(&srds_regs->srdspccr0, 2 << 28);
	456	setbits_be32(&regs->pdb_stat, 0x08000000);
	457	in_be32(&regs->pdb_stat);
	458	udelay(100);
	459	clrbits_be32(&regs->pdb_stat, 0x08000000);
	460	asm("sync;isync");
	461	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	462	udelay(1000);
	463	}
	464	}
adc983b4	465	#endif
b89e3d92 HZ	466
	467	/*
	468	* The Read-Only Write Enable bit defaults to 1 instead of 0.
	469	* Set to 0 to protect the read-only registers.
	470	*/
adc983b4 HZ	471	#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	472	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
	473	#endif
b89e3d92 HZ	474
	475	/*
	476	* Enable All Error Interrupts except
	477	* - Master abort (pci)
	478	* - Master PERR (pci)
	479	* - ICCA (PCIe)
	480	*/
	481	out_be32(&regs->peer, ~0x20140);
	482
	483	/* set URR, FER, NFER (but not CER) */
	484	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	485	val_32 \|= 0xf000e;
	486	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
	487
	488	/* Clear all error indications */
	489	out_be32(&regs->pme_msg_det, 0xffffffff);
	490	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	491	out_be32(&regs->pedr, 0xffffffff);
	492
	493	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	494	if (val_16)
	495	fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
	496
	497	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	498	if (val_16)
	499	fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
	500
	501	return 0;
	502	}
	503
	504	static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
	505	{
	506	ccsr_fsl_pci_t *regs = pcie->regs;
d18d06ac	507	u32 classcode_reg;
b89e3d92 HZ	508	u32 val;
b89e3d92 HZ	509
d18d06ac HZ	510	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	511	classcode_reg = PCI_CLASS_REVISION;
	512	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	513	} else {
	514	classcode_reg = CSR_CLASSCODE;
	515	}
	516
	517	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
b89e3d92 HZ	518	val &= 0xff;
b89e3d92 HZ	519	val \|= PCI_CLASS_BRIDGE_PCI << 16;
d18d06ac HZ	520	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
	521
	522	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
	523	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
b89e3d92 HZ	524
	525	return 0;
	526	}
	527
	528	static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
	529	{
	530	return fsl_pcie_fixup_classcode(pcie);
	531	}
	532
	533	static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
	534	{
	535	fsl_pcie_config_ready(pcie);
	536
	537	return 0;
	538	}
	539
	540	static int fsl_pcie_probe(struct udevice *dev)
	541	{
	542	struct fsl_pcie *pcie = dev_get_priv(dev);
	543	ccsr_fsl_pci_t *regs = pcie->regs;
	544	u16 val_16;
	545
	546	pcie->bus = dev;
	547	pcie->block_rev = in_be32(&regs->block_rev1);
	548
	549	list_add(&pcie->list, &fsl_pcie_list);
	550	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	551	if (!pcie->enabled) {
	552	printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
	553	return 0;
	554	}
	555
	556	fsl_pcie_setup_law(pcie);
	557
	558	pcie->mode = fsl_pcie_is_agent(pcie);
	559
	560	fsl_pcie_init_port(pcie);
	561
	562	printf("PCIe%d: %s ", pcie->idx, dev->name);
	563
	564	if (pcie->mode) {
	565	printf("Endpoint");
	566	fsl_pcie_init_ep(pcie);
	567	} else {
	568	printf("Root Complex");
	569	fsl_pcie_init_rc(pcie);
	570	}
	571
	572	if (!fsl_pcie_link_up(pcie)) {
	573	printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
	574	return 0;
	575	}
	576
	577	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	578	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
	579
	580	return 0;
	581	}
	582
	583	static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
	584	{
	585	struct fsl_pcie *pcie = dev_get_priv(dev);
fbcb2ff5	586	struct fsl_pcie_data *info;
b89e3d92 HZ	587	int ret;
	588
	589	pcie->regs = dev_remap_addr(dev);
	590	if (!pcie->regs) {
	591	pr_err("\"reg\" resource not found\n");
	592	return -EINVAL;
	593	}
	594
	595	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	596	if (ret < 0) {
	597	pr_err("\"law_trgt_if\" not found\n");
	598	return ret;
	599	}
	600
fbcb2ff5 HZ	601	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	602	pcie->info = info;
	603	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
	604	info->block_offset) / info->stride;
b89e3d92 HZ	605
	606	return 0;
	607	}
	608
	609	static const struct dm_pci_ops fsl_pcie_ops = {
	610	.read_config = fsl_pcie_read_config,
	611	.write_config = fsl_pcie_write_config,
	612	};
	613
ba827365 HZ	614	static struct fsl_pcie_data p1_p2_data = {
	615	.block_offset = 0xa000,
	616	.block_offset_mask = 0xffff,
	617	.stride = 0x1000,
	618	};
	619
1a92802e HZ	620	static struct fsl_pcie_data p2041_data = {
	621	.block_offset = 0x200000,
	622	.block_offset_mask = 0x3fffff,
	623	.stride = 0x1000,
	624	};
	625
fbcb2ff5 HZ	626	static struct fsl_pcie_data t2080_data = {
	627	.block_offset = 0x240000,
	628	.block_offset_mask = 0x3fffff,
	629	.stride = 0x10000,
	630	};
	631
b89e3d92	632	static const struct udevice_id fsl_pcie_ids[] = {
92e025c6	633	{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
ba827365	634	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
1a92802e	635	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
096d5f80	636	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
7b7e4e1b	637	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
52744596	638	{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
a8c79f61	639	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
4392ddbb	640	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
fbcb2ff5	641	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
9acc038b	642	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
b89e3d92 HZ	643	{ }
	644	};
	645
	646	U_BOOT_DRIVER(fsl_pcie) = {
	647	.name = "fsl_pcie",
	648	.id = UCLASS_PCI,
	649	.of_match = fsl_pcie_ids,
	650	.ops = &fsl_pcie_ops,
	651	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	652	.probe = fsl_pcie_probe,
	653	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
	654	};