[people/ms/u-boot.git] / drivers / pci / pcie_imx.c

/*
 * Freescale i.MX6 PCI Express Root-Complex driver
 *
 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
 *
 * Based on upstream Linux kernel driver:
 * pci-imx6.c:		Sean Cross <xobs@kosagi.com>
 * pcie-designware.c:	Jingoo Han <jg1.han@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <pci.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/crm_regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <errno.h>
#include <asm/arch/sys_proto.h>

#define PCI_ACCESS_READ  0
#define PCI_ACCESS_WRITE 1

#ifdef CONFIG_MX6SX
#define MX6_DBI_ADDR	0x08ffc000
#define MX6_IO_ADDR	0x08000000
#define MX6_MEM_ADDR	0x08100000
#define MX6_ROOT_ADDR	0x08f00000
#else
#define MX6_DBI_ADDR	0x01ffc000
#define MX6_IO_ADDR	0x01000000
#define MX6_MEM_ADDR	0x01100000
#define MX6_ROOT_ADDR	0x01f00000
#endif
#define MX6_DBI_SIZE	0x4000
#define MX6_IO_SIZE	0x100000
#define MX6_MEM_SIZE	0xe00000
#define MX6_ROOT_SIZE	0xfc000

/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP		(1 << 4)
#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(1 << 29)

#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
#define PCIE_PHY_CTRL_WR_LOC 18
#define PCIE_PHY_CTRL_RD_LOC 19

#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
#define PCIE_PHY_STAT_DATA_LOC 0
#define PCIE_PHY_STAT_ACK_LOC 16

/* PHY registers (not memory-mapped) */
#define PCIE_PHY_RX_ASIC_OUT 0x100D

#define PHY_RX_OVRD_IN_LO 0x1005
#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)

#define PCIE_PHY_PUP_REQ		(1 << 7)

/* iATU registers */
#define PCIE_ATU_VIEWPORT		0x900
#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
#define PCIE_ATU_CR1			0x904
#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
#define PCIE_ATU_TYPE_IO		(0x2 << 0)
#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
#define PCIE_ATU_CR2			0x908
#define PCIE_ATU_ENABLE			(0x1 << 31)
#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
#define PCIE_ATU_LOWER_BASE		0x90C
#define PCIE_ATU_UPPER_BASE		0x910
#define PCIE_ATU_LIMIT			0x914
#define PCIE_ATU_LOWER_TARGET		0x918
#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET		0x91C

/*
 * PHY access functions
 */
static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
{
	u32 val;
	u32 max_iterations = 10;
	u32 wait_counter = 0;

	do {
		val = readl(dbi_base + PCIE_PHY_STAT);
		val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
		wait_counter++;

		if (val == exp_val)
			return 0;

		udelay(1);
	} while (wait_counter < max_iterations);

	return -ETIMEDOUT;
}

static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
{
	u32 val;
	int ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	writel(val, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
{
	u32 val, phy_ctl;
	int ret;

	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	/* assert Read signal */
	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	val = readl(dbi_base + PCIE_PHY_STAT);
	*data = val & 0xffff;

	/* deassert Read signal */
	writel(0x00, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	return 0;
}

static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
{
	u32 var;
	int ret;

	/* write addr */
	/* cap addr */
	ret = pcie_phy_wait_ack(dbi_base, addr);
	if (ret)
		return ret;

	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* capture data */
	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
	writel(var, dbi_base + PCIE_PHY_CTRL);

	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert cap data */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	/* assert wr signal */
	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack */
	ret = pcie_phy_poll_ack(dbi_base, 1);
	if (ret)
		return ret;

	/* deassert wr signal */
	var = data << PCIE_PHY_CTRL_DATA_LOC;
	writel(var, dbi_base + PCIE_PHY_CTRL);

	/* wait for ack de-assertion */
	ret = pcie_phy_poll_ack(dbi_base, 0);
	if (ret)
		return ret;

	writel(0x0, dbi_base + PCIE_PHY_CTRL);

	return 0;
}

static int imx6_pcie_link_up(void)
{
	u32 rc, ltssm;
	int rx_valid, temp;

	/* link is debug bit 36, debug register 1 starts at bit 32 */
	rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
	if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
	    !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
		return -EAGAIN;

	/*
	 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
	 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
	 * If (MAC/LTSSM.state == Recovery.RcvrLock)
	 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
	 * to gen2 is stuck
	 */
	pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
	ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;

	if (rx_valid & 0x01)
		return 0;

	if (ltssm != 0x0d)
		return 0;

	printf("transition to gen2 is stuck, reset PHY!\n");

	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);

	udelay(3000);

	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);

	return 0;
}

/*
 * iATU region setup
 */
static int imx_pcie_regions_setup(void)
{
	/*
	 * i.MX6 defines 16MB in the AXI address map for PCIe.
	 *
	 * That address space excepted the pcie registers is
	 * split and defined into different regions by iATU,
	 * with sizes and offsets as follows:
	 *
	 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
	 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
	 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
	 */

	/* CMD reg:I/O space, MEM space, and Bus Master Enable */
	setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
		     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);

	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
	setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
		     PCI_CLASS_BRIDGE_PCI << 16);

	/* Region #0 is used for Outbound CFG space access. */
	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);

	writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
	writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);

	writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
	writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
	writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);

	return 0;
}

/*
 * PCI Express accessors
 */
static uint32_t get_bus_address(pci_dev_t d, int where)
{
	uint32_t va_address;

	/* Reconfigure Region #0 */
	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);

	if (PCI_BUS(d) < 2)
		writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
	else
		writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);

	if (PCI_BUS(d) == 0) {
		va_address = MX6_DBI_ADDR;
	} else {
		writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
		va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
	}

	va_address += (where & ~0x3);

	return va_address;
}

static int imx_pcie_addr_valid(pci_dev_t d)
{
	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
		return -EINVAL;
	if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
		return -EINVAL;
	return 0;
}

/*
 * Replace the original ARM DABT handler with a simple jump-back one.
 *
 * The problem here is that if we have a PCIe bridge attached to this PCIe
 * controller, but no PCIe device is connected to the bridges' downstream
 * port, the attempt to read/write from/to the config space will produce
 * a DABT. This is a behavior of the controller and can not be disabled
 * unfortuatelly.
 *
 * To work around the problem, we backup the current DABT handler address
 * and replace it with our own DABT handler, which only bounces right back
 * into the code.
 */
static void imx_pcie_fix_dabt_handler(bool set)
{
	extern uint32_t *_data_abort;
	uint32_t *data_abort_addr = (uint32_t *)&_data_abort;

	static const uint32_t data_abort_bounce_handler = 0xe25ef004;
	uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;

	static uint32_t data_abort_backup;

	if (set) {
		data_abort_backup = *data_abort_addr;
		*data_abort_addr = data_abort_bounce_addr;
	} else {
		*data_abort_addr = data_abort_backup;
	}
}

static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
				int where, u32 *val)
{
	uint32_t va_address;
	int ret;

	ret = imx_pcie_addr_valid(d);
	if (ret) {
		*val = 0xffffffff;
		return 0;
	}

	va_address = get_bus_address(d, where);

	/*
	 * Read the PCIe config space. We must replace the DABT handler
	 * here in case we got data abort from the PCIe controller, see
	 * imx_pcie_fix_dabt_handler() description. Note that writing the
	 * "val" with valid value is also imperative here as in case we
	 * did got DABT, the val would contain random value.
	 */
	imx_pcie_fix_dabt_handler(true);
	writel(0xffffffff, val);
	*val = readl(va_address);
	imx_pcie_fix_dabt_handler(false);

	return 0;
}

static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
			int where, u32 val)
{
	uint32_t va_address = 0;
	int ret;

	ret = imx_pcie_addr_valid(d);
	if (ret)
		return ret;

	va_address = get_bus_address(d, where);

	/*
	 * Write the PCIe config space. We must replace the DABT handler
	 * here in case we got data abort from the PCIe controller, see
	 * imx_pcie_fix_dabt_handler() description.
	 */
	imx_pcie_fix_dabt_handler(true);
	writel(val, va_address);
	imx_pcie_fix_dabt_handler(false);

	return 0;
}

/*
 * Initial bus setup
 */
static int imx6_pcie_assert_core_reset(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	if (is_mx6dqp())
		setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);

#if defined(CONFIG_MX6SX)
	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;

	/* SSP_EN is not used on MX6SX anymore */
	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	/* Force PCIe PHY reset */
	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
	/* Power up PCIe PHY */
	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
#else
	/*
	 * If the bootloader already enabled the link we need some special
	 * handling to get the core back into a state where it is safe to
	 * touch it for configuration.  As there is no dedicated reset signal
	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
	 * state before completely disabling LTSSM, which is a prerequisite
	 * for core configuration.
	 *
	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	 * indication that the bootloader activated the link.
	 */
	if (is_mx6dq()) {
		u32 val, gpr1, gpr12;

		gpr1 = readl(&iomuxc_regs->gpr[1]);
		gpr12 = readl(&iomuxc_regs->gpr[12]);
		if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
		    (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
			val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
			val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
			val |= PCIE_PL_PFLR_FORCE_LINK;

			imx_pcie_fix_dabt_handler(true);
			writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
			imx_pcie_fix_dabt_handler(false);

			gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
			writel(val, &iomuxc_regs->gpr[12]);
		}
	}
	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
#endif

	return 0;
}

static int imx6_pcie_init_phy(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);

	clrsetbits_le32(&iomuxc_regs->gpr[12],
			IOMUXC_GPR12_DEVICE_TYPE_MASK,
			IOMUXC_GPR12_DEVICE_TYPE_RC);
	clrsetbits_le32(&iomuxc_regs->gpr[12],
			IOMUXC_GPR12_LOS_LEVEL_MASK,
			IOMUXC_GPR12_LOS_LEVEL_9);

#ifdef CONFIG_MX6SX
	clrsetbits_le32(&iomuxc_regs->gpr[12],
			IOMUXC_GPR12_RX_EQ_MASK,
			IOMUXC_GPR12_RX_EQ_2);
#endif

	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
	       (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
	       (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
	       &iomuxc_regs->gpr[8]);

	return 0;
}

__weak int imx6_pcie_toggle_power(void)
{
#ifdef CONFIG_PCIE_IMX_POWER_GPIO
	gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
	mdelay(20);
	gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
	mdelay(20);
#endif
	return 0;
}

__weak int imx6_pcie_toggle_reset(void)
{
	/*
	 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
	 * for detailed understanding of the PCIe CR reset logic.
	 *
	 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
	 * design does not conform to the specification. You must wait at
	 * least 20 ms after de-asserting the #PERST so the EP device can
	 * do self-initialisation.
	 *
	 * In case your #PERST pin is connected to a plain GPIO pin of the
	 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
	 * configuration file and the condition below will handle the rest
	 * of the reset toggling.
	 *
	 * In case your #PERST toggling logic is more complex, for example
	 * connected via CPLD or somesuch, you can override this function
	 * in your board file and implement reset logic as needed. You must
	 * not forget to wait at least 20 ms after de-asserting #PERST in
	 * this case either though.
	 *
	 * In case your #PERST line of the PCIe EP device is not connected
	 * at all, your design is broken and you should fix your design,
	 * otherwise you will observe problems like for example the link
	 * not coming up after rebooting the system back from running Linux
	 * that uses the PCIe as well OR the PCIe link might not come up in
	 * Linux at all in the first place since it's in some non-reset
	 * state due to being previously used in U-Boot.
	 */
#ifdef CONFIG_PCIE_IMX_PERST_GPIO
	gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
	mdelay(20);
	gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
	mdelay(20);
#else
	puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
#endif
	return 0;
}

static int imx6_pcie_deassert_core_reset(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	imx6_pcie_toggle_power();

	enable_pcie_clock();

	if (is_mx6dqp())
		clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);

	/*
	 * Wait for the clock to settle a bit, when the clock are sourced
	 * from the CPU, we need about 30 ms to settle.
	 */
	mdelay(50);

#if defined(CONFIG_MX6SX)
	/* SSP_EN is not used on MX6SX anymore */
	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	/* Clear PCIe PHY reset bit */
	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
#else
	/* Enable PCIe */
	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
#endif

	imx6_pcie_toggle_reset();

	return 0;
}

static int imx_pcie_link_up(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	uint32_t tmp;
	int count = 0;

	imx6_pcie_assert_core_reset();
	imx6_pcie_init_phy();
	imx6_pcie_deassert_core_reset();

	imx_pcie_regions_setup();

	/*
	 * FIXME: Force the PCIe RC to Gen1 operation
	 * The RC must be forced into Gen1 mode before bringing the link
	 * up, otherwise no downstream devices are detected. After the
	 * link is up, a managed Gen1->Gen2 transition can be initiated.
	 */
	tmp = readl(MX6_DBI_ADDR + 0x7c);
	tmp &= ~0xf;
	tmp |= 0x1;
	writel(tmp, MX6_DBI_ADDR + 0x7c);

	/* LTSSM enable, starting link. */
	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);

	while (!imx6_pcie_link_up()) {
		udelay(10);
		count++;
		if (count >= 4000) {
#ifdef CONFIG_PCI_SCAN_SHOW
			puts("PCI:   pcie phy link never came up\n");
#endif
			debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
			      readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
			return -EINVAL;
		}
	}

	return 0;
}

void imx_pcie_init(void)
{
	/* Static instance of the controller. */
	static struct pci_controller	pcc;
	struct pci_controller		*hose = &pcc;
	int ret;

	memset(&pcc, 0, sizeof(pcc));

	/* PCI I/O space */
	pci_set_region(&hose->regions[0],
		       MX6_IO_ADDR, MX6_IO_ADDR,
		       MX6_IO_SIZE, PCI_REGION_IO);

	/* PCI memory space */
	pci_set_region(&hose->regions[1],
		       MX6_MEM_ADDR, MX6_MEM_ADDR,
		       MX6_MEM_SIZE, PCI_REGION_MEM);

	/* System memory space */
	pci_set_region(&hose->regions[2],
		       MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
		       0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	hose->region_count = 3;

	pci_set_ops(hose,
		    pci_hose_read_config_byte_via_dword,
		    pci_hose_read_config_word_via_dword,
		    imx_pcie_read_config,
		    pci_hose_write_config_byte_via_dword,
		    pci_hose_write_config_word_via_dword,
		    imx_pcie_write_config);

	/* Start the controller. */
	ret = imx_pcie_link_up();

	if (!ret) {
		pci_register_hose(hose);
		hose->last_busno = pci_hose_scan(hose);
	}
}

void imx_pcie_remove(void)
{
	imx6_pcie_assert_core_reset();
}

/* Probe function. */
void pci_init_board(void)
{
	imx_pcie_init();
}
Commit	Line	Data
e9be4292 MV	1	/*
	2	* Freescale i.MX6 PCI Express Root-Complex driver
	3	*
	4	* Copyright (C) 2013 Marek Vasut <marex@denx.de>
	5	*
	6	* Based on upstream Linux kernel driver:
	7	* pci-imx6.c: Sean Cross <xobs@kosagi.com>
	8	* pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
	9	*
	10	* SPDX-License-Identifier: GPL-2.0
	11	*/
	12
	13	#include <common.h>
	14	#include <pci.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/iomux.h>
	17	#include <asm/arch/crm_regs.h>
bb019563	18	#include <asm/gpio.h>
e9be4292	19	#include <asm/io.h>
1ace4022	20	#include <linux/sizes.h>
e9be4292	21	#include <errno.h>
aaf87f03	22	#include <asm/arch/sys_proto.h>
e9be4292 MV	23
	24	#define PCI_ACCESS_READ 0
	25	#define PCI_ACCESS_WRITE 1
	26
1b8ad74a FE	27	#ifdef CONFIG_MX6SX
	28	#define MX6_DBI_ADDR 0x08ffc000
	29	#define MX6_IO_ADDR 0x08000000
	30	#define MX6_MEM_ADDR 0x08100000
	31	#define MX6_ROOT_ADDR 0x08f00000
	32	#else
e9be4292	33	#define MX6_DBI_ADDR 0x01ffc000
e9be4292	34	#define MX6_IO_ADDR 0x01000000
e9be4292	35	#define MX6_MEM_ADDR 0x01100000
e9be4292	36	#define MX6_ROOT_ADDR 0x01f00000
1b8ad74a FE	37	#endif
	38	#define MX6_DBI_SIZE 0x4000
	39	#define MX6_IO_SIZE 0x100000
	40	#define MX6_MEM_SIZE 0xe00000
e9be4292 MV	41	#define MX6_ROOT_SIZE 0xfc000
	42
	43	/* PCIe Port Logic registers (memory-mapped) */
	44	#define PL_OFFSET 0x700
6ecbe137 TH	45	#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
	46	#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
	47	#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
e9be4292 MV	48	#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
	49	#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
	50	#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
	51	#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
	52
	53	#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
	54	#define PCIE_PHY_CTRL_DATA_LOC 0
	55	#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
	56	#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
	57	#define PCIE_PHY_CTRL_WR_LOC 18
	58	#define PCIE_PHY_CTRL_RD_LOC 19
	59
	60	#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
	61	#define PCIE_PHY_STAT_DATA_LOC 0
	62	#define PCIE_PHY_STAT_ACK_LOC 16
	63
	64	/* PHY registers (not memory-mapped) */
	65	#define PCIE_PHY_RX_ASIC_OUT 0x100D
	66
	67	#define PHY_RX_OVRD_IN_LO 0x1005
	68	#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
	69	#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
	70
1b8ad74a FE	71	#define PCIE_PHY_PUP_REQ (1 << 7)
1b8ad74a FE	72
e9be4292 MV	73	/* iATU registers */
	74	#define PCIE_ATU_VIEWPORT 0x900
	75	#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
	76	#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
	77	#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
	78	#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
	79	#define PCIE_ATU_CR1 0x904
	80	#define PCIE_ATU_TYPE_MEM (0x0 << 0)
	81	#define PCIE_ATU_TYPE_IO (0x2 << 0)
	82	#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
	83	#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
	84	#define PCIE_ATU_CR2 0x908
	85	#define PCIE_ATU_ENABLE (0x1 << 31)
	86	#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
	87	#define PCIE_ATU_LOWER_BASE 0x90C
	88	#define PCIE_ATU_UPPER_BASE 0x910
	89	#define PCIE_ATU_LIMIT 0x914
	90	#define PCIE_ATU_LOWER_TARGET 0x918
	91	#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
	92	#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
	93	#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
	94	#define PCIE_ATU_UPPER_TARGET 0x91C
	95
	96	/*
	97	* PHY access functions
	98	*/
	99	static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
	100	{
	101	u32 val;
	102	u32 max_iterations = 10;
	103	u32 wait_counter = 0;
	104
	105	do {
	106	val = readl(dbi_base + PCIE_PHY_STAT);
	107	val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
	108	wait_counter++;
	109
	110	if (val == exp_val)
	111	return 0;
	112
	113	udelay(1);
	114	} while (wait_counter < max_iterations);
	115
	116	return -ETIMEDOUT;
	117	}
	118
	119	static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
	120	{
	121	u32 val;
	122	int ret;
	123
	124	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	125	writel(val, dbi_base + PCIE_PHY_CTRL);
	126
	127	val \|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
	128	writel(val, dbi_base + PCIE_PHY_CTRL);
	129
	130	ret = pcie_phy_poll_ack(dbi_base, 1);
	131	if (ret)
	132	return ret;
	133
	134	val = addr << PCIE_PHY_CTRL_DATA_LOC;
	135	writel(val, dbi_base + PCIE_PHY_CTRL);
	136
137	ret = pcie_phy_poll_ack(dbi_base, 0);
138	if (ret)
139	return ret;
140
141	return 0;
142	}
143
144	/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
145	static int pcie_phy_read(void __iomem dbi_base, int addr , int data)
146	{
147	u32 val, phy_ctl;
148	int ret;
149
150	ret = pcie_phy_wait_ack(dbi_base, addr);
151	if (ret)
152	return ret;
153
154	/* assert Read signal */
155	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
156	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
157
158	ret = pcie_phy_poll_ack(dbi_base, 1);
159	if (ret)
160	return ret;
161
162	val = readl(dbi_base + PCIE_PHY_STAT);
163	*data = val & 0xffff;
164
165	/* deassert Read signal */
166	writel(0x00, dbi_base + PCIE_PHY_CTRL);
167
168	ret = pcie_phy_poll_ack(dbi_base, 0);
169	if (ret)
170	return ret;
171
172	return 0;
173	}
174
175	static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
176	{
177	u32 var;
178	int ret;
179
180	/* write addr */
181	/* cap addr */
182	ret = pcie_phy_wait_ack(dbi_base, addr);
183	if (ret)
184	return ret;
185
186	var = data << PCIE_PHY_CTRL_DATA_LOC;
187	writel(var, dbi_base + PCIE_PHY_CTRL);
188
189	/* capture data */
190	var \|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
191	writel(var, dbi_base + PCIE_PHY_CTRL);
192
193	ret = pcie_phy_poll_ack(dbi_base, 1);
194	if (ret)
195	return ret;
196
197	/* deassert cap data */
198	var = data << PCIE_PHY_CTRL_DATA_LOC;
199	writel(var, dbi_base + PCIE_PHY_CTRL);
200
201	/* wait for ack de-assertion */
202	ret = pcie_phy_poll_ack(dbi_base, 0);
203	if (ret)
204	return ret;
205
206	/* assert wr signal */
207	var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
208	writel(var, dbi_base + PCIE_PHY_CTRL);
209
210	/* wait for ack */
211	ret = pcie_phy_poll_ack(dbi_base, 1);
212	if (ret)
213	return ret;
214
215	/* deassert wr signal */
216	var = data << PCIE_PHY_CTRL_DATA_LOC;
217	writel(var, dbi_base + PCIE_PHY_CTRL);
218
219	/* wait for ack de-assertion */
220	ret = pcie_phy_poll_ack(dbi_base, 0);
221	if (ret)
222	return ret;
223
224	writel(0x0, dbi_base + PCIE_PHY_CTRL);
225
226	return 0;
227	}
228
229	static int imx6_pcie_link_up(void)
230	{
231	u32 rc, ltssm;
232	int rx_valid, temp;
233
234	/* link is debug bit 36, debug register 1 starts at bit 32 */
235	rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
236	if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
237	!(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
238	return -EAGAIN;
239
240	/*
241	* From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
242	* Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
243	* If (MAC/LTSSM.state == Recovery.RcvrLock)
244	* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
245	* to gen2 is stuck
246	*/
247	pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
248	ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
249
250	if (rx_valid & 0x01)
251	return 0;
252
253	if (ltssm != 0x0d)
254	return 0;
255
256	printf("transition to gen2 is stuck, reset PHY!\n");
257
258	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
259	temp \|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN \| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
260	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
261
262	udelay(3000);
263
264	pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
265	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN \| PHY_RX_OVRD_IN_LO_RX_PLL_EN);
266	pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
267
268	return 0;
269	}
270
271	/*
272	* iATU region setup
273	*/
274	static int imx_pcie_regions_setup(void)
275	{
276	/*
277	* i.MX6 defines 16MB in the AXI address map for PCIe.
278	*
279	* That address space excepted the pcie registers is
280	* split and defined into different regions by iATU,
281	* with sizes and offsets as follows:
282	*
283	* 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
284	* 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
285	* 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
286	*/
287
288	/* CMD reg:I/O space, MEM space, and Bus Master Enable */
289	setbits_le32(MX6_DBI_ADDR \| PCI_COMMAND,
290	PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
291
292	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
293	setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
294	PCI_CLASS_BRIDGE_PCI << 16);
295
296	/* Region #0 is used for Outbound CFG space access. */
297	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
298
299	writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
300	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
301	writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
302
303	writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
304	writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
305	writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
306	writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
307
308	return 0;
309	}
310
311	/*
312	* PCI Express accessors
313	*/
314	static uint32_t get_bus_address(pci_dev_t d, int where)
315	{
316	uint32_t va_address;
317
318	/* Reconfigure Region #0 */
319	writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
320
321	if (PCI_BUS(d) < 2)
322	writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
323	else
324	writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
325
326	if (PCI_BUS(d) == 0) {
327	va_address = MX6_DBI_ADDR;
328	} else {
329	writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
330	va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
331	}
332
333	va_address += (where & ~0x3);
334
335	return va_address;
336	}
337
338	static int imx_pcie_addr_valid(pci_dev_t d)
339	{
340	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
341	return -EINVAL;
342	if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
343	return -EINVAL;
344	return 0;
345	}
346
347	/*
348	* Replace the original ARM DABT handler with a simple jump-back one.
349	*
350	* The problem here is that if we have a PCIe bridge attached to this PCIe
351	* controller, but no PCIe device is connected to the bridges' downstream
352	* port, the attempt to read/write from/to the config space will produce
353	* a DABT. This is a behavior of the controller and can not be disabled
354	* unfortuatelly.
355	*
356	* To work around the problem, we backup the current DABT handler address
357	* and replace it with our own DABT handler, which only bounces right back
358	* into the code.
359	*/
360	static void imx_pcie_fix_dabt_handler(bool set)
361	{
362	extern uint32_t *_data_abort;
363	uint32_t data_abort_addr = (uint32_t )&_data_abort;
364
365	static const uint32_t data_abort_bounce_handler = 0xe25ef004;
366	uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
367
368	static uint32_t data_abort_backup;
369
370	if (set) {
371	data_abort_backup = *data_abort_addr;
372	*data_abort_addr = data_abort_bounce_addr;
373	} else {
374	*data_abort_addr = data_abort_backup;
375	}
376	}
377
378	static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
379	int where, u32 *val)
380	{
381	uint32_t va_address;
382	int ret;
383
384	ret = imx_pcie_addr_valid(d);
385	if (ret) {
386	*val = 0xffffffff;
9642b78c	387	return 0;
e9be4292 MV	388	}
	389
	390	va_address = get_bus_address(d, where);
	391
	392	/*
	393	* Read the PCIe config space. We must replace the DABT handler
	394	* here in case we got data abort from the PCIe controller, see
	395	* imx_pcie_fix_dabt_handler() description. Note that writing the
	396	* "val" with valid value is also imperative here as in case we
	397	* did got DABT, the val would contain random value.
	398	*/
	399	imx_pcie_fix_dabt_handler(true);
	400	writel(0xffffffff, val);
	401	*val = readl(va_address);
	402	imx_pcie_fix_dabt_handler(false);
	403
	404	return 0;
	405	}
	406
	407	static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
	408	int where, u32 val)
	409	{
	410	uint32_t va_address = 0;
	411	int ret;
	412
	413	ret = imx_pcie_addr_valid(d);
	414	if (ret)
	415	return ret;
	416
	417	va_address = get_bus_address(d, where);
	418
	419	/*
	420	* Write the PCIe config space. We must replace the DABT handler
	421	* here in case we got data abort from the PCIe controller, see
	422	* imx_pcie_fix_dabt_handler() description.
	423	*/
	424	imx_pcie_fix_dabt_handler(true);
	425	writel(val, va_address);
	426	imx_pcie_fix_dabt_handler(false);
	427
	428	return 0;
	429	}
	430
	431	/*
	432	* Initial bus setup
	433	*/
	434	static int imx6_pcie_assert_core_reset(void)
	435	{
	436	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
aaf87f03 FE	437
	438	if (is_mx6dqp())
	439	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
	440
1b8ad74a FE	441	#if defined(CONFIG_MX6SX)
	442	struct gpc gpc_regs = (struct gpc )GPC_BASE_ADDR;
	443
	444	/* SSP_EN is not used on MX6SX anymore */
	445	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	446	/* Force PCIe PHY reset */
	447	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
	448	/* Power up PCIe PHY */
	449	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
	450	#else
6ecbe137 TH	451	/*
	452	* If the bootloader already enabled the link we need some special
	453	* handling to get the core back into a state where it is safe to
	454	* touch it for configuration. As there is no dedicated reset signal
	455	* wired up for MX6QDL, we need to manually force LTSSM into "detect"
	456	* state before completely disabling LTSSM, which is a prerequisite
	457	* for core configuration.
	458	*
	459	* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
	460	* indication that the bootloader activated the link.
	461	*/
	462	if (is_mx6dq()) {
	463	u32 val, gpr1, gpr12;
	464
	465	gpr1 = readl(&iomuxc_regs->gpr[1]);
	466	gpr12 = readl(&iomuxc_regs->gpr[12]);
	467	if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
	468	(gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
	469	val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
	470	val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
	471	val \|= PCIE_PL_PFLR_FORCE_LINK;
	472
	473	imx_pcie_fix_dabt_handler(true);
	474	writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
	475	imx_pcie_fix_dabt_handler(false);
	476
	477	gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
	478	writel(val, &iomuxc_regs->gpr[12]);
	479	}
	480	}
e9be4292 MV	481	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
e9be4292 MV	482	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
1b8ad74a	483	#endif
e9be4292 MV	484
	485	return 0;
	486	}
	487
	488	static int imx6_pcie_init_phy(void)
	489	{
	490	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	491
	492	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
	493
	494	clrsetbits_le32(&iomuxc_regs->gpr[12],
	495	IOMUXC_GPR12_DEVICE_TYPE_MASK,
	496	IOMUXC_GPR12_DEVICE_TYPE_RC);
	497	clrsetbits_le32(&iomuxc_regs->gpr[12],
	498	IOMUXC_GPR12_LOS_LEVEL_MASK,
	499	IOMUXC_GPR12_LOS_LEVEL_9);
	500
1b8ad74a FE	501	#ifdef CONFIG_MX6SX
	502	clrsetbits_le32(&iomuxc_regs->gpr[12],
	503	IOMUXC_GPR12_RX_EQ_MASK,
	504	IOMUXC_GPR12_RX_EQ_2);
	505	#endif
	506
e9be4292 MV	507	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) \|
	508	(0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) \|
	509	(20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) \|
	510	(127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) \|
	511	(127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
	512	&iomuxc_regs->gpr[8]);
	513
	514	return 0;
	515	}
	516
a778aeae MV	517	__weak int imx6_pcie_toggle_power(void)
	518	{
	519	#ifdef CONFIG_PCIE_IMX_POWER_GPIO
	520	gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
	521	mdelay(20);
	522	gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
	523	mdelay(20);
	524	#endif
	525	return 0;
	526	}
	527
bb019563 MV	528	__weak int imx6_pcie_toggle_reset(void)
	529	{
	530	/*
	531	* See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
	532	* for detailed understanding of the PCIe CR reset logic.
	533	*
	534	* The PCIe #PERST reset line _MUST_ be connected, otherwise your
	535	* design does not conform to the specification. You must wait at
8f6edf6d	536	* least 20 ms after de-asserting the #PERST so the EP device can
bb019563 MV	537	* do self-initialisation.
	538	*
	539	* In case your #PERST pin is connected to a plain GPIO pin of the
	540	* CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
	541	* configuration file and the condition below will handle the rest
	542	* of the reset toggling.
	543	*
	544	* In case your #PERST toggling logic is more complex, for example
	545	* connected via CPLD or somesuch, you can override this function
	546	* in your board file and implement reset logic as needed. You must
8f6edf6d	547	* not forget to wait at least 20 ms after de-asserting #PERST in
bb019563 MV	548	* this case either though.
	549	*
	550	* In case your #PERST line of the PCIe EP device is not connected
	551	* at all, your design is broken and you should fix your design,
	552	* otherwise you will observe problems like for example the link
	553	* not coming up after rebooting the system back from running Linux
	554	* that uses the PCIe as well OR the PCIe link might not come up in
	555	* Linux at all in the first place since it's in some non-reset
	556	* state due to being previously used in U-Boot.
	557	*/
	558	#ifdef CONFIG_PCIE_IMX_PERST_GPIO
	559	gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
	560	mdelay(20);
	561	gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
	562	mdelay(20);
	563	#else
	564	puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
	565	#endif
	566	return 0;
	567	}
	568
e9be4292 MV	569	static int imx6_pcie_deassert_core_reset(void)
	570	{
	571	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	572
a778aeae	573	imx6_pcie_toggle_power();
e9be4292	574
e9be4292 MV	575	enable_pcie_clock();
e9be4292 MV	576
aaf87f03 FE	577	if (is_mx6dqp())
	578	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
	579
e9be4292 MV	580	/*
e9be4292 MV	581	* Wait for the clock to settle a bit, when the clock are sourced
8f6edf6d	582	* from the CPU, we need about 30 ms to settle.
e9be4292	583	*/
bb019563	584	mdelay(50);
e9be4292	585
1b8ad74a FE	586	#if defined(CONFIG_MX6SX)
	587	/* SSP_EN is not used on MX6SX anymore */
	588	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
	589	/* Clear PCIe PHY reset bit */
	590	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
	591	#else
5a82e1a2 TH	592	/* Enable PCIe */
	593	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
	594	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
1b8ad74a	595	#endif
5a82e1a2	596
bb019563	597	imx6_pcie_toggle_reset();
e9be4292 MV	598
	599	return 0;
	600	}
	601
	602	static int imx_pcie_link_up(void)
	603	{
	604	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	605	uint32_t tmp;
	606	int count = 0;
	607
	608	imx6_pcie_assert_core_reset();
	609	imx6_pcie_init_phy();
	610	imx6_pcie_deassert_core_reset();
	611
	612	imx_pcie_regions_setup();
	613
	614	/*
	615	* FIXME: Force the PCIe RC to Gen1 operation
	616	* The RC must be forced into Gen1 mode before bringing the link
	617	* up, otherwise no downstream devices are detected. After the
	618	* link is up, a managed Gen1->Gen2 transition can be initiated.
	619	*/
	620	tmp = readl(MX6_DBI_ADDR + 0x7c);
	621	tmp &= ~0xf;
	622	tmp \|= 0x1;
	623	writel(tmp, MX6_DBI_ADDR + 0x7c);
	624
	625	/* LTSSM enable, starting link. */
	626	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
	627
	628	while (!imx6_pcie_link_up()) {
	629	udelay(10);
	630	count++;
a32b4a03	631	if (count >= 4000) {
378b02d7 TH	632	#ifdef CONFIG_PCI_SCAN_SHOW
	633	puts("PCI: pcie phy link never came up\n");
	634	#endif
e9be4292 MV	635	debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
	636	readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
	637	readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
	638	return -EINVAL;
	639	}
	640	}
	641
	642	return 0;
	643	}
	644
	645	void imx_pcie_init(void)
	646	{
	647	/* Static instance of the controller. */
	648	static struct pci_controller pcc;
	649	struct pci_controller *hose = &pcc;
	650	int ret;
	651
	652	memset(&pcc, 0, sizeof(pcc));
	653
	654	/* PCI I/O space */
	655	pci_set_region(&hose->regions[0],
	656	MX6_IO_ADDR, MX6_IO_ADDR,
	657	MX6_IO_SIZE, PCI_REGION_IO);
	658
	659	/* PCI memory space */
	660	pci_set_region(&hose->regions[1],
	661	MX6_MEM_ADDR, MX6_MEM_ADDR,
	662	MX6_MEM_SIZE, PCI_REGION_MEM);
	663
	664	/* System memory space */
	665	pci_set_region(&hose->regions[2],
	666	MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
	667	0xefffffff, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
	668
	669	hose->region_count = 3;
	670
	671	pci_set_ops(hose,
	672	pci_hose_read_config_byte_via_dword,
	673	pci_hose_read_config_word_via_dword,
	674	imx_pcie_read_config,
	675	pci_hose_write_config_byte_via_dword,
	676	pci_hose_write_config_word_via_dword,
	677	imx_pcie_write_config);
	678
	679	/* Start the controller. */
	680	ret = imx_pcie_link_up();
	681
	682	if (!ret) {
	683	pci_register_hose(hose);
	684	hose->last_busno = pci_hose_scan(hose);
	685	}
	686	}
	687
6ecbe137 TH	688	void imx_pcie_remove(void)
	689	{
	690	imx6_pcie_assert_core_reset();
	691	}
	692
e9be4292 MV	693	/* Probe function. */
	694	void pci_init_board(void)
	695	{
	696	imx_pcie_init();
	697	}