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9226e7d6 | 1 | /* |
2 | * (C) Copyright 2004 Tundra Semiconductor Corp. | |
3 | * Alex Bounine <alexandreb@tundra.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * PCI initialisation for the Tsi108 EMU board. | |
26 | */ | |
27 | ||
28 | #include <config.h> | |
29 | ||
30 | #ifdef CONFIG_TSI108_PCI | |
31 | ||
32 | #include <common.h> | |
33 | #include <pci.h> | |
34 | #include <asm/io.h> | |
35 | #include <tsi108.h> | |
589c0427 GVB |
36 | #if defined(CONFIG_OF_LIBFDT) |
37 | #include <libfdt.h> | |
38 | #include <fdt_support.h> | |
409ecdc0 | 39 | #endif |
9226e7d6 | 40 | |
41 | struct pci_controller local_hose; | |
42 | ||
ee311214 | 43 | void tsi108_clear_pci_error (void) |
9226e7d6 | 44 | { |
45 | u32 err_stat, err_addr, pci_stat; | |
46 | ||
47 | /* | |
48 | * Quietly clear errors signalled as result of PCI/X configuration read | |
49 | * requests. | |
50 | */ | |
51 | /* Read PB Error Log Registers */ | |
52 | err_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + | |
53 | TSI108_PB_REG_OFFSET + PB_ERRCS); | |
54 | err_addr = *(volatile u32 *)(CFG_TSI108_CSR_BASE + | |
55 | TSI108_PB_REG_OFFSET + PB_AERR); | |
56 | if (err_stat & PB_ERRCS_ES) { | |
57 | /* Clear PCI/X bus errors if applicable */ | |
58 | if ((err_addr & 0xFF000000) == CFG_PCI_CFG_BASE) { | |
59 | /* Clear error flag */ | |
60 | *(u32 *) (CFG_TSI108_CSR_BASE + | |
61 | TSI108_PB_REG_OFFSET + PB_ERRCS) = | |
62 | PB_ERRCS_ES; | |
63 | ||
64 | /* Clear read error reported in PB_ISR */ | |
65 | *(u32 *) (CFG_TSI108_CSR_BASE + | |
66 | TSI108_PB_REG_OFFSET + PB_ISR) = | |
67 | PB_ISR_PBS_RD_ERR; | |
68 | ||
69 | /* Clear errors reported by PCI CSR (Normally Master Abort) */ | |
70 | pci_stat = *(volatile u32 *)(CFG_TSI108_CSR_BASE + | |
71 | TSI108_PCI_REG_OFFSET + | |
72 | PCI_CSR); | |
73 | *(volatile u32 *)(CFG_TSI108_CSR_BASE + | |
74 | TSI108_PCI_REG_OFFSET + PCI_CSR) = | |
75 | pci_stat; | |
76 | ||
77 | *(volatile u32 *)(CFG_TSI108_CSR_BASE + | |
78 | TSI108_PCI_REG_OFFSET + | |
79 | PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR; | |
80 | } | |
81 | } | |
82 | ||
83 | return; | |
84 | } | |
85 | ||
ee311214 | 86 | unsigned int __get_pci_config_dword (u32 addr) |
9226e7d6 | 87 | { |
88 | unsigned int retval; | |
89 | ||
ee311214 | 90 | __asm__ __volatile__ (" lwbrx %0,0,%1\n" |
9226e7d6 | 91 | "1: eieio\n" |
92 | "2:\n" | |
93 | ".section .fixup,\"ax\"\n" | |
94 | "3: li %0,-1\n" | |
95 | " b 2b\n" | |
96 | ".section __ex_table,\"a\"\n" | |
97 | " .align 2\n" | |
98 | " .long 1b,3b\n" | |
99 | ".text":"=r"(retval):"r"(addr)); | |
100 | ||
101 | return (retval); | |
102 | } | |
103 | ||
ee311214 | 104 | static int tsi108_read_config_dword (struct pci_controller *hose, |
9226e7d6 | 105 | pci_dev_t dev, int offset, u32 * value) |
106 | { | |
107 | dev &= (CFG_PCI_CFG_SIZE - 1); | |
108 | dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); | |
109 | *value = __get_pci_config_dword(dev); | |
110 | if (0xFFFFFFFF == *value) | |
ee311214 | 111 | tsi108_clear_pci_error (); |
9226e7d6 | 112 | return 0; |
113 | } | |
114 | ||
ee311214 | 115 | static int tsi108_write_config_dword (struct pci_controller *hose, |
9226e7d6 | 116 | pci_dev_t dev, int offset, u32 value) |
117 | { | |
118 | dev &= (CFG_PCI_CFG_SIZE - 1); | |
119 | dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc)); | |
120 | ||
ee311214 | 121 | out_le32 ((volatile unsigned *)dev, value); |
9226e7d6 | 122 | |
123 | return 0; | |
124 | } | |
125 | ||
ee311214 | 126 | void pci_init_board (void) |
9226e7d6 | 127 | { |
128 | struct pci_controller *hose = (struct pci_controller *)&local_hose; | |
129 | ||
130 | hose->first_busno = 0; | |
131 | hose->last_busno = 0xff; | |
132 | ||
ee311214 | 133 | pci_set_region (hose->regions + 0, |
9226e7d6 | 134 | CFG_PCI_MEMORY_BUS, |
135 | CFG_PCI_MEMORY_PHYS, | |
136 | CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); | |
137 | ||
138 | /* PCI memory space */ | |
ee311214 | 139 | pci_set_region (hose->regions + 1, |
9226e7d6 | 140 | CFG_PCI_MEM_BUS, |
141 | CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); | |
142 | ||
143 | /* PCI I/O space */ | |
ee311214 | 144 | pci_set_region (hose->regions + 2, |
9226e7d6 | 145 | CFG_PCI_IO_BUS, |
146 | CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); | |
147 | ||
148 | hose->region_count = 3; | |
149 | ||
ee311214 | 150 | pci_set_ops (hose, |
9226e7d6 | 151 | pci_hose_read_config_byte_via_dword, |
152 | pci_hose_read_config_word_via_dword, | |
153 | tsi108_read_config_dword, | |
154 | pci_hose_write_config_byte_via_dword, | |
155 | pci_hose_write_config_word_via_dword, | |
156 | tsi108_write_config_dword); | |
157 | ||
ee311214 | 158 | pci_register_hose (hose); |
9226e7d6 | 159 | |
ee311214 | 160 | hose->last_busno = pci_hose_scan (hose); |
9226e7d6 | 161 | |
ee311214 | 162 | debug ("Done PCI initialization\n"); |
9226e7d6 | 163 | return; |
164 | } | |
165 | ||
589c0427 GVB |
166 | #if defined(CONFIG_OF_LIBFDT) |
167 | void ft_pci_setup(void *blob, bd_t *bd) | |
9226e7d6 | 168 | { |
589c0427 GVB |
169 | int nodeoffset; |
170 | int tmp[2]; | |
171 | const char *path; | |
172 | ||
173 | nodeoffset = fdt_path_offset(blob, "/aliases"); | |
174 | if (nodeoffset >= 0) { | |
175 | path = fdt_getprop(blob, nodeoffset, "pci", NULL); | |
176 | if (path) { | |
177 | tmp[0] = cpu_to_be32(local_hose.first_busno); | |
178 | tmp[1] = cpu_to_be32(local_hose.last_busno); | |
179 | do_fixup_by_path(blob, path, "bus-range", | |
180 | &tmp, sizeof(tmp), 1); | |
181 | } | |
9226e7d6 | 182 | } |
9226e7d6 | 183 | } |
589c0427 | 184 | #endif /* CONFIG_OF_LIBFDT */ |
9226e7d6 | 185 | |
186 | #endif /* CONFIG_TSI108_PCI */ |