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1df49e27 WD |
1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
1df49e27 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Initialisation of the PCI-to-ISA bridge and disabling the BIOS | |
10 | * write protection (for flash) in function 0 of the chip. | |
11 | * Enabling function 1 (IDE controller of the chip. | |
12 | */ | |
13 | ||
14 | #include <common.h> | |
15 | #include <config.h> | |
16 | ||
1df49e27 WD |
17 | #include <asm/io.h> |
18 | #include <pci.h> | |
19 | ||
20 | #include <w83c553f.h> | |
21 | ||
22 | #define out8(addr,val) do { \ | |
23 | out_8((u8*) (addr),(val)); udelay(1); \ | |
24 | } while (0) | |
25 | #define out16(addr,val) do { \ | |
26 | out_be16((u16*) (addr),(val)); udelay(1); \ | |
27 | } while (0) | |
28 | ||
6d0f6bcf | 29 | extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; |
1df49e27 WD |
30 | |
31 | void initialise_pic(void); | |
32 | void initialise_dma(void); | |
33 | ||
34 | void initialise_w83c553f(void) | |
35 | { | |
36 | pci_dev_t devbusfn; | |
37 | unsigned char reg8; | |
38 | unsigned short reg16; | |
39 | unsigned int reg32; | |
40 | ||
41 | devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); | |
42 | if (devbusfn == -1) | |
43 | { | |
44 | printf("Error: Cannot find W83C553F controller on any PCI bus."); | |
45 | return; | |
46 | } | |
47 | ||
48 | pci_read_config_word(devbusfn, PCI_COMMAND, ®16); | |
49 | reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; | |
50 | pci_write_config_word(devbusfn, PCI_COMMAND, reg16); | |
51 | ||
52 | pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); | |
53 | /* 16 MB ISA memory space */ | |
54 | reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); | |
55 | reg8 &= ~IPADCR_MBE512; | |
56 | pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); | |
57 | ||
58 | pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); | |
59 | /* switch off BIOS write protection */ | |
60 | reg8 |= CSCR_UBIOSCSE; | |
61 | reg8 &= ~CSCR_BIOSWP; | |
62 | pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); | |
63 | ||
64 | /* | |
65 | * Interrupt routing: | |
66 | * - IDE -> IRQ 9/0 | |
67 | * - INTA -> IRQ 10 | |
68 | * - INTB -> IRQ 11 | |
69 | * - INTC -> IRQ 14 | |
70 | * - INTD -> IRQ 15 | |
71 | */ | |
72 | pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); | |
73 | pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); | |
74 | ||
75 | /* | |
76 | * Read IDE bus offsets from function 1 device. | |
77 | * We must unmask the LSB indicating that ist is an IO address. | |
78 | */ | |
79 | devbusfn |= PCI_BDF(0,0,1); | |
80 | ||
81 | /* | |
82 | * Switch off legacy IRQ for IDE and IDE port 1. | |
83 | */ | |
84 | pci_write_config_byte(devbusfn, 0x09, 0x8F); | |
85 | ||
86 | pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); | |
87 | reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); | |
88 | pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); | |
89 | ||
90 | pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); | |
91 | ide_bus_offset[0] &= ~1; | |
6d0f6bcf | 92 | #if CONFIG_SYS_IDE_MAXBUS > 1 |
1df49e27 WD |
93 | pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); |
94 | ide_bus_offset[1] &= ~1; | |
95 | #endif | |
96 | ||
97 | /* | |
98 | * Enable function 1, IDE -> busmastering and IO space access | |
99 | */ | |
100 | pci_read_config_word(devbusfn, PCI_COMMAND, ®16); | |
101 | reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; | |
102 | pci_write_config_word(devbusfn, PCI_COMMAND, reg16); | |
103 | ||
104 | /* | |
105 | * Initialise ISA interrupt controller | |
106 | */ | |
107 | initialise_pic(); | |
108 | ||
109 | /* | |
110 | * Initialise DMA controller | |
111 | */ | |
112 | initialise_dma(); | |
113 | } | |
114 | ||
115 | void initialise_pic(void) | |
116 | { | |
117 | out8(W83C553F_PIC1_ICW1, 0x11); | |
118 | out8(W83C553F_PIC1_ICW2, 0x08); | |
119 | out8(W83C553F_PIC1_ICW3, 0x04); | |
120 | out8(W83C553F_PIC1_ICW4, 0x01); | |
121 | out8(W83C553F_PIC1_OCW1, 0xfb); | |
122 | out8(W83C553F_PIC1_ELC, 0x20); | |
123 | ||
124 | out8(W83C553F_PIC2_ICW1, 0x11); | |
125 | out8(W83C553F_PIC2_ICW2, 0x08); | |
126 | out8(W83C553F_PIC2_ICW3, 0x02); | |
127 | out8(W83C553F_PIC2_ICW4, 0x01); | |
128 | out8(W83C553F_PIC2_OCW1, 0xff); | |
129 | out8(W83C553F_PIC2_ELC, 0xce); | |
130 | ||
131 | out8(W83C553F_TMR1_CMOD, 0x74); | |
132 | ||
133 | out8(W83C553F_PIC2_OCW1, 0x20); | |
134 | out8(W83C553F_PIC1_OCW1, 0x20); | |
135 | ||
136 | out8(W83C553F_PIC2_OCW1, 0x2b); | |
137 | out8(W83C553F_PIC1_OCW1, 0x2b); | |
138 | } | |
139 | ||
140 | void initialise_dma(void) | |
141 | { | |
142 | unsigned int channel; | |
143 | unsigned int rvalue1, rvalue2; | |
144 | ||
145 | /* perform a H/W reset of the devices */ | |
146 | ||
147 | out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); | |
148 | out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); | |
149 | ||
150 | /* initialise all channels to a sane state */ | |
151 | ||
152 | for (channel = 0; channel < 4; channel++) { | |
153 | /* | |
154 | * dependent upon the channel, setup the specifics: | |
155 | * | |
156 | * demand | |
157 | * address-increment | |
158 | * autoinitialize-disable | |
159 | * verify-transfer | |
160 | */ | |
161 | ||
162 | switch (channel) { | |
163 | case 0: | |
164 | rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); | |
165 | rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); | |
166 | break; | |
53677ef1 | 167 | case 1: |
1df49e27 WD |
168 | rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); |
169 | rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); | |
170 | break; | |
171 | case 2: | |
172 | rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); | |
173 | rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); | |
174 | break; | |
175 | case 3: | |
176 | rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); | |
177 | rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); | |
178 | break; | |
179 | default: | |
180 | rvalue1 = 0x00; | |
181 | rvalue2 = 0x00; | |
182 | break; | |
183 | } | |
184 | ||
185 | /* write to write mode registers */ | |
186 | ||
187 | out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF); | |
188 | out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); | |
189 | } | |
190 | ||
191 | /* enable all channels */ | |
192 | ||
193 | out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); | |
194 | out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); | |
195 | /* | |
196 | * initialize the global DMA configuration | |
197 | * | |
198 | * DACK# active low | |
199 | * DREQ active high | |
200 | * fixed priority | |
201 | * channel group enable | |
202 | */ | |
203 | ||
204 | out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); | |
205 | out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); | |
206 | } |