[people/ms/u-boot.git] / drivers / pci_auto.c

/*
 * arch/ppc/kernel/pci_auto.c
 *
 * PCI autoconfiguration library
 *
 * Author: Matt Porter <mporter@mvista.com>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>

#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */

#define	PCIAUTO_IDE_MODE_MASK		0x05

/*
 *
 */

void pciauto_region_init(struct pci_region* res)
{
	res->bus_lower = res->bus_start;
}

void pciauto_region_align(struct pci_region *res, unsigned long size)
{
	res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}

int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
{
	unsigned long addr;

	if (!res) {
		DEBUGF("No resource");
		goto error;
	}

	addr = ((res->bus_lower - 1) | (size - 1)) + 1;

	if (addr - res->bus_start + size > res->size) {
		DEBUGF("No room in resource");
		goto error;
	}

	res->bus_lower = addr + size;

	DEBUGF("address=0x%lx", addr);

	*bar = addr;
	return 0;

 error:
	*bar = 0xffffffff;
	return -1;
}

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *io)
{
	unsigned int bar_value, bar_response, bar_size;
	unsigned int cmdstat = 0;
	struct pci_region *bar_res;
	int bar, bar_nr = 0;
	int found_mem64 = 0;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
		/* Tickle the BAR and get the response */
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
			bar_res = io;

			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
		} else {
			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
			bar_res = mem;

			DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
		}

		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, bar_value);

			/*
			 * If we are a 64-bit decoder then increment to the
			 * upper 32 bits of the bar and force it to locate
			 * in the lower 4GB of memory.
			 */
			if (found_mem64) {
				bar += 4;
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
			}

			cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
				PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
		}

		DEBUGF("\n");

		bar_nr++;
	}

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_io = hose->pci_io;
	unsigned int cmdstat;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* We don't support prefetchable memory for now, so disable */
	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}

static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
					(pci_mem->bus_lower-1) >> 16);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
					((pci_io->bus_lower-1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
					((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	}
}

/*
 *
 */

void pciauto_config_init(struct pci_controller *hose)
{
	int i;

	hose->pci_io = hose->pci_mem = NULL;

	for (i=0; i<hose->region_count; i++) {
		switch(hose->regions[i].flags) {
		case PCI_REGION_IO:
			if (!hose->pci_io ||
			    hose->pci_io->size < hose->regions[i].size)
				hose->pci_io = hose->regions + i;
			break;
		case PCI_REGION_MEM:
			if (!hose->pci_mem ||
			    hose->pci_mem->size < hose->regions[i].size)
				hose->pci_mem = hose->regions + i;
			break;
		}
	}


	if (hose->pci_mem) {
		pciauto_region_init(hose->pci_mem);

		DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
		    hose->pci_mem->bus_start,
		    hose->pci_mem->bus_start + hose->pci_mem->size - 1);
	}

	if (hose->pci_io) {
		pciauto_region_init(hose->pci_io);

		DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
		    hose->pci_io->bus_start,
		    hose->pci_io->bus_start + hose->pci_io->size - 1);
	}
}

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	unsigned char prg_iface;
	int n;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch(class) {
	case PCI_CLASS_BRIDGE_PCI:
		hose->current_busno++;
		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));

		/* Passing in current_busno allows for sibling P2P bridges */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/*
		 * need to figure out if this is a subordinate bridge on the bus
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* figure out the deepest we've gone for this leg */
		sub_bus = max(n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_STORAGE_IDE:
		pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
		if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
			DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
			return sub_bus;
		}

		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/* just do a minimal setup of the bridge, let the OS take care of the rest */
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));

		hose->current_busno++;
		break;

#ifdef CONFIG_MPC5200
	case PCI_CLASS_BRIDGE_OTHER:
		DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
		       PCI_DEV(dev));
		break;
#endif

	default:
		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
		break;
	}

	return sub_bus;
}

#endif /* CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*
	2	* arch/ppc/kernel/pci_auto.c
	3	*
	4	* PCI autoconfiguration library
	5	*
	6	* Author: Matt Porter <mporter@mvista.com>
	7	*
	8	* Copyright 2000 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <common.h>
	17
	18	#ifdef CONFIG_PCI
	19
	20	#include <pci.h>
	21
	22	#undef DEBUG
	23	#ifdef DEBUG
	24	#define DEBUGF(x...) printf(x)
	25	#else
	26	#define DEBUGF(x...)
	27	#endif /* DEBUG */
	28
	29	#define PCIAUTO_IDE_MODE_MASK 0x05
	30
	31	/*
	32	*
	33	*/
	34
	35	void pciauto_region_init(struct pci_region* res)
	36	{
	37	res->bus_lower = res->bus_start;
	38	}
	39
	40	void pciauto_region_align(struct pci_region *res, unsigned long size)
	41	{
	42	res->bus_lower = ((res->bus_lower - 1) \| (size - 1)) + 1;
	43	}
	44
	45	int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
	46	{
	47	unsigned long addr;
	48
3c74e32a	49	if (!res) {
c609719b WD	50	DEBUGF("No resource");
	51	goto error;
	52	}
	53
	54	addr = ((res->bus_lower - 1) \| (size - 1)) + 1;
	55
3c74e32a	56	if (addr - res->bus_start + size > res->size) {
c609719b WD	57	DEBUGF("No room in resource");
	58	goto error;
	59	}
	60
	61	res->bus_lower = addr + size;
	62
	63	DEBUGF("address=0x%lx", addr);
	64
	65	*bar = addr;
	66	return 0;
	67
	68	error:
	69	*bar = 0xffffffff;
	70	return -1;
	71	}
	72
	73	/*
	74	*
	75	*/
	76
	77	void pciauto_setup_device(struct pci_controller *hose,
	78	pci_dev_t dev, int bars_num,
	79	struct pci_region *mem,
	80	struct pci_region *io)
	81	{
	82	unsigned int bar_value, bar_response, bar_size;
	83	unsigned int cmdstat = 0;
	84	struct pci_region *bar_res;
	85	int bar, bar_nr = 0;
	86	int found_mem64 = 0;
	87
	88	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	89	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
	90
3c74e32a	91	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
c609719b WD	92	/* Tickle the BAR and get the response */
	93	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
	94	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
	95
	96	/* If BAR is not implemented go to the next BAR */
	97	if (!bar_response)
	98	continue;
	99
	100	found_mem64 = 0;
	101
	102	/* Check the BAR type and set our address mask */
3c74e32a	103	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
c609719b WD	104	bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
	105	bar_res = io;
	106
	107	DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
3c74e32a	108	} else {
c609719b WD	109	if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
	110	PCI_BASE_ADDRESS_MEM_TYPE_64)
	111	found_mem64 = 1;
	112
	113	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
	114	bar_res = mem;
	115
	116	DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
	117	}
	118
3c74e32a	119	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
c609719b WD	120	/* Write it out and update our limit */
	121	pci_hose_write_config_dword(hose, dev, bar, bar_value);
	122
	123	/*
	124	* If we are a 64-bit decoder then increment to the
	125	* upper 32 bits of the bar and force it to locate
	126	* in the lower 4GB of memory.
	127	*/
3c74e32a	128	if (found_mem64) {
c609719b WD	129	bar += 4;
	130	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
	131	}
	132
	133	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
	134	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
	135	}
	136
	137	DEBUGF("\n");
	138
	139	bar_nr++;
	140	}
	141
	142	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	143	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	144	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	145	}
	146
	147	static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
	148	pci_dev_t dev, int sub_bus)
	149	{
	150	struct pci_region *pci_mem = hose->pci_mem;
	151	struct pci_region *pci_io = hose->pci_io;
	152	unsigned int cmdstat;
	153
	154	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	155
	156	/* Configure bus number registers */
	157	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
5653fc33	158	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
c609719b WD	159	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
c609719b WD	160
3c74e32a	161	if (pci_mem) {
c609719b WD	162	/* Round memory allocator to 1MB boundary */
	163	pciauto_region_align(pci_mem, 0x100000);
	164
	165	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	166	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	167	(pci_mem->bus_lower & 0xfff00000) >> 16);
	168
	169	cmdstat \|= PCI_COMMAND_MEMORY;
	170	}
	171
3c74e32a	172	if (pci_io) {
c609719b WD	173	/* Round I/O allocator to 4KB boundary */
	174	pciauto_region_align(pci_io, 0x1000);
	175
	176	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	177	(pci_io->bus_lower & 0x0000f000) >> 8);
	178	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	179	(pci_io->bus_lower & 0xffff0000) >> 16);
	180
	181	cmdstat \|= PCI_COMMAND_IO;
	182	}
	183
	184	/* We don't support prefetchable memory for now, so disable */
	185	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
	186	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
	187
	188	/* Enable memory and I/O accesses, enable bus master */
	189	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat \| PCI_COMMAND_MASTER);
	190	}
	191
	192	static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
	193	pci_dev_t dev, int sub_bus)
	194	{
	195	struct pci_region *pci_mem = hose->pci_mem;
	196	struct pci_region *pci_io = hose->pci_io;
	197
	198	/* Configure bus number registers */
	199	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
	200
3c74e32a	201	if (pci_mem) {
c609719b WD	202	/* Round memory allocator to 1MB boundary */
	203	pciauto_region_align(pci_mem, 0x100000);
	204
	205	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
	206	(pci_mem->bus_lower-1) >> 16);
	207	}
	208
3c74e32a	209	if (pci_io) {
c609719b WD	210	/* Round I/O allocator to 4KB boundary */
	211	pciauto_region_align(pci_io, 0x1000);
	212
	213	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
	214	((pci_io->bus_lower-1) & 0x0000f000) >> 8);
	215	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
	216	((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	217	}
	218	}
	219
	220	/*
	221	*
	222	*/
	223
	224	void pciauto_config_init(struct pci_controller *hose)
	225	{
	226	int i;
	227
	228	hose->pci_io = hose->pci_mem = NULL;
	229
3c74e32a WD	230	for (i=0; i<hose->region_count; i++) {
3c74e32a WD	231	switch(hose->regions[i].flags) {
c609719b WD	232	case PCI_REGION_IO:
	233	if (!hose->pci_io \|\|
	234	hose->pci_io->size < hose->regions[i].size)
	235	hose->pci_io = hose->regions + i;
	236	break;
	237	case PCI_REGION_MEM:
	238	if (!hose->pci_mem \|\|
	239	hose->pci_mem->size < hose->regions[i].size)
	240	hose->pci_mem = hose->regions + i;
	241	break;
	242	}
	243	}
	244
	245
3c74e32a	246	if (hose->pci_mem) {
c609719b WD	247	pciauto_region_init(hose->pci_mem);
	248
	249	DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
	250	hose->pci_mem->bus_start,
	251	hose->pci_mem->bus_start + hose->pci_mem->size - 1);
	252	}
	253
3c74e32a	254	if (hose->pci_io) {
c609719b WD	255	pciauto_region_init(hose->pci_io);
	256
	257	DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
	258	hose->pci_io->bus_start,
	259	hose->pci_io->bus_start + hose->pci_io->size - 1);
	260	}
	261	}
	262
c7de829c WD	263	/* HJF: Changed this to return int. I think this is required
	264	* to get the correct result when scanning bridges
	265	*/
	266	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	267	{
c7de829c	268	unsigned int sub_bus = PCI_BUS(dev);
c609719b WD	269	unsigned short class;
c609719b WD	270	unsigned char prg_iface;
5653fc33	271	int n;
c609719b WD	272
	273	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	274
3c74e32a	275	switch(class) {
c609719b	276	case PCI_CLASS_BRIDGE_PCI:
db2f721f	277	hose->current_busno++;
c609719b WD	278	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
c609719b WD	279
db2f721f	280	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
cd37d9e6	281
3c74e32a	282	/* Passing in current_busno allows for sibling P2P bridges */
5653fc33	283	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
cd37d9e6	284	/*
3c74e32a	285	* need to figure out if this is a subordinate bridge on the bus
5653fc33 WD	286	* to be able to properly set the pri/sec/sub bridge registers.
	287	*/
	288	n = pci_hose_scan_bus(hose, hose->current_busno);
	289
3c74e32a	290	/* figure out the deepest we've gone for this leg */
5653fc33	291	sub_bus = max(n, sub_bus);
db2f721f	292	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	293
db2f721f	294	sub_bus = hose->current_busno;
c609719b WD	295	break;
	296
	297	case PCI_CLASS_STORAGE_IDE:
	298	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
3c74e32a WD	299	if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
	300	DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
	301	return sub_bus;
	302	}
c609719b WD	303
	304	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
	305	break;
	306
1cb8e980 WD	307	case PCI_CLASS_BRIDGE_CARDBUS:
	308	/* just do a minimal setup of the bridge, let the OS take care of the rest */
	309	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
	310
3c74e32a	311	DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
1cb8e980 WD	312
	313	hose->current_busno++;
	314	break;
	315
e0ac62d7 WD	316	#ifdef CONFIG_MPC5200
	317	case PCI_CLASS_BRIDGE_OTHER:
	318	DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
	319	PCI_DEV(dev));
	320	break;
	321	#endif
	322
c609719b WD	323	default:
	324	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
	325	break;
	326	}
c7de829c WD	327
c7de829c WD	328	return sub_bus;
c609719b WD	329	}
	330
	331	#endif /* CONFIG_PCI */