[people/ms/u-boot.git] / drivers / pci_auto.c

/*
 * arch/ppc/kernel/pci_auto.c
 *
 * PCI autoconfiguration library
 *
 * Author: Matt Porter <mporter@mvista.com>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>

#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */

#define	PCIAUTO_IDE_MODE_MASK		0x05

/*
 *
 */

void pciauto_region_init(struct pci_region* res)
{
	/*
	 * Avoid allocating PCI resources from address 0 -- this is illegal
	 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
	 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
	 */
	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}

void pciauto_region_align(struct pci_region *res, unsigned long size)
{
	res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}

int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
{
	unsigned long addr;

	if (!res) {
		DEBUGF("No resource");
		goto error;
	}

	addr = ((res->bus_lower - 1) | (size - 1)) + 1;

	if (addr - res->bus_start + size > res->size) {
		DEBUGF("No room in resource");
		goto error;
	}

	res->bus_lower = addr + size;

	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);

	*bar = addr;
	return 0;

 error:
	*bar = 0xffffffff;
	return -1;
}

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *prefetch,
			  struct pci_region *io)
{
	unsigned int bar_value, bar_response, bar_size;
	unsigned int cmdstat = 0;
	struct pci_region *bar_res;
	int bar, bar_nr = 0;
	int found_mem64 = 0;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
		/* Tickle the BAR and get the response */
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
				   & 0xffff) + 1;
			bar_res = io;

			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
		} else {
			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
			if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
				bar_res = prefetch;
			else
				bar_res = mem;

			DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
		}

		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, bar_value);

			/*
			 * If we are a 64-bit decoder then increment to the
			 * upper 32 bits of the bar and force it to locate
			 * in the lower 4GB of memory.
			 */
			if (found_mem64) {
				bar += 4;
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
			}

			cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
				PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
		}

		DEBUGF("\n");

		bar_nr++;
	}

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;
	unsigned int cmdstat;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
				   PCI_BUS(dev) - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
				   sub_bus - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
					(pci_prefetch->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	} else {
		/* We don't support prefetchable memory for now, so disable */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}

void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
				   sub_bus - hose->first_busno);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
					(pci_mem->bus_lower-1) >> 16);
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
					(pci_prefetch->bus_lower-1) >> 16);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
					((pci_io->bus_lower-1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
					((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	}
}

/*
 *
 */

void pciauto_config_init(struct pci_controller *hose)
{
	int i;

	hose->pci_io = hose->pci_mem = NULL;

	for (i=0; i<hose->region_count; i++) {
		switch(hose->regions[i].flags) {
		case PCI_REGION_IO:
			if (!hose->pci_io ||
			    hose->pci_io->size < hose->regions[i].size)
				hose->pci_io = hose->regions + i;
			break;
		case PCI_REGION_MEM:
			if (!hose->pci_mem ||
			    hose->pci_mem->size < hose->regions[i].size)
				hose->pci_mem = hose->regions + i;
			break;
		case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
			if (!hose->pci_prefetch ||
			    hose->pci_prefetch->size < hose->regions[i].size)
				hose->pci_prefetch = hose->regions + i;
			break;
		}
	}


	if (hose->pci_mem) {
		pciauto_region_init(hose->pci_mem);

		DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_mem->bus_start,
		    hose->pci_mem->bus_start + hose->pci_mem->size - 1,
		    hose->pci_mem->phys_start,
		    hose->pci_mem->phys_start + hose->pci_mem->size - 1);
	}

	if (hose->pci_prefetch) {
		pciauto_region_init(hose->pci_prefetch);

		DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_prefetch->bus_start,
		    hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
		    hose->pci_prefetch->phys_start,
		    hose->pci_prefetch->phys_start +
				hose->pci_prefetch->size - 1);
	}

	if (hose->pci_io) {
		pciauto_region_init(hose->pci_io);

		DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
		       "\t\tPhysical Memory: [%x-%x]\n",
		    hose->pci_io->bus_start,
		    hose->pci_io->bus_start + hose->pci_io->size - 1,
		    hose->pci_io->phys_start,
		    hose->pci_io->phys_start + hose->pci_io->size - 1);

	}
}

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	unsigned char prg_iface;
	int n;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch(class) {
	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
		DEBUGF("PCI AutoConfig: Found PowerPC device\n");
		pciauto_setup_device(hose, dev, 6, hose->pci_mem,
				     hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_PCI:
		hose->current_busno++;
		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));

		/* Passing in current_busno allows for sibling P2P bridges */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/*
		 * need to figure out if this is a subordinate bridge on the bus
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* figure out the deepest we've gone for this leg */
		sub_bus = max(n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_STORAGE_IDE:
		pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
		if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
			DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
			return sub_bus;
		}

		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/* just do a minimal setup of the bridge, let the OS take care of the rest */
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));

		hose->current_busno++;
		break;

#ifdef CONFIG_MPC5200
	case PCI_CLASS_BRIDGE_OTHER:
		DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
		       PCI_DEV(dev));
		break;
#endif
#ifdef CONFIG_MPC834X
	case PCI_CLASS_BRIDGE_OTHER:
		/*
		 * The host/PCI bridge 1 seems broken in 8349 - it presents
		 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
		 * device claiming resources io/mem/irq.. we only allow for
		 * the PIMMR window to be allocated (BAR0 - 1MB size)
		 */
		DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
#endif
	default:
		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
	}

	return sub_bus;
}

#endif /* CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*
	2	* arch/ppc/kernel/pci_auto.c
	3	*
	4	* PCI autoconfiguration library
	5	*
	6	* Author: Matt Porter <mporter@mvista.com>
	7	*
	8	* Copyright 2000 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <common.h>
	17
	18	#ifdef CONFIG_PCI
	19
	20	#include <pci.h>
	21
	22	#undef DEBUG
	23	#ifdef DEBUG
	24	#define DEBUGF(x...) printf(x)
	25	#else
	26	#define DEBUGF(x...)
	27	#endif /* DEBUG */
	28
	29	#define PCIAUTO_IDE_MODE_MASK 0x05
	30
	31	/*
	32	*
	33	*/
	34
	35	void pciauto_region_init(struct pci_region* res)
	36	{
b7598a43 SS	37	/*
	38	* Avoid allocating PCI resources from address 0 -- this is illegal
	39	* according to PCI 2.1 and moreover, this is known to cause Linux IDE
	40	* drivers to fail. Use a reasonable starting value of 0x1000 instead.
	41	*/
	42	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
c609719b WD	43	}
	44
	45	void pciauto_region_align(struct pci_region *res, unsigned long size)
	46	{
	47	res->bus_lower = ((res->bus_lower - 1) \| (size - 1)) + 1;
	48	}
	49
	50	int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
	51	{
	52	unsigned long addr;
	53
3c74e32a	54	if (!res) {
c609719b WD	55	DEBUGF("No resource");
	56	goto error;
	57	}
	58
	59	addr = ((res->bus_lower - 1) \| (size - 1)) + 1;
	60
3c74e32a	61	if (addr - res->bus_start + size > res->size) {
c609719b WD	62	DEBUGF("No room in resource");
	63	goto error;
	64	}
	65
	66	res->bus_lower = addr + size;
	67
ba5feb12	68	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);
c609719b WD	69
	70	*bar = addr;
	71	return 0;
	72
	73	error:
	74	*bar = 0xffffffff;
	75	return -1;
	76	}
	77
	78	/*
	79	*
	80	*/
	81
	82	void pciauto_setup_device(struct pci_controller *hose,
	83	pci_dev_t dev, int bars_num,
	84	struct pci_region *mem,
a179012e	85	struct pci_region *prefetch,
c609719b WD	86	struct pci_region *io)
	87	{
	88	unsigned int bar_value, bar_response, bar_size;
	89	unsigned int cmdstat = 0;
	90	struct pci_region *bar_res;
	91	int bar, bar_nr = 0;
	92	int found_mem64 = 0;
	93
	94	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	95	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
	96
936b3e69	97	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
c609719b WD	98	/* Tickle the BAR and get the response */
	99	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
	100	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
	101
	102	/* If BAR is not implemented go to the next BAR */
	103	if (!bar_response)
	104	continue;
	105
	106	found_mem64 = 0;
	107
	108	/* Check the BAR type and set our address mask */
3c74e32a	109	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bd22c2b9 JZR	110	bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
bd22c2b9 JZR	111	& 0xffff) + 1;
c609719b WD	112	bar_res = io;
	113
	114	DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
3c74e32a	115	} else {
c609719b WD	116	if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
	117	PCI_BASE_ADDRESS_MEM_TYPE_64)
	118	found_mem64 = 1;
	119
	120	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
a179012e KG	121	if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
	122	bar_res = prefetch;
	123	else
	124	bar_res = mem;
c609719b WD	125
	126	DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
	127	}
	128
3c74e32a	129	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
c609719b WD	130	/* Write it out and update our limit */
	131	pci_hose_write_config_dword(hose, dev, bar, bar_value);
	132
	133	/*
	134	* If we are a 64-bit decoder then increment to the
	135	* upper 32 bits of the bar and force it to locate
	136	* in the lower 4GB of memory.
	137	*/
3c74e32a	138	if (found_mem64) {
c609719b WD	139	bar += 4;
	140	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
	141	}
	142
	143	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
	144	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
	145	}
	146
	147	DEBUGF("\n");
	148
	149	bar_nr++;
	150	}
	151
	152	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	153	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	154	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	155	}
	156
ba5feb12	157	void pciauto_prescan_setup_bridge(struct pci_controller *hose,
c609719b WD	158	pci_dev_t dev, int sub_bus)
	159	{
	160	struct pci_region *pci_mem = hose->pci_mem;
a179012e	161	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	162	struct pci_region *pci_io = hose->pci_io;
	163	unsigned int cmdstat;
	164
	165	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	166
	167	/* Configure bus number registers */
e8b85f3b ES	168	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
	169	PCI_BUS(dev) - hose->first_busno);
	170	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
	171	sub_bus - hose->first_busno);
c609719b WD	172	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
c609719b WD	173
3c74e32a	174	if (pci_mem) {
c609719b WD	175	/* Round memory allocator to 1MB boundary */
	176	pciauto_region_align(pci_mem, 0x100000);
	177
	178	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	179	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	180	(pci_mem->bus_lower & 0xfff00000) >> 16);
	181
	182	cmdstat \|= PCI_COMMAND_MEMORY;
	183	}
	184
a179012e KG	185	if (pci_prefetch) {
	186	/* Round memory allocator to 1MB boundary */
	187	pciauto_region_align(pci_prefetch, 0x100000);
	188
	189	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	190	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
	191	(pci_prefetch->bus_lower & 0xfff00000) >> 16);
	192
	193	cmdstat \|= PCI_COMMAND_MEMORY;
	194	} else {
	195	/* We don't support prefetchable memory for now, so disable */
	196	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
a4e11558	197	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
a179012e KG	198	}
a179012e KG	199
3c74e32a	200	if (pci_io) {
c609719b WD	201	/* Round I/O allocator to 4KB boundary */
	202	pciauto_region_align(pci_io, 0x1000);
	203
	204	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	205	(pci_io->bus_lower & 0x0000f000) >> 8);
	206	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	207	(pci_io->bus_lower & 0xffff0000) >> 16);
	208
	209	cmdstat \|= PCI_COMMAND_IO;
	210	}
	211
c609719b WD	212	/* Enable memory and I/O accesses, enable bus master */
	213	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat \| PCI_COMMAND_MASTER);
	214	}
	215
ba5feb12	216	void pciauto_postscan_setup_bridge(struct pci_controller *hose,
c609719b WD	217	pci_dev_t dev, int sub_bus)
	218	{
	219	struct pci_region *pci_mem = hose->pci_mem;
a179012e	220	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	221	struct pci_region *pci_io = hose->pci_io;
	222
	223	/* Configure bus number registers */
e8b85f3b ES	224	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
e8b85f3b ES	225	sub_bus - hose->first_busno);
c609719b	226
3c74e32a	227	if (pci_mem) {
c609719b WD	228	/* Round memory allocator to 1MB boundary */
	229	pciauto_region_align(pci_mem, 0x100000);
	230
	231	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
	232	(pci_mem->bus_lower-1) >> 16);
	233	}
	234
a179012e KG	235	if (pci_prefetch) {
	236	/* Round memory allocator to 1MB boundary */
	237	pciauto_region_align(pci_prefetch, 0x100000);
	238
	239	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
	240	(pci_prefetch->bus_lower-1) >> 16);
	241	}
	242
3c74e32a	243	if (pci_io) {
c609719b WD	244	/* Round I/O allocator to 4KB boundary */
	245	pciauto_region_align(pci_io, 0x1000);
	246
	247	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
	248	((pci_io->bus_lower-1) & 0x0000f000) >> 8);
	249	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
	250	((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	251	}
	252	}
	253
	254	/*
	255	*
	256	*/
	257
	258	void pciauto_config_init(struct pci_controller *hose)
	259	{
	260	int i;
	261
	262	hose->pci_io = hose->pci_mem = NULL;
	263
3c74e32a WD	264	for (i=0; i<hose->region_count; i++) {
3c74e32a WD	265	switch(hose->regions[i].flags) {
c609719b WD	266	case PCI_REGION_IO:
	267	if (!hose->pci_io \|\|
	268	hose->pci_io->size < hose->regions[i].size)
	269	hose->pci_io = hose->regions + i;
	270	break;
	271	case PCI_REGION_MEM:
	272	if (!hose->pci_mem \|\|
	273	hose->pci_mem->size < hose->regions[i].size)
	274	hose->pci_mem = hose->regions + i;
	275	break;
a179012e KG	276	case (PCI_REGION_MEM \| PCI_REGION_PREFETCH):
	277	if (!hose->pci_prefetch \|\|
	278	hose->pci_prefetch->size < hose->regions[i].size)
	279	hose->pci_prefetch = hose->regions + i;
	280	break;
c609719b WD	281	}
	282	}
	283
	284
3c74e32a	285	if (hose->pci_mem) {
c609719b WD	286	pciauto_region_init(hose->pci_mem);
c609719b WD	287
ba5feb12 ES	288	DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
ba5feb12 ES	289	"\t\tPhysical Memory [%x-%x]\n",
c609719b	290	hose->pci_mem->bus_start,
ba5feb12 ES	291	hose->pci_mem->bus_start + hose->pci_mem->size - 1,
	292	hose->pci_mem->phys_start,
	293	hose->pci_mem->phys_start + hose->pci_mem->size - 1);
c609719b WD	294	}
c609719b WD	295
a179012e KG	296	if (hose->pci_prefetch) {
	297	pciauto_region_init(hose->pci_prefetch);
	298
ba5feb12 ES	299	DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
ba5feb12 ES	300	"\t\tPhysical Memory [%x-%x]\n",
a179012e	301	hose->pci_prefetch->bus_start,
ba5feb12 ES	302	hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
	303	hose->pci_prefetch->phys_start,
	304	hose->pci_prefetch->phys_start +
	305	hose->pci_prefetch->size - 1);
a179012e KG	306	}
a179012e KG	307
3c74e32a	308	if (hose->pci_io) {
c609719b WD	309	pciauto_region_init(hose->pci_io);
c609719b WD	310
ba5feb12 ES	311	DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
ba5feb12 ES	312	"\t\tPhysical Memory: [%x-%x]\n",
c609719b	313	hose->pci_io->bus_start,
ba5feb12 ES	314	hose->pci_io->bus_start + hose->pci_io->size - 1,
	315	hose->pci_io->phys_start,
	316	hose->pci_io->phys_start + hose->pci_io->size - 1);
	317
c609719b WD	318	}
	319	}
	320
c7de829c WD	321	/* HJF: Changed this to return int. I think this is required
	322	* to get the correct result when scanning bridges
	323	*/
	324	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	325	{
c7de829c	326	unsigned int sub_bus = PCI_BUS(dev);
c609719b WD	327	unsigned short class;
c609719b WD	328	unsigned char prg_iface;
5653fc33	329	int n;
c609719b WD	330
	331	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	332
3c74e32a	333	switch(class) {
5dc210de ES	334	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
	335	DEBUGF("PCI AutoConfig: Found PowerPC device\n");
	336	pciauto_setup_device(hose, dev, 6, hose->pci_mem,
	337	hose->pci_prefetch, hose->pci_io);
	338	break;
	339
c609719b	340	case PCI_CLASS_BRIDGE_PCI:
db2f721f	341	hose->current_busno++;
a179012e	342	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b	343
db2f721f	344	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
cd37d9e6	345
3c74e32a	346	/* Passing in current_busno allows for sibling P2P bridges */
5653fc33	347	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
cd37d9e6	348	/*
3c74e32a	349	* need to figure out if this is a subordinate bridge on the bus
5653fc33 WD	350	* to be able to properly set the pri/sec/sub bridge registers.
	351	*/
	352	n = pci_hose_scan_bus(hose, hose->current_busno);
	353
3c74e32a	354	/* figure out the deepest we've gone for this leg */
5653fc33	355	sub_bus = max(n, sub_bus);
db2f721f	356	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	357
db2f721f	358	sub_bus = hose->current_busno;
c609719b WD	359	break;
	360
	361	case PCI_CLASS_STORAGE_IDE:
	362	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
3c74e32a WD	363	if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
	364	DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
	365	return sub_bus;
	366	}
c609719b	367
a179012e	368	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	369	break;
c609719b WD	370
1cb8e980 WD	371	case PCI_CLASS_BRIDGE_CARDBUS:
1cb8e980 WD	372	/* just do a minimal setup of the bridge, let the OS take care of the rest */
a179012e	373	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
1cb8e980	374
3c74e32a	375	DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
1cb8e980 WD	376
	377	hose->current_busno++;
	378	break;
	379
e0ac62d7 WD	380	#ifdef CONFIG_MPC5200
	381	case PCI_CLASS_BRIDGE_OTHER:
	382	DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
	383	PCI_DEV(dev));
	384	break;
	385	#endif
6902df56 RJ	386	#ifdef CONFIG_MPC834X
	387	case PCI_CLASS_BRIDGE_OTHER:
	388	/*
	389	* The host/PCI bridge 1 seems broken in 8349 - it presents
	390	* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
	391	* device claiming resources io/mem/irq.. we only allow for
	392	* the PIMMR window to be allocated (BAR0 - 1MB size)
	393	*/
	394	DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
a179012e	395	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
6902df56 RJ	396	break;
6902df56 RJ	397	#endif
c609719b	398	default:
a179012e	399	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	400	break;
c609719b WD	401	}
c7de829c WD	402
c7de829c WD	403	return sub_bus;
c609719b WD	404	}
	405
	406	#endif /* CONFIG_PCI */