[people/ms/u-boot.git] / drivers / pci_auto.c

/*
 * arch/ppc/kernel/pci_auto.c
 *
 * PCI autoconfiguration library
 *
 * Author: Matt Porter <mporter@mvista.com>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>

#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */

#define	PCIAUTO_IDE_MODE_MASK		0x05

/*
 *
 */

void pciauto_region_init(struct pci_region* res)
{
	res->bus_lower = res->bus_start;
}

void pciauto_region_align(struct pci_region *res, unsigned long size)
{
	res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}

int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
{
	unsigned long addr;

	if (!res)
	{
		DEBUGF("No resource");
		goto error;
	}

	addr = ((res->bus_lower - 1) | (size - 1)) + 1;

	if (addr - res->bus_start + size > res->size)
	{
		DEBUGF("No room in resource");
		goto error;
	}

	res->bus_lower = addr + size;

	DEBUGF("address=0x%lx", addr);

	*bar = addr;
	return 0;

 error:
	*bar = 0xffffffff;
	return -1;
}

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *io)
{
	unsigned int bar_value, bar_response, bar_size;
	unsigned int cmdstat = 0;
	struct pci_region *bar_res;
	int bar, bar_nr = 0;
	int found_mem64 = 0;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
	{
		/* Tickle the BAR and get the response */
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE)
		{
			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
			bar_res = io;

			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
		}
		else
		{
			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
			bar_res = mem;

			DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
		}

		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
		{
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, bar_value);

			/*
			 * If we are a 64-bit decoder then increment to the
			 * upper 32 bits of the bar and force it to locate
			 * in the lower 4GB of memory.
			 */
			if (found_mem64)
			{
				bar += 4;
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
			}

			cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
				PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
		}

		DEBUGF("\n");

		bar_nr++;
	}

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_io = hose->pci_io;
	unsigned int cmdstat;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
	/* TBS: passed in sub_bus is correct, removed the +1 */
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem)
	{
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_io)
	{
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* We don't support prefetchable memory for now, so disable */
	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}

static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);

	if (pci_mem)
	{
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
					(pci_mem->bus_lower-1) >> 16);
	}

	if (pci_io)
	{
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
					((pci_io->bus_lower-1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
					((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	}
}

/*
 *
 */

void pciauto_config_init(struct pci_controller *hose)
{
	int i;

	hose->pci_io = hose->pci_mem = NULL;

	for (i=0; i<hose->region_count; i++)
	{
		switch(hose->regions[i].flags)
		{
		case PCI_REGION_IO:
			if (!hose->pci_io ||
			    hose->pci_io->size < hose->regions[i].size)
				hose->pci_io = hose->regions + i;
			break;
		case PCI_REGION_MEM:
			if (!hose->pci_mem ||
			    hose->pci_mem->size < hose->regions[i].size)
				hose->pci_mem = hose->regions + i;
			break;
		}
	}


	if (hose->pci_mem)
	{
		pciauto_region_init(hose->pci_mem);

		DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
		    hose->pci_mem->bus_start,
		    hose->pci_mem->bus_start + hose->pci_mem->size - 1);
	}

	if (hose->pci_io)
	{
		pciauto_region_init(hose->pci_io);

		DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
		    hose->pci_io->bus_start,
		    hose->pci_io->bus_start + hose->pci_io->size - 1);
	}
}

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	unsigned char prg_iface;
	int n;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch(class)
	{
	case PCI_CLASS_BRIDGE_PCI:
		hose->current_busno++;
		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
		
		/* TBS: Passing in current_busno allows for sibling P2P bridges */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/* 
		 * TBS: need to figure out if this is a subordinate bridge on the bus 
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* TBS: figure out the deepest we've gone for this leg */
		sub_bus = max(n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_STORAGE_IDE:
		pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
		if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
			{
				DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
				return sub_bus;
			}

		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/* just do a minimal setup of the bridge, let the OS take care of the rest */
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
			PCI_DEV(dev));

		hose->current_busno++;
		break;

#ifdef CONFIG_MPC5200
	case PCI_CLASS_BRIDGE_OTHER:
		DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
		       PCI_DEV(dev));
		break;
#endif

	default:
		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
		break;
	}

	return sub_bus;
}

#endif /* CONFIG_PCI */
Commit	Line	Data
c609719b WD	1	/*
	2	* arch/ppc/kernel/pci_auto.c
	3	*
	4	* PCI autoconfiguration library
	5	*
	6	* Author: Matt Porter <mporter@mvista.com>
	7	*
	8	* Copyright 2000 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <common.h>
	17
	18	#ifdef CONFIG_PCI
	19
	20	#include <pci.h>
	21
	22	#undef DEBUG
	23	#ifdef DEBUG
	24	#define DEBUGF(x...) printf(x)
	25	#else
	26	#define DEBUGF(x...)
	27	#endif /* DEBUG */
	28
	29	#define PCIAUTO_IDE_MODE_MASK 0x05
	30
	31	/*
	32	*
	33	*/
	34
	35	void pciauto_region_init(struct pci_region* res)
	36	{
	37	res->bus_lower = res->bus_start;
	38	}
	39
	40	void pciauto_region_align(struct pci_region *res, unsigned long size)
	41	{
	42	res->bus_lower = ((res->bus_lower - 1) \| (size - 1)) + 1;
	43	}
	44
	45	int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
	46	{
	47	unsigned long addr;
	48
	49	if (!res)
	50	{
	51	DEBUGF("No resource");
	52	goto error;
	53	}
	54
	55	addr = ((res->bus_lower - 1) \| (size - 1)) + 1;
	56
	57	if (addr - res->bus_start + size > res->size)
	58	{
	59	DEBUGF("No room in resource");
	60	goto error;
	61	}
	62
	63	res->bus_lower = addr + size;
	64
65	DEBUGF("address=0x%lx", addr);
66
67	*bar = addr;
68	return 0;
69
70	error:
71	*bar = 0xffffffff;
72	return -1;
73	}
74
75	/*
76	*
77	*/
78
79	void pciauto_setup_device(struct pci_controller *hose,
80	pci_dev_t dev, int bars_num,
81	struct pci_region *mem,
82	struct pci_region *io)
83	{
84	unsigned int bar_value, bar_response, bar_size;
85	unsigned int cmdstat = 0;
86	struct pci_region *bar_res;
87	int bar, bar_nr = 0;
88	int found_mem64 = 0;
89
90	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
91	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
92
93	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
94	{
95	/* Tickle the BAR and get the response */
96	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
97	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
98
99	/* If BAR is not implemented go to the next BAR */
100	if (!bar_response)
101	continue;
102
103	found_mem64 = 0;
104
105	/* Check the BAR type and set our address mask */
106	if (bar_response & PCI_BASE_ADDRESS_SPACE)
107	{
108	bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
109	bar_res = io;
110
111	DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
112	}
113	else
114	{
115	if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
116	PCI_BASE_ADDRESS_MEM_TYPE_64)
117	found_mem64 = 1;
118
119	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
120	bar_res = mem;
121
122	DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
123	}
124
125	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
126	{
127	/* Write it out and update our limit */
128	pci_hose_write_config_dword(hose, dev, bar, bar_value);
129
130	/*
131	* If we are a 64-bit decoder then increment to the
132	* upper 32 bits of the bar and force it to locate
133	* in the lower 4GB of memory.
134	*/
135	if (found_mem64)
136	{
137	bar += 4;
138	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
139	}
140
141	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
142	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
143	}
144
145	DEBUGF("\n");
146
147	bar_nr++;
148	}
149
150	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
151	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
152	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
153	}
154
155	static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
156	pci_dev_t dev, int sub_bus)
157	{
158	struct pci_region *pci_mem = hose->pci_mem;
159	struct pci_region *pci_io = hose->pci_io;
160	unsigned int cmdstat;
161
162	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
163
164	/* Configure bus number registers */
165	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
5653fc33 WD	166	/* TBS: passed in sub_bus is correct, removed the +1 */
5653fc33 WD	167	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
c609719b WD	168	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
	169
	170	if (pci_mem)
	171	{
	172	/* Round memory allocator to 1MB boundary */
	173	pciauto_region_align(pci_mem, 0x100000);
	174
	175	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	176	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	177	(pci_mem->bus_lower & 0xfff00000) >> 16);
	178
	179	cmdstat \|= PCI_COMMAND_MEMORY;
	180	}
	181
	182	if (pci_io)
	183	{
	184	/* Round I/O allocator to 4KB boundary */
	185	pciauto_region_align(pci_io, 0x1000);
	186
	187	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	188	(pci_io->bus_lower & 0x0000f000) >> 8);
	189	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	190	(pci_io->bus_lower & 0xffff0000) >> 16);
	191
	192	cmdstat \|= PCI_COMMAND_IO;
	193	}
	194
	195	/* We don't support prefetchable memory for now, so disable */
	196	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
	197	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
	198
	199	/* Enable memory and I/O accesses, enable bus master */
	200	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat \| PCI_COMMAND_MASTER);
	201	}
	202
	203	static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
	204	pci_dev_t dev, int sub_bus)
	205	{
	206	struct pci_region *pci_mem = hose->pci_mem;
	207	struct pci_region *pci_io = hose->pci_io;
	208
	209	/* Configure bus number registers */
	210	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
	211
	212	if (pci_mem)
	213	{
	214	/* Round memory allocator to 1MB boundary */
	215	pciauto_region_align(pci_mem, 0x100000);
	216
	217	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
	218	(pci_mem->bus_lower-1) >> 16);
	219	}
	220
	221	if (pci_io)
	222	{
	223	/* Round I/O allocator to 4KB boundary */
	224	pciauto_region_align(pci_io, 0x1000);
	225
	226	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
	227	((pci_io->bus_lower-1) & 0x0000f000) >> 8);
	228	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
	229	((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	230	}
	231	}
232
233	/*
234	*
235	*/
236
237	void pciauto_config_init(struct pci_controller *hose)
238	{
239	int i;
240
241	hose->pci_io = hose->pci_mem = NULL;
242
243	for (i=0; i<hose->region_count; i++)
244	{
245	switch(hose->regions[i].flags)
246	{
247	case PCI_REGION_IO:
248	if (!hose->pci_io \|\|
249	hose->pci_io->size < hose->regions[i].size)
250	hose->pci_io = hose->regions + i;
251	break;
252	case PCI_REGION_MEM:
253	if (!hose->pci_mem \|\|
254	hose->pci_mem->size < hose->regions[i].size)
255	hose->pci_mem = hose->regions + i;
256	break;
257	}
258	}
259
260
c609719b WD	261	if (hose->pci_mem)
	262	{
	263	pciauto_region_init(hose->pci_mem);
	264
	265	DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
	266	hose->pci_mem->bus_start,
	267	hose->pci_mem->bus_start + hose->pci_mem->size - 1);
	268	}
	269
	270	if (hose->pci_io)
	271	{
	272	pciauto_region_init(hose->pci_io);
	273
	274	DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
	275	hose->pci_io->bus_start,
	276	hose->pci_io->bus_start + hose->pci_io->size - 1);
	277	}
	278	}
	279
c7de829c WD	280	/* HJF: Changed this to return int. I think this is required
	281	* to get the correct result when scanning bridges
	282	*/
	283	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	284	{
c7de829c	285	unsigned int sub_bus = PCI_BUS(dev);
c609719b WD	286	unsigned short class;
c609719b WD	287	unsigned char prg_iface;
5653fc33	288	int n;
c609719b WD	289
	290	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	291
	292	switch(class)
	293	{
	294	case PCI_CLASS_BRIDGE_PCI:
db2f721f	295	hose->current_busno++;
c609719b WD	296	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
c609719b WD	297
db2f721f	298	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
5653fc33 WD	299
	300	/* TBS: Passing in current_busno allows for sibling P2P bridges */
	301	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
	302	/*
	303	* TBS: need to figure out if this is a subordinate bridge on the bus
	304	* to be able to properly set the pri/sec/sub bridge registers.
	305	*/
	306	n = pci_hose_scan_bus(hose, hose->current_busno);
	307
	308	/* TBS: figure out the deepest we've gone for this leg */
	309	sub_bus = max(n, sub_bus);
db2f721f	310	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	311
db2f721f	312	sub_bus = hose->current_busno;
c609719b WD	313	break;
	314
	315	case PCI_CLASS_STORAGE_IDE:
	316	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
	317	if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
	318	{
	319	DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
c7de829c	320	return sub_bus;
c609719b WD	321	}
	322
	323	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
	324	break;
	325
1cb8e980 WD	326	case PCI_CLASS_BRIDGE_CARDBUS:
	327	/* just do a minimal setup of the bridge, let the OS take care of the rest */
	328	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
	329
	330	DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
	331	PCI_DEV(dev));
	332
	333	hose->current_busno++;
	334	break;
	335
e0ac62d7 WD	336	#ifdef CONFIG_MPC5200
	337	case PCI_CLASS_BRIDGE_OTHER:
	338	DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
	339	PCI_DEV(dev));
	340	break;
	341	#endif
	342
c609719b WD	343	default:
	344	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
	345	break;
	346	}
c7de829c WD	347
c7de829c WD	348	return sub_bus;
c609719b WD	349	}
	350
	351	#endif /* CONFIG_PCI */