]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/pcmcia/mpc8xx_pcmcia.c
Merge branch 'iu-boot/master' into 'u-boot-arm/master'
[people/ms/u-boot.git] / drivers / pcmcia / mpc8xx_pcmcia.c
CommitLineData
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1#include <common.h>
2#include <mpc8xx.h>
3#include <pcmcia.h>
045a9672 4#include <linux/compiler.h>
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5
6#undef CONFIG_PCMCIA
7
07d38a17 8#if defined(CONFIG_CMD_PCMCIA)
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9#define CONFIG_PCMCIA
10#endif
11
07d38a17 12#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
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13#define CONFIG_PCMCIA
14#endif
15
daaf74f1 16#if defined(CONFIG_PCMCIA)
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17
18#if defined(CONFIG_IDE_8xx_PCCARD)
19extern int check_ide_device (int slot);
20#endif
21
22extern int pcmcia_hardware_enable (int slot);
23extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
24
07d38a17 25#if defined(CONFIG_CMD_PCMCIA)
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26extern int pcmcia_hardware_disable(int slot);
27#endif
28
29static u_int m8xx_get_graycode(u_int size);
30#if 0 /* Disabled */
31static u_int m8xx_get_speed(u_int ns, u_int is_io);
32#endif
33
34/* look up table for pgcrx registers */
35u_int *pcmcia_pgcrx[2] = {
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36 &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,
37 &((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,
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38};
39
40/*
41 * Search this table to see if the windowsize is
42 * supported...
43 */
44
45#define M8XX_SIZES_NO 32
46
47static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
48{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
49 0x00000080, 0x00000040, 0x00000010, 0x00000020,
50 0x00008000, 0x00004000, 0x00001000, 0x00002000,
51 0x00000100, 0x00000200, 0x00000800, 0x00000400,
52
53 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
54 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
55 0x00010000, 0x00020000, 0x00080000, 0x00040000,
56 0x00800000, 0x00400000, 0x00100000, 0x00200000 };
57
58
59/* -------------------------------------------------------------------- */
60
9d407995 61#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
6d0f6bcf 62#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \
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63 | PCMCIA_SST(3) \
64 | PCMCIA_SL(12))
9d407995 65#else
6d0f6bcf 66#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \
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67 | PCMCIA_SST(4) \
68 | PCMCIA_SL(9))
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69#endif
70
71/* -------------------------------------------------------------------- */
72
73int pcmcia_on (void)
74{
75 u_long reg, base;
76 pcmcia_win_t *win;
9d407995 77 u_int rc, slot;
045a9672 78 __maybe_unused u_int slotbit;
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79 int i;
80
81 debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
82
83 /* intialize the fixed memory windows */
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JCPV
84 win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
85 base = CONFIG_SYS_PCMCIA_MEM_ADDR;
9d407995 86
6d0f6bcf 87 if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {
9d407995 88 printf ("Cannot set window size to 0x%08x\n",
6d0f6bcf 89 CONFIG_SYS_PCMCIA_MEM_SIZE);
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90 return (1);
91 }
92
93 slotbit = PCMCIA_SLOT_x;
94 for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
95 win->br = base;
96
97#if (PCMCIA_SOCKETS_NO == 2)
98 if (i == 4) /* Another slot starting from win 4 */
99 slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
100#endif
101 switch (i) {
102#ifdef CONFIG_IDE_8xx_PCCARD
103 case 4:
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104 case 0: { /* map attribute memory */
105 win->or = ( PCMCIA_BSIZE_64M
106 | PCMCIA_PPS_8
107 | PCMCIA_PRS_ATTR
108 | slotbit
109 | PCMCIA_PV
6d0f6bcf 110 | CONFIG_SYS_PCMCIA_TIMING );
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111 break;
112 }
113 case 5:
114 case 1: { /* map I/O window for data reg */
115 win->or = ( PCMCIA_BSIZE_1K
116 | PCMCIA_PPS_16
117 | PCMCIA_PRS_IO
118 | slotbit
119 | PCMCIA_PV
6d0f6bcf 120 | CONFIG_SYS_PCMCIA_TIMING );
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121 break;
122 }
123 case 6:
124 case 2: { /* map I/O window for cmd/ctrl reg block */
125 win->or = ( PCMCIA_BSIZE_1K
126 | PCMCIA_PPS_8
127 | PCMCIA_PRS_IO
128 | slotbit
129 | PCMCIA_PV
6d0f6bcf 130 | CONFIG_SYS_PCMCIA_TIMING );
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131 break;
132 }
133#endif /* CONFIG_IDE_8xx_PCCARD */
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134 default: /* set to not valid */
135 win->or = 0;
136 break;
137 }
138
139 debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
140 i, win->br, win->or);
6d0f6bcf 141 base += CONFIG_SYS_PCMCIA_MEM_SIZE;
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142 ++win;
143 }
144
145 for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
146 /* turn off voltage */
147 if ((rc = pcmcia_voltage_set(slot, 0, 0)))
148 continue;
149
150 /* Enable external hardware */
151 if ((rc = pcmcia_hardware_enable(slot)))
152 continue;
153
154#ifdef CONFIG_IDE_8xx_PCCARD
155 if ((rc = check_ide_device(i)))
156 continue;
157#endif
158 }
159 return rc;
160}
161
07d38a17 162#if defined(CONFIG_CMD_PCMCIA)
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163int pcmcia_off (void)
164{
165 int i;
166 pcmcia_win_t *win;
167
168 printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
169
170 /* clear interrupt state, and disable interrupts */
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171 ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
172 ((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
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173
174 /* turn off interrupt and disable CxOE */
175 PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
176
177 /* turn off memory windows */
6d0f6bcf 178 win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
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179
180 for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
181 /* disable memory window */
182 win->or = 0;
183 ++win;
184 }
185
186 /* turn off voltage */
187 pcmcia_voltage_set(_slot_, 0, 0);
188
189 /* disable external hardware */
190 printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
191 pcmcia_hardware_disable(_slot_);
192 return 0;
193}
ddb5d86f 194#endif
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195
196
197static u_int m8xx_get_graycode(u_int size)
198{
199 u_int k;
200
201 for (k = 0; k < M8XX_SIZES_NO; k++) {
202 if(m8xx_size_to_gray[k] == size)
203 break;
204 }
205
206 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
207 k = -1;
208
209 return k;
210}
211
212#if 0
213
214#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
215
216/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
217 * SYPCR is write once only, therefore must the slowest memory be faster
218 * than the bus monitor or we will get a machine check due to the bus timeout.
219 */
220#undef PCMCIA_BMT_LIMIT
221#define PCMCIA_BMT_LIMIT (6*8)
222#endif
223
224static u_int m8xx_get_speed(u_int ns, u_int is_io)
225{
226 u_int reg, clocks, psst, psl, psht;
227
228 if(!ns) {
229
230 /*
231 * We get called with IO maps setup to 0ns
232 * if not specified by the user.
233 * They should be 255ns.
234 */
235
236 if(is_io)
237 ns = 255;
238 else
239 ns = 100; /* fast memory if 0 */
240 }
241
242 /*
243 * In PSST, PSL, PSHT fields we tell the controller
244 * timing parameters in CLKOUT clock cycles.
245 * CLKOUT is the same as GCLK2_50.
246 */
247
248 /* how we want to adjust the timing - in percent */
249
250#define ADJ 180 /* 80 % longer accesstime - to be sure */
251
252 clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
253 clocks = (clocks * ADJ) / (100*1000);
254
255 if(clocks >= PCMCIA_BMT_LIMIT) {
256 DEBUG(0, "Max access time limit reached\n");
257 clocks = PCMCIA_BMT_LIMIT-1;
258 }
259
260 psst = clocks / 7; /* setup time */
261 psht = clocks / 7; /* hold time */
262 psl = (clocks * 5) / 7; /* strobe length */
263
264 psst += clocks - (psst + psht + psl);
265
266 reg = psst << 12;
267 reg |= psl << 7;
268 reg |= psht << 16;
269
270 return reg;
271}
272#endif /* 0 */
273
daaf74f1 274#endif /* CONFIG_PCMCIA */