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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c0132f60 SR |
2 | /* |
3 | * Copyright (C) 2015-2016 Marvell International Ltd. | |
c0132f60 SR |
4 | */ |
5 | ||
6 | #include <common.h> | |
7 | #include <fdtdec.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/arch/cpu.h> | |
10 | #include <asm/arch/soc.h> | |
11 | ||
12 | #include "comphy.h" | |
13 | #include "comphy_hpipe.h" | |
14 | #include "sata.h" | |
15 | #include "utmi_phy.h" | |
16 | ||
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
19 | #define SD_ADDR(base, lane) (base + 0x1000 * lane) | |
20 | #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) | |
21 | #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) | |
22 | ||
23 | struct utmi_phy_data { | |
24 | void __iomem *utmi_base_addr; | |
25 | void __iomem *usb_cfg_addr; | |
26 | void __iomem *utmi_cfg_addr; | |
27 | u32 utmi_phy_port; | |
28 | }; | |
29 | ||
30 | /* | |
31 | * For CP-110 we have 2 Selector registers "PHY Selectors", | |
32 | * and "PIPE Selectors". | |
33 | * PIPE selector include USB and PCIe options. | |
34 | * PHY selector include the Ethernet and SATA options, every Ethernet | |
35 | * option has different options, for example: serdes lane2 had option | |
e7ed9574 | 36 | * Eth_port_0 that include (SGMII0, RXAUI0, SFI) |
c0132f60 SR |
37 | */ |
38 | struct comphy_mux_data cp110_comphy_phy_mux_data[] = { | |
fdc9e880 SR |
39 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ |
40 | {PHY_TYPE_SATA1, 0x4} } }, | |
41 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ | |
42 | {PHY_TYPE_SATA0, 0x4} } }, | |
c0132f60 | 43 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ |
fdc9e880 SR |
44 | {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, |
45 | {PHY_TYPE_SATA0, 0x4} } }, | |
46 | {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ | |
47 | {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, | |
e7ed9574 | 48 | {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ |
fdc9e880 | 49 | {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, |
e7ed9574 | 50 | {PHY_TYPE_SGMII1, 0x1} } }, |
fdc9e880 SR |
51 | {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ |
52 | {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, | |
c0132f60 SR |
53 | }; |
54 | ||
55 | struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { | |
56 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ | |
57 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ | |
58 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, | |
59 | {PHY_TYPE_PEX0, 0x4} } }, | |
60 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ | |
61 | {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, | |
62 | {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ | |
63 | {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, | |
64 | {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ | |
65 | {PHY_TYPE_USB3_HOST1, 0x1}, | |
66 | {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, | |
67 | {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ | |
68 | }; | |
69 | ||
70 | static u32 polling_with_timeout(void __iomem *addr, u32 val, | |
71 | u32 mask, unsigned long usec_timout) | |
72 | { | |
73 | u32 data; | |
74 | ||
75 | do { | |
76 | udelay(1); | |
77 | data = readl(addr) & mask; | |
78 | } while (data != val && --usec_timout > 0); | |
79 | ||
80 | if (usec_timout == 0) | |
81 | return data; | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
7dda98e0 SR |
86 | static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, |
87 | bool is_end_point, void __iomem *hpipe_base, | |
c0132f60 SR |
88 | void __iomem *comphy_base) |
89 | { | |
90 | u32 mask, data, ret = 1; | |
91 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
92 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
93 | void __iomem *addr; | |
94 | u32 pcie_clk = 0; /* set input by default */ | |
95 | ||
96 | debug_enter(); | |
97 | ||
98 | /* | |
99 | * ToDo: | |
100 | * Add SAR (Sample-At-Reset) configuration for the PCIe clock | |
101 | * direction. SAR code is currently not ported from Marvell | |
102 | * U-Boot to mainline version. | |
103 | * | |
104 | * SerDes Lane 4/5 got the PCIe ref-clock #1, | |
105 | * and SerDes Lane 0 got PCIe ref-clock #0 | |
106 | */ | |
107 | debug("PCIe clock = %x\n", pcie_clk); | |
7dda98e0 | 108 | debug("PCIe RC = %d\n", !is_end_point); |
c0132f60 SR |
109 | debug("PCIe width = %d\n", pcie_width); |
110 | ||
111 | /* enable PCIe by4 and by2 */ | |
112 | if (lane == 0) { | |
113 | if (pcie_width == 4) { | |
114 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
115 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET, | |
116 | COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); | |
117 | } else if (pcie_width == 2) { | |
118 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
119 | 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET, | |
120 | COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); | |
121 | } | |
122 | } | |
123 | ||
124 | /* | |
125 | * If PCIe clock is output and clock source from SerDes lane 5, | |
126 | * we need to configure the clock-source MUX. | |
127 | * By default, the clock source is from lane 4 | |
128 | */ | |
129 | if (pcie_clk && clk_src && (lane == 5)) { | |
130 | reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, | |
131 | 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET, | |
132 | DFX_DEV_GEN_PCIE_CLK_SRC_MASK); | |
133 | } | |
134 | ||
135 | debug("stage: RFU configurations - hard reset comphy\n"); | |
136 | /* RFU configurations - hard reset comphy */ | |
137 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
138 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
139 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
140 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
141 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; | |
142 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; | |
143 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; | |
144 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; | |
145 | mask |= COMMON_PHY_PHY_MODE_MASK; | |
146 | data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; | |
147 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
148 | ||
149 | /* release from hard reset */ | |
150 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; | |
151 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; | |
152 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; | |
153 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; | |
154 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
155 | ||
156 | /* Wait 1ms - until band gap and ref clock ready */ | |
157 | mdelay(1); | |
158 | /* Start comphy Configuration */ | |
159 | debug("stage: Comphy configuration\n"); | |
160 | /* Set PIPE soft reset */ | |
161 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; | |
162 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; | |
163 | /* Set PHY datapath width mode for V0 */ | |
164 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; | |
165 | data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; | |
166 | /* Set Data bus width USB mode for V0 */ | |
167 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; | |
168 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; | |
169 | /* Set CORE_CLK output frequency for 250Mhz */ | |
170 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; | |
171 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; | |
172 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); | |
173 | /* Set PLL ready delay for 0x2 */ | |
174 | data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; | |
175 | mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; | |
176 | if (pcie_width != 1) { | |
177 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; | |
178 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; | |
179 | data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; | |
180 | mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; | |
181 | } | |
182 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); | |
183 | ||
184 | /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ | |
185 | data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; | |
186 | mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; | |
187 | if (pcie_width != 1) { | |
188 | mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; | |
189 | mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; | |
190 | mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; | |
191 | if (lane == 0) { | |
192 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; | |
193 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; | |
194 | } else if (lane == (pcie_width - 1)) { | |
195 | data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; | |
196 | } | |
197 | } | |
198 | reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); | |
199 | /* Config update polarity equalization */ | |
200 | reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, | |
201 | 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET, | |
202 | HPIPE_CFG_UPDATE_POLARITY_MASK); | |
203 | /* Set PIPE version 4 to mode enable */ | |
204 | reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, | |
205 | 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, | |
206 | HPIPE_DFE_CTRL_28_PIPE4_MASK); | |
207 | /* TODO: check if pcie clock is output/input - for bringup use input*/ | |
208 | /* Enable PIN clock 100M_125M */ | |
209 | mask = 0; | |
210 | data = 0; | |
211 | /* Only if clock is output, configure the clock-source mux */ | |
212 | if (pcie_clk) { | |
213 | mask |= HPIPE_MISC_CLK100M_125M_MASK; | |
214 | data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; | |
215 | } | |
216 | /* | |
217 | * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz | |
218 | * clock | |
219 | */ | |
220 | mask |= HPIPE_MISC_TXDCLK_2X_MASK; | |
221 | data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; | |
222 | /* Enable 500MHz Clock */ | |
223 | mask |= HPIPE_MISC_CLK500_EN_MASK; | |
224 | data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; | |
225 | if (pcie_clk) { /* output */ | |
226 | /* Set reference clock comes from group 1 */ | |
227 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; | |
228 | data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; | |
229 | } else { | |
230 | /* Set reference clock comes from group 2 */ | |
231 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; | |
232 | data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; | |
233 | } | |
ae07a70a IL |
234 | mask |= HPIPE_MISC_ICP_FORCE_MASK; |
235 | data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; | |
c0132f60 SR |
236 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); |
237 | if (pcie_clk) { /* output */ | |
238 | /* Set reference frequcency select - 0x2 for 25MHz*/ | |
239 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
240 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
241 | } else { | |
242 | /* Set reference frequcency select - 0x0 for 100MHz*/ | |
243 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
244 | data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
245 | } | |
246 | /* Set PHY mode to PCIe */ | |
247 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
248 | data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
249 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
250 | ||
251 | /* ref clock alignment */ | |
252 | if (pcie_width != 1) { | |
253 | mask = HPIPE_LANE_ALIGN_OFF_MASK; | |
254 | data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; | |
255 | reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); | |
256 | } | |
257 | ||
258 | /* | |
259 | * Set the amount of time spent in the LoZ state - set for 0x7 only if | |
260 | * the PCIe clock is output | |
261 | */ | |
262 | if (pcie_clk) { | |
263 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, | |
264 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, | |
265 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); | |
266 | } | |
267 | ||
268 | /* Set Maximal PHY Generation Setting(8Gbps) */ | |
269 | mask = HPIPE_INTERFACE_GEN_MAX_MASK; | |
270 | data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; | |
ae07a70a IL |
271 | /* Bypass frame detection and sync detection for RX DATA */ |
272 | mask = HPIPE_INTERFACE_DET_BYPASS_MASK; | |
273 | data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; | |
c0132f60 SR |
274 | /* Set Link Train Mode (Tx training control pins are used) */ |
275 | mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; | |
276 | data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; | |
277 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); | |
278 | ||
279 | /* Set Idle_sync enable */ | |
280 | mask = HPIPE_PCIE_IDLE_SYNC_MASK; | |
281 | data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; | |
282 | /* Select bits for PCIE Gen3(32bit) */ | |
283 | mask |= HPIPE_PCIE_SEL_BITS_MASK; | |
284 | data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; | |
285 | reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); | |
286 | ||
287 | /* Enable Tx_adapt_g1 */ | |
288 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; | |
289 | data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; | |
290 | /* Enable Tx_adapt_gn1 */ | |
291 | mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; | |
292 | data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; | |
293 | /* Disable Tx_adapt_g0 */ | |
294 | mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; | |
295 | data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; | |
296 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); | |
297 | ||
298 | /* Set reg_tx_train_chk_init */ | |
299 | mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; | |
300 | data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; | |
301 | /* Enable TX_COE_FM_PIN_PCIE3_EN */ | |
302 | mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; | |
303 | data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; | |
304 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); | |
305 | ||
306 | debug("stage: TRx training parameters\n"); | |
307 | /* Set Preset sweep configurations */ | |
308 | mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; | |
309 | data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; | |
310 | ||
311 | mask |= HPIPE_TX_NUM_OF_PRESET_MASK; | |
312 | data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; | |
313 | ||
314 | mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; | |
315 | data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; | |
316 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); | |
317 | ||
318 | /* Tx train start configuration */ | |
319 | mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; | |
320 | data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; | |
321 | ||
322 | mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; | |
323 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; | |
324 | ||
325 | mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; | |
326 | data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; | |
327 | ||
328 | mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; | |
329 | data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; | |
330 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); | |
331 | ||
332 | /* Enable Tx train P2P */ | |
333 | mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; | |
334 | data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; | |
335 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); | |
336 | ||
337 | /* Configure Tx train timeout */ | |
338 | mask = HPIPE_TRX_TRAIN_TIMER_MASK; | |
339 | data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; | |
340 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); | |
341 | ||
342 | /* Disable G0/G1/GN1 adaptation */ | |
343 | mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK | |
344 | | HPIPE_TX_TRAIN_CTRL_G0_OFFSET; | |
345 | data = 0; | |
346 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); | |
347 | ||
348 | /* Disable DTL frequency loop */ | |
349 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; | |
350 | data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; | |
351 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); | |
352 | ||
353 | /* Configure G3 DFE */ | |
354 | mask = HPIPE_G3_DFE_RES_MASK; | |
355 | data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; | |
356 | reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); | |
357 | ||
ae07a70a | 358 | /* Use TX/RX training result for DFE */ |
c0132f60 | 359 | mask = HPIPE_DFE_RES_FORCE_MASK; |
ae07a70a | 360 | data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; |
c0132f60 SR |
361 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); |
362 | ||
363 | /* Configure initial and final coefficient value for receiver */ | |
c01f9fe8 IL |
364 | mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; |
365 | data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; | |
c0132f60 | 366 | |
c01f9fe8 IL |
367 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; |
368 | data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; | |
c0132f60 | 369 | |
c01f9fe8 IL |
370 | mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; |
371 | data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; | |
372 | reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); | |
c0132f60 SR |
373 | |
374 | /* Trigger sampler enable pulse */ | |
375 | mask = HPIPE_SMAPLER_MASK; | |
376 | data = 0x1 << HPIPE_SMAPLER_OFFSET; | |
377 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); | |
378 | udelay(5); | |
379 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); | |
380 | ||
381 | /* FFE resistor tuning for different bandwidth */ | |
382 | mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; | |
383 | data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; | |
384 | ||
385 | mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; | |
ae07a70a | 386 | data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; |
c0132f60 SR |
387 | reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); |
388 | ||
ae07a70a IL |
389 | /* Pattern lock lost timeout disable */ |
390 | mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; | |
391 | data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; | |
392 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); | |
393 | ||
394 | /* Configure DFE adaptations */ | |
395 | mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; | |
396 | data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; | |
397 | mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; | |
398 | data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; | |
399 | mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; | |
400 | data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; | |
401 | reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); | |
402 | mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; | |
403 | data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; | |
404 | reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); | |
405 | ||
406 | /* Genration 2 setting 1*/ | |
407 | mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; | |
408 | data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; | |
409 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; | |
410 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; | |
411 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; | |
412 | data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; | |
413 | reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); | |
414 | ||
415 | /* DFE enable */ | |
416 | mask = HPIPE_G2_DFE_RES_MASK; | |
417 | data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; | |
418 | reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); | |
419 | ||
420 | /* Configure DFE Resolution */ | |
421 | mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; | |
422 | data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; | |
423 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); | |
424 | ||
425 | /* VDD calibration control */ | |
426 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; | |
427 | data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; | |
428 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); | |
429 | ||
430 | /* Set PLL Charge-pump Current Control */ | |
431 | mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; | |
432 | data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; | |
433 | reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); | |
434 | ||
435 | /* Set lane rqualization remote setting */ | |
436 | mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; | |
437 | data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; | |
438 | mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; | |
439 | data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; | |
440 | mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; | |
441 | data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; | |
442 | reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); | |
443 | ||
7dda98e0 SR |
444 | if (!is_end_point) { |
445 | /* Set phy in root complex mode */ | |
446 | mask = HPIPE_CFG_PHY_RC_EP_MASK; | |
447 | data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; | |
448 | reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); | |
449 | } | |
c0132f60 SR |
450 | |
451 | debug("stage: Comphy power up\n"); | |
452 | ||
453 | /* | |
454 | * For PCIe by4 or by2 - release from reset only after finish to | |
455 | * configure all lanes | |
456 | */ | |
457 | if ((pcie_width == 1) || (lane == (pcie_width - 1))) { | |
458 | u32 i, start_lane, end_lane; | |
459 | ||
460 | if (pcie_width != 1) { | |
461 | /* allows writing to all lanes in one write */ | |
462 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
463 | 0x0 << | |
464 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, | |
465 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); | |
466 | start_lane = 0; | |
467 | end_lane = pcie_width; | |
468 | ||
469 | /* | |
470 | * Release from PIPE soft reset | |
471 | * for PCIe by4 or by2 - release from soft reset | |
472 | * all lanes - can't use read modify write | |
473 | */ | |
474 | reg_set(HPIPE_ADDR(hpipe_base, 0) + | |
475 | HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); | |
476 | } else { | |
477 | start_lane = lane; | |
478 | end_lane = lane + 1; | |
479 | ||
480 | /* | |
481 | * Release from PIPE soft reset | |
482 | * for PCIe by4 or by2 - release from soft reset | |
483 | * all lanes | |
484 | */ | |
485 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, | |
486 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, | |
487 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); | |
488 | } | |
489 | ||
490 | ||
491 | if (pcie_width != 1) { | |
492 | /* disable writing to all lanes with one write */ | |
493 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
494 | 0x3210 << | |
495 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET, | |
496 | COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); | |
497 | } | |
498 | ||
499 | debug("stage: Check PLL\n"); | |
500 | /* Read lane status */ | |
501 | for (i = start_lane; i < end_lane; i++) { | |
502 | addr = HPIPE_ADDR(hpipe_base, i) + | |
503 | HPIPE_LANE_STATUS1_REG; | |
504 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; | |
505 | mask = data; | |
506 | data = polling_with_timeout(addr, data, mask, 15000); | |
507 | if (data != 0) { | |
508 | debug("Read from reg = %p - value = 0x%x\n", | |
509 | hpipe_addr + HPIPE_LANE_STATUS1_REG, | |
510 | data); | |
9b643e31 | 511 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
c0132f60 SR |
512 | ret = 0; |
513 | } | |
514 | } | |
515 | } | |
516 | ||
517 | debug_exit(); | |
518 | return ret; | |
519 | } | |
520 | ||
521 | static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, | |
522 | void __iomem *comphy_base) | |
523 | { | |
524 | u32 mask, data, ret = 1; | |
525 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
526 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
527 | void __iomem *addr; | |
528 | ||
529 | debug_enter(); | |
530 | debug("stage: RFU configurations - hard reset comphy\n"); | |
531 | /* RFU configurations - hard reset comphy */ | |
532 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
533 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
534 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
535 | data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
536 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; | |
537 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; | |
538 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; | |
539 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; | |
540 | mask |= COMMON_PHY_PHY_MODE_MASK; | |
541 | data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; | |
542 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
543 | ||
544 | /* release from hard reset */ | |
545 | mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; | |
546 | data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; | |
547 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; | |
548 | data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; | |
549 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
550 | ||
551 | /* Wait 1ms - until band gap and ref clock ready */ | |
552 | mdelay(1); | |
553 | ||
554 | /* Start comphy Configuration */ | |
555 | debug("stage: Comphy configuration\n"); | |
556 | /* Set PIPE soft reset */ | |
557 | mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; | |
558 | data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; | |
559 | /* Set PHY datapath width mode for V0 */ | |
560 | mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; | |
561 | data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; | |
562 | /* Set Data bus width USB mode for V0 */ | |
563 | mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; | |
564 | data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; | |
565 | /* Set CORE_CLK output frequency for 250Mhz */ | |
566 | mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; | |
567 | data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; | |
568 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); | |
569 | /* Set PLL ready delay for 0x2 */ | |
570 | reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, | |
571 | 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, | |
572 | HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); | |
573 | /* Set reference clock to come from group 1 - 25Mhz */ | |
574 | reg_set(hpipe_addr + HPIPE_MISC_REG, | |
575 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, | |
576 | HPIPE_MISC_REFCLK_SEL_MASK); | |
577 | /* Set reference frequcency select - 0x2 */ | |
578 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
579 | data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
580 | /* Set PHY mode to USB - 0x5 */ | |
581 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
582 | data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
583 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
584 | /* Set the amount of time spent in the LoZ state - set for 0x7 */ | |
585 | reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, | |
586 | 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, | |
587 | HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); | |
588 | /* Set max PHY generation setting - 5Gbps */ | |
589 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, | |
590 | 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, | |
591 | HPIPE_INTERFACE_GEN_MAX_MASK); | |
592 | /* Set select data width 20Bit (SEL_BITS[2:0]) */ | |
593 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, | |
594 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, | |
595 | HPIPE_LOOPBACK_SEL_MASK); | |
596 | /* select de-emphasize 3.5db */ | |
597 | reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, | |
598 | 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, | |
599 | HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); | |
600 | /* override tx margining from the MAC */ | |
601 | reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, | |
602 | 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, | |
603 | HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); | |
604 | ||
605 | /* Start analog paramters from ETP(HW) */ | |
606 | debug("stage: Analog paramters from ETP(HW)\n"); | |
607 | /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ | |
608 | mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; | |
609 | data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; | |
610 | /* Set Override PHY DFE control pins for 0x1 */ | |
611 | mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; | |
612 | data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; | |
613 | /* Set Spread Spectrum Clock Enable fot 0x1 */ | |
614 | mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; | |
615 | data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; | |
616 | reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); | |
617 | /* End of analog parameters */ | |
618 | ||
619 | debug("stage: Comphy power up\n"); | |
620 | /* Release from PIPE soft reset */ | |
621 | reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, | |
622 | 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, | |
623 | HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); | |
624 | ||
625 | /* wait 15ms - for comphy calibration done */ | |
626 | debug("stage: Check PLL\n"); | |
627 | /* Read lane status */ | |
628 | addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; | |
629 | data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; | |
630 | mask = data; | |
631 | data = polling_with_timeout(addr, data, mask, 15000); | |
632 | if (data != 0) { | |
633 | debug("Read from reg = %p - value = 0x%x\n", | |
634 | hpipe_addr + HPIPE_LANE_STATUS1_REG, data); | |
9b643e31 | 635 | pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); |
c0132f60 SR |
636 | ret = 0; |
637 | } | |
638 | ||
639 | debug_exit(); | |
640 | return ret; | |
641 | } | |
642 | ||
643 | static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, | |
528213d3 | 644 | void __iomem *comphy_base, int cp_index) |
c0132f60 SR |
645 | { |
646 | u32 mask, data, i, ret = 1; | |
647 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
648 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); | |
649 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
650 | void __iomem *addr; | |
651 | void __iomem *sata_base = NULL; | |
652 | int sata_node = -1; /* Set to -1 in order to read the first sata node */ | |
653 | ||
654 | debug_enter(); | |
655 | ||
656 | /* | |
657 | * Assumption - each CP has only one SATA controller | |
658 | * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 | |
659 | * will return the first node always. | |
660 | * In order to parse each CPs SATA node, fdt_node_offset_by_compatible | |
661 | * must be called again (according to the CP id) | |
662 | */ | |
528213d3 | 663 | for (i = 0; i < (cp_index + 1); i++) |
c0132f60 SR |
664 | sata_node = fdt_node_offset_by_compatible( |
665 | gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); | |
666 | ||
667 | if (sata_node == 0) { | |
9b643e31 | 668 | pr_err("SATA node not found in FDT\n"); |
c0132f60 SR |
669 | return 0; |
670 | } | |
671 | ||
672 | sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent( | |
673 | gd->fdt_blob, sata_node, "reg", 0, NULL, true); | |
674 | if (sata_base == NULL) { | |
9b643e31 | 675 | pr_err("SATA address not found in FDT\n"); |
c0132f60 SR |
676 | return 0; |
677 | } | |
678 | ||
679 | debug("SATA address found in FDT %p\n", sata_base); | |
680 | ||
681 | debug("stage: MAC configuration - power down comphy\n"); | |
682 | /* | |
683 | * MAC configuration powe down comphy use indirect address for | |
684 | * vendor spesific SATA control register | |
685 | */ | |
686 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, | |
687 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, | |
688 | SATA3_VENDOR_ADDR_MASK); | |
689 | /* SATA 0 power down */ | |
690 | mask = SATA3_CTRL_SATA0_PD_MASK; | |
691 | data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; | |
692 | /* SATA 1 power down */ | |
693 | mask |= SATA3_CTRL_SATA1_PD_MASK; | |
694 | data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; | |
695 | /* SATA SSU disable */ | |
696 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; | |
697 | data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; | |
698 | /* SATA port 1 disable */ | |
699 | mask |= SATA3_CTRL_SATA_SSU_MASK; | |
700 | data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; | |
701 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); | |
702 | ||
703 | debug("stage: RFU configurations - hard reset comphy\n"); | |
704 | /* RFU configurations - hard reset comphy */ | |
705 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
706 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
707 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
708 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
709 | mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; | |
710 | data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; | |
711 | mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; | |
712 | data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; | |
713 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
714 | ||
715 | /* Set select data width 40Bit - SATA mode only */ | |
716 | reg_set(comphy_addr + COMMON_PHY_CFG6_REG, | |
717 | 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, | |
718 | COMMON_PHY_CFG6_IF_40_SEL_MASK); | |
719 | ||
720 | /* release from hard reset in SD external */ | |
721 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
722 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
723 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
724 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
725 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
726 | ||
727 | /* Wait 1ms - until band gap and ref clock ready */ | |
728 | mdelay(1); | |
729 | ||
730 | debug("stage: Comphy configuration\n"); | |
731 | /* Start comphy Configuration */ | |
732 | /* Set reference clock to comes from group 1 - choose 25Mhz */ | |
733 | reg_set(hpipe_addr + HPIPE_MISC_REG, | |
734 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, | |
735 | HPIPE_MISC_REFCLK_SEL_MASK); | |
736 | /* Reference frequency select set 1 (for SATA = 25Mhz) */ | |
737 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
738 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
739 | /* PHY mode select (set SATA = 0x0 */ | |
740 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
741 | data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
742 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
743 | /* Set max PHY generation setting - 6Gbps */ | |
744 | reg_set(hpipe_addr + HPIPE_INTERFACE_REG, | |
745 | 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, | |
746 | HPIPE_INTERFACE_GEN_MAX_MASK); | |
747 | /* Set select data width 40Bit (SEL_BITS[2:0]) */ | |
748 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, | |
749 | 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); | |
750 | ||
751 | debug("stage: Analog paramters from ETP(HW)\n"); | |
c01f9fe8 IL |
752 | /* Set analog parameters from ETP(HW) */ |
753 | /* G1 settings */ | |
754 | mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; | |
755 | data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; | |
756 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; | |
757 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; | |
758 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; | |
759 | data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; | |
760 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; | |
761 | data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; | |
762 | mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; | |
763 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; | |
764 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); | |
765 | ||
766 | mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; | |
767 | data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; | |
768 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; | |
769 | data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; | |
770 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; | |
771 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; | |
772 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; | |
773 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; | |
774 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; | |
775 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; | |
776 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); | |
777 | ||
778 | /* G2 settings */ | |
779 | mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; | |
780 | data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; | |
781 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; | |
782 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; | |
783 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; | |
784 | data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; | |
785 | mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; | |
786 | data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; | |
787 | mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; | |
788 | data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; | |
789 | reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); | |
790 | ||
791 | /* G3 settings */ | |
792 | mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; | |
793 | data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; | |
794 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; | |
795 | data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; | |
796 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; | |
797 | data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; | |
798 | mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; | |
799 | data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; | |
800 | mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; | |
801 | data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; | |
802 | mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; | |
803 | data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; | |
804 | mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; | |
805 | data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; | |
806 | reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); | |
807 | ||
808 | /* DTL Control */ | |
809 | mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; | |
810 | data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; | |
811 | mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; | |
812 | data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; | |
813 | mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; | |
814 | data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; | |
815 | mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; | |
816 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; | |
817 | mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; | |
818 | data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; | |
819 | mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; | |
820 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; | |
821 | mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; | |
822 | data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; | |
823 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); | |
824 | ||
825 | /* Trigger sampler enable pulse (by toggleing the bit) */ | |
826 | mask = HPIPE_SMAPLER_MASK; | |
827 | data = 0x1 << HPIPE_SMAPLER_OFFSET; | |
828 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); | |
829 | mask = HPIPE_SMAPLER_MASK; | |
830 | data = 0x0 << HPIPE_SMAPLER_OFFSET; | |
831 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); | |
832 | ||
833 | /* VDD Calibration Control 3 */ | |
834 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; | |
835 | data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; | |
836 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); | |
837 | ||
838 | /* DFE Resolution Control */ | |
839 | mask = HPIPE_DFE_RES_FORCE_MASK; | |
840 | data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; | |
841 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); | |
842 | ||
843 | /* DFE F3-F5 Coefficient Control */ | |
844 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; | |
845 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; | |
846 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; | |
847 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; | |
848 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); | |
849 | ||
850 | /* G3 Setting 3 */ | |
851 | mask = HPIPE_G3_FFE_CAP_SEL_MASK; | |
852 | data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; | |
853 | mask |= HPIPE_G3_FFE_RES_SEL_MASK; | |
854 | data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; | |
855 | mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; | |
856 | data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; | |
857 | mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; | |
858 | data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; | |
859 | mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; | |
860 | data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; | |
861 | reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); | |
862 | ||
863 | /* G3 Setting 4 */ | |
864 | mask = HPIPE_G3_DFE_RES_MASK; | |
865 | data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; | |
866 | reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); | |
867 | ||
868 | /* Offset Phase Control */ | |
869 | mask = HPIPE_OS_PH_OFFSET_MASK; | |
870 | data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; | |
871 | mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; | |
872 | data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; | |
873 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); | |
874 | mask = HPIPE_OS_PH_VALID_MASK; | |
875 | data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; | |
876 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); | |
877 | mask = HPIPE_OS_PH_VALID_MASK; | |
878 | data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; | |
879 | reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); | |
880 | ||
881 | /* Set G1 TX amplitude and TX post emphasis value */ | |
882 | mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; | |
883 | data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; | |
884 | mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; | |
885 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; | |
886 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; | |
887 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; | |
888 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; | |
889 | data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; | |
890 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); | |
891 | ||
892 | /* Set G2 TX amplitude and TX post emphasis value */ | |
893 | mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; | |
894 | data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; | |
895 | mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; | |
896 | data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; | |
897 | mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; | |
898 | data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; | |
899 | mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; | |
900 | data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; | |
901 | reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); | |
902 | ||
903 | /* Set G3 TX amplitude and TX post emphasis value */ | |
904 | mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; | |
905 | data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; | |
906 | mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; | |
907 | data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; | |
908 | mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; | |
909 | data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; | |
910 | mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; | |
911 | data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; | |
912 | mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; | |
913 | data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; | |
914 | mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; | |
915 | data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; | |
916 | reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); | |
917 | ||
918 | /* SERDES External Configuration 2 register */ | |
919 | mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; | |
920 | data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; | |
921 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); | |
c0132f60 SR |
922 | |
923 | /* DFE reset sequence */ | |
924 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, | |
925 | 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, | |
926 | HPIPE_PWR_CTR_RST_DFE_MASK); | |
927 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, | |
928 | 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, | |
929 | HPIPE_PWR_CTR_RST_DFE_MASK); | |
930 | /* SW reset for interupt logic */ | |
931 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, | |
932 | 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, | |
933 | HPIPE_PWR_CTR_SFT_RST_MASK); | |
934 | reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, | |
935 | 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, | |
936 | HPIPE_PWR_CTR_SFT_RST_MASK); | |
937 | ||
938 | debug("stage: Comphy power up\n"); | |
939 | /* | |
940 | * MAC configuration power up comphy - power up PLL/TX/RX | |
941 | * use indirect address for vendor spesific SATA control register | |
942 | */ | |
943 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, | |
944 | SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, | |
945 | SATA3_VENDOR_ADDR_MASK); | |
946 | /* SATA 0 power up */ | |
947 | mask = SATA3_CTRL_SATA0_PD_MASK; | |
948 | data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; | |
949 | /* SATA 1 power up */ | |
950 | mask |= SATA3_CTRL_SATA1_PD_MASK; | |
951 | data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; | |
952 | /* SATA SSU enable */ | |
953 | mask |= SATA3_CTRL_SATA1_ENABLE_MASK; | |
954 | data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; | |
955 | /* SATA port 1 enable */ | |
956 | mask |= SATA3_CTRL_SATA_SSU_MASK; | |
957 | data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; | |
958 | reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); | |
959 | ||
960 | /* MBUS request size and interface select register */ | |
961 | reg_set(sata_base + SATA3_VENDOR_ADDRESS, | |
962 | SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET, | |
963 | SATA3_VENDOR_ADDR_MASK); | |
964 | /* Mbus regret enable */ | |
965 | reg_set(sata_base + SATA3_VENDOR_DATA, | |
966 | 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK); | |
967 | ||
968 | debug("stage: Check PLL\n"); | |
969 | ||
970 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
971 | data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & | |
972 | SD_EXTERNAL_STATUS0_PLL_RX_MASK; | |
973 | mask = data; | |
974 | data = polling_with_timeout(addr, data, mask, 15000); | |
975 | if (data != 0) { | |
976 | debug("Read from reg = %p - value = 0x%x\n", | |
977 | hpipe_addr + HPIPE_LANE_STATUS1_REG, data); | |
9b643e31 | 978 | pr_err("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n", |
c0132f60 SR |
979 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), |
980 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); | |
981 | ret = 0; | |
982 | } | |
983 | ||
984 | debug_exit(); | |
985 | return ret; | |
986 | } | |
987 | ||
988 | static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, | |
989 | void __iomem *hpipe_base, | |
990 | void __iomem *comphy_base) | |
991 | { | |
992 | u32 mask, data, ret = 1; | |
993 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
994 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); | |
995 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
996 | void __iomem *addr; | |
997 | ||
998 | debug_enter(); | |
999 | debug("stage: RFU configurations - hard reset comphy\n"); | |
1000 | /* RFU configurations - hard reset comphy */ | |
1001 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
1002 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
1003 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
1004 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
1005 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
1006 | ||
1007 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ | |
1008 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1009 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1010 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; | |
1011 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; | |
1012 | if (sgmii_speed == PHY_SPEED_1_25G) { | |
1013 | data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; | |
1014 | data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; | |
1015 | } else { | |
1016 | /* 3.125G */ | |
1017 | data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; | |
1018 | data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; | |
1019 | } | |
1020 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1021 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1022 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1023 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1024 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; | |
1025 | data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; | |
1026 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1027 | ||
1028 | /* release from hard reset */ | |
1029 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1030 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1031 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1032 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1033 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1034 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1035 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1036 | ||
1037 | /* release from hard reset */ | |
1038 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1039 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1040 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1041 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1042 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1043 | ||
1044 | ||
1045 | /* Wait 1ms - until band gap and ref clock ready */ | |
1046 | mdelay(1); | |
1047 | ||
1048 | /* Start comphy Configuration */ | |
1049 | debug("stage: Comphy configuration\n"); | |
1050 | /* set reference clock */ | |
1051 | mask = HPIPE_MISC_REFCLK_SEL_MASK; | |
1052 | data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; | |
1053 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); | |
1054 | /* Power and PLL Control */ | |
1055 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
1056 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
1057 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
1058 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
1059 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
1060 | /* Loopback register */ | |
1061 | mask = HPIPE_LOOPBACK_SEL_MASK; | |
1062 | data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; | |
1063 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); | |
1064 | /* rx control 1 */ | |
1065 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; | |
1066 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; | |
1067 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; | |
1068 | data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; | |
1069 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); | |
1070 | /* DTL Control */ | |
1071 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; | |
1072 | data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; | |
1073 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); | |
1074 | ||
1075 | /* Set analog paramters from ETP(HW) - for now use the default datas */ | |
1076 | debug("stage: Analog paramters from ETP(HW)\n"); | |
1077 | ||
1078 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, | |
1079 | 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, | |
1080 | HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); | |
1081 | ||
1082 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); | |
1083 | /* SERDES External Configuration */ | |
1084 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1085 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1086 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1087 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1088 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1089 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1090 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1091 | ||
1092 | /* check PLL rx & tx ready */ | |
1093 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1094 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | | |
1095 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; | |
1096 | mask = data; | |
1097 | data = polling_with_timeout(addr, data, mask, 15000); | |
1098 | if (data != 0) { | |
1099 | debug("Read from reg = %p - value = 0x%x\n", | |
1100 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1101 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
c0132f60 SR |
1102 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
1103 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); | |
1104 | ret = 0; | |
1105 | } | |
1106 | ||
1107 | /* RX init */ | |
1108 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; | |
1109 | data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; | |
1110 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1111 | ||
1112 | /* check that RX init done */ | |
1113 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1114 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; | |
1115 | mask = data; | |
1116 | data = polling_with_timeout(addr, data, mask, 100); | |
1117 | if (data != 0) { | |
1118 | debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1119 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
c0132f60 SR |
1120 | ret = 0; |
1121 | } | |
1122 | ||
1123 | debug("stage: RF Reset\n"); | |
1124 | /* RF Reset */ | |
1125 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; | |
1126 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; | |
1127 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1128 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1129 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1130 | ||
1131 | debug_exit(); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
cb686454 | 1135 | static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, |
b617a0d7 | 1136 | void __iomem *comphy_base, u32 speed) |
c0132f60 SR |
1137 | { |
1138 | u32 mask, data, ret = 1; | |
1139 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
1140 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); | |
1141 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
1142 | void __iomem *addr; | |
1143 | ||
1144 | debug_enter(); | |
1145 | debug("stage: RFU configurations - hard reset comphy\n"); | |
1146 | /* RFU configurations - hard reset comphy */ | |
1147 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
1148 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
1149 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
1150 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
1151 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
1152 | ||
1153 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ | |
1154 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1155 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1156 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; | |
1157 | data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; | |
1158 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; | |
1159 | data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; | |
1160 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1161 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1162 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1163 | data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1164 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; | |
1165 | data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; | |
1166 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1167 | ||
1168 | /* release from hard reset */ | |
1169 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1170 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1171 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1172 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1173 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1174 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1175 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1176 | ||
1177 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1178 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1179 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1180 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1181 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1182 | ||
1183 | ||
1184 | /* Wait 1ms - until band gap and ref clock ready */ | |
1185 | mdelay(1); | |
1186 | ||
1187 | /* Start comphy Configuration */ | |
1188 | debug("stage: Comphy configuration\n"); | |
1189 | /* set reference clock */ | |
1190 | mask = HPIPE_MISC_ICP_FORCE_MASK; | |
b617a0d7 IL |
1191 | data = (speed == PHY_SPEED_5_15625G) ? |
1192 | (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : | |
1193 | (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); | |
c0132f60 SR |
1194 | mask |= HPIPE_MISC_REFCLK_SEL_MASK; |
1195 | data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; | |
1196 | reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); | |
1197 | /* Power and PLL Control */ | |
1198 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
1199 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
1200 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
1201 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
1202 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
1203 | /* Loopback register */ | |
1204 | mask = HPIPE_LOOPBACK_SEL_MASK; | |
1205 | data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; | |
1206 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); | |
1207 | /* rx control 1 */ | |
1208 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; | |
1209 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; | |
1210 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; | |
1211 | data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; | |
1212 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); | |
1213 | /* DTL Control */ | |
1214 | mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; | |
1215 | data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; | |
1216 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); | |
1217 | ||
b617a0d7 IL |
1218 | /* Transmitter/Receiver Speed Divider Force */ |
1219 | if (speed == PHY_SPEED_5_15625G) { | |
1220 | mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; | |
1221 | data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; | |
1222 | mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; | |
1223 | data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; | |
1224 | mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; | |
1225 | data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; | |
1226 | mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; | |
1227 | data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; | |
781ea0ab IL |
1228 | } else { |
1229 | mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; | |
1230 | data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; | |
b617a0d7 | 1231 | } |
781ea0ab | 1232 | reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); |
b617a0d7 | 1233 | |
c0132f60 SR |
1234 | /* Set analog paramters from ETP(HW) */ |
1235 | debug("stage: Analog paramters from ETP(HW)\n"); | |
1236 | /* SERDES External Configuration 2 */ | |
1237 | mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; | |
1238 | data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; | |
1239 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); | |
1240 | /* 0x7-DFE Resolution control */ | |
1241 | mask = HPIPE_DFE_RES_FORCE_MASK; | |
1242 | data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; | |
1243 | reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); | |
1244 | /* 0xd-G1_Setting_0 */ | |
b617a0d7 IL |
1245 | if (speed == PHY_SPEED_5_15625G) { |
1246 | mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; | |
1247 | data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; | |
1248 | } else { | |
1249 | mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; | |
1250 | data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; | |
1251 | mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; | |
1252 | data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; | |
1253 | } | |
c0132f60 SR |
1254 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); |
1255 | /* Genration 1 setting 2 (G1_Setting_2) */ | |
1256 | mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; | |
1257 | data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; | |
1258 | mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; | |
1259 | data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; | |
1260 | reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); | |
1261 | /* Transmitter Slew Rate Control register (tx_reg1) */ | |
1262 | mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; | |
1263 | data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; | |
1264 | mask |= HPIPE_TX_REG1_SLC_EN_MASK; | |
1265 | data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; | |
1266 | reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); | |
1267 | /* Impedance Calibration Control register (cal_reg1) */ | |
1268 | mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; | |
1269 | data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; | |
1270 | mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; | |
1271 | data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; | |
1272 | reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); | |
1273 | /* Generation 1 Setting 5 (g1_setting_5) */ | |
1274 | mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; | |
1275 | data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; | |
1276 | reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); | |
1277 | /* 0xE-G1_Setting_1 */ | |
781ea0ab IL |
1278 | mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; |
1279 | data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; | |
1280 | if (speed == PHY_SPEED_5_15625G) { | |
1281 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; | |
1282 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; | |
1283 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; | |
1284 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; | |
1285 | } else { | |
1286 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; | |
1287 | data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; | |
1288 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; | |
1289 | data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; | |
1290 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; | |
1291 | data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; | |
1292 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; | |
1293 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; | |
1294 | mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; | |
1295 | data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; | |
1296 | } | |
c0132f60 | 1297 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); |
781ea0ab | 1298 | |
c0132f60 SR |
1299 | /* 0xA-DFE_Reg3 */ |
1300 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; | |
1301 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; | |
1302 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; | |
1303 | data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; | |
1304 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); | |
1305 | ||
1306 | /* 0x111-G1_Setting_4 */ | |
1307 | mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; | |
1308 | data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; | |
1309 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); | |
1310 | /* Genration 1 setting 3 (G1_Setting_3) */ | |
1311 | mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; | |
1312 | data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; | |
b617a0d7 IL |
1313 | if (speed == PHY_SPEED_5_15625G) { |
1314 | /* Force FFE (Feed Forward Equalization) to 5G */ | |
1315 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; | |
1316 | data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; | |
1317 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; | |
1318 | data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; | |
1319 | mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; | |
1320 | data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; | |
1321 | } | |
c0132f60 SR |
1322 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); |
1323 | ||
781ea0ab IL |
1324 | /* Connfigure RX training timer */ |
1325 | mask = HPIPE_RX_TRAIN_TIMER_MASK; | |
1326 | data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; | |
1327 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); | |
1328 | ||
1329 | /* Enable TX train peak to peak hold */ | |
1330 | mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; | |
1331 | data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; | |
1332 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); | |
1333 | ||
1334 | /* Configure TX preset index */ | |
1335 | mask = HPIPE_TX_PRESET_INDEX_MASK; | |
1336 | data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; | |
1337 | reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); | |
1338 | ||
1339 | /* Disable pattern lock lost timeout */ | |
1340 | mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; | |
1341 | data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; | |
1342 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); | |
1343 | ||
1344 | /* Configure TX training pattern and TX training 16bit auto */ | |
1345 | mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; | |
1346 | data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; | |
1347 | mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; | |
1348 | data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; | |
1349 | reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); | |
1350 | ||
1351 | /* Configure Training patten number */ | |
1352 | mask = HPIPE_TRAIN_PAT_NUM_MASK; | |
1353 | data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; | |
1354 | reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); | |
1355 | ||
1356 | /* Configure differencial manchester encoter to ethernet mode */ | |
1357 | mask = HPIPE_DME_ETHERNET_MODE_MASK; | |
1358 | data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; | |
1359 | reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); | |
1360 | ||
1361 | /* Configure VDD Continuous Calibration */ | |
1362 | mask = HPIPE_CAL_VDD_CONT_MODE_MASK; | |
1363 | data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; | |
1364 | reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); | |
1365 | ||
1366 | /* Trigger sampler enable pulse (by toggleing the bit) */ | |
1367 | mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; | |
1368 | data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; | |
1369 | mask |= HPIPE_SMAPLER_MASK; | |
1370 | data |= 0x1 << HPIPE_SMAPLER_OFFSET; | |
1371 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); | |
1372 | mask = HPIPE_SMAPLER_MASK; | |
1373 | data = 0x0 << HPIPE_SMAPLER_OFFSET; | |
1374 | reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); | |
1375 | ||
1376 | /* Set External RX Regulator Control */ | |
1377 | mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; | |
1378 | data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; | |
1379 | reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); | |
1380 | ||
c0132f60 SR |
1381 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); |
1382 | /* SERDES External Configuration */ | |
1383 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1384 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1385 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1386 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1387 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1388 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1389 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1390 | ||
1391 | ||
1392 | /* check PLL rx & tx ready */ | |
1393 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1394 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | | |
1395 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; | |
1396 | mask = data; | |
1397 | data = polling_with_timeout(addr, data, mask, 15000); | |
1398 | if (data != 0) { | |
1399 | debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1400 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
c0132f60 SR |
1401 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
1402 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); | |
1403 | ret = 0; | |
1404 | } | |
1405 | ||
1406 | /* RX init */ | |
1407 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; | |
1408 | data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; | |
1409 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1410 | ||
1411 | ||
1412 | /* check that RX init done */ | |
1413 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1414 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; | |
1415 | mask = data; | |
1416 | data = polling_with_timeout(addr, data, mask, 100); | |
1417 | if (data != 0) { | |
1418 | debug("Read from reg = %p - value = 0x%x\n", | |
1419 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1420 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
c0132f60 SR |
1421 | ret = 0; |
1422 | } | |
1423 | ||
1424 | debug("stage: RF Reset\n"); | |
1425 | /* RF Reset */ | |
1426 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; | |
1427 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; | |
1428 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1429 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1430 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1431 | ||
1432 | debug_exit(); | |
1433 | return ret; | |
1434 | } | |
1435 | ||
1436 | static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base, | |
1437 | void __iomem *comphy_base) | |
1438 | { | |
1439 | u32 mask, data, ret = 1; | |
1440 | void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); | |
1441 | void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane); | |
1442 | void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); | |
1443 | void __iomem *addr; | |
1444 | ||
1445 | debug_enter(); | |
1446 | debug("stage: RFU configurations - hard reset comphy\n"); | |
1447 | /* RFU configurations - hard reset comphy */ | |
1448 | mask = COMMON_PHY_CFG1_PWR_UP_MASK; | |
1449 | data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; | |
1450 | mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; | |
1451 | data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; | |
1452 | reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); | |
1453 | ||
1454 | if (lane == 2) { | |
1455 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
1456 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET, | |
1457 | COMMON_PHY_SD_CTRL1_RXAUI0_MASK); | |
1458 | } | |
1459 | if (lane == 4) { | |
1460 | reg_set(comphy_base + COMMON_PHY_SD_CTRL1, | |
1461 | 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET, | |
1462 | COMMON_PHY_SD_CTRL1_RXAUI1_MASK); | |
1463 | } | |
1464 | ||
1465 | /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */ | |
1466 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1467 | data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1468 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; | |
1469 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; | |
1470 | mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; | |
1471 | data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; | |
1472 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1473 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1474 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1475 | data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1476 | mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; | |
1477 | data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; | |
1478 | mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; | |
1479 | data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; | |
1480 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1481 | ||
1482 | /* release from hard reset */ | |
1483 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1484 | data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1485 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1486 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1487 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1488 | data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1489 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1490 | ||
1491 | mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; | |
1492 | data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; | |
1493 | mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; | |
1494 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; | |
1495 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1496 | ||
1497 | /* Wait 1ms - until band gap and ref clock ready */ | |
1498 | mdelay(1); | |
1499 | ||
1500 | /* Start comphy Configuration */ | |
1501 | debug("stage: Comphy configuration\n"); | |
1502 | /* set reference clock */ | |
1503 | reg_set(hpipe_addr + HPIPE_MISC_REG, | |
1504 | 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, | |
1505 | HPIPE_MISC_REFCLK_SEL_MASK); | |
1506 | /* Power and PLL Control */ | |
1507 | mask = HPIPE_PWR_PLL_REF_FREQ_MASK; | |
1508 | data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; | |
1509 | mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; | |
1510 | data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; | |
1511 | reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); | |
1512 | /* Loopback register */ | |
1513 | reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, | |
1514 | 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); | |
1515 | /* rx control 1 */ | |
1516 | mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; | |
1517 | data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; | |
1518 | mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; | |
1519 | data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; | |
1520 | reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); | |
1521 | /* DTL Control */ | |
1522 | reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, | |
1523 | 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, | |
1524 | HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); | |
1525 | ||
1526 | /* Set analog paramters from ETP(HW) */ | |
1527 | debug("stage: Analog paramters from ETP(HW)\n"); | |
1528 | /* SERDES External Configuration 2 */ | |
1529 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, | |
1530 | 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, | |
1531 | SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK); | |
1532 | /* 0x7-DFE Resolution control */ | |
1533 | reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET, | |
1534 | HPIPE_DFE_RES_FORCE_MASK); | |
1535 | /* 0xd-G1_Setting_0 */ | |
1536 | reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, | |
1537 | 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, | |
1538 | HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); | |
1539 | /* 0xE-G1_Setting_1 */ | |
1540 | mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; | |
1541 | data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; | |
1542 | mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; | |
1543 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; | |
1544 | mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; | |
1545 | data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; | |
1546 | reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); | |
1547 | /* 0xA-DFE_Reg3 */ | |
1548 | mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; | |
1549 | data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; | |
1550 | mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; | |
1551 | data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; | |
1552 | reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); | |
1553 | ||
1554 | /* 0x111-G1_Setting_4 */ | |
1555 | mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; | |
1556 | data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; | |
1557 | reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); | |
1558 | ||
1559 | debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); | |
1560 | /* SERDES External Configuration */ | |
1561 | mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; | |
1562 | data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; | |
1563 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; | |
1564 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; | |
1565 | mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; | |
1566 | data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; | |
1567 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); | |
1568 | ||
1569 | ||
1570 | /* check PLL rx & tx ready */ | |
1571 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1572 | data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | | |
1573 | SD_EXTERNAL_STATUS0_PLL_TX_MASK; | |
1574 | mask = data; | |
1575 | data = polling_with_timeout(addr, data, mask, 15000); | |
1576 | if (data != 0) { | |
1577 | debug("Read from reg = %p - value = 0x%x\n", | |
1578 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1579 | pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", |
c0132f60 SR |
1580 | (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), |
1581 | (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); | |
1582 | ret = 0; | |
1583 | } | |
1584 | ||
1585 | /* RX init */ | |
1586 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, | |
1587 | 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET, | |
1588 | SD_EXTERNAL_CONFIG1_RX_INIT_MASK); | |
1589 | ||
1590 | /* check that RX init done */ | |
1591 | addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; | |
1592 | data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; | |
1593 | mask = data; | |
1594 | data = polling_with_timeout(addr, data, mask, 100); | |
1595 | if (data != 0) { | |
1596 | debug("Read from reg = %p - value = 0x%x\n", | |
1597 | sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); | |
9b643e31 | 1598 | pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n"); |
c0132f60 SR |
1599 | ret = 0; |
1600 | } | |
1601 | ||
1602 | debug("stage: RF Reset\n"); | |
1603 | /* RF Reset */ | |
1604 | mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; | |
1605 | data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; | |
1606 | mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; | |
1607 | data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; | |
1608 | reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); | |
1609 | ||
1610 | debug_exit(); | |
1611 | return ret; | |
1612 | } | |
1613 | ||
1614 | static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, | |
1615 | void __iomem *usb_cfg_addr, | |
1616 | void __iomem *utmi_cfg_addr, | |
1617 | u32 utmi_phy_port) | |
1618 | { | |
1619 | u32 mask, data; | |
1620 | ||
1621 | debug_enter(); | |
1622 | debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", | |
1623 | utmi_index); | |
1624 | /* Power down UTMI PHY */ | |
1625 | reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET, | |
1626 | UTMI_PHY_CFG_PU_MASK); | |
1627 | ||
1628 | /* | |
1629 | * If UTMI connected to USB Device, configure mux prior to PHY init | |
1630 | * (Device can be connected to UTMI0 or to UTMI1) | |
1631 | */ | |
e89acc4b | 1632 | if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { |
c0132f60 SR |
1633 | debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", |
1634 | utmi_index); | |
1635 | /* USB3 Device UTMI enable */ | |
1636 | mask = UTMI_USB_CFG_DEVICE_EN_MASK; | |
1637 | data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; | |
1638 | /* USB3 Device UTMI MUX */ | |
1639 | mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; | |
1640 | data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; | |
1641 | reg_set(usb_cfg_addr, data, mask); | |
1642 | } | |
1643 | ||
1644 | /* Set Test suspendm mode */ | |
1645 | mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; | |
1646 | data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; | |
1647 | /* Enable Test UTMI select */ | |
1648 | mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; | |
1649 | data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; | |
1650 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); | |
1651 | ||
1652 | /* Wait for UTMI power down */ | |
1653 | mdelay(1); | |
1654 | ||
1655 | debug_exit(); | |
1656 | return; | |
1657 | } | |
1658 | ||
1659 | static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr, | |
1660 | void __iomem *usb_cfg_addr, | |
1661 | void __iomem *utmi_cfg_addr, | |
1662 | u32 utmi_phy_port) | |
1663 | { | |
1664 | u32 mask, data; | |
1665 | ||
1666 | debug_exit(); | |
1667 | debug("stage: Configure UTMI PHY %d registers\n", utmi_index); | |
1668 | /* Reference Clock Divider Select */ | |
1669 | mask = UTMI_PLL_CTRL_REFDIV_MASK; | |
1670 | data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; | |
1671 | /* Feedback Clock Divider Select - 90 for 25Mhz*/ | |
1672 | mask |= UTMI_PLL_CTRL_FBDIV_MASK; | |
1673 | data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; | |
1674 | /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ | |
1675 | mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; | |
1676 | data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; | |
1677 | reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); | |
1678 | ||
1679 | /* Impedance Calibration Threshold Setting */ | |
1680 | reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG, | |
1681 | 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, | |
1682 | UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); | |
1683 | ||
1684 | /* Set LS TX driver strength coarse control */ | |
1685 | mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; | |
1686 | data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; | |
1687 | /* Set LS TX driver fine adjustment */ | |
1688 | mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; | |
1689 | data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; | |
1690 | reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); | |
1691 | ||
1692 | /* Enable SQ */ | |
1693 | mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; | |
1694 | data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; | |
1695 | /* Enable analog squelch detect */ | |
1696 | mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; | |
1697 | data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; | |
1698 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); | |
1699 | ||
1700 | /* Set External squelch calibration number */ | |
1701 | mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; | |
1702 | data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; | |
1703 | /* Enable the External squelch calibration */ | |
1704 | mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; | |
1705 | data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; | |
1706 | reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); | |
1707 | ||
1708 | /* Set Control VDAT Reference Voltage - 0.325V */ | |
1709 | mask = UTMI_CHGDTC_CTRL_VDAT_MASK; | |
1710 | data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; | |
1711 | /* Set Control VSRC Reference Voltage - 0.6V */ | |
1712 | mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; | |
1713 | data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; | |
1714 | reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); | |
1715 | ||
1716 | debug_exit(); | |
1717 | return; | |
1718 | } | |
1719 | ||
1720 | static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr, | |
1721 | void __iomem *usb_cfg_addr, | |
1722 | void __iomem *utmi_cfg_addr, u32 utmi_phy_port) | |
1723 | { | |
1724 | u32 data, mask, ret = 1; | |
1725 | void __iomem *addr; | |
1726 | ||
1727 | debug_enter(); | |
1728 | debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", | |
1729 | utmi_index); | |
1730 | /* Power UP UTMI PHY */ | |
1731 | reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET, | |
1732 | UTMI_PHY_CFG_PU_MASK); | |
1733 | /* Disable Test UTMI select */ | |
1734 | reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, | |
1735 | 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET, | |
1736 | UTMI_CTRL_STATUS0_TEST_SEL_MASK); | |
1737 | ||
1738 | debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n"); | |
1739 | addr = utmi_base_addr + UTMI_CALIB_CTRL_REG; | |
1740 | data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; | |
1741 | mask = data; | |
1742 | data = polling_with_timeout(addr, data, mask, 100); | |
1743 | if (data != 0) { | |
9b643e31 | 1744 | pr_err("Impedance calibration is not done\n"); |
c0132f60 SR |
1745 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
1746 | ret = 0; | |
1747 | } | |
1748 | ||
1749 | data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; | |
1750 | mask = data; | |
1751 | data = polling_with_timeout(addr, data, mask, 100); | |
1752 | if (data != 0) { | |
9b643e31 | 1753 | pr_err("PLL calibration is not done\n"); |
c0132f60 SR |
1754 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
1755 | ret = 0; | |
1756 | } | |
1757 | ||
1758 | addr = utmi_base_addr + UTMI_PLL_CTRL_REG; | |
1759 | data = UTMI_PLL_CTRL_PLL_RDY_MASK; | |
1760 | mask = data; | |
1761 | data = polling_with_timeout(addr, data, mask, 100); | |
1762 | if (data != 0) { | |
9b643e31 | 1763 | pr_err("PLL is not ready\n"); |
c0132f60 SR |
1764 | debug("Read from reg = %p - value = 0x%x\n", addr, data); |
1765 | ret = 0; | |
1766 | } | |
1767 | ||
1768 | if (ret) | |
1769 | debug("Passed\n"); | |
1770 | else | |
1771 | debug("\n"); | |
1772 | ||
1773 | debug_exit(); | |
1774 | return ret; | |
1775 | } | |
1776 | ||
1777 | /* | |
1778 | * comphy_utmi_phy_init initialize the UTMI PHY | |
1779 | * the init split in 3 parts: | |
1780 | * 1. Power down transceiver and PLL | |
1781 | * 2. UTMI PHY configure | |
1782 | * 3. Powe up transceiver and PLL | |
1783 | * Note: - Power down/up should be once for both UTMI PHYs | |
1784 | * - comphy_dedicated_phys_init call this function if at least there is | |
1785 | * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is | |
1786 | * legal | |
1787 | */ | |
1788 | static void comphy_utmi_phy_init(u32 utmi_phy_count, | |
1789 | struct utmi_phy_data *cp110_utmi_data) | |
1790 | { | |
1791 | u32 i; | |
1792 | ||
1793 | debug_enter(); | |
1794 | /* UTMI Power down */ | |
1795 | for (i = 0; i < utmi_phy_count; i++) { | |
1796 | comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr, | |
1797 | cp110_utmi_data[i].usb_cfg_addr, | |
1798 | cp110_utmi_data[i].utmi_cfg_addr, | |
1799 | cp110_utmi_data[i].utmi_phy_port); | |
1800 | } | |
1801 | /* PLL Power down */ | |
1802 | debug("stage: UTMI PHY power down PLL\n"); | |
1803 | for (i = 0; i < utmi_phy_count; i++) { | |
1804 | reg_set(cp110_utmi_data[i].usb_cfg_addr, | |
1805 | 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); | |
1806 | } | |
1807 | /* UTMI configure */ | |
1808 | for (i = 0; i < utmi_phy_count; i++) { | |
1809 | comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr, | |
1810 | cp110_utmi_data[i].usb_cfg_addr, | |
1811 | cp110_utmi_data[i].utmi_cfg_addr, | |
1812 | cp110_utmi_data[i].utmi_phy_port); | |
1813 | } | |
1814 | /* UTMI Power up */ | |
1815 | for (i = 0; i < utmi_phy_count; i++) { | |
1816 | if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr, | |
1817 | cp110_utmi_data[i].usb_cfg_addr, | |
1818 | cp110_utmi_data[i].utmi_cfg_addr, | |
1819 | cp110_utmi_data[i].utmi_phy_port)) { | |
9b643e31 | 1820 | pr_err("Failed to initialize UTMI PHY %d\n", i); |
c0132f60 SR |
1821 | continue; |
1822 | } | |
1823 | printf("UTMI PHY %d initialized to ", i); | |
e89acc4b SR |
1824 | if (cp110_utmi_data[i].utmi_phy_port == |
1825 | UTMI_PHY_TO_USB3_DEVICE0) | |
c0132f60 SR |
1826 | printf("USB Device\n"); |
1827 | else | |
1828 | printf("USB Host%d\n", | |
1829 | cp110_utmi_data[i].utmi_phy_port); | |
1830 | } | |
1831 | /* PLL Power up */ | |
1832 | debug("stage: UTMI PHY power up PLL\n"); | |
1833 | for (i = 0; i < utmi_phy_count; i++) { | |
1834 | reg_set(cp110_utmi_data[i].usb_cfg_addr, | |
1835 | 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK); | |
1836 | } | |
1837 | ||
1838 | debug_exit(); | |
1839 | return; | |
1840 | } | |
1841 | ||
1842 | /* | |
1843 | * comphy_dedicated_phys_init initialize the dedicated PHYs | |
1844 | * - not muxed SerDes lanes e.g. UTMI PHY | |
1845 | */ | |
1846 | void comphy_dedicated_phys_init(void) | |
1847 | { | |
1848 | struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT]; | |
1849 | int node; | |
1850 | int i; | |
1851 | ||
1852 | debug_enter(); | |
1853 | debug("Initialize USB UTMI PHYs\n"); | |
1854 | ||
1855 | /* Find the UTMI phy node in device tree and go over them */ | |
1856 | node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, | |
1857 | "marvell,mvebu-utmi-2.6.0"); | |
1858 | ||
1859 | i = 0; | |
1860 | while (node > 0) { | |
1861 | /* get base address of UTMI phy */ | |
1862 | cp110_utmi_data[i].utmi_base_addr = | |
1863 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( | |
1864 | gd->fdt_blob, node, "reg", 0, NULL, true); | |
1865 | if (cp110_utmi_data[i].utmi_base_addr == NULL) { | |
9b643e31 | 1866 | pr_err("UTMI PHY base address is invalid\n"); |
c0132f60 SR |
1867 | i++; |
1868 | continue; | |
1869 | } | |
1870 | ||
1871 | /* get usb config address */ | |
1872 | cp110_utmi_data[i].usb_cfg_addr = | |
1873 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( | |
1874 | gd->fdt_blob, node, "reg", 1, NULL, true); | |
1875 | if (cp110_utmi_data[i].usb_cfg_addr == NULL) { | |
9b643e31 | 1876 | pr_err("UTMI PHY base address is invalid\n"); |
c0132f60 SR |
1877 | i++; |
1878 | continue; | |
1879 | } | |
1880 | ||
1881 | /* get UTMI config address */ | |
1882 | cp110_utmi_data[i].utmi_cfg_addr = | |
1883 | (void __iomem *)fdtdec_get_addr_size_auto_noparent( | |
1884 | gd->fdt_blob, node, "reg", 2, NULL, true); | |
1885 | if (cp110_utmi_data[i].utmi_cfg_addr == NULL) { | |
9b643e31 | 1886 | pr_err("UTMI PHY base address is invalid\n"); |
c0132f60 SR |
1887 | i++; |
1888 | continue; | |
1889 | } | |
1890 | ||
1891 | /* | |
1892 | * get the port number (to check if the utmi connected to | |
1893 | * host/device) | |
1894 | */ | |
1895 | cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int( | |
1896 | gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); | |
1897 | if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) { | |
9b643e31 | 1898 | pr_err("UTMI PHY port type is invalid\n"); |
c0132f60 SR |
1899 | i++; |
1900 | continue; | |
1901 | } | |
1902 | ||
1903 | node = fdt_node_offset_by_compatible( | |
1904 | gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); | |
1905 | i++; | |
1906 | } | |
1907 | ||
1908 | if (i > 0) | |
1909 | comphy_utmi_phy_init(i, cp110_utmi_data); | |
1910 | ||
1911 | debug_exit(); | |
1912 | } | |
1913 | ||
1914 | static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, | |
1915 | struct comphy_map *serdes_map) | |
1916 | { | |
1917 | void __iomem *comphy_base_addr; | |
1918 | struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS]; | |
1919 | struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS]; | |
1920 | u32 lane, comphy_max_count; | |
1921 | ||
1922 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; | |
1923 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; | |
1924 | ||
1925 | /* | |
1926 | * Copy the SerDes map configuration for PIPE map and PHY map | |
1927 | * the comphy_mux_init modify the type of the lane if the type | |
1928 | * is not valid because we have 2 selectores run the | |
1929 | * comphy_mux_init twice and after that update the original | |
1930 | * serdes_map | |
1931 | */ | |
1932 | for (lane = 0; lane < comphy_max_count; lane++) { | |
1933 | comphy_map_pipe_data[lane].type = serdes_map[lane].type; | |
1934 | comphy_map_pipe_data[lane].speed = serdes_map[lane].speed; | |
1935 | comphy_map_phy_data[lane].type = serdes_map[lane].type; | |
1936 | comphy_map_phy_data[lane].speed = serdes_map[lane].speed; | |
1937 | } | |
1938 | ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; | |
1939 | comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data, | |
1940 | comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET); | |
1941 | ||
1942 | ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; | |
1943 | comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data, | |
1944 | comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); | |
1945 | /* Fix the type after check the PHY and PIPE configuration */ | |
1946 | for (lane = 0; lane < comphy_max_count; lane++) { | |
1947 | if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && | |
1948 | (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) | |
1949 | serdes_map[lane].type = PHY_TYPE_UNCONNECTED; | |
1950 | } | |
1951 | } | |
1952 | ||
1953 | int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, | |
1954 | struct comphy_map *serdes_map) | |
1955 | { | |
1956 | struct comphy_map *ptr_comphy_map; | |
1957 | void __iomem *comphy_base_addr, *hpipe_base_addr; | |
1958 | u32 comphy_max_count, lane, ret = 0; | |
1959 | u32 pcie_width = 0; | |
1960 | ||
1961 | debug_enter(); | |
1962 | ||
1963 | comphy_max_count = ptr_chip_cfg->comphy_lanes_count; | |
1964 | comphy_base_addr = ptr_chip_cfg->comphy_base_addr; | |
1965 | hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; | |
1966 | ||
1967 | /* Config Comphy mux configuration */ | |
1968 | comphy_mux_cp110_init(ptr_chip_cfg, serdes_map); | |
1969 | ||
1970 | /* Check if the first 4 lanes configured as By-4 */ | |
1971 | for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; | |
1972 | lane++, ptr_comphy_map++) { | |
1973 | if (ptr_comphy_map->type != PHY_TYPE_PEX0) | |
1974 | break; | |
1975 | pcie_width++; | |
1976 | } | |
1977 | ||
1978 | for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count; | |
1979 | lane++, ptr_comphy_map++) { | |
1980 | debug("Initialize serdes number %d\n", lane); | |
1981 | debug("Serdes type = 0x%x\n", ptr_comphy_map->type); | |
1982 | if (lane == 4) { | |
1983 | /* | |
1984 | * PCIe lanes above the first 4 lanes, can be only | |
1985 | * by1 | |
1986 | */ | |
1987 | pcie_width = 1; | |
1988 | } | |
1989 | switch (ptr_comphy_map->type) { | |
1990 | case PHY_TYPE_UNCONNECTED: | |
6ecc0b1c | 1991 | case PHY_TYPE_IGNORE: |
c0132f60 SR |
1992 | continue; |
1993 | break; | |
1994 | case PHY_TYPE_PEX0: | |
1995 | case PHY_TYPE_PEX1: | |
1996 | case PHY_TYPE_PEX2: | |
1997 | case PHY_TYPE_PEX3: | |
1998 | ret = comphy_pcie_power_up( | |
1999 | lane, pcie_width, ptr_comphy_map->clk_src, | |
7dda98e0 | 2000 | serdes_map->end_point, |
c0132f60 SR |
2001 | hpipe_base_addr, comphy_base_addr); |
2002 | break; | |
2003 | case PHY_TYPE_SATA0: | |
2004 | case PHY_TYPE_SATA1: | |
2005 | case PHY_TYPE_SATA2: | |
2006 | case PHY_TYPE_SATA3: | |
2007 | ret = comphy_sata_power_up( | |
2008 | lane, hpipe_base_addr, comphy_base_addr, | |
528213d3 | 2009 | ptr_chip_cfg->cp_index); |
c0132f60 SR |
2010 | break; |
2011 | case PHY_TYPE_USB3_HOST0: | |
2012 | case PHY_TYPE_USB3_HOST1: | |
2013 | case PHY_TYPE_USB3_DEVICE: | |
2014 | ret = comphy_usb3_power_up(lane, hpipe_base_addr, | |
2015 | comphy_base_addr); | |
2016 | break; | |
2017 | case PHY_TYPE_SGMII0: | |
2018 | case PHY_TYPE_SGMII1: | |
2019 | case PHY_TYPE_SGMII2: | |
2020 | case PHY_TYPE_SGMII3: | |
2021 | if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { | |
2022 | debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", | |
2023 | lane); | |
2024 | ptr_comphy_map->speed = PHY_SPEED_1_25G; | |
2025 | } | |
2026 | ret = comphy_sgmii_power_up( | |
2027 | lane, ptr_comphy_map->speed, hpipe_base_addr, | |
2028 | comphy_base_addr); | |
2029 | break; | |
cb686454 SR |
2030 | case PHY_TYPE_SFI: |
2031 | ret = comphy_sfi_power_up(lane, hpipe_base_addr, | |
b617a0d7 IL |
2032 | comphy_base_addr, |
2033 | ptr_comphy_map->speed); | |
c0132f60 SR |
2034 | break; |
2035 | case PHY_TYPE_RXAUI0: | |
2036 | case PHY_TYPE_RXAUI1: | |
2037 | ret = comphy_rxauii_power_up(lane, hpipe_base_addr, | |
2038 | comphy_base_addr); | |
2039 | break; | |
2040 | default: | |
2041 | debug("Unknown SerDes type, skip initialize SerDes %d\n", | |
2042 | lane); | |
2043 | break; | |
2044 | } | |
2045 | if (ret == 0) { | |
2046 | /* | |
d37f020e | 2047 | * If interface wans't initialized, set the lane to |
c0132f60 SR |
2048 | * PHY_TYPE_UNCONNECTED state. |
2049 | */ | |
2050 | ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; | |
9b643e31 | 2051 | pr_err("PLL is not locked - Failed to initialize lane %d\n", |
c0132f60 SR |
2052 | lane); |
2053 | } | |
2054 | } | |
2055 | ||
2056 | debug_exit(); | |
2057 | return 0; | |
2058 | } |