]>
Commit | Line | Data |
---|---|---|
c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
57f6ce07 | 2 | /* |
a70143bb | 3 | * phy-ti-pipe3 - PIPE3 PHY driver. |
57f6ce07 KVA |
4 | * |
5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
57f6ce07 | 6 | * Author: Kishon Vijay Abraham I <kishon@ti.com> |
57f6ce07 KVA |
7 | */ |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/slab.h> | |
a70143bb | 12 | #include <linux/phy/phy.h> |
57f6ce07 KVA |
13 | #include <linux/of.h> |
14 | #include <linux/clk.h> | |
15 | #include <linux/err.h> | |
a70143bb | 16 | #include <linux/io.h> |
57f6ce07 KVA |
17 | #include <linux/pm_runtime.h> |
18 | #include <linux/delay.h> | |
14da699b | 19 | #include <linux/phy/omap_control_phy.h> |
918ee0d2 | 20 | #include <linux/of_platform.h> |
c934b361 RQ |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/regmap.h> | |
57f6ce07 | 23 | |
57f6ce07 KVA |
24 | #define PLL_STATUS 0x00000004 |
25 | #define PLL_GO 0x00000008 | |
26 | #define PLL_CONFIGURATION1 0x0000000C | |
27 | #define PLL_CONFIGURATION2 0x00000010 | |
28 | #define PLL_CONFIGURATION3 0x00000014 | |
29 | #define PLL_CONFIGURATION4 0x00000020 | |
30 | ||
31 | #define PLL_REGM_MASK 0x001FFE00 | |
32 | #define PLL_REGM_SHIFT 0x9 | |
33 | #define PLL_REGM_F_MASK 0x0003FFFF | |
34 | #define PLL_REGM_F_SHIFT 0x0 | |
35 | #define PLL_REGN_MASK 0x000001FE | |
36 | #define PLL_REGN_SHIFT 0x1 | |
37 | #define PLL_SELFREQDCO_MASK 0x0000000E | |
38 | #define PLL_SELFREQDCO_SHIFT 0x1 | |
39 | #define PLL_SD_MASK 0x0003FC00 | |
1562864f | 40 | #define PLL_SD_SHIFT 10 |
57f6ce07 | 41 | #define SET_PLL_GO 0x1 |
629138db RQ |
42 | #define PLL_LDOPWDN BIT(15) |
43 | #define PLL_TICOPWDN BIT(16) | |
57f6ce07 KVA |
44 | #define PLL_LOCK 0x2 |
45 | #define PLL_IDLE 0x1 | |
46 | ||
c934b361 RQ |
47 | #define SATA_PLL_SOFT_RESET BIT(18) |
48 | ||
9d009d9c | 49 | #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14) |
c396a1c7 KVA |
50 | #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 |
51 | ||
9d009d9c | 52 | #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22) |
c396a1c7 KVA |
53 | #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 |
54 | ||
9d009d9c RQ |
55 | #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) |
56 | #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) | |
c396a1c7 | 57 | |
3f2362c5 KVA |
58 | #define PCIE_PCS_MASK 0xFF0000 |
59 | #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 | |
60 | ||
fdef2f9f | 61 | #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C |
2796ceb0 KVA |
62 | #define INTERFACE_MASK GENMASK(31, 27) |
63 | #define INTERFACE_SHIFT 27 | |
fdef2f9f RQ |
64 | #define INTERFACE_MODE_USBSS BIT(4) |
65 | #define INTERFACE_MODE_SATA_1P5 BIT(3) | |
66 | #define INTERFACE_MODE_SATA_3P0 BIT(2) | |
67 | #define INTERFACE_MODE_PCIE BIT(0) | |
68 | ||
2796ceb0 KVA |
69 | #define LOSD_MASK GENMASK(17, 14) |
70 | #define LOSD_SHIFT 14 | |
71 | #define MEM_PLLDIV GENMASK(6, 5) | |
72 | ||
fdef2f9f RQ |
73 | #define PIPE3_PHY_RX_TRIM 0x0000001C |
74 | #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30) | |
2796ceb0 KVA |
75 | #define MEM_DLL_TRIM_SHIFT 30 |
76 | ||
fdef2f9f RQ |
77 | #define PIPE3_PHY_RX_DLL 0x00000024 |
78 | #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30) | |
79 | #define MEM_DLL_PHINT_RATE_SHIFT 30 | |
2796ceb0 | 80 | |
fdef2f9f RQ |
81 | #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028 |
82 | #define MEM_HS_RATE_MASK GENMASK(28, 27) | |
83 | #define MEM_HS_RATE_SHIFT 27 | |
84 | #define MEM_OVRD_HS_RATE BIT(26) | |
85 | #define MEM_OVRD_HS_RATE_SHIFT 26 | |
2796ceb0 | 86 | #define MEM_CDR_FASTLOCK BIT(23) |
fdef2f9f RQ |
87 | #define MEM_CDR_FASTLOCK_SHIFT 23 |
88 | #define MEM_CDR_LBW_MASK GENMASK(22, 21) | |
89 | #define MEM_CDR_LBW_SHIFT 21 | |
90 | #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19) | |
91 | #define MEM_CDR_STEPCNT_SHIFT 19 | |
2796ceb0 KVA |
92 | #define MEM_CDR_STL_MASK GENMASK(18, 16) |
93 | #define MEM_CDR_STL_SHIFT 16 | |
94 | #define MEM_CDR_THR_MASK GENMASK(15, 13) | |
95 | #define MEM_CDR_THR_SHIFT 13 | |
96 | #define MEM_CDR_THR_MODE BIT(12) | |
fdef2f9f RQ |
97 | #define MEM_CDR_THR_MODE_SHIFT 12 |
98 | #define MEM_CDR_2NDO_SDM_MODE BIT(11) | |
99 | #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11 | |
100 | ||
101 | #define PIPE3_PHY_RX_EQUALIZER 0x00000038 | |
102 | #define MEM_EQLEV_MASK GENMASK(31, 16) | |
103 | #define MEM_EQLEV_SHIFT 16 | |
104 | #define MEM_EQFTC_MASK GENMASK(15, 11) | |
105 | #define MEM_EQFTC_SHIFT 11 | |
106 | #define MEM_EQCTL_MASK GENMASK(10, 7) | |
2796ceb0 KVA |
107 | #define MEM_EQCTL_SHIFT 7 |
108 | #define MEM_OVRD_EQLEV BIT(2) | |
fdef2f9f | 109 | #define MEM_OVRD_EQLEV_SHIFT 2 |
2796ceb0 | 110 | #define MEM_OVRD_EQFTC BIT(1) |
fdef2f9f RQ |
111 | #define MEM_OVRD_EQFTC_SHIFT 1 |
112 | ||
113 | #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44 | |
114 | #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) | |
115 | #define MEM_CDR_LOS_SOURCE_SHIFT 9 | |
2796ceb0 | 116 | |
57f6ce07 KVA |
117 | /* |
118 | * This is an Empirical value that works, need to confirm the actual | |
a70143bb KVA |
119 | * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status |
120 | * to be correctly reflected in the PIPE3PHY_PLL_STATUS register. | |
57f6ce07 | 121 | */ |
629138db RQ |
122 | #define PLL_IDLE_TIME 100 /* in milliseconds */ |
123 | #define PLL_LOCK_TIME 100 /* in milliseconds */ | |
57f6ce07 | 124 | |
22940823 RQ |
125 | enum pipe3_mode { PIPE3_MODE_PCIE = 1, |
126 | PIPE3_MODE_SATA, | |
127 | PIPE3_MODE_USBSS }; | |
128 | ||
a70143bb KVA |
129 | struct pipe3_dpll_params { |
130 | u16 m; | |
131 | u8 n; | |
132 | u8 freq:3; | |
133 | u8 sd; | |
134 | u32 mf; | |
135 | }; | |
136 | ||
61f54674 RQ |
137 | struct pipe3_dpll_map { |
138 | unsigned long rate; | |
139 | struct pipe3_dpll_params params; | |
140 | }; | |
141 | ||
fdef2f9f RQ |
142 | struct pipe3_settings { |
143 | u8 ana_interface; | |
144 | u8 ana_losd; | |
145 | u8 dig_fastlock; | |
146 | u8 dig_lbw; | |
147 | u8 dig_stepcnt; | |
148 | u8 dig_stl; | |
149 | u8 dig_thr; | |
150 | u8 dig_thr_mode; | |
151 | u8 dig_2ndo_sdm_mode; | |
152 | u8 dig_hs_rate; | |
153 | u8 dig_ovrd_hs_rate; | |
154 | u8 dll_trim_sel; | |
155 | u8 dll_phint_rate; | |
156 | u8 eq_lev; | |
157 | u8 eq_ftc; | |
158 | u8 eq_ctl; | |
159 | u8 eq_ovrd_lev; | |
160 | u8 eq_ovrd_ftc; | |
161 | }; | |
162 | ||
a70143bb KVA |
163 | struct ti_pipe3 { |
164 | void __iomem *pll_ctrl_base; | |
2796ceb0 KVA |
165 | void __iomem *phy_rx; |
166 | void __iomem *phy_tx; | |
a70143bb KVA |
167 | struct device *dev; |
168 | struct device *control_dev; | |
169 | struct clk *wkupclk; | |
170 | struct clk *sys_clk; | |
1562864f | 171 | struct clk *refclk; |
99bbd48c | 172 | struct clk *div_clk; |
61f54674 | 173 | struct pipe3_dpll_map *dpll_map; |
c396a1c7 | 174 | struct regmap *phy_power_syscon; /* ctrl. reg. acces */ |
3f2362c5 | 175 | struct regmap *pcs_syscon; /* ctrl. reg. acces */ |
c934b361 RQ |
176 | struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */ |
177 | unsigned int dpll_reset_reg; /* reg. index within syscon */ | |
c396a1c7 | 178 | unsigned int power_reg; /* power reg. index within syscon */ |
3f2362c5 | 179 | unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ |
c934b361 | 180 | bool sata_refclk_enabled; |
22940823 | 181 | enum pipe3_mode mode; |
fdef2f9f | 182 | struct pipe3_settings settings; |
a70143bb KVA |
183 | }; |
184 | ||
61f54674 | 185 | static struct pipe3_dpll_map dpll_map_usb[] = { |
519c6013 RQ |
186 | {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ |
187 | {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ | |
188 | {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ | |
189 | {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ | |
190 | {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ | |
191 | {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ | |
61f54674 RQ |
192 | { }, /* Terminator */ |
193 | }; | |
194 | ||
195 | static struct pipe3_dpll_map dpll_map_sata[] = { | |
325ce0fe RQ |
196 | {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */ |
197 | {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */ | |
61f54674 | 198 | {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ |
325ce0fe RQ |
199 | {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */ |
200 | {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */ | |
201 | {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */ | |
61f54674 | 202 | { }, /* Terminator */ |
57f6ce07 KVA |
203 | }; |
204 | ||
22940823 RQ |
205 | struct pipe3_data { |
206 | enum pipe3_mode mode; | |
207 | struct pipe3_dpll_map *dpll_map; | |
fdef2f9f | 208 | struct pipe3_settings settings; |
22940823 RQ |
209 | }; |
210 | ||
211 | static struct pipe3_data data_usb = { | |
212 | .mode = PIPE3_MODE_USBSS, | |
213 | .dpll_map = dpll_map_usb, | |
fdef2f9f RQ |
214 | .settings = { |
215 | /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */ | |
216 | .ana_interface = INTERFACE_MODE_USBSS, | |
217 | .ana_losd = 0xa, | |
218 | .dig_fastlock = 1, | |
219 | .dig_lbw = 3, | |
220 | .dig_stepcnt = 0, | |
221 | .dig_stl = 0x3, | |
222 | .dig_thr = 1, | |
223 | .dig_thr_mode = 1, | |
224 | .dig_2ndo_sdm_mode = 0, | |
225 | .dig_hs_rate = 0, | |
226 | .dig_ovrd_hs_rate = 1, | |
227 | .dll_trim_sel = 0x2, | |
228 | .dll_phint_rate = 0x3, | |
229 | .eq_lev = 0, | |
230 | .eq_ftc = 0, | |
231 | .eq_ctl = 0x9, | |
232 | .eq_ovrd_lev = 0, | |
233 | .eq_ovrd_ftc = 0, | |
234 | }, | |
22940823 RQ |
235 | }; |
236 | ||
237 | static struct pipe3_data data_sata = { | |
238 | .mode = PIPE3_MODE_SATA, | |
239 | .dpll_map = dpll_map_sata, | |
fdef2f9f RQ |
240 | .settings = { |
241 | /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */ | |
242 | .ana_interface = INTERFACE_MODE_SATA_3P0, | |
243 | .ana_losd = 0x5, | |
244 | .dig_fastlock = 1, | |
245 | .dig_lbw = 3, | |
246 | .dig_stepcnt = 0, | |
247 | .dig_stl = 0x3, | |
248 | .dig_thr = 1, | |
249 | .dig_thr_mode = 1, | |
250 | .dig_2ndo_sdm_mode = 0, | |
251 | .dig_hs_rate = 0, /* Not in TRM preferred settings */ | |
252 | .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */ | |
253 | .dll_trim_sel = 0x1, | |
254 | .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */ | |
255 | .eq_lev = 0, | |
256 | .eq_ftc = 0x1f, | |
257 | .eq_ctl = 0, | |
258 | .eq_ovrd_lev = 1, | |
259 | .eq_ovrd_ftc = 1, | |
260 | }, | |
22940823 RQ |
261 | }; |
262 | ||
263 | static struct pipe3_data data_pcie = { | |
264 | .mode = PIPE3_MODE_PCIE, | |
fdef2f9f RQ |
265 | .settings = { |
266 | /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */ | |
267 | .ana_interface = INTERFACE_MODE_PCIE, | |
268 | .ana_losd = 0xa, | |
269 | .dig_fastlock = 1, | |
270 | .dig_lbw = 3, | |
271 | .dig_stepcnt = 0, | |
272 | .dig_stl = 0x3, | |
273 | .dig_thr = 1, | |
274 | .dig_thr_mode = 1, | |
275 | .dig_2ndo_sdm_mode = 0, | |
276 | .dig_hs_rate = 0, | |
277 | .dig_ovrd_hs_rate = 0, | |
278 | .dll_trim_sel = 0x2, | |
279 | .dll_phint_rate = 0x3, | |
280 | .eq_lev = 0, | |
281 | .eq_ftc = 0x1f, | |
282 | .eq_ctl = 1, | |
283 | .eq_ovrd_lev = 0, | |
284 | .eq_ovrd_ftc = 0, | |
285 | }, | |
22940823 RQ |
286 | }; |
287 | ||
a70143bb KVA |
288 | static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) |
289 | { | |
290 | return __raw_readl(addr + offset); | |
291 | } | |
292 | ||
293 | static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset, | |
294 | u32 data) | |
295 | { | |
296 | __raw_writel(data, addr + offset); | |
297 | } | |
298 | ||
61f54674 | 299 | static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) |
519c6013 | 300 | { |
61f54674 RQ |
301 | unsigned long rate; |
302 | struct pipe3_dpll_map *dpll_map = phy->dpll_map; | |
519c6013 | 303 | |
61f54674 RQ |
304 | rate = clk_get_rate(phy->sys_clk); |
305 | ||
306 | for (; dpll_map->rate; dpll_map++) { | |
307 | if (rate == dpll_map->rate) | |
308 | return &dpll_map->params; | |
519c6013 RQ |
309 | } |
310 | ||
61f54674 RQ |
311 | dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); |
312 | ||
1b97be8c | 313 | return NULL; |
519c6013 RQ |
314 | } |
315 | ||
0a0830fe RQ |
316 | static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy); |
317 | static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); | |
318 | ||
a70143bb KVA |
319 | static int ti_pipe3_power_off(struct phy *x) |
320 | { | |
c396a1c7 | 321 | int ret; |
a70143bb | 322 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
a70143bb | 323 | |
c396a1c7 KVA |
324 | if (!phy->phy_power_syscon) { |
325 | omap_control_phy_power(phy->control_dev, 0); | |
326 | return 0; | |
327 | } | |
a70143bb | 328 | |
c396a1c7 | 329 | ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
9d009d9c | 330 | PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0); |
c396a1c7 | 331 | return ret; |
a70143bb KVA |
332 | } |
333 | ||
1d1bae72 RQ |
334 | static void ti_pipe3_calibrate(struct ti_pipe3 *phy); |
335 | ||
a70143bb | 336 | static int ti_pipe3_power_on(struct phy *x) |
57f6ce07 | 337 | { |
c396a1c7 KVA |
338 | u32 val; |
339 | u32 mask; | |
340 | int ret; | |
341 | unsigned long rate; | |
a70143bb | 342 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
9d009d9c | 343 | bool rx_pending = false; |
57f6ce07 | 344 | |
c396a1c7 KVA |
345 | if (!phy->phy_power_syscon) { |
346 | omap_control_phy_power(phy->control_dev, 1); | |
347 | return 0; | |
348 | } | |
57f6ce07 | 349 | |
c396a1c7 KVA |
350 | rate = clk_get_rate(phy->sys_clk); |
351 | if (!rate) { | |
352 | dev_err(phy->dev, "Invalid clock rate\n"); | |
353 | return -EINVAL; | |
354 | } | |
355 | rate = rate / 1000000; | |
9d009d9c RQ |
356 | mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; |
357 | val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; | |
c396a1c7 KVA |
358 | ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, |
359 | mask, val); | |
9d009d9c RQ |
360 | /* |
361 | * For PCIe, TX and RX must be powered on simultaneously. | |
362 | * For USB and SATA, TX must be powered on before RX | |
363 | */ | |
364 | mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; | |
365 | if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { | |
366 | val = PIPE3_PHY_TX_POWERON; | |
367 | rx_pending = true; | |
368 | } else { | |
369 | val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; | |
370 | } | |
371 | ||
372 | regmap_update_bits(phy->phy_power_syscon, phy->power_reg, | |
373 | mask, val); | |
374 | ||
375 | if (rx_pending) { | |
376 | val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; | |
377 | regmap_update_bits(phy->phy_power_syscon, phy->power_reg, | |
378 | mask, val); | |
379 | } | |
380 | ||
1d1bae72 RQ |
381 | if (phy->mode == PIPE3_MODE_PCIE) |
382 | ti_pipe3_calibrate(phy); | |
383 | ||
9d009d9c | 384 | return 0; |
57f6ce07 KVA |
385 | } |
386 | ||
629138db | 387 | static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) |
57f6ce07 KVA |
388 | { |
389 | u32 val; | |
390 | unsigned long timeout; | |
391 | ||
629138db | 392 | timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME); |
57f6ce07 | 393 | do { |
629138db | 394 | cpu_relax(); |
a70143bb | 395 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
57f6ce07 | 396 | if (val & PLL_LOCK) |
a5e5d3c0 | 397 | return 0; |
629138db RQ |
398 | } while (!time_after(jiffies, timeout)); |
399 | ||
a5e5d3c0 AL |
400 | dev_err(phy->dev, "DPLL failed to lock\n"); |
401 | return -EBUSY; | |
57f6ce07 KVA |
402 | } |
403 | ||
629138db | 404 | static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) |
57f6ce07 KVA |
405 | { |
406 | u32 val; | |
a70143bb | 407 | struct pipe3_dpll_params *dpll_params; |
57f6ce07 | 408 | |
61f54674 RQ |
409 | dpll_params = ti_pipe3_get_dpll_params(phy); |
410 | if (!dpll_params) | |
57f6ce07 | 411 | return -EINVAL; |
57f6ce07 | 412 | |
a70143bb | 413 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 414 | val &= ~PLL_REGN_MASK; |
519c6013 | 415 | val |= dpll_params->n << PLL_REGN_SHIFT; |
a70143bb | 416 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 417 | |
a70143bb | 418 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); |
57f6ce07 | 419 | val &= ~PLL_SELFREQDCO_MASK; |
519c6013 | 420 | val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; |
a70143bb | 421 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); |
57f6ce07 | 422 | |
a70143bb | 423 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); |
57f6ce07 | 424 | val &= ~PLL_REGM_MASK; |
519c6013 | 425 | val |= dpll_params->m << PLL_REGM_SHIFT; |
a70143bb | 426 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); |
57f6ce07 | 427 | |
a70143bb | 428 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); |
57f6ce07 | 429 | val &= ~PLL_REGM_F_MASK; |
519c6013 | 430 | val |= dpll_params->mf << PLL_REGM_F_SHIFT; |
a70143bb | 431 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); |
57f6ce07 | 432 | |
a70143bb | 433 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); |
57f6ce07 | 434 | val &= ~PLL_SD_MASK; |
519c6013 | 435 | val |= dpll_params->sd << PLL_SD_SHIFT; |
a70143bb | 436 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); |
57f6ce07 | 437 | |
629138db | 438 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); |
57f6ce07 | 439 | |
629138db | 440 | return ti_pipe3_dpll_wait_lock(phy); |
57f6ce07 KVA |
441 | } |
442 | ||
2796ceb0 KVA |
443 | static void ti_pipe3_calibrate(struct ti_pipe3 *phy) |
444 | { | |
445 | u32 val; | |
fdef2f9f | 446 | struct pipe3_settings *s = &phy->settings; |
2796ceb0 | 447 | |
fdef2f9f | 448 | val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); |
2796ceb0 | 449 | val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); |
fdef2f9f RQ |
450 | val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); |
451 | ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); | |
452 | ||
453 | val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); | |
454 | val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | | |
455 | MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK | | |
456 | MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE); | |
457 | val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | | |
458 | s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | | |
459 | s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | | |
460 | s->dig_lbw << MEM_CDR_LBW_SHIFT | | |
461 | s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | | |
462 | s->dig_stl << MEM_CDR_STL_SHIFT | | |
463 | s->dig_thr << MEM_CDR_THR_SHIFT | | |
464 | s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | | |
465 | s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; | |
466 | ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); | |
467 | ||
468 | val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); | |
469 | val &= ~MEM_DLL_TRIM_SEL_MASK; | |
470 | val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; | |
471 | ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); | |
472 | ||
473 | val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); | |
474 | val &= ~MEM_DLL_PHINT_RATE_MASK; | |
475 | val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; | |
476 | ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); | |
477 | ||
478 | val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); | |
479 | val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | | |
480 | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); | |
481 | val |= s->eq_lev << MEM_EQLEV_SHIFT | | |
482 | s->eq_ftc << MEM_EQFTC_SHIFT | | |
483 | s->eq_ctl << MEM_EQCTL_SHIFT | | |
484 | s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | | |
485 | s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; | |
486 | ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); | |
487 | ||
488 | if (phy->mode == PIPE3_MODE_SATA) { | |
489 | val = ti_pipe3_readl(phy->phy_rx, | |
490 | SATA_PHY_RX_IO_AND_A2D_OVERRIDES); | |
491 | val &= ~MEM_CDR_LOS_SOURCE_MASK; | |
492 | ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, | |
493 | val); | |
494 | } | |
2796ceb0 KVA |
495 | } |
496 | ||
a70143bb | 497 | static int ti_pipe3_init(struct phy *x) |
57f6ce07 | 498 | { |
a70143bb | 499 | struct ti_pipe3 *phy = phy_get_drvdata(x); |
629138db RQ |
500 | u32 val; |
501 | int ret = 0; | |
519c6013 | 502 | |
0a0830fe | 503 | ti_pipe3_enable_clocks(phy); |
0bc09f9c V |
504 | /* |
505 | * Set pcie_pcs register to 0x96 for proper functioning of phy | |
506 | * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table | |
507 | * 18-1804. | |
508 | */ | |
22940823 | 509 | if (phy->mode == PIPE3_MODE_PCIE) { |
3f2362c5 KVA |
510 | if (!phy->pcs_syscon) { |
511 | omap_control_pcie_pcs(phy->control_dev, 0x96); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; | |
516 | ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, | |
517 | PCIE_PCS_MASK, val); | |
1d1bae72 | 518 | return ret; |
f0e2cf7b | 519 | } |
99bbd48c | 520 | |
629138db RQ |
521 | /* Bring it out of IDLE if it is IDLE */ |
522 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
523 | if (val & PLL_IDLE) { | |
524 | val &= ~PLL_IDLE; | |
525 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
526 | ret = ti_pipe3_dpll_wait_lock(phy); | |
527 | } | |
57f6ce07 | 528 | |
31b2a32f | 529 | /* SATA has issues if re-programmed when locked */ |
629138db | 530 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); |
22940823 | 531 | if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) |
31b2a32f RQ |
532 | return ret; |
533 | ||
534 | /* Program the DPLL */ | |
535 | ret = ti_pipe3_dpll_program(phy); | |
536 | if (ret) { | |
537 | ti_pipe3_disable_clocks(phy); | |
538 | return -EINVAL; | |
539 | } | |
57f6ce07 | 540 | |
fdef2f9f RQ |
541 | ti_pipe3_calibrate(phy); |
542 | ||
629138db | 543 | return ret; |
57f6ce07 KVA |
544 | } |
545 | ||
629138db RQ |
546 | static int ti_pipe3_exit(struct phy *x) |
547 | { | |
548 | struct ti_pipe3 *phy = phy_get_drvdata(x); | |
549 | u32 val; | |
550 | unsigned long timeout; | |
551 | ||
c934b361 RQ |
552 | /* If dpll_reset_syscon is not present we wont power down SATA DPLL |
553 | * due to Errata i783 | |
554 | */ | |
22940823 | 555 | if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) |
56042e4e RQ |
556 | return 0; |
557 | ||
0a0830fe | 558 | /* PCIe doesn't have internal DPLL */ |
22940823 | 559 | if (phy->mode != PIPE3_MODE_PCIE) { |
0a0830fe RQ |
560 | /* Put DPLL in IDLE mode */ |
561 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); | |
562 | val |= PLL_IDLE; | |
563 | ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); | |
629138db | 564 | |
0a0830fe RQ |
565 | /* wait for LDO and Oscillator to power down */ |
566 | timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME); | |
567 | do { | |
568 | cpu_relax(); | |
569 | val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); | |
570 | if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) | |
571 | break; | |
572 | } while (!time_after(jiffies, timeout)); | |
573 | ||
574 | if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { | |
575 | dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n", | |
576 | val); | |
577 | return -EBUSY; | |
578 | } | |
629138db RQ |
579 | } |
580 | ||
c934b361 | 581 | /* i783: SATA needs control bit toggle after PLL unlock */ |
22940823 | 582 | if (phy->mode == PIPE3_MODE_SATA) { |
c934b361 RQ |
583 | regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, |
584 | SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); | |
585 | regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, | |
586 | SATA_PLL_SOFT_RESET, 0); | |
587 | } | |
588 | ||
0a0830fe RQ |
589 | ti_pipe3_disable_clocks(phy); |
590 | ||
629138db RQ |
591 | return 0; |
592 | } | |
4a9e5ca1 | 593 | static const struct phy_ops ops = { |
a70143bb | 594 | .init = ti_pipe3_init, |
629138db | 595 | .exit = ti_pipe3_exit, |
a70143bb KVA |
596 | .power_on = ti_pipe3_power_on, |
597 | .power_off = ti_pipe3_power_off, | |
598 | .owner = THIS_MODULE, | |
599 | }; | |
600 | ||
61f54674 | 601 | static const struct of_device_id ti_pipe3_id_table[]; |
61f54674 | 602 | |
234738ea | 603 | static int ti_pipe3_get_clk(struct ti_pipe3 *phy) |
57f6ce07 | 604 | { |
99bbd48c | 605 | struct clk *clk; |
234738ea | 606 | struct device *dev = phy->dev; |
9c7f0443 | 607 | |
d65ff52e | 608 | phy->refclk = devm_clk_get(dev, "refclk"); |
7f33912d | 609 | if (IS_ERR(phy->refclk)) { |
d65ff52e | 610 | dev_err(dev, "unable to get refclk\n"); |
7f33912d RQ |
611 | /* older DTBs have missing refclk in SATA PHY |
612 | * so don't bail out in case of SATA PHY. | |
613 | */ | |
22940823 | 614 | if (phy->mode != PIPE3_MODE_SATA) |
7f33912d RQ |
615 | return PTR_ERR(phy->refclk); |
616 | } | |
617 | ||
22940823 | 618 | if (phy->mode != PIPE3_MODE_SATA) { |
d65ff52e | 619 | phy->wkupclk = devm_clk_get(dev, "wkupclk"); |
9c7f0443 | 620 | if (IS_ERR(phy->wkupclk)) { |
d65ff52e | 621 | dev_err(dev, "unable to get wkupclk\n"); |
9c7f0443 RQ |
622 | return PTR_ERR(phy->wkupclk); |
623 | } | |
9c7f0443 RQ |
624 | } else { |
625 | phy->wkupclk = ERR_PTR(-ENODEV); | |
234738ea KVA |
626 | } |
627 | ||
22940823 | 628 | if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { |
234738ea KVA |
629 | phy->sys_clk = devm_clk_get(dev, "sysclk"); |
630 | if (IS_ERR(phy->sys_clk)) { | |
631 | dev_err(dev, "unable to get sysclk\n"); | |
632 | return -EINVAL; | |
c934b361 | 633 | } |
57f6ce07 | 634 | } |
57f6ce07 | 635 | |
22940823 | 636 | if (phy->mode == PIPE3_MODE_PCIE) { |
d65ff52e | 637 | clk = devm_clk_get(dev, "dpll_ref"); |
99bbd48c | 638 | if (IS_ERR(clk)) { |
d65ff52e | 639 | dev_err(dev, "unable to get dpll ref clk\n"); |
99bbd48c KVA |
640 | return PTR_ERR(clk); |
641 | } | |
642 | clk_set_rate(clk, 1500000000); | |
643 | ||
d65ff52e | 644 | clk = devm_clk_get(dev, "dpll_ref_m2"); |
99bbd48c | 645 | if (IS_ERR(clk)) { |
d65ff52e | 646 | dev_err(dev, "unable to get dpll ref m2 clk\n"); |
99bbd48c KVA |
647 | return PTR_ERR(clk); |
648 | } | |
649 | clk_set_rate(clk, 100000000); | |
650 | ||
d65ff52e | 651 | clk = devm_clk_get(dev, "phy-div"); |
99bbd48c | 652 | if (IS_ERR(clk)) { |
d65ff52e | 653 | dev_err(dev, "unable to get phy-div clk\n"); |
99bbd48c KVA |
654 | return PTR_ERR(clk); |
655 | } | |
656 | clk_set_rate(clk, 100000000); | |
657 | ||
d65ff52e | 658 | phy->div_clk = devm_clk_get(dev, "div-clk"); |
99bbd48c | 659 | if (IS_ERR(phy->div_clk)) { |
d65ff52e | 660 | dev_err(dev, "unable to get div-clk\n"); |
99bbd48c KVA |
661 | return PTR_ERR(phy->div_clk); |
662 | } | |
663 | } else { | |
664 | phy->div_clk = ERR_PTR(-ENODEV); | |
57f6ce07 KVA |
665 | } |
666 | ||
234738ea KVA |
667 | return 0; |
668 | } | |
669 | ||
73bbc78e KVA |
670 | static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) |
671 | { | |
672 | struct device *dev = phy->dev; | |
673 | struct device_node *node = dev->of_node; | |
674 | struct device_node *control_node; | |
675 | struct platform_device *control_pdev; | |
676 | ||
c396a1c7 KVA |
677 | phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node, |
678 | "syscon-phy-power"); | |
679 | if (IS_ERR(phy->phy_power_syscon)) { | |
680 | dev_dbg(dev, | |
681 | "can't get syscon-phy-power, using control device\n"); | |
682 | phy->phy_power_syscon = NULL; | |
683 | } else { | |
684 | if (of_property_read_u32_index(node, | |
685 | "syscon-phy-power", 1, | |
686 | &phy->power_reg)) { | |
687 | dev_err(dev, "couldn't get power reg. offset\n"); | |
688 | return -EINVAL; | |
689 | } | |
73bbc78e KVA |
690 | } |
691 | ||
c396a1c7 KVA |
692 | if (!phy->phy_power_syscon) { |
693 | control_node = of_parse_phandle(node, "ctrl-module", 0); | |
694 | if (!control_node) { | |
695 | dev_err(dev, "Failed to get control device phandle\n"); | |
696 | return -EINVAL; | |
697 | } | |
73bbc78e | 698 | |
c396a1c7 KVA |
699 | control_pdev = of_find_device_by_node(control_node); |
700 | if (!control_pdev) { | |
701 | dev_err(dev, "Failed to get control device\n"); | |
702 | return -EINVAL; | |
703 | } | |
704 | ||
705 | phy->control_dev = &control_pdev->dev; | |
706 | } | |
73bbc78e | 707 | |
22940823 | 708 | if (phy->mode == PIPE3_MODE_PCIE) { |
3f2362c5 KVA |
709 | phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, |
710 | "syscon-pcs"); | |
711 | if (IS_ERR(phy->pcs_syscon)) { | |
712 | dev_dbg(dev, | |
713 | "can't get syscon-pcs, using omap control\n"); | |
714 | phy->pcs_syscon = NULL; | |
715 | } else { | |
716 | if (of_property_read_u32_index(node, | |
717 | "syscon-pcs", 1, | |
718 | &phy->pcie_pcs_reg)) { | |
719 | dev_err(dev, | |
720 | "couldn't get pcie pcs reg. offset\n"); | |
721 | return -EINVAL; | |
722 | } | |
723 | } | |
724 | } | |
725 | ||
22940823 | 726 | if (phy->mode == PIPE3_MODE_SATA) { |
73bbc78e KVA |
727 | phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, |
728 | "syscon-pllreset"); | |
729 | if (IS_ERR(phy->dpll_reset_syscon)) { | |
730 | dev_info(dev, | |
731 | "can't get syscon-pllreset, sata dpll won't idle\n"); | |
732 | phy->dpll_reset_syscon = NULL; | |
733 | } else { | |
734 | if (of_property_read_u32_index(node, | |
735 | "syscon-pllreset", 1, | |
736 | &phy->dpll_reset_reg)) { | |
737 | dev_err(dev, | |
738 | "couldn't get pllreset reg. offset\n"); | |
739 | return -EINVAL; | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
2796ceb0 KVA |
747 | static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) |
748 | { | |
749 | struct resource *res; | |
750 | struct device *dev = phy->dev; | |
2796ceb0 KVA |
751 | struct platform_device *pdev = to_platform_device(dev); |
752 | ||
2796ceb0 KVA |
753 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
754 | "phy_rx"); | |
755 | phy->phy_rx = devm_ioremap_resource(dev, res); | |
756 | if (IS_ERR(phy->phy_rx)) | |
757 | return PTR_ERR(phy->phy_rx); | |
758 | ||
759 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
760 | "phy_tx"); | |
761 | phy->phy_tx = devm_ioremap_resource(dev, res); | |
762 | ||
763 | return PTR_ERR_OR_ZERO(phy->phy_tx); | |
764 | } | |
765 | ||
1fe52122 KVA |
766 | static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) |
767 | { | |
768 | struct resource *res; | |
1fe52122 | 769 | struct device *dev = phy->dev; |
1fe52122 KVA |
770 | struct platform_device *pdev = to_platform_device(dev); |
771 | ||
22940823 | 772 | if (phy->mode == PIPE3_MODE_PCIE) |
1fe52122 KVA |
773 | return 0; |
774 | ||
1fe52122 KVA |
775 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
776 | "pll_ctrl"); | |
777 | phy->pll_ctrl_base = devm_ioremap_resource(dev, res); | |
045ef311 | 778 | return PTR_ERR_OR_ZERO(phy->pll_ctrl_base); |
1fe52122 KVA |
779 | } |
780 | ||
234738ea KVA |
781 | static int ti_pipe3_probe(struct platform_device *pdev) |
782 | { | |
783 | struct ti_pipe3 *phy; | |
784 | struct phy *generic_phy; | |
785 | struct phy_provider *phy_provider; | |
234738ea KVA |
786 | struct device *dev = &pdev->dev; |
787 | int ret; | |
22940823 RQ |
788 | const struct of_device_id *match; |
789 | struct pipe3_data *data; | |
234738ea KVA |
790 | |
791 | phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); | |
792 | if (!phy) | |
793 | return -ENOMEM; | |
794 | ||
22940823 RQ |
795 | match = of_match_device(ti_pipe3_id_table, dev); |
796 | if (!match) | |
797 | return -EINVAL; | |
798 | ||
799 | data = (struct pipe3_data *)match->data; | |
800 | if (!data) { | |
801 | dev_err(dev, "no driver data\n"); | |
802 | return -EINVAL; | |
803 | } | |
804 | ||
805 | phy->dev = dev; | |
806 | phy->mode = data->mode; | |
807 | phy->dpll_map = data->dpll_map; | |
fdef2f9f | 808 | phy->settings = data->settings; |
234738ea | 809 | |
1fe52122 KVA |
810 | ret = ti_pipe3_get_pll_base(phy); |
811 | if (ret) | |
812 | return ret; | |
234738ea | 813 | |
2796ceb0 KVA |
814 | ret = ti_pipe3_get_tx_rx_base(phy); |
815 | if (ret) | |
816 | return ret; | |
817 | ||
73bbc78e KVA |
818 | ret = ti_pipe3_get_sysctrl(phy); |
819 | if (ret) | |
820 | return ret; | |
234738ea KVA |
821 | |
822 | ret = ti_pipe3_get_clk(phy); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
57f6ce07 | 826 | platform_set_drvdata(pdev, phy); |
d65ff52e | 827 | pm_runtime_enable(dev); |
c934b361 RQ |
828 | |
829 | /* | |
830 | * Prevent auto-disable of refclk for SATA PHY due to Errata i783 | |
831 | */ | |
22940823 | 832 | if (phy->mode == PIPE3_MODE_SATA) { |
c934b361 | 833 | if (!IS_ERR(phy->refclk)) { |
0a0830fe | 834 | clk_prepare_enable(phy->refclk); |
c934b361 RQ |
835 | phy->sata_refclk_enabled = true; |
836 | } | |
837 | } | |
a70143bb | 838 | |
d65ff52e | 839 | generic_phy = devm_phy_create(dev, NULL, &ops); |
a70143bb KVA |
840 | if (IS_ERR(generic_phy)) |
841 | return PTR_ERR(generic_phy); | |
842 | ||
843 | phy_set_drvdata(generic_phy, phy); | |
cc34ace7 KVA |
844 | |
845 | ti_pipe3_power_off(generic_phy); | |
846 | ||
d65ff52e | 847 | phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
045ef311 | 848 | return PTR_ERR_OR_ZERO(phy_provider); |
57f6ce07 KVA |
849 | } |
850 | ||
a70143bb | 851 | static int ti_pipe3_remove(struct platform_device *pdev) |
57f6ce07 | 852 | { |
57f6ce07 KVA |
853 | pm_runtime_disable(&pdev->dev); |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
0a0830fe | 858 | static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy) |
7f33912d | 859 | { |
0a0830fe | 860 | int ret = 0; |
7f33912d | 861 | |
0a0830fe | 862 | if (!IS_ERR(phy->refclk)) { |
7f33912d RQ |
863 | ret = clk_prepare_enable(phy->refclk); |
864 | if (ret) { | |
865 | dev_err(phy->dev, "Failed to enable refclk %d\n", ret); | |
866 | return ret; | |
867 | } | |
7f33912d RQ |
868 | } |
869 | ||
1562864f RQ |
870 | if (!IS_ERR(phy->wkupclk)) { |
871 | ret = clk_prepare_enable(phy->wkupclk); | |
872 | if (ret) { | |
873 | dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); | |
0a0830fe | 874 | goto disable_refclk; |
1562864f | 875 | } |
57f6ce07 KVA |
876 | } |
877 | ||
99bbd48c KVA |
878 | if (!IS_ERR(phy->div_clk)) { |
879 | ret = clk_prepare_enable(phy->div_clk); | |
880 | if (ret) { | |
881 | dev_err(phy->dev, "Failed to enable div_clk %d\n", ret); | |
0a0830fe | 882 | goto disable_wkupclk; |
99bbd48c KVA |
883 | } |
884 | } | |
6e738432 | 885 | |
57f6ce07 KVA |
886 | return 0; |
887 | ||
0a0830fe | 888 | disable_wkupclk: |
99bbd48c KVA |
889 | if (!IS_ERR(phy->wkupclk)) |
890 | clk_disable_unprepare(phy->wkupclk); | |
891 | ||
0a0830fe | 892 | disable_refclk: |
1562864f RQ |
893 | if (!IS_ERR(phy->refclk)) |
894 | clk_disable_unprepare(phy->refclk); | |
57f6ce07 | 895 | |
6e738432 RQ |
896 | return ret; |
897 | } | |
898 | ||
899 | static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) | |
900 | { | |
6e738432 RQ |
901 | if (!IS_ERR(phy->wkupclk)) |
902 | clk_disable_unprepare(phy->wkupclk); | |
c934b361 | 903 | if (!IS_ERR(phy->refclk)) { |
0a0830fe | 904 | clk_disable_unprepare(phy->refclk); |
c934b361 RQ |
905 | /* |
906 | * SATA refclk needs an additional disable as we left it | |
907 | * on in probe to avoid Errata i783 | |
908 | */ | |
909 | if (phy->sata_refclk_enabled) { | |
910 | clk_disable_unprepare(phy->refclk); | |
911 | phy->sata_refclk_enabled = false; | |
912 | } | |
913 | } | |
914 | ||
6e738432 RQ |
915 | if (!IS_ERR(phy->div_clk)) |
916 | clk_disable_unprepare(phy->div_clk); | |
6e738432 RQ |
917 | } |
918 | ||
a70143bb | 919 | static const struct of_device_id ti_pipe3_id_table[] = { |
61f54674 RQ |
920 | { |
921 | .compatible = "ti,phy-usb3", | |
22940823 | 922 | .data = &data_usb, |
61f54674 RQ |
923 | }, |
924 | { | |
925 | .compatible = "ti,omap-usb3", | |
22940823 | 926 | .data = &data_usb, |
61f54674 RQ |
927 | }, |
928 | { | |
929 | .compatible = "ti,phy-pipe3-sata", | |
22940823 | 930 | .data = &data_sata, |
61f54674 | 931 | }, |
99bbd48c KVA |
932 | { |
933 | .compatible = "ti,phy-pipe3-pcie", | |
22940823 | 934 | .data = &data_pcie, |
99bbd48c | 935 | }, |
57f6ce07 KVA |
936 | {} |
937 | }; | |
a70143bb | 938 | MODULE_DEVICE_TABLE(of, ti_pipe3_id_table); |
57f6ce07 | 939 | |
a70143bb KVA |
940 | static struct platform_driver ti_pipe3_driver = { |
941 | .probe = ti_pipe3_probe, | |
942 | .remove = ti_pipe3_remove, | |
57f6ce07 | 943 | .driver = { |
a70143bb | 944 | .name = "ti-pipe3", |
298fe56e | 945 | .of_match_table = ti_pipe3_id_table, |
57f6ce07 KVA |
946 | }, |
947 | }; | |
948 | ||
a70143bb | 949 | module_platform_driver(ti_pipe3_driver); |
57f6ce07 | 950 | |
dd64ad38 | 951 | MODULE_ALIAS("platform:ti_pipe3"); |
57f6ce07 | 952 | MODULE_AUTHOR("Texas Instruments Inc."); |
a70143bb | 953 | MODULE_DESCRIPTION("TI PIPE3 phy driver"); |
57f6ce07 | 954 | MODULE_LICENSE("GPL v2"); |