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Commit | Line | Data |
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d90a5a30 MY |
1 | # |
2 | # PINCTRL infrastructure and drivers | |
3 | # | |
4 | ||
5 | menu "Pin controllers" | |
6 | ||
7 | config PINCTRL | |
8 | bool "Support pin controllers" | |
9 | depends on DM | |
10 | help | |
11 | This enables the basic support for pinctrl framework. You may want | |
12 | to enable some more options depending on what you want to do. | |
13 | ||
14 | config PINCTRL_FULL | |
15 | bool "Support full pin controllers" | |
16 | depends on PINCTRL && OF_CONTROL | |
17 | default y | |
18 | help | |
19 | This provides Linux-compatible device tree interface for the pinctrl | |
20 | subsystem. This feature depends on device tree configuration because | |
21 | it parses a device tree to look for the pinctrl device which the | |
22 | peripheral device is associated with. | |
23 | ||
24 | If this option is disabled (it is the only possible choice for non-DT | |
25 | boards), the pinctrl core provides no systematic mechanism for | |
26 | identifying peripheral devices, applying needed pinctrl settings. | |
27 | It is totally up to the implementation of each low-level driver. | |
28 | You can save memory footprint in return for some limitations. | |
29 | ||
30 | config PINCTRL_GENERIC | |
31 | bool "Support generic pin controllers" | |
32 | depends on PINCTRL_FULL | |
33 | default y | |
34 | help | |
35 | Say Y here if you want to use the pinctrl subsystem through the | |
36 | generic DT interface. If enabled, some functions become available | |
37 | to parse common properties such as "pins", "groups", "functions" and | |
38 | some pin configuration parameters. It would be easier if you only | |
39 | need the generic DT interface for pin muxing and pin configuration. | |
40 | If you need to handle vendor-specific DT properties, you can disable | |
41 | this option and implement your own set_state callback in the pinctrl | |
42 | operations. | |
43 | ||
44 | config PINMUX | |
45 | bool "Support pin multiplexing controllers" | |
46 | depends on PINCTRL_GENERIC | |
47 | default y | |
48 | help | |
49 | This option enables pin multiplexing through the generic pinctrl | |
458a0700 SG |
50 | framework. Most SoCs have their own own multiplexing arrangement |
51 | where a single pin can be used for several functions. An SoC pinctrl | |
52 | driver allows the required function to be selected for each pin. | |
53 | The driver is typically controlled by the device tree. | |
d90a5a30 MY |
54 | |
55 | config PINCONF | |
56 | bool "Support pin configuration controllers" | |
57 | depends on PINCTRL_GENERIC | |
58 | help | |
59 | This option enables pin configuration through the generic pinctrl | |
60 | framework. | |
61 | ||
62 | config SPL_PINCTRL | |
0fa0abec | 63 | bool "Support pin controllers in SPL" |
d90a5a30 MY |
64 | depends on SPL && SPL_DM |
65 | help | |
66 | This option is an SPL-variant of the PINCTRL option. | |
67 | See the help of PINCTRL for details. | |
68 | ||
69 | config SPL_PINCTRL_FULL | |
70 | bool "Support full pin controllers in SPL" | |
71 | depends on SPL_PINCTRL && SPL_OF_CONTROL | |
b9747696 | 72 | default n if TARGET_STM32F746_DISCO |
d90a5a30 MY |
73 | default y |
74 | help | |
75 | This option is an SPL-variant of the PINCTRL_FULL option. | |
76 | See the help of PINCTRL_FULL for details. | |
77 | ||
78 | config SPL_PINCTRL_GENERIC | |
79 | bool "Support generic pin controllers in SPL" | |
80 | depends on SPL_PINCTRL_FULL | |
81 | default y | |
82 | help | |
83 | This option is an SPL-variant of the PINCTRL_GENERIC option. | |
84 | See the help of PINCTRL_GENERIC for details. | |
85 | ||
86 | config SPL_PINMUX | |
87 | bool "Support pin multiplexing controllers in SPL" | |
88 | depends on SPL_PINCTRL_GENERIC | |
89 | default y | |
90 | help | |
91 | This option is an SPL-variant of the PINMUX option. | |
92 | See the help of PINMUX for details. | |
458a0700 SG |
93 | The pinctrl subsystem can add a substantial overhead to the SPL |
94 | image since it typically requires quite a few tables either in the | |
95 | driver or in the device tree. If this is acceptable and you need | |
96 | to adjust pin multiplexing in SPL in order to boot into U-Boot, | |
97 | enable this option. You will need to enable device tree in SPL | |
98 | for this to work. | |
d90a5a30 MY |
99 | |
100 | config SPL_PINCONF | |
101 | bool "Support pin configuration controllers in SPL" | |
102 | depends on SPL_PINCTRL_GENERIC | |
103 | help | |
104 | This option is an SPL-variant of the PINCONF option. | |
105 | See the help of PINCONF for details. | |
106 | ||
107 | if PINCTRL || SPL_PINCTRL | |
108 | ||
51c7f348 | 109 | config PINCTRL_AR933X |
a79d0643 WW |
110 | bool "QCA/Athores ar933x pin control driver" |
111 | depends on DM && SOC_AR933X | |
112 | help | |
113 | Support pin multiplexing control on QCA/Athores ar933x SoCs. | |
114 | The driver is controlled by a device tree node which contains | |
115 | both the GPIO definitions and pin control functions for each | |
116 | available multiplex function. | |
117 | ||
51c7f348 PT |
118 | config PINCTRL_AT91 |
119 | bool "AT91 pinctrl driver" | |
120 | depends on DM | |
121 | help | |
122 | This option is to enable the AT91 pinctrl driver for AT91 PIO | |
123 | controller. | |
124 | ||
125 | AT91 PIO controller is a combined gpio-controller, pin-mux and | |
126 | pin-config module. Each I/O pin may be dedicated as a general-purpose | |
127 | I/O or be assigned to a function of an embedded peripheral. Each I/O | |
128 | pin has a glitch filter providing rejection of glitches lower than | |
129 | one-half of peripheral clock cycle and a debouncing filter providing | |
130 | rejection of unwanted pulses from key or push button operations. You | |
131 | can also control the multi-driver capability, pull-up and pull-down | |
132 | feature on each I/O pin. | |
133 | ||
134 | config PINCTRL_AT91PIO4 | |
135 | bool "AT91 PIO4 pinctrl driver" | |
136 | depends on DM | |
137 | help | |
138 | This option is to enable the AT91 pinctrl driver for AT91 PIO4 | |
139 | controller which is available on SAMA5D2 SoC. | |
140 | ||
141 | config PINCTRL_PIC32 | |
142 | bool "Microchip PIC32 pin-control and pin-mux driver" | |
143 | depends on DM && MACH_PIC32 | |
144 | default y | |
145 | help | |
146 | Supports individual pin selection and configuration for each | |
147 | remappable peripheral available on Microchip PIC32 | |
148 | SoCs. This driver is controlled by a device tree node which | |
149 | contains both GPIO defintion and pin control functions. | |
150 | ||
151 | config PINCTRL_QCA953X | |
c102453a WW |
152 | bool "QCA/Athores qca953x pin control driver" |
153 | depends on DM && SOC_QCA953X | |
154 | help | |
155 | Support pin multiplexing control on QCA/Athores qca953x SoCs. | |
c102453a | 156 | |
51c7f348 PT |
157 | The driver is controlled by a device tree node which contains both |
158 | the GPIO definitions and pin control functions for each available | |
159 | multiplex function. | |
160 | ||
161 | config PINCTRL_ROCKCHIP_RK3036 | |
041cdb5f | 162 | bool "Rockchip rk3036 pin control driver" |
bb4e4a5d SG |
163 | depends on DM |
164 | help | |
51c7f348 PT |
165 | Support pin multiplexing control on Rockchip rk3036 SoCs. |
166 | ||
167 | The driver is controlled by a device tree node which contains both | |
168 | the GPIO definitions and pin control functions for each available | |
169 | multiplex function. | |
bb4e4a5d | 170 | |
51c7f348 | 171 | config PINCTRL_ROCKCHIP_RK3188 |
f3f1af93 | 172 | bool "Rockchip rk3188 pin control driver" |
155cd37f HS |
173 | depends on DM |
174 | help | |
51c7f348 | 175 | Support pin multiplexing control on Rockchip rk3188 SoCs. |
bb4e4a5d | 176 | |
51c7f348 PT |
177 | The driver is controlled by a device tree node which contains both |
178 | the GPIO definitions and pin control functions for each available | |
179 | multiplex function. | |
49ecaa92 | 180 | |
5cc9d31a KY |
181 | config PINCTRL_ROCKCHIP_RK322X |
182 | bool "Rockchip rk322x pin control driver" | |
183 | depends on DM | |
184 | help | |
185 | Support pin multiplexing control on Rockchip rk322x SoCs. | |
186 | ||
187 | The driver is controlled by a device tree node which contains both | |
188 | the GPIO definitions and pin control functions for each available | |
189 | multiplex function. | |
190 | ||
51c7f348 PT |
191 | config PINCTRL_ROCKCHIP_RK3288 |
192 | bool "Rockchip rk3288 pin control driver" | |
9319a756 WY |
193 | depends on DM |
194 | help | |
51c7f348 | 195 | Support pin multiplexing control on Rockchip rk3288 SoCs. |
9319a756 | 196 | |
51c7f348 PT |
197 | The driver is controlled by a device tree node which contains both |
198 | the GPIO definitions and pin control functions for each available | |
199 | multiplex function. | |
ac72e174 | 200 | |
51c7f348 | 201 | config PINCTRL_ROCKCHIP_RK3328 |
f3f1af93 | 202 | bool "Rockchip rk3328 pin control driver" |
d439a46e KY |
203 | depends on DM |
204 | help | |
51c7f348 PT |
205 | Support pin multiplexing control on Rockchip rk3328 SoCs. |
206 | ||
207 | The driver is controlled by a device tree node which contains both | |
208 | the GPIO definitions and pin control functions for each available | |
209 | multiplex function. | |
d439a46e | 210 | |
27600a58 AY |
211 | config PINCTRL_ROCKCHIP_RK3368 |
212 | bool "Rockchip RK3368 pin control driver" | |
213 | depends on DM | |
214 | help | |
215 | Support pin multiplexing control on Rockchip rk3368 SoCs. | |
216 | ||
217 | The driver is controlled by a device tree node which contains both | |
218 | the GPIO definitions and pin control functions for each available | |
219 | multiplex function. | |
220 | ||
51c7f348 | 221 | config PINCTRL_ROCKCHIP_RK3399 |
f3f1af93 | 222 | bool "Rockchip rk3399 pin control driver" |
a2c08df3 KY |
223 | depends on DM |
224 | help | |
51c7f348 PT |
225 | Support pin multiplexing control on Rockchip rk3399 SoCs. |
226 | ||
227 | The driver is controlled by a device tree node which contains both | |
228 | the GPIO definitions and pin control functions for each available | |
229 | multiplex function. | |
a2c08df3 | 230 | |
09aa7c46 AY |
231 | config PINCTRL_ROCKCHIP_RV1108 |
232 | bool "Rockchip rv1108 pin control driver" | |
233 | depends on DM | |
234 | help | |
235 | Support pin multiplexing control on Rockchip rv1108 SoC. | |
236 | ||
237 | The driver is controlled by a device tree node which contains | |
238 | both the GPIO definitions and pin control functions for each | |
239 | available multiplex function. | |
240 | ||
9c6a3c67 MY |
241 | config PINCTRL_SANDBOX |
242 | bool "Sandbox pinctrl driver" | |
243 | depends on SANDBOX | |
244 | help | |
51c7f348 | 245 | This enables pinctrl driver for sandbox. |
9c6a3c67 | 246 | |
51c7f348 PT |
247 | Currently, this driver actually does nothing but print debug |
248 | messages when pinctrl operations are invoked. | |
249 | ||
250 | config PINCTRL_SINGLE | |
251 | bool "Single register pin-control and pin-multiplex driver" | |
252 | depends on DM | |
5f266c60 | 253 | help |
51c7f348 PT |
254 | This enables pinctrl driver for systems using a single register for |
255 | pin configuration and multiplexing. TI's AM335X SoCs are examples of | |
256 | such systems. | |
257 | ||
258 | Depending on the platform make sure to also enable OF_TRANSLATE and | |
259 | eventually SPL_OF_TRANSLATE to get correct address translations. | |
5f266c60 | 260 | |
0c563102 PC |
261 | config PINCTRL_STI |
262 | bool "STMicroelectronics STi pin-control and pin-mux driver" | |
263 | depends on DM && ARCH_STI | |
264 | default y | |
265 | help | |
266 | Support pin multiplexing control on STMicrolectronics STi SoCs. | |
51c7f348 | 267 | |
0c563102 | 268 | The driver is controlled by a device tree node which contains both |
51c7f348 PT |
269 | the GPIO definitions and pin control functions for each available |
270 | multiplex function. | |
0c563102 | 271 | |
94d53084 VM |
272 | config PINCTRL_STM32 |
273 | bool "ST STM32 pin control driver" | |
274 | depends on DM | |
275 | help | |
51c7f348 | 276 | Supports pin multiplexing control on stm32 SoCs. |
94d53084 | 277 | |
51c7f348 PT |
278 | The driver is controlled by a device tree node which contains both |
279 | the GPIO definitions and pin control functions for each available | |
280 | multiplex function. | |
44d5c371 | 281 | |
4f0e44e4 | 282 | config ASPEED_AST2500_PINCTRL |
283 | bool "Aspeed AST2500 pin control driver" | |
284 | depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 | |
285 | default y | |
286 | help | |
287 | Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses | |
288 | Generic Pinctrl framework and is compatible with the Linux driver, | |
289 | i.e. it uses the same device tree configuration. | |
290 | ||
d90a5a30 MY |
291 | endif |
292 | ||
677b5358 | 293 | source "drivers/pinctrl/meson/Kconfig" |
745df68d | 294 | source "drivers/pinctrl/nxp/Kconfig" |
5dc626f8 | 295 | source "drivers/pinctrl/uniphier/Kconfig" |
16ca80ad | 296 | source "drivers/pinctrl/exynos/Kconfig" |
656e6cc8 | 297 | source "drivers/pinctrl/mvebu/Kconfig" |
5dc626f8 | 298 | |
d90a5a30 | 299 | endmenu |