[people/ms/u-boot.git] / drivers / pinctrl / exynos / pinctrl-exynos.h

/*
 * Exynos pinctrl driver header.
 * Copyright (C) 2016 Samsung Electronics
 * Thomas Abraham <thomas.ab@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __PINCTRL_EXYNOS_H_
#define __PINCTRL_EXYNOS__H_

#define PIN_CON		0x00	/* Offset of pin function register */
#define PIN_DAT		0x04	/* Offset of pin data register */
#define PIN_PUD		0x08	/* Offset of pin pull up/down config register */
#define PIN_DRV		0x0C	/* Offset of pin drive strength register */

/**
 * struct samsung_pin_bank_data: represent a controller pin-bank data.
 * @offset: starting offset of the pin-bank registers.
 * @nr_pins: number of pins included in this bank.
 * @name: name to be prefixed for each pin in this pin bank.
 */
struct samsung_pin_bank_data {
	u32		offset;
	u8		nr_pins;
	const char	*name;
};

#define EXYNOS_PIN_BANK(pins, reg, id)			\
	{						\
		.offset	= reg,				\
		.nr_pins	= pins,			\
		.name		= id			\
	}

/**
 * struct samsung_pin_ctrl: represent a pin controller.
 * @pin_banks: list of pin banks included in this controller.
 * @nr_banks: number of pin banks.
 */
struct samsung_pin_ctrl {
	const struct samsung_pin_bank_data *pin_banks;
	u32 nr_banks;
};

/**
 * struct exynos_pinctrl_priv: exynos pin controller driver private data
 * @pin_ctrl: pin controller bank information.
 * @base: base address of the pin controller instance.
 * @num_banks: number of pin banks included in the pin controller.
 */
struct exynos_pinctrl_priv {
	const struct samsung_pin_ctrl *pin_ctrl;
	unsigned long base;
	int num_banks;
};

/**
 * struct exynos_pinctrl_config_data: configuration for a peripheral.
 * @offset: offset of the config registers in the controller.
 * @mask: value of the register to be masked with.
 * @value: new value to be programmed.
 */
struct exynos_pinctrl_config_data {
	const unsigned int	offset;
	const unsigned int	mask;
	const unsigned int	value;
};


void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
		unsigned int num_conf, unsigned long base);
int exynos_pinctrl_set_state(struct udevice *dev,
		struct udevice *config);
int exynos_pinctrl_probe(struct udevice *dev);

#endif /* __PINCTRL_EXYNOS_H_ */
Commit	Line	Data
16ca80ad TA	1	/*
	2	* Exynos pinctrl driver header.
	3	* Copyright (C) 2016 Samsung Electronics
	4	* Thomas Abraham <thomas.ab@samsung.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __PINCTRL_EXYNOS_H_
	10	#define __PINCTRL_EXYNOS__H_
	11
	12	#define PIN_CON 0x00 /* Offset of pin function register */
	13	#define PIN_DAT 0x04 /* Offset of pin data register */
	14	#define PIN_PUD 0x08 /* Offset of pin pull up/down config register */
	15	#define PIN_DRV 0x0C /* Offset of pin drive strength register */
	16
	17	/**
	18	* struct samsung_pin_bank_data: represent a controller pin-bank data.
	19	* @offset: starting offset of the pin-bank registers.
	20	* @nr_pins: number of pins included in this bank.
	21	* @name: name to be prefixed for each pin in this pin bank.
	22	*/
	23	struct samsung_pin_bank_data {
	24	u32 offset;
	25	u8 nr_pins;
	26	const char *name;
	27	};
	28
	29	#define EXYNOS_PIN_BANK(pins, reg, id) \
	30	{ \
	31	.offset = reg, \
	32	.nr_pins = pins, \
	33	.name = id \
	34	}
	35
	36	/**
	37	* struct samsung_pin_ctrl: represent a pin controller.
	38	* @pin_banks: list of pin banks included in this controller.
	39	* @nr_banks: number of pin banks.
	40	*/
	41	struct samsung_pin_ctrl {
	42	const struct samsung_pin_bank_data *pin_banks;
	43	u32 nr_banks;
	44	};
	45
	46	/**
	47	* struct exynos_pinctrl_priv: exynos pin controller driver private data
	48	* @pin_ctrl: pin controller bank information.
	49	* @base: base address of the pin controller instance.
	50	* @num_banks: number of pin banks included in the pin controller.
	51	*/
	52	struct exynos_pinctrl_priv {
	53	const struct samsung_pin_ctrl *pin_ctrl;
	54	unsigned long base;
	55	int num_banks;
	56	};
	57
	58	/**
	59	* struct exynos_pinctrl_config_data: configuration for a peripheral.
	60	* @offset: offset of the config registers in the controller.
	61	* @mask: value of the register to be masked with.
	62	* @value: new value to be programmed.
	63	*/
	64	struct exynos_pinctrl_config_data {
65	const unsigned int offset;
66	const unsigned int mask;
67	const unsigned int value;
68	};
69
70
71	void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
72	unsigned int num_conf, unsigned long base);
73	int exynos_pinctrl_set_state(struct udevice *dev,
74	struct udevice *config);
75	int exynos_pinctrl_probe(struct udevice *dev);
76
77	#endif /* __PINCTRL_EXYNOS_H_ */