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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / pinctrl / intel / pinctrl-cherryview.c
CommitLineData
875a92b3 1// SPDX-License-Identifier: GPL-2.0
6e08d6bb
MW		 2/*
3 * Cherryview/Braswell pinctrl driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This driver is based on the original Cherryview GPIO driver by
9 * Ning Li <ning.li@intel.com>
10 * Alan Cox <alan@linux.intel.com>
6e08d6bb
MW		 11 */
12
994f8865 13#include <linux/acpi.h>
70365027 14#include <linux/dmi.h>
994f8865 15#include <linux/gpio/driver.h>
6e08d6bb
MW		 16#include <linux/kernel.h>
17#include <linux/module.h>
994f8865 18#include <linux/platform_device.h>
6e08d6bb 19#include <linux/types.h>
994f8865 20
6e08d6bb
MW		 21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinconf-generic.h>
6e08d6bb 25
5458b7ce
AS		 26#include "pinctrl-intel.h"
27
6e08d6bb
MW		 28#define CHV_INTSTAT 0x300
29#define CHV_INTMASK 0x380
30
31#define FAMILY_PAD_REGS_OFF 0x4400
32#define FAMILY_PAD_REGS_SIZE 0x400
33#define MAX_FAMILY_PAD_GPIO_NO 15
34#define GPIO_REGS_SIZE 8
35
36#define CHV_PADCTRL0 0x000
37#define CHV_PADCTRL0_INTSEL_SHIFT 28
38#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
39#define CHV_PADCTRL0_TERM_UP BIT(23)
40#define CHV_PADCTRL0_TERM_SHIFT 20
41#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
42#define CHV_PADCTRL0_TERM_20K 1
43#define CHV_PADCTRL0_TERM_5K 2
44#define CHV_PADCTRL0_TERM_1K 4
45#define CHV_PADCTRL0_PMODE_SHIFT 16
46#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
47#define CHV_PADCTRL0_GPIOEN BIT(15)
48#define CHV_PADCTRL0_GPIOCFG_SHIFT 8
49#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
50#define CHV_PADCTRL0_GPIOCFG_GPIO 0
51#define CHV_PADCTRL0_GPIOCFG_GPO 1
52#define CHV_PADCTRL0_GPIOCFG_GPI 2
53#define CHV_PADCTRL0_GPIOCFG_HIZ 3
54#define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
55#define CHV_PADCTRL0_GPIORXSTATE BIT(0)
56
57#define CHV_PADCTRL1 0x004
58#define CHV_PADCTRL1_CFGLOCK BIT(31)
59#define CHV_PADCTRL1_INVRXTX_SHIFT 4
60#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
61#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
62#define CHV_PADCTRL1_ODEN BIT(3)
63#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
64#define CHV_PADCTRL1_INTWAKECFG_MASK 7
65#define CHV_PADCTRL1_INTWAKECFG_FALLING 1
66#define CHV_PADCTRL1_INTWAKECFG_RISING 2
67#define CHV_PADCTRL1_INTWAKECFG_BOTH 3
68#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
69
70/**
71 * struct chv_alternate_function - A per group or per pin alternate function
72 * @pin: Pin number (only used in per pin configs)
73 * @mode: Mode the pin should be set in
74 * @invert_oe: Invert OE for this pin
75 */
76struct chv_alternate_function {
4e737af8 77 unsigned int pin;
6e08d6bb
MW		 78 u8 mode;
79 bool invert_oe;
80};
81
82/**
83 * struct chv_pincgroup - describes a CHV pin group
84 * @name: Name of the group
85 * @pins: An array of pins in this group
86 * @npins: Number of pins in this group
87 * @altfunc: Alternate function applied to all pins in this group
88 * @overrides: Alternate function override per pin or %NULL if not used
89 * @noverrides: Number of per pin alternate function overrides if
90 * @overrides != NULL.
91 */
92struct chv_pingroup {
93 const char *name;
4e737af8 94 const unsigned int *pins;
6e08d6bb
MW		 95 size_t npins;
96 struct chv_alternate_function altfunc;
97 const struct chv_alternate_function *overrides;
98 size_t noverrides;
99};
100
6e08d6bb
MW		 101/**
102 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
103 * @base: Start pin number
104 * @npins: Number of pins in this range
105 */
106struct chv_gpio_pinrange {
4e737af8
AS		 107 unsigned int base;
108 unsigned int npins;
6e08d6bb
MW		 109};
110
111/**
112 * struct chv_community - A community specific configuration
113 * @uid: ACPI _UID used to match the community
114 * @pins: All pins in this community
115 * @npins: Number of pins
116 * @groups: All groups in this community
117 * @ngroups: Number of groups
118 * @functions: All functions in this community
119 * @nfunctions: Number of functions
6e08d6bb
MW		 120 * @gpio_ranges: An array of GPIO ranges in this community
121 * @ngpio_ranges: Number of GPIO ranges
47c950d1 122 * @nirqs: Total number of IRQs this community can generate
a919684f 123 * @acpi_space_id: An address space ID for ACPI OpRegion handler
6e08d6bb
MW		 124 */
125struct chv_community {
126 const char *uid;
127 const struct pinctrl_pin_desc *pins;
128 size_t npins;
129 const struct chv_pingroup *groups;
130 size_t ngroups;
5458b7ce 131 const struct intel_function *functions;
6e08d6bb
MW		 132 size_t nfunctions;
133 const struct chv_gpio_pinrange *gpio_ranges;
134 size_t ngpio_ranges;
47c950d1 135 size_t nirqs;
a0b02859 136 acpi_adr_space_type acpi_space_id;
6e08d6bb
MW		 137};
138
9eb457b5
MW		 139struct chv_pin_context {
140 u32 padctrl0;
141 u32 padctrl1;
142};
143
6e08d6bb
MW		 144/**
145 * struct chv_pinctrl - CHV pinctrl private structure
146 * @dev: Pointer to the parent device
147 * @pctldesc: Pin controller description
148 * @pctldev: Pointer to the pin controller device
149 * @chip: GPIO chip in this pin controller
e58e1773 150 * @irqchip: IRQ chip in this pin controller
6e08d6bb 151 * @regs: MMIO registers
b9a19bdb 152 * @irq: Our parent irq
6e08d6bb
MW		 153 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
154 * offset (in GPIO number space)
155 * @community: Community this pinctrl instance represents
a919684f
AS		 156 * @saved_intmask: Interrupt mask saved for system sleep
157 * @saved_pin_context: Pointer to a context of the pins saved for system sleep
6e08d6bb
MW		 158 *
159 * The first group in @groups is expected to contain all pins that can be
160 * used as GPIOs.
161 */
162struct chv_pinctrl {
163 struct device *dev;
164 struct pinctrl_desc pctldesc;
165 struct pinctrl_dev *pctldev;
166 struct gpio_chip chip;
e58e1773 167 struct irq_chip irqchip;
6e08d6bb 168 void __iomem *regs;
b9a19bdb 169 unsigned int irq;
8ae93b5e 170 unsigned int intr_lines[16];
6e08d6bb 171 const struct chv_community *community;
9eb457b5
MW		 172 u32 saved_intmask;
173 struct chv_pin_context *saved_pin_context;
6e08d6bb
MW		 174};
175
6e08d6bb
MW		 176#define ALTERNATE_FUNCTION(p, m, i) \
177 { \
178 .pin = (p), \
179 .mode = (m), \
180 .invert_oe = (i), \
181 }
182
5458b7ce 183#define PIN_GROUP_WITH_ALT(n, p, m, i) \
6e08d6bb
MW		 184 { \
185 .name = (n), \
186 .pins = (p), \
187 .npins = ARRAY_SIZE((p)), \
188 .altfunc.mode = (m), \
189 .altfunc.invert_oe = (i), \
190 }
191
192#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
193 { \
194 .name = (n), \
195 .pins = (p), \
196 .npins = ARRAY_SIZE((p)), \
197 .altfunc.mode = (m), \
198 .altfunc.invert_oe = (i), \
199 .overrides = (o), \
200 .noverrides = ARRAY_SIZE((o)), \
201 }
202
6e08d6bb
MW		 203#define GPIO_PINRANGE(start, end) \
204 { \
205 .base = (start), \
206 .npins = (end) - (start) + 1, \
207 }
208
209static const struct pinctrl_pin_desc southwest_pins[] = {
210 PINCTRL_PIN(0, "FST_SPI_D2"),
211 PINCTRL_PIN(1, "FST_SPI_D0"),
212 PINCTRL_PIN(2, "FST_SPI_CLK"),
213 PINCTRL_PIN(3, "FST_SPI_D3"),
214 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
215 PINCTRL_PIN(5, "FST_SPI_D1"),
216 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
217 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
218
219 PINCTRL_PIN(15, "UART1_RTS_B"),
220 PINCTRL_PIN(16, "UART1_RXD"),
221 PINCTRL_PIN(17, "UART2_RXD"),
222 PINCTRL_PIN(18, "UART1_CTS_B"),
223 PINCTRL_PIN(19, "UART2_RTS_B"),
224 PINCTRL_PIN(20, "UART1_TXD"),
225 PINCTRL_PIN(21, "UART2_TXD"),
226 PINCTRL_PIN(22, "UART2_CTS_B"),
227
228 PINCTRL_PIN(30, "MF_HDA_CLK"),
229 PINCTRL_PIN(31, "MF_HDA_RSTB"),
230 PINCTRL_PIN(32, "MF_HDA_SDIO"),
231 PINCTRL_PIN(33, "MF_HDA_SDO"),
232 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
233 PINCTRL_PIN(35, "MF_HDA_SYNC"),
234 PINCTRL_PIN(36, "MF_HDA_SDI1"),
235 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
236
237 PINCTRL_PIN(45, "I2C5_SDA"),
238 PINCTRL_PIN(46, "I2C4_SDA"),
239 PINCTRL_PIN(47, "I2C6_SDA"),
240 PINCTRL_PIN(48, "I2C5_SCL"),
241 PINCTRL_PIN(49, "I2C_NFC_SDA"),
242 PINCTRL_PIN(50, "I2C4_SCL"),
243 PINCTRL_PIN(51, "I2C6_SCL"),
244 PINCTRL_PIN(52, "I2C_NFC_SCL"),
245
246 PINCTRL_PIN(60, "I2C1_SDA"),
247 PINCTRL_PIN(61, "I2C0_SDA"),
248 PINCTRL_PIN(62, "I2C2_SDA"),
249 PINCTRL_PIN(63, "I2C1_SCL"),
250 PINCTRL_PIN(64, "I2C3_SDA"),
251 PINCTRL_PIN(65, "I2C0_SCL"),
252 PINCTRL_PIN(66, "I2C2_SCL"),
253 PINCTRL_PIN(67, "I2C3_SCL"),
254
255 PINCTRL_PIN(75, "SATA_GP0"),
256 PINCTRL_PIN(76, "SATA_GP1"),
257 PINCTRL_PIN(77, "SATA_LEDN"),
258 PINCTRL_PIN(78, "SATA_GP2"),
259 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
260 PINCTRL_PIN(80, "SATA_GP3"),
261 PINCTRL_PIN(81, "MF_SMB_CLK"),
262 PINCTRL_PIN(82, "MF_SMB_DATA"),
263
264 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
265 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
266 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
267 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
268 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
269 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
270 PINCTRL_PIN(96, "GP_SSP_2_FS"),
271 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
272};
273
6e08d6bb
MW		 274static const unsigned southwest_uart0_pins[] = { 16, 20 };
275static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
276static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
277static const unsigned southwest_i2c0_pins[] = { 61, 65 };
278static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
279static const unsigned southwest_lpe_pins[] = {
280 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
281};
282static const unsigned southwest_i2c1_pins[] = { 60, 63 };
283static const unsigned southwest_i2c2_pins[] = { 62, 66 };
284static const unsigned southwest_i2c3_pins[] = { 64, 67 };
285static const unsigned southwest_i2c4_pins[] = { 46, 50 };
286static const unsigned southwest_i2c5_pins[] = { 45, 48 };
287static const unsigned southwest_i2c6_pins[] = { 47, 51 };
288static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
6e08d6bb
MW		 289static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
290
291/* LPE I2S TXD pins need to have invert_oe set */
292static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
293 ALTERNATE_FUNCTION(30, 1, true),
294 ALTERNATE_FUNCTION(34, 1, true),
295 ALTERNATE_FUNCTION(97, 1, true),
296};
297
298/*
299 * Two spi3 chipselects are available in different mode than the main spi3
300 * functionality, which is using mode 1.
301 */
302static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
303 ALTERNATE_FUNCTION(76, 3, false),
304 ALTERNATE_FUNCTION(80, 3, false),
305};
306
307static const struct chv_pingroup southwest_groups[] = {
5458b7ce
AS		 308 PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
309 PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
310 PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
311 PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
312 PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
313 PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
314 PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
315 PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
316 PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
317 PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
318 PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
319 PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
6e08d6bb
MW		 320
321 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
322 southwest_lpe_altfuncs),
323 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
324 southwest_spi3_altfuncs),
325};
326
327static const char * const southwest_uart0_groups[] = { "uart0_grp" };
328static const char * const southwest_uart1_groups[] = { "uart1_grp" };
329static const char * const southwest_uart2_groups[] = { "uart2_grp" };
330static const char * const southwest_hda_groups[] = { "hda_grp" };
331static const char * const southwest_lpe_groups[] = { "lpe_grp" };
332static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
333static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
334static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
335static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
336static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
337static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
338static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
339static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
340static const char * const southwest_spi3_groups[] = { "spi3_grp" };
341
342/*
343 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
344 * enabled only as GPIOs.
345 */
5458b7ce 346static const struct intel_function southwest_functions[] = {
6e08d6bb
MW		 347 FUNCTION("uart0", southwest_uart0_groups),
348 FUNCTION("uart1", southwest_uart1_groups),
349 FUNCTION("uart2", southwest_uart2_groups),
350 FUNCTION("hda", southwest_hda_groups),
351 FUNCTION("lpe", southwest_lpe_groups),
352 FUNCTION("i2c0", southwest_i2c0_groups),
353 FUNCTION("i2c1", southwest_i2c1_groups),
354 FUNCTION("i2c2", southwest_i2c2_groups),
355 FUNCTION("i2c3", southwest_i2c3_groups),
356 FUNCTION("i2c4", southwest_i2c4_groups),
357 FUNCTION("i2c5", southwest_i2c5_groups),
358 FUNCTION("i2c6", southwest_i2c6_groups),
359 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
360 FUNCTION("spi3", southwest_spi3_groups),
361};
362
363static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
364 GPIO_PINRANGE(0, 7),
365 GPIO_PINRANGE(15, 22),
366 GPIO_PINRANGE(30, 37),
367 GPIO_PINRANGE(45, 52),
368 GPIO_PINRANGE(60, 67),
369 GPIO_PINRANGE(75, 82),
370 GPIO_PINRANGE(90, 97),
371};
372
373static const struct chv_community southwest_community = {
374 .uid = "1",
375 .pins = southwest_pins,
376 .npins = ARRAY_SIZE(southwest_pins),
377 .groups = southwest_groups,
378 .ngroups = ARRAY_SIZE(southwest_groups),
379 .functions = southwest_functions,
380 .nfunctions = ARRAY_SIZE(southwest_functions),
381 .gpio_ranges = southwest_gpio_ranges,
382 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
47c950d1 383 /*
17d49c62 384 * Southwest community can generate GPIO interrupts only for the
47c950d1
MW		 385 * first 8 interrupts. The upper half (8-15) can only be used to
386 * trigger GPEs.
387 */
388 .nirqs = 8,
a0b02859 389 .acpi_space_id = 0x91,
6e08d6bb
MW		 390};
391
392static const struct pinctrl_pin_desc north_pins[] = {
393 PINCTRL_PIN(0, "GPIO_DFX_0"),
394 PINCTRL_PIN(1, "GPIO_DFX_3"),
395 PINCTRL_PIN(2, "GPIO_DFX_7"),
396 PINCTRL_PIN(3, "GPIO_DFX_1"),
397 PINCTRL_PIN(4, "GPIO_DFX_5"),
398 PINCTRL_PIN(5, "GPIO_DFX_4"),
399 PINCTRL_PIN(6, "GPIO_DFX_8"),
400 PINCTRL_PIN(7, "GPIO_DFX_2"),
401 PINCTRL_PIN(8, "GPIO_DFX_6"),
402
403 PINCTRL_PIN(15, "GPIO_SUS0"),
404 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
405 PINCTRL_PIN(17, "GPIO_SUS3"),
406 PINCTRL_PIN(18, "GPIO_SUS7"),
407 PINCTRL_PIN(19, "GPIO_SUS1"),
408 PINCTRL_PIN(20, "GPIO_SUS5"),
409 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
410 PINCTRL_PIN(22, "GPIO_SUS4"),
411 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
412 PINCTRL_PIN(24, "GPIO_SUS2"),
413 PINCTRL_PIN(25, "GPIO_SUS6"),
414 PINCTRL_PIN(26, "CX_PREQ_B"),
415 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
416
417 PINCTRL_PIN(30, "TRST_B"),
418 PINCTRL_PIN(31, "TCK"),
419 PINCTRL_PIN(32, "PROCHOT_B"),
420 PINCTRL_PIN(33, "SVIDO_DATA"),
421 PINCTRL_PIN(34, "TMS"),
422 PINCTRL_PIN(35, "CX_PRDY_B_2"),
423 PINCTRL_PIN(36, "TDO_2"),
424 PINCTRL_PIN(37, "CX_PRDY_B"),
425 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
426 PINCTRL_PIN(39, "TDO"),
427 PINCTRL_PIN(40, "SVIDO_CLK"),
428 PINCTRL_PIN(41, "TDI"),
429
430 PINCTRL_PIN(45, "GP_CAMERASB_05"),
431 PINCTRL_PIN(46, "GP_CAMERASB_02"),
432 PINCTRL_PIN(47, "GP_CAMERASB_08"),
433 PINCTRL_PIN(48, "GP_CAMERASB_00"),
434 PINCTRL_PIN(49, "GP_CAMERASB_06"),
435 PINCTRL_PIN(50, "GP_CAMERASB_10"),
436 PINCTRL_PIN(51, "GP_CAMERASB_03"),
437 PINCTRL_PIN(52, "GP_CAMERASB_09"),
438 PINCTRL_PIN(53, "GP_CAMERASB_01"),
439 PINCTRL_PIN(54, "GP_CAMERASB_07"),
440 PINCTRL_PIN(55, "GP_CAMERASB_11"),
441 PINCTRL_PIN(56, "GP_CAMERASB_04"),
442
443 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
444 PINCTRL_PIN(61, "HV_DDI0_HPD"),
445 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
446 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
447 PINCTRL_PIN(64, "HV_DDI1_HPD"),
448 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
449 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
450 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
451 PINCTRL_PIN(68, "HV_DDI2_HPD"),
452 PINCTRL_PIN(69, "PANEL1_VDDEN"),
453 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
454 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
455 PINCTRL_PIN(72, "PANEL0_VDDEN"),
456};
457
458static const struct chv_gpio_pinrange north_gpio_ranges[] = {
459 GPIO_PINRANGE(0, 8),
460 GPIO_PINRANGE(15, 27),
461 GPIO_PINRANGE(30, 41),
462 GPIO_PINRANGE(45, 56),
463 GPIO_PINRANGE(60, 72),
464};
465
466static const struct chv_community north_community = {
467 .uid = "2",
468 .pins = north_pins,
469 .npins = ARRAY_SIZE(north_pins),
470 .gpio_ranges = north_gpio_ranges,
471 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
47c950d1 472 /*
505485a8 473 * North community can generate GPIO interrupts only for the first
47c950d1
MW		 474 * 8 interrupts. The upper half (8-15) can only be used to trigger
475 * GPEs.
476 */
477 .nirqs = 8,
a0b02859 478 .acpi_space_id = 0x92,
6e08d6bb
MW		 479};
480
481static const struct pinctrl_pin_desc east_pins[] = {
482 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
483 PINCTRL_PIN(1, "PMU_BATLOW_B"),
484 PINCTRL_PIN(2, "SUS_STAT_B"),
485 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
486 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
487 PINCTRL_PIN(5, "PMU_PLTRST_B"),
488 PINCTRL_PIN(6, "PMU_SUSCLK"),
489 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
490 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
491 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
492 PINCTRL_PIN(10, "PMU_WAKE_B"),
493 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
494
495 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
496 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
497 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
498 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
499 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
500 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
501 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
502 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
503 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
504 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
505 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
506 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
507};
508
509static const struct chv_gpio_pinrange east_gpio_ranges[] = {
510 GPIO_PINRANGE(0, 11),
511 GPIO_PINRANGE(15, 26),
512};
513
514static const struct chv_community east_community = {
515 .uid = "3",
516 .pins = east_pins,
517 .npins = ARRAY_SIZE(east_pins),
518 .gpio_ranges = east_gpio_ranges,
519 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
47c950d1 520 .nirqs = 16,
a0b02859 521 .acpi_space_id = 0x93,
6e08d6bb
MW		 522};
523
524static const struct pinctrl_pin_desc southeast_pins[] = {
525 PINCTRL_PIN(0, "MF_PLT_CLK0"),
526 PINCTRL_PIN(1, "PWM1"),
527 PINCTRL_PIN(2, "MF_PLT_CLK1"),
528 PINCTRL_PIN(3, "MF_PLT_CLK4"),
529 PINCTRL_PIN(4, "MF_PLT_CLK3"),
530 PINCTRL_PIN(5, "PWM0"),
531 PINCTRL_PIN(6, "MF_PLT_CLK5"),
532 PINCTRL_PIN(7, "MF_PLT_CLK2"),
533
534 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
535 PINCTRL_PIN(16, "SDMMC1_CLK"),
536 PINCTRL_PIN(17, "SDMMC1_D0"),
537 PINCTRL_PIN(18, "SDMMC2_D1"),
538 PINCTRL_PIN(19, "SDMMC2_CLK"),
539 PINCTRL_PIN(20, "SDMMC1_D2"),
540 PINCTRL_PIN(21, "SDMMC2_D2"),
541 PINCTRL_PIN(22, "SDMMC2_CMD"),
542 PINCTRL_PIN(23, "SDMMC1_CMD"),
543 PINCTRL_PIN(24, "SDMMC1_D1"),
544 PINCTRL_PIN(25, "SDMMC2_D0"),
545 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
546
547 PINCTRL_PIN(30, "SDMMC3_D1"),
548 PINCTRL_PIN(31, "SDMMC3_CLK"),
549 PINCTRL_PIN(32, "SDMMC3_D3"),
550 PINCTRL_PIN(33, "SDMMC3_D2"),
551 PINCTRL_PIN(34, "SDMMC3_CMD"),
552 PINCTRL_PIN(35, "SDMMC3_D0"),
553
554 PINCTRL_PIN(45, "MF_LPC_AD2"),
555 PINCTRL_PIN(46, "LPC_CLKRUNB"),
556 PINCTRL_PIN(47, "MF_LPC_AD0"),
557 PINCTRL_PIN(48, "LPC_FRAMEB"),
558 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
559 PINCTRL_PIN(50, "MF_LPC_AD3"),
560 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
561 PINCTRL_PIN(52, "MF_LPC_AD1"),
562
563 PINCTRL_PIN(60, "SPI1_MISO"),
564 PINCTRL_PIN(61, "SPI1_CSO_B"),
565 PINCTRL_PIN(62, "SPI1_CLK"),
566 PINCTRL_PIN(63, "MMC1_D6"),
567 PINCTRL_PIN(64, "SPI1_MOSI"),
568 PINCTRL_PIN(65, "MMC1_D5"),
569 PINCTRL_PIN(66, "SPI1_CS1_B"),
570 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
571 PINCTRL_PIN(68, "MMC1_D7"),
572 PINCTRL_PIN(69, "MMC1_RCLK"),
573
574 PINCTRL_PIN(75, "USB_OC1_B"),
575 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
576 PINCTRL_PIN(77, "GPIO_ALERT"),
577 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
578 PINCTRL_PIN(79, "ILB_SERIRQ"),
579 PINCTRL_PIN(80, "USB_OC0_B"),
580 PINCTRL_PIN(81, "SDMMC3_CD_B"),
581 PINCTRL_PIN(82, "SPKR"),
582 PINCTRL_PIN(83, "SUSPWRDNACK"),
583 PINCTRL_PIN(84, "SPARE_PIN"),
584 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
585};
586
587static const unsigned southeast_pwm0_pins[] = { 5 };
588static const unsigned southeast_pwm1_pins[] = { 1 };
589static const unsigned southeast_sdmmc1_pins[] = {
590 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
591};
592static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
593static const unsigned southeast_sdmmc3_pins[] = {
594 30, 31, 32, 33, 34, 35, 78, 81, 85,
595};
596static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
597static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
598
599static const struct chv_pingroup southeast_groups[] = {
5458b7ce
AS		 600 PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
601 PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
602 PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
603 PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
604 PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
605 PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
606 PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
6e08d6bb
MW		 607};
608
609static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
610static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
611static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
612static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
613static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
614static const char * const southeast_spi1_groups[] = { "spi1_grp" };
615static const char * const southeast_spi2_groups[] = { "spi2_grp" };
616
5458b7ce 617static const struct intel_function southeast_functions[] = {
6e08d6bb
MW		 618 FUNCTION("pwm0", southeast_pwm0_groups),
619 FUNCTION("pwm1", southeast_pwm1_groups),
620 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
621 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
622 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
623 FUNCTION("spi1", southeast_spi1_groups),
624 FUNCTION("spi2", southeast_spi2_groups),
625};
626
627static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
628 GPIO_PINRANGE(0, 7),
629 GPIO_PINRANGE(15, 26),
630 GPIO_PINRANGE(30, 35),
631 GPIO_PINRANGE(45, 52),
632 GPIO_PINRANGE(60, 69),
633 GPIO_PINRANGE(75, 85),
634};
635
636static const struct chv_community southeast_community = {
637 .uid = "4",
638 .pins = southeast_pins,
639 .npins = ARRAY_SIZE(southeast_pins),
640 .groups = southeast_groups,
641 .ngroups = ARRAY_SIZE(southeast_groups),
642 .functions = southeast_functions,
643 .nfunctions = ARRAY_SIZE(southeast_functions),
644 .gpio_ranges = southeast_gpio_ranges,
645 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
47c950d1 646 .nirqs = 16,
a0b02859 647 .acpi_space_id = 0x94,
6e08d6bb
MW		 648};
649
650static const struct chv_community *chv_communities[] = {
651 &southwest_community,
652 &north_community,
653 &east_community,
654 &southeast_community,
655};
656
0bd50d71
DD		 657/*
658 * Lock to serialize register accesses
659 *
660 * Due to a silicon issue, a shared lock must be used to prevent
661 * concurrent accesses across the 4 GPIO controllers.
662 *
663 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
664 * errata #CHT34, for further information.
665 */
666static DEFINE_RAW_SPINLOCK(chv_lock);
667
4e737af8
AS		 668static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
669 unsigned int reg)
6e08d6bb 670{
4e737af8
AS		 671 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
672 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
6e08d6bb
MW		 673
674 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
675 GPIO_REGS_SIZE * pad_no;
676
677 return pctrl->regs + offset + reg;
678}
679
680static void chv_writel(u32 value, void __iomem *reg)
681{
682 writel(value, reg);
683 /* simple readback to confirm the bus transferring done */
684 readl(reg);
685}
686
687/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
4e737af8 688static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
6e08d6bb
MW		 689{
690 void __iomem *reg;
691
692 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
693 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
694}
695
696static int chv_get_groups_count(struct pinctrl_dev *pctldev)
697{
698 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
699
700 return pctrl->community->ngroups;
701}
702
703static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
4e737af8 704 unsigned int group)
6e08d6bb
MW		 705{
706 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
707
708 return pctrl->community->groups[group].name;
709}
710
4e737af8
AS		 711static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
712 const unsigned int **pins, unsigned int *npins)
6e08d6bb
MW		 713{
714 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
715
716 *pins = pctrl->community->groups[group].pins;
717 *npins = pctrl->community->groups[group].npins;
718 return 0;
719}
720
721static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
4e737af8 722 unsigned int offset)
6e08d6bb
MW		 723{
724 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
725 unsigned long flags;
726 u32 ctrl0, ctrl1;
727 bool locked;
728
0bd50d71 729 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 730
731 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
732 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
733 locked = chv_pad_locked(pctrl, offset);
734
0bd50d71 735 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 736
737 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
738 seq_puts(s, "GPIO ");
739 } else {
740 u32 mode;
741
742 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
743 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
744
745 seq_printf(s, "mode %d ", mode);
746 }
747
684373ea 748 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
6e08d6bb
MW		 749
750 if (locked)
751 seq_puts(s, " [LOCKED]");
752}
753
754static const struct pinctrl_ops chv_pinctrl_ops = {
755 .get_groups_count = chv_get_groups_count,
756 .get_group_name = chv_get_group_name,
757 .get_group_pins = chv_get_group_pins,
758 .pin_dbg_show = chv_pin_dbg_show,
759};
760
761static int chv_get_functions_count(struct pinctrl_dev *pctldev)
762{
763 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
764
765 return pctrl->community->nfunctions;
766}
767
768static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
4e737af8 769 unsigned int function)
6e08d6bb
MW		 770{
771 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
772
773 return pctrl->community->functions[function].name;
774}
775
776static int chv_get_function_groups(struct pinctrl_dev *pctldev,
4e737af8 777 unsigned int function,
6e08d6bb 778 const char * const **groups,
4e737af8 779 unsigned int * const ngroups)
6e08d6bb
MW		 780{
781 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
782
783 *groups = pctrl->community->functions[function].groups;
784 *ngroups = pctrl->community->functions[function].ngroups;
785 return 0;
786}
787
4e737af8
AS		 788static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
789 unsigned int function, unsigned int group)
6e08d6bb
MW		 790{
791 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
792 const struct chv_pingroup *grp;
793 unsigned long flags;
794 int i;
795
796 grp = &pctrl->community->groups[group];
797
0bd50d71 798 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 799
800 /* Check first that the pad is not locked */
801 for (i = 0; i < grp->npins; i++) {
802 if (chv_pad_locked(pctrl, grp->pins[i])) {
803 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
804 grp->pins[i]);
0bd50d71 805 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 806 return -EBUSY;
807 }
808 }
809
810 for (i = 0; i < grp->npins; i++) {
811 const struct chv_alternate_function *altfunc = &grp->altfunc;
812 int pin = grp->pins[i];
813 void __iomem *reg;
814 u32 value;
815
816 /* Check if there is pin-specific config */
817 if (grp->overrides) {
818 int j;
819
820 for (j = 0; j < grp->noverrides; j++) {
821 if (grp->overrides[j].pin == pin) {
822 altfunc = &grp->overrides[j];
823 break;
824 }
825 }
826 }
827
828 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
829 value = readl(reg);
830 /* Disable GPIO mode */
831 value &= ~CHV_PADCTRL0_GPIOEN;
832 /* Set to desired mode */
833 value &= ~CHV_PADCTRL0_PMODE_MASK;
834 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
835 chv_writel(value, reg);
836
837 /* Update for invert_oe */
838 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
839 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
840 if (altfunc->invert_oe)
841 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
842 chv_writel(value, reg);
843
844 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
845 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
846 }
847
0bd50d71 848 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 849
850 return 0;
851}
852
b6fb6e11
HG		 853static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
854 unsigned int offset)
855{
856 void __iomem *reg;
857 u32 value;
858
859 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
860 value = readl(reg);
861 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
862 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
863 chv_writel(value, reg);
864}
865
6e08d6bb
MW		 866static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
867 struct pinctrl_gpio_range *range,
4e737af8 868 unsigned int offset)
6e08d6bb
MW		 869{
870 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
871 unsigned long flags;
872 void __iomem *reg;
873 u32 value;
874
0bd50d71 875 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 876
877 if (chv_pad_locked(pctrl, offset)) {
878 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
879 if (!(value & CHV_PADCTRL0_GPIOEN)) {
880 /* Locked so cannot enable */
0bd50d71 881 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 882 return -EBUSY;
883 }
884 } else {
885 int i;
886
887 /* Reset the interrupt mapping */
888 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
889 if (pctrl->intr_lines[i] == offset) {
890 pctrl->intr_lines[i] = 0;
891 break;
892 }
893 }
894
895 /* Disable interrupt generation */
b6fb6e11 896 chv_gpio_clear_triggering(pctrl, offset);
6e08d6bb 897
6e08d6bb 898 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
2479c730
MW		 899 value = readl(reg);
900
901 /*
902 * If the pin is in HiZ mode (both TX and RX buffers are
903 * disabled) we turn it to be input now.
904 */
905 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
906 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
907 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
908 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
909 CHV_PADCTRL0_GPIOCFG_SHIFT;
910 }
911
912 /* Switch to a GPIO mode */
913 value |= CHV_PADCTRL0_GPIOEN;
6e08d6bb
MW		 914 chv_writel(value, reg);
915 }
916
0bd50d71 917 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 918
919 return 0;
920}
921
922static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
923 struct pinctrl_gpio_range *range,
4e737af8 924 unsigned int offset)
6e08d6bb
MW		 925{
926 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
927 unsigned long flags;
6e08d6bb 928
0bd50d71 929 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 930
1adde32a
HG		 931 if (!chv_pad_locked(pctrl, offset))
932 chv_gpio_clear_triggering(pctrl, offset);
6e08d6bb 933
0bd50d71 934 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 935}
936
937static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
938 struct pinctrl_gpio_range *range,
4e737af8 939 unsigned int offset, bool input)
6e08d6bb
MW		 940{
941 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
942 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
943 unsigned long flags;
944 u32 ctrl0;
945
0bd50d71 946 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 947
948 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
949 if (input)
950 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
951 else
952 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
953 chv_writel(ctrl0, reg);
954
0bd50d71 955 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 956
957 return 0;
958}
959
960static const struct pinmux_ops chv_pinmux_ops = {
961 .get_functions_count = chv_get_functions_count,
962 .get_function_name = chv_get_function_name,
963 .get_function_groups = chv_get_function_groups,
964 .set_mux = chv_pinmux_set_mux,
965 .gpio_request_enable = chv_gpio_request_enable,
966 .gpio_disable_free = chv_gpio_disable_free,
967 .gpio_set_direction = chv_gpio_set_direction,
968};
969
4e737af8 970static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
6e08d6bb
MW		 971 unsigned long *config)
972{
973 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
974 enum pin_config_param param = pinconf_to_config_param(*config);
975 unsigned long flags;
976 u32 ctrl0, ctrl1;
977 u16 arg = 0;
978 u32 term;
979
0bd50d71 980 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 981 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
982 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
0bd50d71 983 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 984
985 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
986
987 switch (param) {
988 case PIN_CONFIG_BIAS_DISABLE:
989 if (term)
990 return -EINVAL;
991 break;
992
993 case PIN_CONFIG_BIAS_PULL_UP:
994 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
995 return -EINVAL;
996
997 switch (term) {
998 case CHV_PADCTRL0_TERM_20K:
999 arg = 20000;
1000 break;
1001 case CHV_PADCTRL0_TERM_5K:
1002 arg = 5000;
1003 break;
1004 case CHV_PADCTRL0_TERM_1K:
1005 arg = 1000;
1006 break;
1007 }
1008
1009 break;
1010
1011 case PIN_CONFIG_BIAS_PULL_DOWN:
1012 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1013 return -EINVAL;
1014
1015 switch (term) {
1016 case CHV_PADCTRL0_TERM_20K:
1017 arg = 20000;
1018 break;
1019 case CHV_PADCTRL0_TERM_5K:
1020 arg = 5000;
1021 break;
1022 }
1023
1024 break;
1025
1026 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1027 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1028 return -EINVAL;
1029 break;
1030
1031 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1032 u32 cfg;
1033
1034 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1035 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1036 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1037 return -EINVAL;
1038
1039 break;
1040 }
1041
1042 default:
1043 return -ENOTSUPP;
1044 }
1045
1046 *config = pinconf_to_config_packed(param, arg);
1047 return 0;
1048}
1049
4e737af8 1050static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
58957d2e 1051 enum pin_config_param param, u32 arg)
6e08d6bb
MW		 1052{
1053 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1054 unsigned long flags;
1055 u32 ctrl0, pull;
1056
0bd50d71 1057 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1058 ctrl0 = readl(reg);
1059
1060 switch (param) {
1061 case PIN_CONFIG_BIAS_DISABLE:
1062 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1063 break;
1064
1065 case PIN_CONFIG_BIAS_PULL_UP:
1066 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1067
1068 switch (arg) {
1069 case 1000:
1070 /* For 1k there is only pull up */
1071 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1072 break;
1073 case 5000:
1074 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1075 break;
1076 case 20000:
1077 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1078 break;
1079 default:
0bd50d71 1080 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1081 return -EINVAL;
1082 }
1083
1084 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1085 break;
1086
1087 case PIN_CONFIG_BIAS_PULL_DOWN:
1088 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1089
1090 switch (arg) {
1091 case 5000:
1092 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1093 break;
1094 case 20000:
1095 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1096 break;
1097 default:
0bd50d71 1098 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1099 return -EINVAL;
1100 }
1101
1102 ctrl0 |= pull;
1103 break;
1104
1105 default:
0bd50d71 1106 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1107 return -EINVAL;
1108 }
1109
1110 chv_writel(ctrl0, reg);
0bd50d71 1111 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1112
1113 return 0;
1114}
1115
ccdf81d0
DD		 1116static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1117 bool enable)
1118{
1119 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1120 unsigned long flags;
1121 u32 ctrl1;
1122
1123 raw_spin_lock_irqsave(&chv_lock, flags);
1124 ctrl1 = readl(reg);
1125
1126 if (enable)
1127 ctrl1 |= CHV_PADCTRL1_ODEN;
1128 else
1129 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1130
1131 chv_writel(ctrl1, reg);
1132 raw_spin_unlock_irqrestore(&chv_lock, flags);
1133
1134 return 0;
1135}
1136
4e737af8
AS		 1137static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1138 unsigned long *configs, unsigned int nconfigs)
6e08d6bb
MW		 1139{
1140 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1141 enum pin_config_param param;
1142 int i, ret;
58957d2e 1143 u32 arg;
6e08d6bb
MW		 1144
1145 if (chv_pad_locked(pctrl, pin))
1146 return -EBUSY;
1147
1148 for (i = 0; i < nconfigs; i++) {
1149 param = pinconf_to_config_param(configs[i]);
1150 arg = pinconf_to_config_argument(configs[i]);
1151
1152 switch (param) {
1153 case PIN_CONFIG_BIAS_DISABLE:
1154 case PIN_CONFIG_BIAS_PULL_UP:
1155 case PIN_CONFIG_BIAS_PULL_DOWN:
1156 ret = chv_config_set_pull(pctrl, pin, param, arg);
1157 if (ret)
1158 return ret;
1159 break;
1160
ccdf81d0
DD		 1161 case PIN_CONFIG_DRIVE_PUSH_PULL:
1162 ret = chv_config_set_oden(pctrl, pin, false);
1163 if (ret)
1164 return ret;
1165 break;
1166
1167 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1168 ret = chv_config_set_oden(pctrl, pin, true);
1169 if (ret)
1170 return ret;
1171 break;
1172
6e08d6bb
MW		 1173 default:
1174 return -ENOTSUPP;
1175 }
1176
1177 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1178 param, arg);
1179 }
1180
1181 return 0;
1182}
1183
77401d7f
DD		 1184static int chv_config_group_get(struct pinctrl_dev *pctldev,
1185 unsigned int group,
1186 unsigned long *config)
1187{
1188 const unsigned int *pins;
1189 unsigned int npins;
1190 int ret;
1191
1192 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1193 if (ret)
1194 return ret;
1195
1196 ret = chv_config_get(pctldev, pins[0], config);
1197 if (ret)
1198 return ret;
1199
1200 return 0;
1201}
1202
1203static int chv_config_group_set(struct pinctrl_dev *pctldev,
1204 unsigned int group, unsigned long *configs,
1205 unsigned int num_configs)
1206{
1207 const unsigned int *pins;
1208 unsigned int npins;
1209 int i, ret;
1210
1211 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1212 if (ret)
1213 return ret;
1214
1215 for (i = 0; i < npins; i++) {
1216 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1217 if (ret)
1218 return ret;
1219 }
1220
1221 return 0;
1222}
1223
6e08d6bb
MW		 1224static const struct pinconf_ops chv_pinconf_ops = {
1225 .is_generic = true,
1226 .pin_config_set = chv_config_set,
1227 .pin_config_get = chv_config_get,
77401d7f
DD		 1228 .pin_config_group_get = chv_config_group_get,
1229 .pin_config_group_set = chv_config_group_set,
6e08d6bb
MW		 1230};
1231
1232static struct pinctrl_desc chv_pinctrl_desc = {
1233 .pctlops = &chv_pinctrl_ops,
1234 .pmxops = &chv_pinmux_ops,
1235 .confops = &chv_pinconf_ops,
1236 .owner = THIS_MODULE,
1237};
1238
4e737af8 1239static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
6e08d6bb 1240{
0587d3db 1241 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
4585b000 1242 unsigned long flags;
6e08d6bb
MW		 1243 u32 ctrl0, cfg;
1244
0bd50d71 1245 raw_spin_lock_irqsave(&chv_lock, flags);
03c4749d 1246 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
0bd50d71 1247 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1248
1249 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1250 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1251
1252 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1253 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1254 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1255}
1256
4e737af8 1257static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
6e08d6bb 1258{
0587d3db 1259 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb
MW		 1260 unsigned long flags;
1261 void __iomem *reg;
1262 u32 ctrl0;
1263
0bd50d71 1264 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 1265
03c4749d 1266 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
6e08d6bb
MW		 1267 ctrl0 = readl(reg);
1268
1269 if (value)
1270 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1271 else
1272 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1273
1274 chv_writel(ctrl0, reg);
1275
0bd50d71 1276 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1277}
1278
4e737af8 1279static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
6e08d6bb 1280{
0587d3db 1281 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
6e08d6bb 1282 u32 ctrl0, direction;
4585b000 1283 unsigned long flags;
6e08d6bb 1284
0bd50d71 1285 raw_spin_lock_irqsave(&chv_lock, flags);
03c4749d 1286 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
0bd50d71 1287 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1288
1289 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1290 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1291
90a1eb18
MV		 1292 if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1293 return GPIO_LINE_DIRECTION_OUT;
1294
1295 return GPIO_LINE_DIRECTION_IN;
6e08d6bb
MW		 1296}
1297
4e737af8 1298static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
6e08d6bb
MW		 1299{
1300 return pinctrl_gpio_direction_input(chip->base + offset);
1301}
1302
4e737af8 1303static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
6e08d6bb
MW		 1304 int value)
1305{
549e783f 1306 chv_gpio_set(chip, offset, value);
6e08d6bb
MW		 1307 return pinctrl_gpio_direction_output(chip->base + offset);
1308}
1309
1310static const struct gpio_chip chv_gpio_chip = {
1311 .owner = THIS_MODULE,
98c85d58
JG		 1312 .request = gpiochip_generic_request,
1313 .free = gpiochip_generic_free,
6e08d6bb
MW		 1314 .get_direction = chv_gpio_get_direction,
1315 .direction_input = chv_gpio_direction_input,
1316 .direction_output = chv_gpio_direction_output,
1317 .get = chv_gpio_get,
1318 .set = chv_gpio_set,
1319};
1320
1321static void chv_gpio_irq_ack(struct irq_data *d)
1322{
1323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1324 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
03c4749d 1325 int pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1326 u32 intr_line;
1327
0bd50d71 1328 raw_spin_lock(&chv_lock);
6e08d6bb
MW		 1329
1330 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1331 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1332 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1333 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1334
0bd50d71 1335 raw_spin_unlock(&chv_lock);
6e08d6bb
MW		 1336}
1337
1338static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1339{
1340 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1341 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
03c4749d 1342 int pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1343 u32 value, intr_line;
1344 unsigned long flags;
1345
0bd50d71 1346 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1347
1348 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1349 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1350 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1351
1352 value = readl(pctrl->regs + CHV_INTMASK);
1353 if (mask)
1354 value &= ~BIT(intr_line);
1355 else
1356 value |= BIT(intr_line);
1357 chv_writel(value, pctrl->regs + CHV_INTMASK);
1358
0bd50d71 1359 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1360}
1361
1362static void chv_gpio_irq_mask(struct irq_data *d)
1363{
1364 chv_gpio_irq_mask_unmask(d, true);
1365}
1366
1367static void chv_gpio_irq_unmask(struct irq_data *d)
1368{
1369 chv_gpio_irq_mask_unmask(d, false);
1370}
1371
e6c906de
MW		 1372static unsigned chv_gpio_irq_startup(struct irq_data *d)
1373{
1374 /*
1375 * Check if the interrupt has been requested with 0 as triggering
1376 * type. In that case it is assumed that the current values
1377 * programmed to the hardware are used (e.g BIOS configured
1378 * defaults).
1379 *
1380 * In that case ->irq_set_type() will never be called so we need to
1381 * read back the values from hardware now, set correct flow handler
1382 * and update mappings before the interrupt is being used.
1383 */
1384 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1385 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1386 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
4e737af8 1387 unsigned int pin = irqd_to_hwirq(d);
e6c906de
MW		 1388 irq_flow_handler_t handler;
1389 unsigned long flags;
1390 u32 intsel, value;
1391
0bd50d71 1392 raw_spin_lock_irqsave(&chv_lock, flags);
e6c906de
MW		 1393 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1394 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1395 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1396
1397 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1398 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1399 handler = handle_level_irq;
1400 else
1401 handler = handle_edge_irq;
1402
e6c906de 1403 if (!pctrl->intr_lines[intsel]) {
a4e3f783 1404 irq_set_handler_locked(d, handler);
03c4749d 1405 pctrl->intr_lines[intsel] = pin;
e6c906de 1406 }
0bd50d71 1407 raw_spin_unlock_irqrestore(&chv_lock, flags);
e6c906de
MW		 1408 }
1409
1410 chv_gpio_irq_unmask(d);
1411 return 0;
1412}
1413
4e737af8 1414static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
6e08d6bb
MW		 1415{
1416 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0587d3db 1417 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
4e737af8 1418 unsigned int pin = irqd_to_hwirq(d);
6e08d6bb
MW		 1419 unsigned long flags;
1420 u32 value;
1421
0bd50d71 1422 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb
MW		 1423
1424 /*
1425 * Pins which can be used as shared interrupt are configured in
1426 * BIOS. Driver trusts BIOS configurations and assigns different
1427 * handler according to the irq type.
1428 *
1429 * Driver needs to save the mapping between each pin and
1430 * its interrupt line.
1431 * 1. If the pin cfg is locked in BIOS:
1432 * Trust BIOS has programmed IntWakeCfg bits correctly,
1433 * driver just needs to save the mapping.
1434 * 2. If the pin cfg is not locked in BIOS:
1435 * Driver programs the IntWakeCfg bits and save the mapping.
1436 */
1437 if (!chv_pad_locked(pctrl, pin)) {
1438 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1439
1440 value = readl(reg);
1441 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1442 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1443
1444 if (type & IRQ_TYPE_EDGE_BOTH) {
1445 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1446 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1447 else if (type & IRQ_TYPE_EDGE_RISING)
1448 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1449 else if (type & IRQ_TYPE_EDGE_FALLING)
1450 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1451 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1452 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1453 if (type & IRQ_TYPE_LEVEL_LOW)
1454 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1455 }
1456
1457 chv_writel(value, reg);
1458 }
1459
1460 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1461 value &= CHV_PADCTRL0_INTSEL_MASK;
1462 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1463
03c4749d 1464 pctrl->intr_lines[value] = pin;
6e08d6bb
MW		 1465
1466 if (type & IRQ_TYPE_EDGE_BOTH)
a4e3f783 1467 irq_set_handler_locked(d, handle_edge_irq);
6e08d6bb 1468 else if (type & IRQ_TYPE_LEVEL_MASK)
a4e3f783 1469 irq_set_handler_locked(d, handle_level_irq);
6e08d6bb 1470
0bd50d71 1471 raw_spin_unlock_irqrestore(&chv_lock, flags);
6e08d6bb
MW		 1472
1473 return 0;
1474}
1475
bd0b9ac4 1476static void chv_gpio_irq_handler(struct irq_desc *desc)
6e08d6bb
MW		 1477{
1478 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0587d3db 1479 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
5663bb27 1480 struct irq_chip *chip = irq_desc_get_chip(desc);
6e08d6bb 1481 unsigned long pending;
69388e15 1482 unsigned long flags;
6e08d6bb
MW		 1483 u32 intr_line;
1484
1485 chained_irq_enter(chip, desc);
1486
69388e15 1487 raw_spin_lock_irqsave(&chv_lock, flags);
6e08d6bb 1488 pending = readl(pctrl->regs + CHV_INTSTAT);
69388e15
GK		 1489 raw_spin_unlock_irqrestore(&chv_lock, flags);
1490
47c950d1 1491 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
8ae93b5e 1492 unsigned int irq, offset;
6e08d6bb
MW		 1493
1494 offset = pctrl->intr_lines[intr_line];
f0fbe7bc 1495 irq = irq_find_mapping(gc->irq.domain, offset);
6e08d6bb
MW		 1496 generic_handle_irq(irq);
1497 }
1498
1499 chained_irq_exit(chip, desc);
1500}
1501
70365027
MW		 1502/*
1503 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1504 * tables. Since we leave GPIOs that are not capable of generating
1505 * interrupts out of the irqdomain the numbering will be different and
1506 * cause devices using the hardcoded IRQ numbers fail. In order not to
1507 * break such machines we will only mask pins from irqdomain if the machine
1508 * is not listed below.
1509 */
1510static const struct dmi_system_id chv_no_valid_mask[] = {
2a8209fa 1511 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
70365027 1512 {
2a8209fa 1513 .ident = "Intel_Strago based Chromebooks (All models)",
70365027
MW		 1514 .matches = {
1515 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
2a8209fa
MW		 1516 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1517 },
1518 },
2d80bd3f
AS		 1519 {
1520 .ident = "HP Chromebook 11 G5 (Setzer)",
1521 .matches = {
1522 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1523 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1524 },
1525 },
2a8209fa
MW		 1526 {
1527 .ident = "Acer Chromebook R11 (Cyan)",
1528 .matches = {
1529 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1530 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1531 },
1532 },
1533 {
1534 .ident = "Samsung Chromebook 3 (Celes)",
1535 .matches = {
1536 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1537 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
70365027 1538 },
a9de080b
WY		 1539 },
1540 {}
70365027
MW		 1541};
1542
5fbe5b58
LW		 1543static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1544 unsigned long *valid_mask,
1545 unsigned int ngpios)
1546{
1547 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1548 const struct chv_community *community = pctrl->community;
1549 int i;
1550
1551 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1552 for (i = 0; i < community->npins; i++) {
1553 const struct pinctrl_pin_desc *desc;
1554 u32 intsel;
1555
1556 desc = &community->pins[i];
1557
1558 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1559 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1560 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1561
1562 if (intsel >= community->nirqs)
37398985 1563 clear_bit(desc->number, valid_mask);
5fbe5b58
LW		 1564 }
1565}
1566
82d9beb4
HG		 1567static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1568{
1569 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1570
1571 /*
1572 * The same set of machines in chv_no_valid_mask[] have incorrectly
1573 * configured GPIOs that generate spurious interrupts so we use
1574 * this same list to apply another quirk for them.
1575 *
1576 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1577 */
1578 if (!pctrl->chip.irq.init_valid_mask) {
1579 /*
1580 * Mask all interrupts the community is able to generate
1581 * but leave the ones that can only generate GPEs unmasked.
1582 */
1583 chv_writel(GENMASK(31, pctrl->community->nirqs),
1584 pctrl->regs + CHV_INTMASK);
1585 }
1586
1587 /* Clear all interrupts */
1588 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1589
1590 return 0;
1591}
1592
bd90633a
HG		 1593static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1594{
1595 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1596 const struct chv_community *community = pctrl->community;
1597 const struct chv_gpio_pinrange *range;
1598 int ret, i;
1599
1600 for (i = 0; i < community->ngpio_ranges; i++) {
1601 range = &community->gpio_ranges[i];
1602 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1603 range->base, range->base,
1604 range->npins);
1605 if (ret) {
1606 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1607 return ret;
1608 }
1609 }
1610
1611 return 0;
1612}
1613
6e08d6bb
MW		 1614static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1615{
1616 const struct chv_gpio_pinrange *range;
1617 struct gpio_chip *chip = &pctrl->chip;
70365027 1618 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
03c4749d
MW		 1619 const struct chv_community *community = pctrl->community;
1620 int ret, i, irq_base;
6e08d6bb
MW		 1621
1622 *chip = chv_gpio_chip;
1623
03c4749d 1624 chip->ngpio = community->pins[community->npins - 1].number + 1;
6e08d6bb 1625 chip->label = dev_name(pctrl->dev);
bd90633a 1626 chip->add_pin_ranges = chv_gpio_add_pin_ranges;
58383c78 1627 chip->parent = pctrl->dev;
6e08d6bb 1628 chip->base = -1;
6e08d6bb 1629
b9a19bdb
HG		 1630 pctrl->irq = irq;
1631 pctrl->irqchip.name = "chv-gpio";
1632 pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1633 pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1634 pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1635 pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1636 pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1637 pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
6e08d6bb 1638
b9a19bdb
HG		 1639 chip->irq.chip = &pctrl->irqchip;
1640 chip->irq.init_hw = chv_gpio_irq_init_hw;
1641 chip->irq.parent_handler = chv_gpio_irq_handler;
1642 chip->irq.num_parents = 1;
1643 chip->irq.parents = &pctrl->irq;
1644 chip->irq.default_type = IRQ_TYPE_NONE;
1645 chip->irq.handler = handle_bad_irq;
1646 if (need_valid_mask) {
1647 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1648 } else {
845e405e 1649 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
83b9dc11 1650 community->npins, NUMA_NO_NODE);
845e405e
GS		 1651 if (irq_base < 0) {
1652 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1653 return irq_base;
1654 }
845e405e
GS		 1655 }
1656
b9a19bdb 1657 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
6e08d6bb 1658 if (ret) {
b9a19bdb 1659 dev_err(pctrl->dev, "Failed to register gpiochip\n");
d1073418 1660 return ret;
6e08d6bb
MW		 1661 }
1662
83b9dc11
MW		 1663 if (!need_valid_mask) {
1664 for (i = 0; i < community->ngpio_ranges; i++) {
1665 range = &community->gpio_ranges[i];
1666
1667 irq_domain_associate_many(chip->irq.domain, irq_base,
1668 range->base, range->npins);
1669 irq_base += range->npins;
1670 }
1671 }
1672
6e08d6bb 1673 return 0;
6e08d6bb
MW		 1674}
1675
a0b02859
HG		 1676static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1677 acpi_physical_address address, u32 bits, u64 *value,
1678 void *handler_context, void *region_context)
1679{
1680 struct chv_pinctrl *pctrl = region_context;
1681 unsigned long flags;
1682 acpi_status ret = AE_OK;
1683
1684 raw_spin_lock_irqsave(&chv_lock, flags);
1685
1686 if (function == ACPI_WRITE)
1687 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1688 else if (function == ACPI_READ)
1689 *value = readl(pctrl->regs + (u32)address);
1690 else
1691 ret = AE_BAD_PARAMETER;
1692
1693 raw_spin_unlock_irqrestore(&chv_lock, flags);
1694
1695 return ret;
1696}
1697
6e08d6bb
MW		 1698static int chv_pinctrl_probe(struct platform_device *pdev)
1699{
1700 struct chv_pinctrl *pctrl;
1701 struct acpi_device *adev;
a0b02859 1702 acpi_status status;
6e08d6bb
MW		 1703 int ret, irq, i;
1704
1705 adev = ACPI_COMPANION(&pdev->dev);
1706 if (!adev)
1707 return -ENODEV;
1708
1709 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1710 if (!pctrl)
1711 return -ENOMEM;
1712
1713 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1714 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1715 pctrl->community = chv_communities[i];
1716 break;
1717 }
1718 if (i == ARRAY_SIZE(chv_communities))
1719 return -ENODEV;
1720
6e08d6bb
MW		 1721 pctrl->dev = &pdev->dev;
1722
9eb457b5
MW		 1723#ifdef CONFIG_PM_SLEEP
1724 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1725 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1726 GFP_KERNEL);
1727 if (!pctrl->saved_pin_context)
1728 return -ENOMEM;
1729#endif
1730
a86f12b2 1731 pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
6e08d6bb
MW		 1732 if (IS_ERR(pctrl->regs))
1733 return PTR_ERR(pctrl->regs);
1734
1735 irq = platform_get_irq(pdev, 0);
57afe3ea 1736 if (irq < 0)
6e08d6bb 1737 return irq;
6e08d6bb
MW		 1738
1739 pctrl->pctldesc = chv_pinctrl_desc;
1740 pctrl->pctldesc.name = dev_name(&pdev->dev);
1741 pctrl->pctldesc.pins = pctrl->community->pins;
1742 pctrl->pctldesc.npins = pctrl->community->npins;
1743
7cf061fa
LD		 1744 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1745 pctrl);
323de9ef 1746 if (IS_ERR(pctrl->pctldev)) {
6e08d6bb 1747 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
323de9ef 1748 return PTR_ERR(pctrl->pctldev);
6e08d6bb
MW		 1749 }
1750
1751 ret = chv_gpio_probe(pctrl, irq);
7cf061fa 1752 if (ret)
6e08d6bb 1753 return ret;
6e08d6bb 1754
a0b02859
HG		 1755 status = acpi_install_address_space_handler(adev->handle,
1756 pctrl->community->acpi_space_id,
1757 chv_pinctrl_mmio_access_handler,
1758 NULL, pctrl);
1759 if (ACPI_FAILURE(status))
1760 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1761
6e08d6bb
MW		 1762 platform_set_drvdata(pdev, pctrl);
1763
1764 return 0;
1765}
1766
a0b02859
HG		 1767static int chv_pinctrl_remove(struct platform_device *pdev)
1768{
1769 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1770
1771 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1772 pctrl->community->acpi_space_id,
1773 chv_pinctrl_mmio_access_handler);
1774
1775 return 0;
1776}
1777
9eb457b5 1778#ifdef CONFIG_PM_SLEEP
d2cdf5dc 1779static int chv_pinctrl_suspend_noirq(struct device *dev)
9eb457b5 1780{
a4833c60 1781 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
56211121 1782 unsigned long flags;
9eb457b5
MW		 1783 int i;
1784
56211121
MW		 1785 raw_spin_lock_irqsave(&chv_lock, flags);
1786
9eb457b5
MW		 1787 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1788
1789 for (i = 0; i < pctrl->community->npins; i++) {
1790 const struct pinctrl_pin_desc *desc;
1791 struct chv_pin_context *ctx;
1792 void __iomem *reg;
1793
1794 desc = &pctrl->community->pins[i];
1795 if (chv_pad_locked(pctrl, desc->number))
1796 continue;
1797
1798 ctx = &pctrl->saved_pin_context[i];
1799
1800 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1801 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1802
1803 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1804 ctx->padctrl1 = readl(reg);
1805 }
1806
56211121
MW		 1807 raw_spin_unlock_irqrestore(&chv_lock, flags);
1808
9eb457b5
MW		 1809 return 0;
1810}
1811
d2cdf5dc 1812static int chv_pinctrl_resume_noirq(struct device *dev)
9eb457b5 1813{
a4833c60 1814 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
56211121 1815 unsigned long flags;
9eb457b5
MW		 1816 int i;
1817
56211121
MW		 1818 raw_spin_lock_irqsave(&chv_lock, flags);
1819
9eb457b5
MW		 1820 /*
1821 * Mask all interrupts before restoring per-pin configuration
1822 * registers because we don't know in which state BIOS left them
1823 * upon exiting suspend.
1824 */
1825 chv_writel(0, pctrl->regs + CHV_INTMASK);
1826
1827 for (i = 0; i < pctrl->community->npins; i++) {
1828 const struct pinctrl_pin_desc *desc;
1829 const struct chv_pin_context *ctx;
1830 void __iomem *reg;
1831 u32 val;
1832
1833 desc = &pctrl->community->pins[i];
1834 if (chv_pad_locked(pctrl, desc->number))
1835 continue;
1836
1837 ctx = &pctrl->saved_pin_context[i];
1838
1839 /* Only restore if our saved state differs from the current */
1840 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1841 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1842 if (ctx->padctrl0 != val) {
1843 chv_writel(ctx->padctrl0, reg);
1844 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1845 desc->number, readl(reg));
1846 }
1847
1848 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1849 val = readl(reg);
1850 if (ctx->padctrl1 != val) {
1851 chv_writel(ctx->padctrl1, reg);
1852 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1853 desc->number, readl(reg));
1854 }
1855 }
1856
1857 /*
1858 * Now that all pins are restored to known state, we can restore
1859 * the interrupt mask register as well.
1860 */
1861 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1862 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1863
56211121
MW		 1864 raw_spin_unlock_irqrestore(&chv_lock, flags);
1865
9eb457b5
MW		 1866 return 0;
1867}
1868#endif
1869
1870static const struct dev_pm_ops chv_pinctrl_pm_ops = {
d2cdf5dc
MW		 1871 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1872 chv_pinctrl_resume_noirq)
9eb457b5
MW		 1873};
1874
6e08d6bb
MW		 1875static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1876 { "INT33FF" },
1877 { }
1878};
1879MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1880
1881static struct platform_driver chv_pinctrl_driver = {
1882 .probe = chv_pinctrl_probe,
a0b02859 1883 .remove = chv_pinctrl_remove,
6e08d6bb
MW		 1884 .driver = {
1885 .name = "cherryview-pinctrl",
9eb457b5 1886 .pm = &chv_pinctrl_pm_ops,
6e08d6bb
MW		 1887 .acpi_match_table = chv_pinctrl_acpi_match,
1888 },
1889};
1890
1891static int __init chv_pinctrl_init(void)
1892{
1893 return platform_driver_register(&chv_pinctrl_driver);
1894}
1895subsys_initcall(chv_pinctrl_init);
1896
1897static void __exit chv_pinctrl_exit(void)
1898{
1899 platform_driver_unregister(&chv_pinctrl_driver);
1900}
1901module_exit(chv_pinctrl_exit);
1902
1903MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1904MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1905MODULE_LICENSE("GPL v2");
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