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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / pinctrl / mediatek / pinctrl-paris.c
CommitLineData
80525098
ZT		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
5 *
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
10 */
11
22d7fe49 12#include <linux/gpio/driver.h>
80525098
ZT		 13#include <dt-bindings/pinctrl/mt65xx.h>
14#include "pinctrl-paris.h"
15
16#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
17
18/* Custom pinconf parameters */
19#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
20#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
5e73de34 23#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
80525098
ZT		 24
25static const struct pinconf_generic_params mtk_custom_bindings[] = {
26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
5e73de34 30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
80525098
ZT		 31};
32
33#ifdef CONFIG_DEBUG_FS
34static const struct pin_config_item mtk_conf_items[] = {
35 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
5e73de34 39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
80525098
ZT		 40};
41#endif
42
43static const char * const mtk_gpio_functions[] = {
44 "func0", "func1", "func2", "func3",
45 "func4", "func5", "func6", "func7",
46 "func8", "func9", "func10", "func11",
47 "func12", "func13", "func14", "func15",
48};
49
50static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
51 struct pinctrl_gpio_range *range,
52 unsigned int pin)
53{
54 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
55 const struct mtk_pin_desc *desc;
56
57 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
58
59 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
60 hw->soc->gpio_m);
61}
62
63static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
64 struct pinctrl_gpio_range *range,
65 unsigned int pin, bool input)
66{
67 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
68 const struct mtk_pin_desc *desc;
69
70 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
71
72 /* hardware would take 0 as input direction */
73 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
74}
75
76static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
77 unsigned int pin, unsigned long *config)
78{
79 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
80 u32 param = pinconf_to_config_param(*config);
cafe19db 81 int pullup, err, reg, ret = 1;
80525098
ZT		 82 const struct mtk_pin_desc *desc;
83
3599cc52
LH		 84 if (pin >= hw->soc->npins) {
85 err = -EINVAL;
86 goto out;
87 }
80525098
ZT		 88 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
89
90 switch (param) {
91 case PIN_CONFIG_BIAS_DISABLE:
80525098 92 case PIN_CONFIG_BIAS_PULL_UP:
80525098 93 case PIN_CONFIG_BIAS_PULL_DOWN:
cafe19db
LH		 94 if (hw->soc->bias_get_combo) {
95 err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
96 if (err)
97 goto out;
98 if (param == PIN_CONFIG_BIAS_DISABLE) {
99 if (ret == MTK_PUPD_SET_R1R0_00)
100 ret = MTK_DISABLE;
101 } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
102 /* When desire to get pull-up value, return
103 * error if current setting is pull-down
104 */
105 if (!pullup)
106 err = -EINVAL;
107 } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
108 /* When desire to get pull-down value, return
109 * error if current setting is pull-up
110 */
111 if (pullup)
112 err = -EINVAL;
113 }
114 } else {
3599cc52 115 err = -ENOTSUPP;
cafe19db 116 }
80525098
ZT		 117 break;
118 case PIN_CONFIG_SLEW_RATE:
1bea6afb 119 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
80525098
ZT		 120 break;
121 case PIN_CONFIG_INPUT_ENABLE:
122 case PIN_CONFIG_OUTPUT_ENABLE:
1bea6afb 123 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
80525098 124 if (err)
3599cc52
LH		 125 goto out;
126 /* CONFIG Current direction return value
127 * ------------- ----------------- ----------------------
128 * OUTPUT_ENABLE output 1 (= HW value)
129 * input 0 (= HW value)
130 * INPUT_ENABLE output 0 (= reverse HW value)
131 * input 1 (= reverse HW value)
132 */
133 if (param == PIN_CONFIG_INPUT_ENABLE)
1bea6afb 134 ret = !ret;
80525098
ZT		 135
136 break;
137 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1bea6afb 138 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
80525098 139 if (err)
1bea6afb
LH		 140 goto out;
141 /* return error when in output mode
142 * because schmitt trigger only work in input mode
143 */
144 if (ret) {
145 err = -EINVAL;
146 goto out;
147 }
80525098 148
1bea6afb 149 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
80525098
ZT		 150
151 break;
152 case PIN_CONFIG_DRIVE_STRENGTH:
3599cc52 153 if (hw->soc->drive_get)
80525098 154 err = hw->soc->drive_get(hw, desc, &ret);
3599cc52 155 else
80525098 156 err = -ENOTSUPP;
80525098
ZT		 157 break;
158 case MTK_PIN_CONFIG_TDSEL:
159 case MTK_PIN_CONFIG_RDSEL:
160 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
161 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
1bea6afb 162 err = mtk_hw_get_value(hw, desc, reg, &ret);
80525098
ZT		 163 break;
164 case MTK_PIN_CONFIG_PU_ADV:
165 case MTK_PIN_CONFIG_PD_ADV:
166 if (hw->soc->adv_pull_get) {
80525098
ZT		 167 pullup = param == MTK_PIN_CONFIG_PU_ADV;
168 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
3599cc52
LH		 169 } else
170 err = -ENOTSUPP;
80525098 171 break;
5e73de34 172 case MTK_PIN_CONFIG_DRV_ADV:
3599cc52 173 if (hw->soc->adv_drive_get)
5e73de34 174 err = hw->soc->adv_drive_get(hw, desc, &ret);
3599cc52
LH		 175 else
176 err = -ENOTSUPP;
5e73de34 177 break;
80525098 178 default:
3599cc52 179 err = -ENOTSUPP;
80525098
ZT		 180 }
181
3599cc52
LH		 182out:
183 if (!err)
184 *config = pinconf_to_config_packed(param, ret);
80525098 185
3599cc52 186 return err;
80525098
ZT		 187}
188
189static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
190 enum pin_config_param param,
191 enum pin_config_param arg)
192{
193 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
194 const struct mtk_pin_desc *desc;
195 int err = 0;
196 u32 reg;
197
3de7deef
LH		 198 if (pin >= hw->soc->npins) {
199 err = -EINVAL;
200 goto err;
201 }
80525098
ZT		 202 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
203
204 switch ((u32)param) {
205 case PIN_CONFIG_BIAS_DISABLE:
cafe19db
LH		 206 if (hw->soc->bias_set_combo)
207 err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
3599cc52
LH		 208 else
209 err = -ENOTSUPP;
80525098
ZT		 210 break;
211 case PIN_CONFIG_BIAS_PULL_UP:
cafe19db
LH		 212 if (hw->soc->bias_set_combo)
213 err = hw->soc->bias_set_combo(hw, desc, 1, arg);
3599cc52
LH		 214 else
215 err = -ENOTSUPP;
80525098
ZT		 216 break;
217 case PIN_CONFIG_BIAS_PULL_DOWN:
cafe19db
LH		 218 if (hw->soc->bias_set_combo)
219 err = hw->soc->bias_set_combo(hw, desc, 0, arg);
3599cc52
LH		 220 else
221 err = -ENOTSUPP;
80525098
ZT		 222 break;
223 case PIN_CONFIG_OUTPUT_ENABLE:
224 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
225 MTK_DISABLE);
3599cc52
LH		 226 /* Keep set direction to consider the case that a GPIO pin
227 * does not have SMT control
228 */
229 if (err != -ENOTSUPP)
80525098
ZT		 230 goto err;
231
232 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
233 MTK_OUTPUT);
80525098
ZT		 234 break;
235 case PIN_CONFIG_INPUT_ENABLE:
3599cc52
LH		 236 /* regard all non-zero value as enable */
237 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
238 if (err)
239 goto err;
80525098
ZT		 240
241 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
242 MTK_INPUT);
80525098
ZT		 243 break;
244 case PIN_CONFIG_SLEW_RATE:
3599cc52
LH		 245 /* regard all non-zero value as enable */
246 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
80525098
ZT		 247 break;
248 case PIN_CONFIG_OUTPUT:
249 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
250 MTK_OUTPUT);
251 if (err)
252 goto err;
253
254 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
255 arg);
80525098 256 break;
3599cc52 257 case PIN_CONFIG_INPUT_SCHMITT:
80525098
ZT		 258 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
259 /* arg = 1: Input mode & SMT enable ;
260 * arg = 0: Output mode & SMT disable
261 */
3599cc52 262 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
80525098
ZT		 263 if (err)
264 goto err;
265
3599cc52 266 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
80525098
ZT		 267 break;
268 case PIN_CONFIG_DRIVE_STRENGTH:
3599cc52 269 if (hw->soc->drive_set)
80525098 270 err = hw->soc->drive_set(hw, desc, arg);
3599cc52
LH		 271 else
272 err = -ENOTSUPP;
80525098
ZT		 273 break;
274 case MTK_PIN_CONFIG_TDSEL:
275 case MTK_PIN_CONFIG_RDSEL:
276 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
277 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
80525098 278 err = mtk_hw_set_value(hw, desc, reg, arg);
80525098
ZT		 279 break;
280 case MTK_PIN_CONFIG_PU_ADV:
281 case MTK_PIN_CONFIG_PD_ADV:
282 if (hw->soc->adv_pull_set) {
283 bool pullup;
284
285 pullup = param == MTK_PIN_CONFIG_PU_ADV;
286 err = hw->soc->adv_pull_set(hw, desc, pullup,
287 arg);
3599cc52
LH		 288 } else
289 err = -ENOTSUPP;
80525098 290 break;
5e73de34 291 case MTK_PIN_CONFIG_DRV_ADV:
3599cc52 292 if (hw->soc->adv_drive_set)
5e73de34 293 err = hw->soc->adv_drive_set(hw, desc, arg);
3599cc52
LH		 294 else
295 err = -ENOTSUPP;
5e73de34 296 break;
80525098
ZT		 297 default:
298 err = -ENOTSUPP;
299 }
300
301err:
302 return err;
303}
304
305static struct mtk_pinctrl_group *
306mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
307{
308 int i;
309
310 for (i = 0; i < hw->soc->ngrps; i++) {
311 struct mtk_pinctrl_group *grp = hw->groups + i;
312
313 if (grp->pin == pin)
314 return grp;
315 }
316
317 return NULL;
318}
319
320static const struct mtk_func_desc *
321mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
322{
323 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
324 const struct mtk_func_desc *func = pin->funcs;
325
326 while (func && func->name) {
327 if (func->muxval == fnum)
328 return func;
329 func++;
330 }
331
332 return NULL;
333}
334
335static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
336 u32 fnum)
337{
338 int i;
339
340 for (i = 0; i < hw->soc->npins; i++) {
341 const struct mtk_pin_desc *pin = hw->soc->pins + i;
342
343 if (pin->number == pin_num) {
344 const struct mtk_func_desc *func = pin->funcs;
345
346 while (func && func->name) {
347 if (func->muxval == fnum)
348 return true;
349 func++;
350 }
351
352 break;
353 }
354 }
355
356 return false;
357}
358
359static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
360 u32 pin, u32 fnum,
361 struct mtk_pinctrl_group *grp,
362 struct pinctrl_map **map,
363 unsigned *reserved_maps,
364 unsigned *num_maps)
365{
366 bool ret;
367
368 if (*num_maps == *reserved_maps)
369 return -ENOSPC;
370
371 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
372 (*map)[*num_maps].data.mux.group = grp->name;
373
374 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
375 if (!ret) {
376 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
377 fnum, pin);
378 return -EINVAL;
379 }
380
381 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
382 (*num_maps)++;
383
384 return 0;
385}
386
387static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
388 struct device_node *node,
389 struct pinctrl_map **map,
390 unsigned *reserved_maps,
391 unsigned *num_maps)
392{
393 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
394 int num_pins, num_funcs, maps_per_pin, i, err;
395 struct mtk_pinctrl_group *grp;
396 unsigned int num_configs;
397 bool has_config = false;
398 unsigned long *configs;
399 u32 pinfunc, pin, func;
400 struct property *pins;
401 unsigned reserve = 0;
402
403 pins = of_find_property(node, "pinmux", NULL);
404 if (!pins) {
9ede2a76
RH		 405 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
406 node);
80525098
ZT		 407 return -EINVAL;
408 }
409
410 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
411 &num_configs);
412 if (err)
413 return err;
414
415 if (num_configs)
416 has_config = true;
417
418 num_pins = pins->length / sizeof(u32);
419 num_funcs = num_pins;
420 maps_per_pin = 0;
421 if (num_funcs)
422 maps_per_pin++;
423 if (has_config && num_pins >= 1)
424 maps_per_pin++;
425
426 if (!num_pins || !maps_per_pin) {
427 err = -EINVAL;
428 goto exit;
429 }
430
431 reserve = num_pins * maps_per_pin;
432
433 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
434 reserve);
435 if (err < 0)
436 goto exit;
437
438 for (i = 0; i < num_pins; i++) {
439 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
440 if (err)
441 goto exit;
442
443 pin = MTK_GET_PIN_NO(pinfunc);
444 func = MTK_GET_PIN_FUNC(pinfunc);
445
446 if (pin >= hw->soc->npins ||
447 func >= ARRAY_SIZE(mtk_gpio_functions)) {
448 dev_err(hw->dev, "invalid pins value.\n");
449 err = -EINVAL;
450 goto exit;
451 }
452
453 grp = mtk_pctrl_find_group_by_pin(hw, pin);
454 if (!grp) {
455 dev_err(hw->dev, "unable to match pin %d to group\n",
456 pin);
457 err = -EINVAL;
458 goto exit;
459 }
460
461 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
462 reserved_maps, num_maps);
463 if (err < 0)
464 goto exit;
465
466 if (has_config) {
467 err = pinctrl_utils_add_map_configs(pctldev, map,
468 reserved_maps,
469 num_maps,
470 grp->name,
471 configs,
472 num_configs,
473 PIN_MAP_TYPE_CONFIGS_GROUP);
474 if (err < 0)
475 goto exit;
476 }
477 }
478
479 err = 0;
480
481exit:
482 kfree(configs);
483 return err;
484}
485
486static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np_config,
488 struct pinctrl_map **map,
489 unsigned *num_maps)
490{
491 struct device_node *np;
492 unsigned reserved_maps;
493 int ret;
494
495 *map = NULL;
496 *num_maps = 0;
497 reserved_maps = 0;
498
499 for_each_child_of_node(np_config, np) {
500 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
501 &reserved_maps,
502 num_maps);
503 if (ret < 0) {
504 pinctrl_utils_free_map(pctldev, *map, *num_maps);
505 of_node_put(np);
506 return ret;
507 }
508 }
509
510 return 0;
511}
512
513static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
514{
515 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
516
517 return hw->soc->ngrps;
518}
519
520static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
521 unsigned group)
522{
523 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
524
525 return hw->groups[group].name;
526}
527
528static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
529 unsigned group, const unsigned **pins,
530 unsigned *num_pins)
531{
532 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
533
534 *pins = (unsigned *)&hw->groups[group].pin;
535 *num_pins = 1;
536
537 return 0;
538}
539
184d8e13
LH		 540static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
541{
542 const struct mtk_pin_desc *desc;
543 int value, err;
544
3385ab72 545 if (gpio >= hw->soc->npins)
184d8e13
LH		 546 return -EINVAL;
547
548 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
549
550 err = mtk_hw_get_value(hw, desc, field, &value);
551 if (err)
552 return err;
553
554 return value;
555}
556
557#define mtk_pctrl_get_pinmux(hw, gpio) \
558 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
559
560#define mtk_pctrl_get_direction(hw, gpio) \
561 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
562
563#define mtk_pctrl_get_out(hw, gpio) \
564 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
565
566#define mtk_pctrl_get_in(hw, gpio) \
567 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
568
569#define mtk_pctrl_get_smt(hw, gpio) \
570 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
571
572#define mtk_pctrl_get_ies(hw, gpio) \
573 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
574
575#define mtk_pctrl_get_driving(hw, gpio) \
576 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
577
578ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
579 unsigned int gpio, char *buf, unsigned int bufLen)
580{
581 int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
582 const struct mtk_pin_desc *desc;
583
3385ab72 584 if (gpio >= hw->soc->npins)
184d8e13
LH		 585 return -EINVAL;
586
587 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
588 pinmux = mtk_pctrl_get_pinmux(hw, gpio);
589 if (pinmux >= hw->soc->nfuncs)
590 pinmux -= hw->soc->nfuncs;
591
592 mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
593 if (pullen == MTK_PUPD_SET_R1R0_00) {
594 pullen = 0;
595 r1 = 0;
596 r0 = 0;
597 } else if (pullen == MTK_PUPD_SET_R1R0_01) {
598 pullen = 1;
599 r1 = 0;
600 r0 = 1;
601 } else if (pullen == MTK_PUPD_SET_R1R0_10) {
602 pullen = 1;
603 r1 = 1;
604 r0 = 0;
605 } else if (pullen == MTK_PUPD_SET_R1R0_11) {
606 pullen = 1;
607 r1 = 1;
608 r0 = 1;
609 } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
610 pullen = 0;
611 }
7eb42f98 612 len += scnprintf(buf + len, bufLen - len,
184d8e13
LH		 613 "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
614 gpio,
615 pinmux,
616 mtk_pctrl_get_direction(hw, gpio),
617 mtk_pctrl_get_out(hw, gpio),
618 mtk_pctrl_get_in(hw, gpio),
619 mtk_pctrl_get_driving(hw, gpio),
620 mtk_pctrl_get_smt(hw, gpio),
621 mtk_pctrl_get_ies(hw, gpio),
622 pullen,
623 pullup);
624
625 if (r1 != -1) {
7eb42f98 626 len += scnprintf(buf + len, bufLen - len, " (%1d %1d)\n",
184d8e13
LH		 627 r1, r0);
628 } else {
7eb42f98 629 len += scnprintf(buf + len, bufLen - len, "\n");
184d8e13
LH		 630 }
631
632 return len;
633}
634
635#define PIN_DBG_BUF_SZ 96
636static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
637 unsigned int gpio)
638{
639 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
640 char buf[PIN_DBG_BUF_SZ];
641
642 (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
643
644 seq_printf(s, "%s", buf);
645}
646
80525098
ZT		 647static const struct pinctrl_ops mtk_pctlops = {
648 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
649 .dt_free_map = pinctrl_utils_free_map,
650 .get_groups_count = mtk_pctrl_get_groups_count,
651 .get_group_name = mtk_pctrl_get_group_name,
652 .get_group_pins = mtk_pctrl_get_group_pins,
184d8e13 653 .pin_dbg_show = mtk_pctrl_dbg_show,
80525098
ZT		 654};
655
656static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
657{
658 return ARRAY_SIZE(mtk_gpio_functions);
659}
660
661static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
662 unsigned selector)
663{
664 return mtk_gpio_functions[selector];
665}
666
667static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
668 unsigned function,
669 const char * const **groups,
670 unsigned * const num_groups)
671{
672 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
673
674 *groups = hw->grp_names;
675 *num_groups = hw->soc->ngrps;
676
677 return 0;
678}
679
680static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
681 unsigned function,
682 unsigned group)
683{
684 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
685 struct mtk_pinctrl_group *grp = hw->groups + group;
686 const struct mtk_func_desc *desc_func;
687 const struct mtk_pin_desc *desc;
688 bool ret;
689
690 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
691 if (!ret) {
692 dev_err(hw->dev, "invalid function %d on group %d .\n",
693 function, group);
694 return -EINVAL;
695 }
696
697 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
698 if (!desc_func)
699 return -EINVAL;
700
701 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
702 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
703
704 return 0;
705}
706
707static const struct pinmux_ops mtk_pmxops = {
708 .get_functions_count = mtk_pmx_get_funcs_cnt,
709 .get_function_name = mtk_pmx_get_func_name,
710 .get_function_groups = mtk_pmx_get_func_groups,
711 .set_mux = mtk_pmx_set_mux,
712 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
713 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
714};
715
716static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
717 unsigned long *config)
718{
719 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
720
721 *config = hw->groups[group].config;
722
723 return 0;
724}
725
726static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
727 unsigned long *configs, unsigned num_configs)
728{
729 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
730 struct mtk_pinctrl_group *grp = &hw->groups[group];
731 int i, ret;
732
733 for (i = 0; i < num_configs; i++) {
734 ret = mtk_pinconf_set(pctldev, grp->pin,
735 pinconf_to_config_param(configs[i]),
736 pinconf_to_config_argument(configs[i]));
737 if (ret < 0)
738 return ret;
739
740 grp->config = configs[i];
741 }
742
743 return 0;
744}
745
746static const struct pinconf_ops mtk_confops = {
747 .pin_config_get = mtk_pinconf_get,
748 .pin_config_group_get = mtk_pconf_group_get,
749 .pin_config_group_set = mtk_pconf_group_set,
184d8e13 750 .is_generic = true,
80525098
ZT		 751};
752
753static struct pinctrl_desc mtk_desc = {
754 .name = PINCTRL_PINCTRL_DEV,
755 .pctlops = &mtk_pctlops,
756 .pmxops = &mtk_pmxops,
757 .confops = &mtk_confops,
758 .owner = THIS_MODULE,
759};
760
761static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
762{
763 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
764 const struct mtk_pin_desc *desc;
765 int value, err;
766
3385ab72 767 if (gpio >= hw->soc->npins)
3de7deef
LH		 768 return -EINVAL;
769
80525098
ZT		 770 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
771
772 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
773 if (err)
774 return err;
775
3c827873
MV		 776 if (value)
777 return GPIO_LINE_DIRECTION_OUT;
778
779 return GPIO_LINE_DIRECTION_IN;
80525098
ZT		 780}
781
782static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
783{
784 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
785 const struct mtk_pin_desc *desc;
786 int value, err;
787
3385ab72 788 if (gpio >= hw->soc->npins)
3de7deef
LH		 789 return -EINVAL;
790
80525098
ZT		 791 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
792
793 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
794 if (err)
795 return err;
796
797 return !!value;
798}
799
800static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
801{
802 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
803 const struct mtk_pin_desc *desc;
804
3385ab72 805 if (gpio >= hw->soc->npins)
3de7deef
LH		 806 return;
807
80525098
ZT		 808 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
809
810 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
811}
812
813static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
814{
3de7deef
LH		 815 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
816
3385ab72 817 if (gpio >= hw->soc->npins)
3de7deef
LH		 818 return -EINVAL;
819
80525098
ZT		 820 return pinctrl_gpio_direction_input(chip->base + gpio);
821}
822
823static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
824 int value)
825{
3de7deef
LH		 826 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
827
3385ab72 828 if (gpio >= hw->soc->npins)
3de7deef
LH		 829 return -EINVAL;
830
80525098
ZT		 831 mtk_gpio_set(chip, gpio, value);
832
833 return pinctrl_gpio_direction_output(chip->base + gpio);
834}
835
6561859b
SW		 836static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
837{
838 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
839 const struct mtk_pin_desc *desc;
840
841 if (!hw->eint)
842 return -ENOTSUPP;
843
844 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
845
846 if (desc->eint.eint_n == EINT_NA)
847 return -ENOTSUPP;
848
849 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
850}
851
80525098
ZT		 852static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
853 unsigned long config)
854{
855 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
856 const struct mtk_pin_desc *desc;
857 u32 debounce;
858
859 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
860
861 if (!hw->eint ||
862 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
863 desc->eint.eint_n == EINT_NA)
864 return -ENOTSUPP;
865
866 debounce = pinconf_to_config_argument(config);
867
868 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
869}
870
871static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
872{
873 struct gpio_chip *chip = &hw->chip;
874 int ret;
875
876 chip->label = PINCTRL_PINCTRL_DEV;
877 chip->parent = hw->dev;
878 chip->request = gpiochip_generic_request;
879 chip->free = gpiochip_generic_free;
880 chip->get_direction = mtk_gpio_get_direction;
881 chip->direction_input = mtk_gpio_direction_input;
882 chip->direction_output = mtk_gpio_direction_output;
883 chip->get = mtk_gpio_get;
884 chip->set = mtk_gpio_set;
6561859b 885 chip->to_irq = mtk_gpio_to_irq,
80525098
ZT		 886 chip->set_config = mtk_gpio_set_config,
887 chip->base = -1;
888 chip->ngpio = hw->soc->npins;
889 chip->of_node = np;
890 chip->of_gpio_n_cells = 2;
891
892 ret = gpiochip_add_data(chip, hw);
893 if (ret < 0)
894 return ret;
895
896 return 0;
897}
898
899static int mtk_pctrl_build_state(struct platform_device *pdev)
900{
901 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
902 int i;
903
904 /* Allocate groups */
905 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
906 sizeof(*hw->groups), GFP_KERNEL);
907 if (!hw->groups)
908 return -ENOMEM;
909
910 /* We assume that one pin is one group, use pin name as group name. */
911 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
912 sizeof(*hw->grp_names), GFP_KERNEL);
913 if (!hw->grp_names)
914 return -ENOMEM;
915
916 for (i = 0; i < hw->soc->npins; i++) {
917 const struct mtk_pin_desc *pin = hw->soc->pins + i;
918 struct mtk_pinctrl_group *group = hw->groups + i;
919
920 group->name = pin->name;
921 group->pin = pin->number;
922
923 hw->grp_names[i] = pin->name;
924 }
925
926 return 0;
927}
928
929int mtk_paris_pinctrl_probe(struct platform_device *pdev,
930 const struct mtk_pin_soc *soc)
931{
932 struct pinctrl_pin_desc *pins;
933 struct mtk_pinctrl *hw;
934 struct resource *res;
935 int err, i;
936
937 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
938 if (!hw)
939 return -ENOMEM;
940
941 platform_set_drvdata(pdev, hw);
942 hw->soc = soc;
943 hw->dev = &pdev->dev;
944
945 if (!hw->soc->nbase_names) {
946 dev_err(&pdev->dev,
947 "SoC should be assigned at least one register base\n");
948 return -EINVAL;
949 }
950
951 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
952 sizeof(*hw->base), GFP_KERNEL);
184744e9
WY		 953 if (!hw->base)
954 return -ENOMEM;
80525098
ZT		 955
956 for (i = 0; i < hw->soc->nbase_names; i++) {
957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
958 hw->soc->base_names[i]);
959 if (!res) {
960 dev_err(&pdev->dev, "missing IO resource\n");
961 return -ENXIO;
962 }
963
964 hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
965 if (IS_ERR(hw->base[i]))
966 return PTR_ERR(hw->base[i]);
967 }
968
969 hw->nbase = hw->soc->nbase_names;
970
971 err = mtk_pctrl_build_state(pdev);
972 if (err) {
973 dev_err(&pdev->dev, "build state failed: %d\n", err);
974 return -EINVAL;
975 }
976
977 /* Copy from internal struct mtk_pin_desc to register to the core */
978 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
979 GFP_KERNEL);
184744e9
WY		 980 if (!pins)
981 return -ENOMEM;
80525098
ZT		 982
983 for (i = 0; i < hw->soc->npins; i++) {
984 pins[i].number = hw->soc->pins[i].number;
985 pins[i].name = hw->soc->pins[i].name;
986 }
987
988 /* Setup pins descriptions per SoC types */
989 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
990 mtk_desc.npins = hw->soc->npins;
991 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
992 mtk_desc.custom_params = mtk_custom_bindings;
993#ifdef CONFIG_DEBUG_FS
994 mtk_desc.custom_conf_items = mtk_conf_items;
995#endif
996
997 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
998 &hw->pctrl);
999 if (err)
1000 return err;
1001
1002 err = pinctrl_enable(hw->pctrl);
1003 if (err)
1004 return err;
1005
6561859b
SW		 1006 err = mtk_build_eint(hw, pdev);
1007 if (err)
1008 dev_warn(&pdev->dev,
1009 "Failed to add EINT, but pinctrl still can work\n");
1010
80525098
ZT		 1011 /* Build gpiochip should be after pinctrl_enable is done */
1012 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
1013 if (err) {
1014 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1015 return err;
1016 }
1017
1018 platform_set_drvdata(pdev, hw);
1019
1020 return 0;
1021}
5c090448
NB		 1022
1023static int mtk_paris_pinctrl_suspend(struct device *device)
1024{
1025 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1026
1027 return mtk_eint_do_suspend(pctl->eint);
1028}
1029
1030static int mtk_paris_pinctrl_resume(struct device *device)
1031{
1032 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1033
1034 return mtk_eint_do_resume(pctl->eint);
1035}
1036
1037const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
1038 .suspend_noirq = mtk_paris_pinctrl_suspend,
1039 .resume_noirq = mtk_paris_pinctrl_resume,
1040};
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