]>
Commit | Line | Data |
---|---|---|
97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f365be09 BA |
2 | /* |
3 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
4 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
f365be09 BA |
5 | */ |
6 | ||
32745581 | 7 | #include <linux/delay.h> |
f365be09 | 8 | #include <linux/err.h> |
f365be09 BA |
9 | #include <linux/io.h> |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/pinctrl/machine.h> | |
14 | #include <linux/pinctrl/pinctrl.h> | |
15 | #include <linux/pinctrl/pinmux.h> | |
16 | #include <linux/pinctrl/pinconf.h> | |
17 | #include <linux/pinctrl/pinconf-generic.h> | |
18 | #include <linux/slab.h> | |
1c5fb66a | 19 | #include <linux/gpio/driver.h> |
f365be09 | 20 | #include <linux/interrupt.h> |
f365be09 | 21 | #include <linux/spinlock.h> |
cf1fc187 | 22 | #include <linux/reboot.h> |
ad644987 | 23 | #include <linux/pm.h> |
47a01ee9 | 24 | #include <linux/log2.h> |
13bec8d4 AK |
25 | #include <linux/qcom_scm.h> |
26 | #include <linux/io.h> | |
32745581 | 27 | |
e35a6ae0 LI |
28 | #include <linux/soc/qcom/irq.h> |
29 | ||
69b78b8d LW |
30 | #include "../core.h" |
31 | #include "../pinconf.h" | |
f365be09 | 32 | #include "pinctrl-msm.h" |
69b78b8d | 33 | #include "../pinctrl-utils.h" |
f365be09 | 34 | |
408e3c66 | 35 | #define MAX_NR_GPIO 300 |
a46d5e98 | 36 | #define MAX_NR_TILES 4 |
32745581 | 37 | #define PS_HOLD_OFFSET 0x820 |
408e3c66 | 38 | |
f365be09 BA |
39 | /** |
40 | * struct msm_pinctrl - state for a pinctrl-msm device | |
41 | * @dev: device handle. | |
42 | * @pctrl: pinctrl handle. | |
f365be09 | 43 | * @chip: gpiochip handle. |
cf1fc187 | 44 | * @restart_nb: restart notifier block. |
f365be09 BA |
45 | * @irq: parent irq for the TLMM irq_chip. |
46 | * @lock: Spinlock to protect register resources as well | |
47 | * as msm_pinctrl data structures. | |
48 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
49 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
50 | * detection. | |
e35a6ae0 | 51 | * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller |
f365be09 | 52 | * @soc; Reference to soc_data of platform specific data. |
a46d5e98 | 53 | * @regs: Base addresses for the TLMM tiles. |
f365be09 BA |
54 | */ |
55 | struct msm_pinctrl { | |
56 | struct device *dev; | |
57 | struct pinctrl_dev *pctrl; | |
f365be09 | 58 | struct gpio_chip chip; |
f265e8b9 | 59 | struct pinctrl_desc desc; |
cf1fc187 | 60 | struct notifier_block restart_nb; |
f265e8b9 TT |
61 | |
62 | struct irq_chip irq_chip; | |
f393e489 | 63 | int irq; |
f365be09 | 64 | |
13bec8d4 AK |
65 | bool intr_target_use_scm; |
66 | ||
47b03ca9 | 67 | raw_spinlock_t lock; |
f365be09 | 68 | |
408e3c66 BA |
69 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
70 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
e35a6ae0 | 71 | DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); |
f365be09 BA |
72 | |
73 | const struct msm_pinctrl_soc_data *soc; | |
a46d5e98 | 74 | void __iomem *regs[MAX_NR_TILES]; |
13bec8d4 | 75 | u32 phys_base[MAX_NR_TILES]; |
f365be09 BA |
76 | }; |
77 | ||
6c736989 BA |
78 | #define MSM_ACCESSOR(name) \ |
79 | static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \ | |
80 | const struct msm_pingroup *g) \ | |
81 | { \ | |
a46d5e98 | 82 | return readl(pctrl->regs[g->tile] + g->name##_reg); \ |
6c736989 BA |
83 | } \ |
84 | static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \ | |
85 | const struct msm_pingroup *g) \ | |
86 | { \ | |
a46d5e98 | 87 | writel(val, pctrl->regs[g->tile] + g->name##_reg); \ |
6c736989 BA |
88 | } |
89 | ||
90 | MSM_ACCESSOR(ctl) | |
91 | MSM_ACCESSOR(io) | |
92 | MSM_ACCESSOR(intr_cfg) | |
93 | MSM_ACCESSOR(intr_status) | |
94 | MSM_ACCESSOR(intr_target) | |
95 | ||
f365be09 BA |
96 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) |
97 | { | |
98 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
99 | ||
100 | return pctrl->soc->ngroups; | |
101 | } | |
102 | ||
103 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
104 | unsigned group) | |
105 | { | |
106 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
107 | ||
108 | return pctrl->soc->groups[group].name; | |
109 | } | |
110 | ||
111 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
112 | unsigned group, | |
113 | const unsigned **pins, | |
114 | unsigned *num_pins) | |
115 | { | |
116 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
117 | ||
118 | *pins = pctrl->soc->groups[group].pins; | |
119 | *num_pins = pctrl->soc->groups[group].npins; | |
120 | return 0; | |
121 | } | |
122 | ||
1f2b2398 | 123 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
124 | .get_groups_count = msm_get_groups_count, |
125 | .get_group_name = msm_get_group_name, | |
126 | .get_group_pins = msm_get_group_pins, | |
127 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
d32f7fd3 | 128 | .dt_free_map = pinctrl_utils_free_map, |
f365be09 BA |
129 | }; |
130 | ||
691bf5d5 SB |
131 | static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) |
132 | { | |
133 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
134 | struct gpio_chip *chip = &pctrl->chip; | |
135 | ||
136 | return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; | |
137 | } | |
138 | ||
f365be09 BA |
139 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) |
140 | { | |
141 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
142 | ||
143 | return pctrl->soc->nfunctions; | |
144 | } | |
145 | ||
146 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
147 | unsigned function) | |
148 | { | |
149 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
150 | ||
151 | return pctrl->soc->functions[function].name; | |
152 | } | |
153 | ||
154 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
155 | unsigned function, | |
156 | const char * const **groups, | |
157 | unsigned * const num_groups) | |
158 | { | |
159 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
160 | ||
161 | *groups = pctrl->soc->functions[function].groups; | |
162 | *num_groups = pctrl->soc->functions[function].ngroups; | |
163 | return 0; | |
164 | } | |
165 | ||
03e9f0ca LW |
166 | static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, |
167 | unsigned function, | |
168 | unsigned group) | |
f365be09 BA |
169 | { |
170 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
171 | const struct msm_pingroup *g; | |
172 | unsigned long flags; | |
47a01ee9 | 173 | u32 val, mask; |
f365be09 BA |
174 | int i; |
175 | ||
176 | g = &pctrl->soc->groups[group]; | |
47a01ee9 | 177 | mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); |
f365be09 | 178 | |
3c25381f | 179 | for (i = 0; i < g->nfuncs; i++) { |
f365be09 BA |
180 | if (g->funcs[i] == function) |
181 | break; | |
182 | } | |
183 | ||
3c25381f | 184 | if (WARN_ON(i == g->nfuncs)) |
f365be09 BA |
185 | return -EINVAL; |
186 | ||
47b03ca9 | 187 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 188 | |
6c736989 | 189 | val = msm_readl_ctl(pctrl, g); |
6bcf3f63 | 190 | val &= ~mask; |
f365be09 | 191 | val |= i << g->mux_bit; |
6c736989 | 192 | msm_writel_ctl(val, pctrl, g); |
f365be09 | 193 | |
47b03ca9 | 194 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
195 | |
196 | return 0; | |
197 | } | |
198 | ||
1de7ddb3 SB |
199 | static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, |
200 | struct pinctrl_gpio_range *range, | |
201 | unsigned offset) | |
202 | { | |
203 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
204 | const struct msm_pingroup *g = &pctrl->soc->groups[offset]; | |
205 | ||
206 | /* No funcs? Probably ACPI so can't do anything here */ | |
207 | if (!g->nfuncs) | |
208 | return 0; | |
209 | ||
210 | /* For now assume function 0 is GPIO because it always is */ | |
de0c18a8 | 211 | return msm_pinmux_set_mux(pctldev, g->funcs[0], offset); |
1de7ddb3 SB |
212 | } |
213 | ||
1f2b2398 | 214 | static const struct pinmux_ops msm_pinmux_ops = { |
691bf5d5 | 215 | .request = msm_pinmux_request, |
f365be09 BA |
216 | .get_functions_count = msm_get_functions_count, |
217 | .get_function_name = msm_get_function_name, | |
218 | .get_function_groups = msm_get_function_groups, | |
1de7ddb3 | 219 | .gpio_request_enable = msm_pinmux_request_gpio, |
03e9f0ca | 220 | .set_mux = msm_pinmux_set_mux, |
f365be09 BA |
221 | }; |
222 | ||
223 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
224 | const struct msm_pingroup *g, | |
225 | unsigned param, | |
f365be09 BA |
226 | unsigned *mask, |
227 | unsigned *bit) | |
228 | { | |
229 | switch (param) { | |
230 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 231 | case PIN_CONFIG_BIAS_PULL_DOWN: |
b831a15e | 232 | case PIN_CONFIG_BIAS_BUS_HOLD: |
f365be09 | 233 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
234 | *bit = g->pull_bit; |
235 | *mask = 3; | |
236 | break; | |
237 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
238 | *bit = g->drv_bit; |
239 | *mask = 7; | |
240 | break; | |
ed118a5f | 241 | case PIN_CONFIG_OUTPUT: |
407f5e39 | 242 | case PIN_CONFIG_INPUT_ENABLE: |
ed118a5f BA |
243 | *bit = g->oe_bit; |
244 | *mask = 1; | |
245 | break; | |
f365be09 | 246 | default: |
f365be09 BA |
247 | return -ENOTSUPP; |
248 | } | |
249 | ||
f365be09 BA |
250 | return 0; |
251 | } | |
252 | ||
83cf5fae RCJ |
253 | #define MSM_NO_PULL 0 |
254 | #define MSM_PULL_DOWN 1 | |
255 | #define MSM_KEEPER 2 | |
256 | #define MSM_PULL_UP_NO_KEEPER 2 | |
257 | #define MSM_PULL_UP 3 | |
f365be09 | 258 | |
7cc34e2e SB |
259 | static unsigned msm_regval_to_drive(u32 val) |
260 | { | |
261 | return (val + 1) * 2; | |
262 | } | |
f365be09 BA |
263 | |
264 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
265 | unsigned int group, | |
266 | unsigned long *config) | |
267 | { | |
268 | const struct msm_pingroup *g; | |
269 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
270 | unsigned param = pinconf_to_config_param(*config); | |
271 | unsigned mask; | |
272 | unsigned arg; | |
273 | unsigned bit; | |
f365be09 BA |
274 | int ret; |
275 | u32 val; | |
276 | ||
277 | g = &pctrl->soc->groups[group]; | |
278 | ||
051a58b4 | 279 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
280 | if (ret < 0) |
281 | return ret; | |
282 | ||
6c736989 | 283 | val = msm_readl_ctl(pctrl, g); |
f365be09 BA |
284 | arg = (val >> bit) & mask; |
285 | ||
286 | /* Convert register value to pinconf value */ | |
287 | switch (param) { | |
288 | case PIN_CONFIG_BIAS_DISABLE: | |
05e0c828 DA |
289 | if (arg != MSM_NO_PULL) |
290 | return -EINVAL; | |
291 | arg = 1; | |
f365be09 BA |
292 | break; |
293 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
05e0c828 DA |
294 | if (arg != MSM_PULL_DOWN) |
295 | return -EINVAL; | |
296 | arg = 1; | |
f365be09 | 297 | break; |
b831a15e | 298 | case PIN_CONFIG_BIAS_BUS_HOLD: |
83cf5fae RCJ |
299 | if (pctrl->soc->pull_no_keeper) |
300 | return -ENOTSUPP; | |
301 | ||
05e0c828 DA |
302 | if (arg != MSM_KEEPER) |
303 | return -EINVAL; | |
304 | arg = 1; | |
b831a15e | 305 | break; |
f365be09 | 306 | case PIN_CONFIG_BIAS_PULL_UP: |
83cf5fae RCJ |
307 | if (pctrl->soc->pull_no_keeper) |
308 | arg = arg == MSM_PULL_UP_NO_KEEPER; | |
309 | else | |
310 | arg = arg == MSM_PULL_UP; | |
05e0c828 DA |
311 | if (!arg) |
312 | return -EINVAL; | |
f365be09 BA |
313 | break; |
314 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 315 | arg = msm_regval_to_drive(arg); |
f365be09 | 316 | break; |
ed118a5f BA |
317 | case PIN_CONFIG_OUTPUT: |
318 | /* Pin is not output */ | |
319 | if (!arg) | |
320 | return -EINVAL; | |
321 | ||
6c736989 | 322 | val = msm_readl_io(pctrl, g); |
ed118a5f BA |
323 | arg = !!(val & BIT(g->in_bit)); |
324 | break; | |
407f5e39 SV |
325 | case PIN_CONFIG_INPUT_ENABLE: |
326 | /* Pin is output */ | |
327 | if (arg) | |
328 | return -EINVAL; | |
329 | arg = 1; | |
330 | break; | |
f365be09 | 331 | default: |
38d756af | 332 | return -ENOTSUPP; |
f365be09 BA |
333 | } |
334 | ||
335 | *config = pinconf_to_config_packed(param, arg); | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
341 | unsigned group, | |
342 | unsigned long *configs, | |
343 | unsigned num_configs) | |
344 | { | |
345 | const struct msm_pingroup *g; | |
346 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
347 | unsigned long flags; | |
348 | unsigned param; | |
349 | unsigned mask; | |
350 | unsigned arg; | |
351 | unsigned bit; | |
f365be09 BA |
352 | int ret; |
353 | u32 val; | |
354 | int i; | |
355 | ||
356 | g = &pctrl->soc->groups[group]; | |
357 | ||
358 | for (i = 0; i < num_configs; i++) { | |
359 | param = pinconf_to_config_param(configs[i]); | |
360 | arg = pinconf_to_config_argument(configs[i]); | |
361 | ||
051a58b4 | 362 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
363 | if (ret < 0) |
364 | return ret; | |
365 | ||
366 | /* Convert pinconf values to register values */ | |
367 | switch (param) { | |
368 | case PIN_CONFIG_BIAS_DISABLE: | |
369 | arg = MSM_NO_PULL; | |
370 | break; | |
371 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
372 | arg = MSM_PULL_DOWN; | |
373 | break; | |
b831a15e | 374 | case PIN_CONFIG_BIAS_BUS_HOLD: |
83cf5fae RCJ |
375 | if (pctrl->soc->pull_no_keeper) |
376 | return -ENOTSUPP; | |
377 | ||
b831a15e AG |
378 | arg = MSM_KEEPER; |
379 | break; | |
f365be09 | 380 | case PIN_CONFIG_BIAS_PULL_UP: |
83cf5fae RCJ |
381 | if (pctrl->soc->pull_no_keeper) |
382 | arg = MSM_PULL_UP_NO_KEEPER; | |
383 | else | |
384 | arg = MSM_PULL_UP; | |
f365be09 BA |
385 | break; |
386 | case PIN_CONFIG_DRIVE_STRENGTH: | |
387 | /* Check for invalid values */ | |
7cc34e2e | 388 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
389 | arg = -1; |
390 | else | |
7cc34e2e | 391 | arg = (arg / 2) - 1; |
f365be09 | 392 | break; |
ed118a5f BA |
393 | case PIN_CONFIG_OUTPUT: |
394 | /* set output value */ | |
47b03ca9 | 395 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
6c736989 | 396 | val = msm_readl_io(pctrl, g); |
ed118a5f BA |
397 | if (arg) |
398 | val |= BIT(g->out_bit); | |
399 | else | |
400 | val &= ~BIT(g->out_bit); | |
6c736989 | 401 | msm_writel_io(val, pctrl, g); |
47b03ca9 | 402 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
ed118a5f BA |
403 | |
404 | /* enable output */ | |
405 | arg = 1; | |
406 | break; | |
407f5e39 SV |
407 | case PIN_CONFIG_INPUT_ENABLE: |
408 | /* disable output */ | |
409 | arg = 0; | |
410 | break; | |
f365be09 BA |
411 | default: |
412 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
413 | param); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | /* Range-check user-supplied value */ | |
418 | if (arg & ~mask) { | |
419 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
420 | return -EINVAL; | |
421 | } | |
422 | ||
47b03ca9 | 423 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
6c736989 | 424 | val = msm_readl_ctl(pctrl, g); |
f365be09 BA |
425 | val &= ~(mask << bit); |
426 | val |= arg << bit; | |
6c736989 | 427 | msm_writel_ctl(val, pctrl, g); |
47b03ca9 | 428 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
429 | } |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
1f2b2398 | 434 | static const struct pinconf_ops msm_pinconf_ops = { |
38d756af | 435 | .is_generic = true, |
f365be09 BA |
436 | .pin_config_group_get = msm_config_group_get, |
437 | .pin_config_group_set = msm_config_group_set, | |
438 | }; | |
439 | ||
f365be09 BA |
440 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
441 | { | |
442 | const struct msm_pingroup *g; | |
fded3f40 | 443 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
444 | unsigned long flags; |
445 | u32 val; | |
446 | ||
f365be09 | 447 | g = &pctrl->soc->groups[offset]; |
f365be09 | 448 | |
47b03ca9 | 449 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 450 | |
6c736989 | 451 | val = msm_readl_ctl(pctrl, g); |
f365be09 | 452 | val &= ~BIT(g->oe_bit); |
6c736989 | 453 | msm_writel_ctl(val, pctrl, g); |
f365be09 | 454 | |
47b03ca9 | 455 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
456 | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
461 | { | |
462 | const struct msm_pingroup *g; | |
fded3f40 | 463 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
464 | unsigned long flags; |
465 | u32 val; | |
466 | ||
f365be09 | 467 | g = &pctrl->soc->groups[offset]; |
f365be09 | 468 | |
47b03ca9 | 469 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 470 | |
6c736989 | 471 | val = msm_readl_io(pctrl, g); |
e476e77f AL |
472 | if (value) |
473 | val |= BIT(g->out_bit); | |
474 | else | |
475 | val &= ~BIT(g->out_bit); | |
6c736989 | 476 | msm_writel_io(val, pctrl, g); |
f365be09 | 477 | |
6c736989 | 478 | val = msm_readl_ctl(pctrl, g); |
f365be09 | 479 | val |= BIT(g->oe_bit); |
6c736989 | 480 | msm_writel_ctl(val, pctrl, g); |
f365be09 | 481 | |
47b03ca9 | 482 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
483 | |
484 | return 0; | |
485 | } | |
486 | ||
8e515337 TT |
487 | static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
488 | { | |
489 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); | |
490 | const struct msm_pingroup *g; | |
491 | u32 val; | |
492 | ||
493 | g = &pctrl->soc->groups[offset]; | |
494 | ||
6c736989 | 495 | val = msm_readl_ctl(pctrl, g); |
8e515337 | 496 | |
3c827873 MV |
497 | return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : |
498 | GPIO_LINE_DIRECTION_IN; | |
8e515337 TT |
499 | } |
500 | ||
f365be09 BA |
501 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
502 | { | |
503 | const struct msm_pingroup *g; | |
fded3f40 | 504 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
505 | u32 val; |
506 | ||
f365be09 BA |
507 | g = &pctrl->soc->groups[offset]; |
508 | ||
6c736989 | 509 | val = msm_readl_io(pctrl, g); |
f365be09 BA |
510 | return !!(val & BIT(g->in_bit)); |
511 | } | |
512 | ||
513 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
514 | { | |
515 | const struct msm_pingroup *g; | |
fded3f40 | 516 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
517 | unsigned long flags; |
518 | u32 val; | |
519 | ||
f365be09 BA |
520 | g = &pctrl->soc->groups[offset]; |
521 | ||
47b03ca9 | 522 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 523 | |
6c736989 | 524 | val = msm_readl_io(pctrl, g); |
e476e77f AL |
525 | if (value) |
526 | val |= BIT(g->out_bit); | |
527 | else | |
528 | val &= ~BIT(g->out_bit); | |
6c736989 | 529 | msm_writel_io(val, pctrl, g); |
f365be09 | 530 | |
47b03ca9 | 531 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
532 | } |
533 | ||
f365be09 BA |
534 | #ifdef CONFIG_DEBUG_FS |
535 | #include <linux/seq_file.h> | |
536 | ||
537 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
538 | struct pinctrl_dev *pctldev, | |
539 | struct gpio_chip *chip, | |
540 | unsigned offset, | |
541 | unsigned gpio) | |
542 | { | |
543 | const struct msm_pingroup *g; | |
fded3f40 | 544 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
545 | unsigned func; |
546 | int is_out; | |
547 | int drive; | |
548 | int pull; | |
59a18c24 SB |
549 | int val; |
550 | u32 ctl_reg, io_reg; | |
f365be09 | 551 | |
53e73a28 | 552 | static const char * const pulls_keeper[] = { |
f365be09 BA |
553 | "no pull", |
554 | "pull down", | |
555 | "keeper", | |
556 | "pull up" | |
557 | }; | |
558 | ||
53e73a28 CP |
559 | static const char * const pulls_no_keeper[] = { |
560 | "no pull", | |
561 | "pull down", | |
562 | "pull up", | |
563 | }; | |
564 | ||
691bf5d5 SB |
565 | if (!gpiochip_line_is_valid(chip, offset)) |
566 | return; | |
567 | ||
f365be09 | 568 | g = &pctrl->soc->groups[offset]; |
6c736989 BA |
569 | ctl_reg = msm_readl_ctl(pctrl, g); |
570 | io_reg = msm_readl_io(pctrl, g); | |
f365be09 BA |
571 | |
572 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
573 | func = (ctl_reg >> g->mux_bit) & 7; | |
574 | drive = (ctl_reg >> g->drv_bit) & 7; | |
575 | pull = (ctl_reg >> g->pull_bit) & 3; | |
576 | ||
59a18c24 SB |
577 | if (is_out) |
578 | val = !!(io_reg & BIT(g->out_bit)); | |
579 | else | |
580 | val = !!(io_reg & BIT(g->in_bit)); | |
581 | ||
582 | seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); | |
583 | seq_printf(s, " %-4s func%d", val ? "high" : "low", func); | |
7cc34e2e | 584 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
53e73a28 CP |
585 | if (pctrl->soc->pull_no_keeper) |
586 | seq_printf(s, " %s", pulls_no_keeper[pull]); | |
587 | else | |
588 | seq_printf(s, " %s", pulls_keeper[pull]); | |
691bf5d5 | 589 | seq_puts(s, "\n"); |
f365be09 BA |
590 | } |
591 | ||
592 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
593 | { | |
594 | unsigned gpio = chip->base; | |
595 | unsigned i; | |
596 | ||
691bf5d5 | 597 | for (i = 0; i < chip->ngpio; i++, gpio++) |
f365be09 | 598 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
f365be09 BA |
599 | } |
600 | ||
601 | #else | |
602 | #define msm_gpio_dbg_show NULL | |
603 | #endif | |
604 | ||
c9fc5aff LW |
605 | static int msm_gpio_init_valid_mask(struct gpio_chip *gc, |
606 | unsigned long *valid_mask, | |
607 | unsigned int ngpios) | |
6f0ec09a | 608 | { |
c9fc5aff | 609 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
6f0ec09a RR |
610 | int ret; |
611 | unsigned int len, i; | |
4c0efbfb | 612 | const int *reserved = pctrl->soc->reserved_gpios; |
6f0ec09a RR |
613 | u16 *tmp; |
614 | ||
4c0efbfb LJ |
615 | /* Driver provided reserved list overrides DT and ACPI */ |
616 | if (reserved) { | |
c9fc5aff | 617 | bitmap_fill(valid_mask, ngpios); |
4c0efbfb | 618 | for (i = 0; reserved[i] >= 0; i++) { |
c9fc5aff | 619 | if (i >= ngpios || reserved[i] >= ngpios) { |
4c0efbfb LJ |
620 | dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); |
621 | return -EINVAL; | |
622 | } | |
c9fc5aff | 623 | clear_bit(reserved[i], valid_mask); |
4c0efbfb LJ |
624 | } |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
6f0ec09a | 629 | /* The number of GPIOs in the ACPI tables */ |
720b8ec6 | 630 | len = ret = device_property_count_u16(pctrl->dev, "gpios"); |
6f0ec09a RR |
631 | if (ret < 0) |
632 | return 0; | |
633 | ||
c9fc5aff | 634 | if (ret > ngpios) |
6f0ec09a RR |
635 | return -EINVAL; |
636 | ||
637 | tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); | |
638 | if (!tmp) | |
639 | return -ENOMEM; | |
640 | ||
641 | ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); | |
642 | if (ret < 0) { | |
643 | dev_err(pctrl->dev, "could not read list of GPIOs\n"); | |
644 | goto out; | |
645 | } | |
646 | ||
c9fc5aff | 647 | bitmap_zero(valid_mask, ngpios); |
6f0ec09a | 648 | for (i = 0; i < len; i++) |
c9fc5aff | 649 | set_bit(tmp[i], valid_mask); |
6f0ec09a RR |
650 | |
651 | out: | |
652 | kfree(tmp); | |
653 | return ret; | |
654 | } | |
655 | ||
12cb90ba | 656 | static const struct gpio_chip msm_gpio_template = { |
f365be09 BA |
657 | .direction_input = msm_gpio_direction_input, |
658 | .direction_output = msm_gpio_direction_output, | |
8e515337 | 659 | .get_direction = msm_gpio_get_direction, |
f365be09 BA |
660 | .get = msm_gpio_get, |
661 | .set = msm_gpio_set, | |
98c85d58 JG |
662 | .request = gpiochip_generic_request, |
663 | .free = gpiochip_generic_free, | |
f365be09 BA |
664 | .dbg_show = msm_gpio_dbg_show, |
665 | }; | |
666 | ||
667 | /* For dual-edge interrupts in software, since some hardware has no | |
668 | * such support: | |
669 | * | |
670 | * At appropriate moments, this function may be called to flip the polarity | |
671 | * settings of both-edge irq lines to try and catch the next edge. | |
672 | * | |
673 | * The attempt is considered successful if: | |
674 | * - the status bit goes high, indicating that an edge was caught, or | |
675 | * - the input value of the gpio doesn't change during the attempt. | |
676 | * If the value changes twice during the process, that would cause the first | |
677 | * test to fail but would force the second, as two opposite | |
678 | * transitions would cause a detection no matter the polarity setting. | |
679 | * | |
680 | * The do-loop tries to sledge-hammer closed the timing hole between | |
681 | * the initial value-read and the polarity-write - if the line value changes | |
682 | * during that window, an interrupt is lost, the new polarity setting is | |
683 | * incorrect, and the first success test will fail, causing a retry. | |
684 | * | |
685 | * Algorithm comes from Google's msmgpio driver. | |
686 | */ | |
687 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
688 | const struct msm_pingroup *g, | |
689 | struct irq_data *d) | |
690 | { | |
691 | int loop_limit = 100; | |
692 | unsigned val, val2, intstat; | |
693 | unsigned pol; | |
694 | ||
695 | do { | |
6c736989 | 696 | val = msm_readl_io(pctrl, g) & BIT(g->in_bit); |
f365be09 | 697 | |
6c736989 | 698 | pol = msm_readl_intr_cfg(pctrl, g); |
f365be09 | 699 | pol ^= BIT(g->intr_polarity_bit); |
90bcb0c3 | 700 | msm_writel_intr_cfg(pol, pctrl, g); |
f365be09 | 701 | |
6c736989 BA |
702 | val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); |
703 | intstat = msm_readl_intr_status(pctrl, g); | |
f365be09 BA |
704 | if (intstat || (val == val2)) |
705 | return; | |
706 | } while (loop_limit-- > 0); | |
707 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
708 | val, val2); | |
709 | } | |
710 | ||
711 | static void msm_gpio_irq_mask(struct irq_data *d) | |
712 | { | |
cdcb0ab6 | 713 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 714 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 715 | const struct msm_pingroup *g; |
f365be09 BA |
716 | unsigned long flags; |
717 | u32 val; | |
718 | ||
e35a6ae0 LI |
719 | if (d->parent_data) |
720 | irq_chip_mask_parent(d); | |
721 | ||
722 | if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
723 | return; | |
724 | ||
f365be09 BA |
725 | g = &pctrl->soc->groups[d->hwirq]; |
726 | ||
47b03ca9 | 727 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 728 | |
6c736989 | 729 | val = msm_readl_intr_cfg(pctrl, g); |
b55326dc SB |
730 | /* |
731 | * There are two bits that control interrupt forwarding to the CPU. The | |
732 | * RAW_STATUS_EN bit causes the level or edge sensed on the line to be | |
733 | * latched into the interrupt status register when the hardware detects | |
734 | * an irq that it's configured for (either edge for edge type or level | |
735 | * for level type irq). The 'non-raw' status enable bit causes the | |
736 | * hardware to assert the summary interrupt to the CPU if the latched | |
737 | * status bit is set. There's a bug though, the edge detection logic | |
738 | * seems to have a problem where toggling the RAW_STATUS_EN bit may | |
739 | * cause the status bit to latch spuriously when there isn't any edge | |
740 | * so we can't touch that bit for edge type irqs and we have to keep | |
741 | * the bit set anyway so that edges are latched while the line is masked. | |
742 | * | |
743 | * To make matters more complicated, leaving the RAW_STATUS_EN bit | |
744 | * enabled all the time causes level interrupts to re-latch into the | |
745 | * status register because the level is still present on the line after | |
746 | * we ack it. We clear the raw status enable bit during mask here and | |
747 | * set the bit on unmask so the interrupt can't latch into the hardware | |
748 | * while it's masked. | |
749 | */ | |
750 | if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) | |
751 | val &= ~BIT(g->intr_raw_status_bit); | |
752 | ||
f365be09 | 753 | val &= ~BIT(g->intr_enable_bit); |
6c736989 | 754 | msm_writel_intr_cfg(val, pctrl, g); |
f365be09 BA |
755 | |
756 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
757 | ||
47b03ca9 | 758 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
759 | } |
760 | ||
4b7618fd | 761 | static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear) |
f365be09 | 762 | { |
cdcb0ab6 | 763 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 764 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 765 | const struct msm_pingroup *g; |
f365be09 BA |
766 | unsigned long flags; |
767 | u32 val; | |
768 | ||
e35a6ae0 LI |
769 | if (d->parent_data) |
770 | irq_chip_unmask_parent(d); | |
771 | ||
772 | if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
773 | return; | |
774 | ||
f365be09 BA |
775 | g = &pctrl->soc->groups[d->hwirq]; |
776 | ||
47b03ca9 | 777 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 778 | |
4b7618fd SR |
779 | if (status_clear) { |
780 | /* | |
781 | * clear the interrupt status bit before unmask to avoid | |
782 | * any erroneous interrupts that would have got latched | |
783 | * when the interrupt is not in use. | |
784 | */ | |
785 | val = msm_readl_intr_status(pctrl, g); | |
786 | val &= ~BIT(g->intr_status_bit); | |
787 | msm_writel_intr_status(val, pctrl, g); | |
788 | } | |
789 | ||
6c736989 | 790 | val = msm_readl_intr_cfg(pctrl, g); |
b55326dc | 791 | val |= BIT(g->intr_raw_status_bit); |
f365be09 | 792 | val |= BIT(g->intr_enable_bit); |
6c736989 | 793 | msm_writel_intr_cfg(val, pctrl, g); |
f365be09 BA |
794 | |
795 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
796 | ||
47b03ca9 | 797 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
798 | } |
799 | ||
4b7618fd SR |
800 | static void msm_gpio_irq_enable(struct irq_data *d) |
801 | { | |
e35a6ae0 LI |
802 | /* |
803 | * Clear the interrupt that may be pending before we enable | |
804 | * the line. | |
805 | * This is especially a problem with the GPIOs routed to the | |
806 | * PDC. These GPIOs are direct-connect interrupts to the GIC. | |
807 | * Disabling the interrupt line at the PDC does not prevent | |
808 | * the interrupt from being latched at the GIC. The state at | |
809 | * GIC needs to be cleared before enabling. | |
810 | */ | |
811 | if (d->parent_data) { | |
812 | irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); | |
813 | irq_chip_enable_parent(d); | |
814 | } | |
4b7618fd SR |
815 | |
816 | msm_gpio_irq_clear_unmask(d, true); | |
817 | } | |
818 | ||
e35a6ae0 LI |
819 | static void msm_gpio_irq_disable(struct irq_data *d) |
820 | { | |
821 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
822 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
823 | ||
824 | if (d->parent_data) | |
825 | irq_chip_disable_parent(d); | |
826 | ||
827 | if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
828 | msm_gpio_irq_mask(d); | |
829 | } | |
830 | ||
4b7618fd SR |
831 | static void msm_gpio_irq_unmask(struct irq_data *d) |
832 | { | |
833 | msm_gpio_irq_clear_unmask(d, false); | |
834 | } | |
835 | ||
f365be09 BA |
836 | static void msm_gpio_irq_ack(struct irq_data *d) |
837 | { | |
cdcb0ab6 | 838 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 839 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 840 | const struct msm_pingroup *g; |
f365be09 BA |
841 | unsigned long flags; |
842 | u32 val; | |
843 | ||
e35a6ae0 LI |
844 | if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) |
845 | return; | |
846 | ||
f365be09 BA |
847 | g = &pctrl->soc->groups[d->hwirq]; |
848 | ||
47b03ca9 | 849 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 | 850 | |
6c736989 | 851 | val = msm_readl_intr_status(pctrl, g); |
48f15e94 BA |
852 | if (g->intr_ack_high) |
853 | val |= BIT(g->intr_status_bit); | |
854 | else | |
855 | val &= ~BIT(g->intr_status_bit); | |
6c736989 | 856 | msm_writel_intr_status(val, pctrl, g); |
f365be09 BA |
857 | |
858 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
859 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
860 | ||
47b03ca9 | 861 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
862 | } |
863 | ||
f365be09 BA |
864 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
865 | { | |
cdcb0ab6 | 866 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 867 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 868 | const struct msm_pingroup *g; |
f365be09 BA |
869 | unsigned long flags; |
870 | u32 val; | |
871 | ||
e35a6ae0 LI |
872 | if (d->parent_data) |
873 | irq_chip_set_type_parent(d, type); | |
874 | ||
875 | if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
876 | return 0; | |
877 | ||
f365be09 BA |
878 | g = &pctrl->soc->groups[d->hwirq]; |
879 | ||
47b03ca9 | 880 | raw_spin_lock_irqsave(&pctrl->lock, flags); |
f365be09 BA |
881 | |
882 | /* | |
883 | * For hw without possibility of detecting both edges | |
884 | */ | |
885 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
886 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
887 | else | |
888 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
889 | ||
13bec8d4 AK |
890 | /* Route interrupts to application cpu. |
891 | * With intr_target_use_scm interrupts are routed to | |
892 | * application cpu using scm calls. | |
893 | */ | |
894 | if (pctrl->intr_target_use_scm) { | |
895 | u32 addr = pctrl->phys_base[0] + g->intr_target_reg; | |
896 | int ret; | |
897 | ||
898 | qcom_scm_io_readl(addr, &val); | |
899 | ||
900 | val &= ~(7 << g->intr_target_bit); | |
901 | val |= g->intr_target_kpss_val << g->intr_target_bit; | |
902 | ||
903 | ret = qcom_scm_io_writel(addr, val); | |
904 | if (ret) | |
905 | dev_err(pctrl->dev, | |
906 | "Failed routing %lu interrupt to Apps proc", | |
907 | d->hwirq); | |
13bec8d4 AK |
908 | } else { |
909 | val = msm_readl_intr_target(pctrl, g); | |
910 | val &= ~(7 << g->intr_target_bit); | |
911 | val |= g->intr_target_kpss_val << g->intr_target_bit; | |
912 | msm_writel_intr_target(val, pctrl, g); | |
913 | } | |
f365be09 BA |
914 | |
915 | /* Update configuration for gpio. | |
916 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
917 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
918 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
919 | */ | |
6c736989 | 920 | val = msm_readl_intr_cfg(pctrl, g); |
f365be09 BA |
921 | val |= BIT(g->intr_raw_status_bit); |
922 | if (g->intr_detection_width == 2) { | |
923 | val &= ~(3 << g->intr_detection_bit); | |
924 | val &= ~(1 << g->intr_polarity_bit); | |
925 | switch (type) { | |
926 | case IRQ_TYPE_EDGE_RISING: | |
927 | val |= 1 << g->intr_detection_bit; | |
928 | val |= BIT(g->intr_polarity_bit); | |
929 | break; | |
930 | case IRQ_TYPE_EDGE_FALLING: | |
931 | val |= 2 << g->intr_detection_bit; | |
932 | val |= BIT(g->intr_polarity_bit); | |
933 | break; | |
934 | case IRQ_TYPE_EDGE_BOTH: | |
935 | val |= 3 << g->intr_detection_bit; | |
936 | val |= BIT(g->intr_polarity_bit); | |
937 | break; | |
938 | case IRQ_TYPE_LEVEL_LOW: | |
939 | break; | |
940 | case IRQ_TYPE_LEVEL_HIGH: | |
941 | val |= BIT(g->intr_polarity_bit); | |
942 | break; | |
943 | } | |
944 | } else if (g->intr_detection_width == 1) { | |
945 | val &= ~(1 << g->intr_detection_bit); | |
946 | val &= ~(1 << g->intr_polarity_bit); | |
947 | switch (type) { | |
948 | case IRQ_TYPE_EDGE_RISING: | |
949 | val |= BIT(g->intr_detection_bit); | |
950 | val |= BIT(g->intr_polarity_bit); | |
951 | break; | |
952 | case IRQ_TYPE_EDGE_FALLING: | |
953 | val |= BIT(g->intr_detection_bit); | |
954 | break; | |
955 | case IRQ_TYPE_EDGE_BOTH: | |
956 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 957 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
958 | break; |
959 | case IRQ_TYPE_LEVEL_LOW: | |
960 | break; | |
961 | case IRQ_TYPE_LEVEL_HIGH: | |
962 | val |= BIT(g->intr_polarity_bit); | |
963 | break; | |
964 | } | |
965 | } else { | |
966 | BUG(); | |
967 | } | |
6c736989 | 968 | msm_writel_intr_cfg(val, pctrl, g); |
f365be09 BA |
969 | |
970 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
971 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
972 | ||
47b03ca9 | 973 | raw_spin_unlock_irqrestore(&pctrl->lock, flags); |
f365be09 BA |
974 | |
975 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
34c0ad84 | 976 | irq_set_handler_locked(d, handle_level_irq); |
f365be09 | 977 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
34c0ad84 | 978 | irq_set_handler_locked(d, handle_edge_irq); |
f365be09 BA |
979 | |
980 | return 0; | |
981 | } | |
982 | ||
983 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
984 | { | |
cdcb0ab6 | 985 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 986 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 987 | |
e35a6ae0 LI |
988 | /* |
989 | * While they may not wake up when the TLMM is powered off, | |
990 | * some GPIOs would like to wakeup the system from suspend | |
991 | * when TLMM is powered on. To allow that, enable the GPIO | |
992 | * summary line to be wakeup capable at GIC. | |
993 | */ | |
994 | if (d->parent_data) | |
995 | irq_chip_set_wake_parent(d, on); | |
996 | ||
6aced33f | 997 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 | 998 | |
f365be09 BA |
999 | return 0; |
1000 | } | |
1001 | ||
fe273121 SB |
1002 | static int msm_gpio_irq_reqres(struct irq_data *d) |
1003 | { | |
1004 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
1005 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
1006 | int ret; | |
1007 | ||
1008 | if (!try_module_get(gc->owner)) | |
1009 | return -ENODEV; | |
1010 | ||
1011 | ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); | |
1012 | if (ret) | |
1013 | goto out; | |
1014 | msm_gpio_direction_input(gc, d->hwirq); | |
1015 | ||
1016 | if (gpiochip_lock_as_irq(gc, d->hwirq)) { | |
1017 | dev_err(gc->parent, | |
1018 | "unable to lock HW IRQ %lu for IRQ\n", | |
1019 | d->hwirq); | |
1020 | ret = -EINVAL; | |
1021 | goto out; | |
1022 | } | |
1023 | return 0; | |
1024 | out: | |
1025 | module_put(gc->owner); | |
1026 | return ret; | |
1027 | } | |
1028 | ||
1029 | static void msm_gpio_irq_relres(struct irq_data *d) | |
1030 | { | |
1031 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
1032 | ||
1033 | gpiochip_unlock_as_irq(gc, d->hwirq); | |
1034 | module_put(gc->owner); | |
1035 | } | |
1036 | ||
dca4f407 VNKG |
1037 | static int msm_gpio_irq_set_affinity(struct irq_data *d, |
1038 | const struct cpumask *dest, bool force) | |
1039 | { | |
1040 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
1041 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
1042 | ||
1043 | if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
1044 | return irq_chip_set_affinity_parent(d, dest, force); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) | |
1050 | { | |
1051 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
1052 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
1053 | ||
1054 | if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) | |
1055 | return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
bd0b9ac4 | 1060 | static void msm_gpio_irq_handler(struct irq_desc *desc) |
f365be09 | 1061 | { |
cdcb0ab6 | 1062 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
f365be09 | 1063 | const struct msm_pingroup *g; |
fded3f40 | 1064 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
5663bb27 | 1065 | struct irq_chip *chip = irq_desc_get_chip(desc); |
f365be09 BA |
1066 | int irq_pin; |
1067 | int handled = 0; | |
1068 | u32 val; | |
1069 | int i; | |
1070 | ||
1071 | chained_irq_enter(chip, desc); | |
1072 | ||
1073 | /* | |
1f2b2398 | 1074 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
1075 | * enabled_irq bitmap to limit the number of reads. |
1076 | */ | |
1077 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
1078 | g = &pctrl->soc->groups[i]; | |
6c736989 | 1079 | val = msm_readl_intr_status(pctrl, g); |
f365be09 | 1080 | if (val & BIT(g->intr_status_bit)) { |
f0fbe7bc | 1081 | irq_pin = irq_find_mapping(gc->irq.domain, i); |
f365be09 BA |
1082 | generic_handle_irq(irq_pin); |
1083 | handled++; | |
1084 | } | |
1085 | } | |
1086 | ||
1f2b2398 | 1087 | /* No interrupts were flagged */ |
f365be09 | 1088 | if (handled == 0) |
bd0b9ac4 | 1089 | handle_bad_irq(desc); |
f365be09 BA |
1090 | |
1091 | chained_irq_exit(chip, desc); | |
1092 | } | |
1093 | ||
e35a6ae0 LI |
1094 | static int msm_gpio_wakeirq(struct gpio_chip *gc, |
1095 | unsigned int child, | |
1096 | unsigned int child_type, | |
1097 | unsigned int *parent, | |
1098 | unsigned int *parent_type) | |
1099 | { | |
1100 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); | |
1101 | const struct msm_gpio_wakeirq_map *map; | |
1102 | int i; | |
1103 | ||
1104 | *parent = GPIO_NO_WAKE_IRQ; | |
1105 | *parent_type = IRQ_TYPE_EDGE_RISING; | |
1106 | ||
1107 | for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { | |
1108 | map = &pctrl->soc->wakeirq_map[i]; | |
1109 | if (map->gpio == child) { | |
1110 | *parent = map->wakeirq; | |
1111 | break; | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
691bf5d5 SB |
1118 | static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) |
1119 | { | |
4c0efbfb LJ |
1120 | if (pctrl->soc->reserved_gpios) |
1121 | return true; | |
1122 | ||
720b8ec6 | 1123 | return device_property_count_u16(pctrl->dev, "gpios") > 0; |
691bf5d5 SB |
1124 | } |
1125 | ||
f365be09 BA |
1126 | static int msm_gpio_init(struct msm_pinctrl *pctrl) |
1127 | { | |
1128 | struct gpio_chip *chip; | |
0ce242ad | 1129 | struct gpio_irq_chip *girq; |
e35a6ae0 LI |
1130 | int i, ret; |
1131 | unsigned gpio, ngpio = pctrl->soc->ngpios; | |
1132 | struct device_node *np; | |
1133 | bool skip; | |
dcd278b8 SB |
1134 | |
1135 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
1136 | return -EINVAL; | |
f365be09 BA |
1137 | |
1138 | chip = &pctrl->chip; | |
a7aa75a2 | 1139 | chip->base = -1; |
dcd278b8 | 1140 | chip->ngpio = ngpio; |
f365be09 | 1141 | chip->label = dev_name(pctrl->dev); |
58383c78 | 1142 | chip->parent = pctrl->dev; |
f365be09 BA |
1143 | chip->owner = THIS_MODULE; |
1144 | chip->of_node = pctrl->dev->of_node; | |
eb1e8bd6 LW |
1145 | if (msm_gpio_needs_valid_mask(pctrl)) |
1146 | chip->init_valid_mask = msm_gpio_init_valid_mask; | |
f365be09 | 1147 | |
f265e8b9 | 1148 | pctrl->irq_chip.name = "msmgpio"; |
4b7618fd | 1149 | pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; |
e35a6ae0 | 1150 | pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; |
f265e8b9 TT |
1151 | pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; |
1152 | pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; | |
1153 | pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; | |
1154 | pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; | |
1155 | pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; | |
fe273121 SB |
1156 | pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; |
1157 | pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; | |
dca4f407 VNKG |
1158 | pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; |
1159 | pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; | |
f265e8b9 | 1160 | |
e35a6ae0 LI |
1161 | np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); |
1162 | if (np) { | |
1163 | chip->irq.parent_domain = irq_find_matching_host(np, | |
1164 | DOMAIN_BUS_WAKEUP); | |
1165 | of_node_put(np); | |
1166 | if (!chip->irq.parent_domain) | |
1167 | return -EPROBE_DEFER; | |
1168 | chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; | |
1cada2f3 | 1169 | pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; |
e35a6ae0 LI |
1170 | /* |
1171 | * Let's skip handling the GPIOs, if the parent irqchip | |
1172 | * is handling the direct connect IRQ of the GPIO. | |
1173 | */ | |
1174 | skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); | |
1175 | for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { | |
1176 | gpio = pctrl->soc->wakeirq_map[i].gpio; | |
1177 | set_bit(gpio, pctrl->skip_wake_irqs); | |
1178 | } | |
1179 | } | |
1180 | ||
0ce242ad LW |
1181 | girq = &chip->irq; |
1182 | girq->chip = &pctrl->irq_chip; | |
1183 | girq->parent_handler = msm_gpio_irq_handler; | |
e35a6ae0 | 1184 | girq->fwnode = pctrl->dev->fwnode; |
0ce242ad LW |
1185 | girq->num_parents = 1; |
1186 | girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), | |
1187 | GFP_KERNEL); | |
1188 | if (!girq->parents) | |
1189 | return -ENOMEM; | |
1190 | girq->default_type = IRQ_TYPE_NONE; | |
1191 | girq->handler = handle_bad_irq; | |
1192 | girq->parents[0] = pctrl->irq; | |
1193 | ||
fded3f40 | 1194 | ret = gpiochip_add_data(&pctrl->chip, pctrl); |
f365be09 BA |
1195 | if (ret) { |
1196 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
1197 | return ret; | |
1198 | } | |
1199 | ||
a86caa9b CL |
1200 | /* |
1201 | * For DeviceTree-supported systems, the gpio core checks the | |
1202 | * pinctrl's device node for the "gpio-ranges" property. | |
1203 | * If it is present, it takes care of adding the pin ranges | |
1204 | * for the driver. In this case the driver can skip ahead. | |
1205 | * | |
1206 | * In order to remain compatible with older, existing DeviceTree | |
1207 | * files which don't set the "gpio-ranges" property or systems that | |
1208 | * utilize ACPI the driver has to call gpiochip_add_pin_range(). | |
1209 | */ | |
1210 | if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { | |
1211 | ret = gpiochip_add_pin_range(&pctrl->chip, | |
1212 | dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
1213 | if (ret) { | |
1214 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
1215 | gpiochip_remove(&pctrl->chip); | |
1216 | return ret; | |
1217 | } | |
f365be09 BA |
1218 | } |
1219 | ||
f365be09 BA |
1220 | return 0; |
1221 | } | |
1222 | ||
cf1fc187 JC |
1223 | static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, |
1224 | void *data) | |
32745581 | 1225 | { |
cf1fc187 JC |
1226 | struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); |
1227 | ||
a46d5e98 | 1228 | writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); |
cf1fc187 JC |
1229 | mdelay(1000); |
1230 | return NOTIFY_DONE; | |
32745581 PG |
1231 | } |
1232 | ||
ad644987 SB |
1233 | static struct msm_pinctrl *poweroff_pctrl; |
1234 | ||
1235 | static void msm_ps_hold_poweroff(void) | |
1236 | { | |
1237 | msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); | |
1238 | } | |
1239 | ||
32745581 PG |
1240 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) |
1241 | { | |
bcd53f85 | 1242 | int i; |
32745581 PG |
1243 | const struct msm_function *func = pctrl->soc->functions; |
1244 | ||
bcd53f85 | 1245 | for (i = 0; i < pctrl->soc->nfunctions; i++) |
32745581 | 1246 | if (!strcmp(func[i].name, "ps_hold")) { |
cf1fc187 JC |
1247 | pctrl->restart_nb.notifier_call = msm_ps_hold_restart; |
1248 | pctrl->restart_nb.priority = 128; | |
1249 | if (register_restart_handler(&pctrl->restart_nb)) | |
1250 | dev_err(pctrl->dev, | |
1251 | "failed to setup restart handler.\n"); | |
ad644987 SB |
1252 | poweroff_pctrl = pctrl; |
1253 | pm_power_off = msm_ps_hold_poweroff; | |
cf1fc187 | 1254 | break; |
32745581 PG |
1255 | } |
1256 | } | |
32745581 | 1257 | |
d1040ea0 | 1258 | static __maybe_unused int msm_pinctrl_suspend(struct device *dev) |
977d057a EG |
1259 | { |
1260 | struct msm_pinctrl *pctrl = dev_get_drvdata(dev); | |
1261 | ||
1262 | return pinctrl_force_sleep(pctrl->pctrl); | |
1263 | } | |
1264 | ||
d1040ea0 | 1265 | static __maybe_unused int msm_pinctrl_resume(struct device *dev) |
977d057a EG |
1266 | { |
1267 | struct msm_pinctrl *pctrl = dev_get_drvdata(dev); | |
1268 | ||
1269 | return pinctrl_force_default(pctrl->pctrl); | |
1270 | } | |
1271 | ||
1272 | SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, | |
1273 | msm_pinctrl_resume); | |
1274 | ||
1275 | EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); | |
1276 | ||
f365be09 BA |
1277 | int msm_pinctrl_probe(struct platform_device *pdev, |
1278 | const struct msm_pinctrl_soc_data *soc_data) | |
1279 | { | |
1280 | struct msm_pinctrl *pctrl; | |
1281 | struct resource *res; | |
1282 | int ret; | |
a46d5e98 | 1283 | int i; |
f365be09 BA |
1284 | |
1285 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
203f4b06 | 1286 | if (!pctrl) |
f365be09 | 1287 | return -ENOMEM; |
203f4b06 | 1288 | |
f365be09 BA |
1289 | pctrl->dev = &pdev->dev; |
1290 | pctrl->soc = soc_data; | |
1291 | pctrl->chip = msm_gpio_template; | |
13bec8d4 AK |
1292 | pctrl->intr_target_use_scm = of_device_is_compatible( |
1293 | pctrl->dev->of_node, | |
1294 | "qcom,ipq8064-pinctrl"); | |
f365be09 | 1295 | |
47b03ca9 | 1296 | raw_spin_lock_init(&pctrl->lock); |
f365be09 | 1297 | |
a46d5e98 BA |
1298 | if (soc_data->tiles) { |
1299 | for (i = 0; i < soc_data->ntiles; i++) { | |
1300 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1301 | soc_data->tiles[i]); | |
1302 | pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); | |
1303 | if (IS_ERR(pctrl->regs[i])) | |
1304 | return PTR_ERR(pctrl->regs[i]); | |
1305 | } | |
1306 | } else { | |
13bec8d4 AK |
1307 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1308 | pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); | |
a46d5e98 BA |
1309 | if (IS_ERR(pctrl->regs[0])) |
1310 | return PTR_ERR(pctrl->regs[0]); | |
13bec8d4 AK |
1311 | |
1312 | pctrl->phys_base[0] = res->start; | |
a46d5e98 | 1313 | } |
f365be09 | 1314 | |
32745581 PG |
1315 | msm_pinctrl_setup_pm_reset(pctrl); |
1316 | ||
f393e489 | 1317 | pctrl->irq = platform_get_irq(pdev, 0); |
64c4dcbf | 1318 | if (pctrl->irq < 0) |
f365be09 | 1319 | return pctrl->irq; |
f365be09 | 1320 | |
f265e8b9 TT |
1321 | pctrl->desc.owner = THIS_MODULE; |
1322 | pctrl->desc.pctlops = &msm_pinctrl_ops; | |
1323 | pctrl->desc.pmxops = &msm_pinmux_ops; | |
1324 | pctrl->desc.confops = &msm_pinconf_ops; | |
1325 | pctrl->desc.name = dev_name(&pdev->dev); | |
1326 | pctrl->desc.pins = pctrl->soc->pins; | |
1327 | pctrl->desc.npins = pctrl->soc->npins; | |
1328 | ||
1329 | pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); | |
323de9ef | 1330 | if (IS_ERR(pctrl->pctrl)) { |
f365be09 | 1331 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 1332 | return PTR_ERR(pctrl->pctrl); |
f365be09 BA |
1333 | } |
1334 | ||
1335 | ret = msm_gpio_init(pctrl); | |
fe0267f4 | 1336 | if (ret) |
f365be09 | 1337 | return ret; |
f365be09 BA |
1338 | |
1339 | platform_set_drvdata(pdev, pctrl); | |
1340 | ||
1341 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
1346 | ||
1347 | int msm_pinctrl_remove(struct platform_device *pdev) | |
1348 | { | |
1349 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
f393e489 | 1350 | |
2fcea6ce | 1351 | gpiochip_remove(&pctrl->chip); |
f365be09 | 1352 | |
cf1fc187 JC |
1353 | unregister_restart_handler(&pctrl->restart_nb); |
1354 | ||
f365be09 BA |
1355 | return 0; |
1356 | } | |
1357 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
1358 |