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040b2583 | 1 | // SPDX-License-Identifier: GPL-2.0 |
cb13e46a MV |
2 | /* |
3 | * R8A77990 processor support - PFC hardware block. | |
4 | * | |
7f2e60f1 | 5 | * Copyright (C) 2018-2019 Renesas Electronics Corp. |
cb13e46a MV |
6 | * |
7 | * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c | |
8 | * | |
8719ca81 | 9 | * R8A7796 processor support - PFC hardware block. |
cb13e46a | 10 | * |
8719ca81 | 11 | * Copyright (C) 2016-2017 Renesas Electronics Corp. |
cb13e46a MV |
12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <dm.h> | |
16 | #include <errno.h> | |
17 | #include <dm/pinctrl.h> | |
18 | #include <linux/kernel.h> | |
19 | ||
20 | #include "sh_pfc.h" | |
21 | ||
bf8d2dab MV |
22 | #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \ |
23 | SH_PFC_PIN_CFG_PULL_DOWN) | |
24 | ||
8719ca81 MV |
25 | #define CPU_ALL_PORT(fn, sfx) \ |
26 | PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ | |
27 | PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ | |
28 | PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ | |
29 | PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
30 | PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ | |
31 | PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ | |
32 | PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ | |
33 | PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ | |
34 | PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
35 | PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ | |
36 | PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ | |
37 | PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ | |
38 | PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \ | |
39 | PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \ | |
40 | PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \ | |
41 | PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \ | |
42 | PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \ | |
43 | PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \ | |
44 | PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \ | |
45 | PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS) | |
cb13e46a MV |
46 | /* |
47 | * F_() : just information | |
48 | * FM() : macro for FN_xxx / xxx_MARK | |
49 | */ | |
50 | ||
51 | /* GPSR0 */ | |
52 | #define GPSR0_17 F_(SDA4, IP7_27_24) | |
53 | #define GPSR0_16 F_(SCL4, IP7_23_20) | |
54 | #define GPSR0_15 F_(D15, IP7_19_16) | |
55 | #define GPSR0_14 F_(D14, IP7_15_12) | |
56 | #define GPSR0_13 F_(D13, IP7_11_8) | |
57 | #define GPSR0_12 F_(D12, IP7_7_4) | |
58 | #define GPSR0_11 F_(D11, IP7_3_0) | |
59 | #define GPSR0_10 F_(D10, IP6_31_28) | |
60 | #define GPSR0_9 F_(D9, IP6_27_24) | |
61 | #define GPSR0_8 F_(D8, IP6_23_20) | |
62 | #define GPSR0_7 F_(D7, IP6_19_16) | |
63 | #define GPSR0_6 F_(D6, IP6_15_12) | |
64 | #define GPSR0_5 F_(D5, IP6_11_8) | |
65 | #define GPSR0_4 F_(D4, IP6_7_4) | |
66 | #define GPSR0_3 F_(D3, IP6_3_0) | |
67 | #define GPSR0_2 F_(D2, IP5_31_28) | |
68 | #define GPSR0_1 F_(D1, IP5_27_24) | |
69 | #define GPSR0_0 F_(D0, IP5_23_20) | |
70 | ||
71 | /* GPSR1 */ | |
72 | #define GPSR1_22 F_(WE0_N, IP5_19_16) | |
73 | #define GPSR1_21 F_(CS0_N, IP5_15_12) | |
74 | #define GPSR1_20 FM(CLKOUT) | |
75 | #define GPSR1_19 F_(A19, IP5_11_8) | |
76 | #define GPSR1_18 F_(A18, IP5_7_4) | |
77 | #define GPSR1_17 F_(A17, IP5_3_0) | |
78 | #define GPSR1_16 F_(A16, IP4_31_28) | |
79 | #define GPSR1_15 F_(A15, IP4_27_24) | |
80 | #define GPSR1_14 F_(A14, IP4_23_20) | |
81 | #define GPSR1_13 F_(A13, IP4_19_16) | |
82 | #define GPSR1_12 F_(A12, IP4_15_12) | |
83 | #define GPSR1_11 F_(A11, IP4_11_8) | |
84 | #define GPSR1_10 F_(A10, IP4_7_4) | |
85 | #define GPSR1_9 F_(A9, IP4_3_0) | |
86 | #define GPSR1_8 F_(A8, IP3_31_28) | |
87 | #define GPSR1_7 F_(A7, IP3_27_24) | |
88 | #define GPSR1_6 F_(A6, IP3_23_20) | |
89 | #define GPSR1_5 F_(A5, IP3_19_16) | |
90 | #define GPSR1_4 F_(A4, IP3_15_12) | |
91 | #define GPSR1_3 F_(A3, IP3_11_8) | |
92 | #define GPSR1_2 F_(A2, IP3_7_4) | |
93 | #define GPSR1_1 F_(A1, IP3_3_0) | |
94 | #define GPSR1_0 F_(A0, IP2_31_28) | |
95 | ||
96 | /* GPSR2 */ | |
97 | #define GPSR2_25 F_(EX_WAIT0, IP2_27_24) | |
98 | #define GPSR2_24 F_(RD_WR_N, IP2_23_20) | |
99 | #define GPSR2_23 F_(RD_N, IP2_19_16) | |
100 | #define GPSR2_22 F_(BS_N, IP2_15_12) | |
101 | #define GPSR2_21 FM(AVB_PHY_INT) | |
102 | #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0) | |
103 | #define GPSR2_19 FM(AVB_RD3) | |
104 | #define GPSR2_18 F_(AVB_RD2, IP1_31_28) | |
105 | #define GPSR2_17 F_(AVB_RD1, IP1_27_24) | |
106 | #define GPSR2_16 F_(AVB_RD0, IP1_23_20) | |
107 | #define GPSR2_15 FM(AVB_RXC) | |
108 | #define GPSR2_14 FM(AVB_RX_CTL) | |
109 | #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16) | |
110 | #define GPSR2_12 F_(RPC_INT_N, IP1_15_12) | |
111 | #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8) | |
112 | #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4) | |
113 | #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0) | |
114 | #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28) | |
115 | #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24) | |
116 | #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20) | |
117 | #define GPSR2_5 FM(QSPI0_SSL) | |
118 | #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16) | |
119 | #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12) | |
120 | #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8) | |
121 | #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4) | |
122 | #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0) | |
123 | ||
124 | /* GPSR3 */ | |
125 | #define GPSR3_15 F_(SD1_WP, IP11_7_4) | |
126 | #define GPSR3_14 F_(SD1_CD, IP11_3_0) | |
127 | #define GPSR3_13 F_(SD0_WP, IP10_31_28) | |
128 | #define GPSR3_12 F_(SD0_CD, IP10_27_24) | |
129 | #define GPSR3_11 F_(SD1_DAT3, IP9_11_8) | |
130 | #define GPSR3_10 F_(SD1_DAT2, IP9_7_4) | |
131 | #define GPSR3_9 F_(SD1_DAT1, IP9_3_0) | |
132 | #define GPSR3_8 F_(SD1_DAT0, IP8_31_28) | |
133 | #define GPSR3_7 F_(SD1_CMD, IP8_27_24) | |
134 | #define GPSR3_6 F_(SD1_CLK, IP8_23_20) | |
135 | #define GPSR3_5 F_(SD0_DAT3, IP8_19_16) | |
136 | #define GPSR3_4 F_(SD0_DAT2, IP8_15_12) | |
137 | #define GPSR3_3 F_(SD0_DAT1, IP8_11_8) | |
138 | #define GPSR3_2 F_(SD0_DAT0, IP8_7_4) | |
139 | #define GPSR3_1 F_(SD0_CMD, IP8_3_0) | |
140 | #define GPSR3_0 F_(SD0_CLK, IP7_31_28) | |
141 | ||
142 | /* GPSR4 */ | |
143 | #define GPSR4_10 F_(SD3_DS, IP10_23_20) | |
144 | #define GPSR4_9 F_(SD3_DAT7, IP10_19_16) | |
145 | #define GPSR4_8 F_(SD3_DAT6, IP10_15_12) | |
146 | #define GPSR4_7 F_(SD3_DAT5, IP10_11_8) | |
147 | #define GPSR4_6 F_(SD3_DAT4, IP10_7_4) | |
148 | #define GPSR4_5 F_(SD3_DAT3, IP10_3_0) | |
149 | #define GPSR4_4 F_(SD3_DAT2, IP9_31_28) | |
150 | #define GPSR4_3 F_(SD3_DAT1, IP9_27_24) | |
151 | #define GPSR4_2 F_(SD3_DAT0, IP9_23_20) | |
152 | #define GPSR4_1 F_(SD3_CMD, IP9_19_16) | |
153 | #define GPSR4_0 F_(SD3_CLK, IP9_15_12) | |
154 | ||
155 | /* GPSR5 */ | |
156 | #define GPSR5_19 F_(MLB_DAT, IP13_23_20) | |
157 | #define GPSR5_18 F_(MLB_SIG, IP13_19_16) | |
158 | #define GPSR5_17 F_(MLB_CLK, IP13_15_12) | |
159 | #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8) | |
160 | #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4) | |
161 | #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0) | |
162 | #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28) | |
163 | #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24) | |
164 | #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20) | |
165 | #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16) | |
166 | #define GPSR5_9 F_(RX2_A, IP12_15_12) | |
167 | #define GPSR5_8 F_(TX2_A, IP12_11_8) | |
168 | #define GPSR5_7 F_(SCK2_A, IP12_7_4) | |
169 | #define GPSR5_6 F_(TX1, IP12_3_0) | |
170 | #define GPSR5_5 F_(RX1, IP11_31_28) | |
7f2e60f1 | 171 | #define GPSR5_4 F_(RTS0_N_A, IP11_23_20) |
cb13e46a MV |
172 | #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) |
173 | #define GPSR5_2 F_(TX0_A, IP11_15_12) | |
174 | #define GPSR5_1 F_(RX0_A, IP11_11_8) | |
175 | #define GPSR5_0 F_(SCK0_A, IP11_27_24) | |
176 | ||
177 | /* GPSR6 */ | |
178 | #define GPSR6_17 F_(USB30_PWEN, IP15_27_24) | |
179 | #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16) | |
180 | #define GPSR6_15 F_(SSI_WS6, IP15_15_12) | |
181 | #define GPSR6_14 F_(SSI_SCK6, IP15_11_8) | |
182 | #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4) | |
183 | #define GPSR6_12 F_(SSI_WS5, IP15_3_0) | |
184 | #define GPSR6_11 F_(SSI_SCK5, IP14_31_28) | |
185 | #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24) | |
186 | #define GPSR6_9 F_(USB30_OVC, IP15_31_28) | |
187 | #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20) | |
188 | #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20) | |
189 | #define GPSR6_6 F_(SSI_WS349, IP14_19_16) | |
190 | #define GPSR6_5 F_(SSI_SCK349, IP14_15_12) | |
191 | #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8) | |
192 | #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4) | |
193 | #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0) | |
194 | #define GPSR6_1 F_(SSI_WS01239, IP13_31_28) | |
195 | #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24) | |
196 | ||
197 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
198 | #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
199 | #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
200 | #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
201 | #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
202 | #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
203 | #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
204 | #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
205 | #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
206 | #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
207 | #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
208 | #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
209 | #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
210 | #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
211 | #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
212 | #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
213 | #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
214 | #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
215 | #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
216 | #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
217 | #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
218 | #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
219 | #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
220 | #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
221 | #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
222 | #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
223 | #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
224 | #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
7f2e60f1 | 225 | #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
cb13e46a MV |
226 | #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
227 | #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
228 | #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
229 | #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
230 | ||
231 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
232 | #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
233 | #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
234 | #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
235 | #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
236 | #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
237 | #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
238 | #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
239 | #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
240 | #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
241 | #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
242 | #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
243 | #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
244 | #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
245 | #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
7f2e60f1 | 246 | #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
cb13e46a MV |
247 | #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
248 | #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
7f2e60f1 | 249 | #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
cb13e46a MV |
250 | #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
251 | #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
252 | #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
253 | #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
254 | #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
255 | #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
256 | #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
257 | #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
258 | #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
259 | #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
260 | #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
261 | #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
262 | #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
263 | #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
264 | ||
265 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
266 | #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
267 | #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
268 | #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
269 | #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
270 | #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
271 | #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
272 | #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
273 | #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
274 | #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
275 | #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
276 | #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
277 | #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
278 | #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
279 | #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
280 | #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
281 | #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
282 | #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
283 | #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
284 | #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
285 | #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
286 | #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
287 | #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
288 | #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
289 | #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
290 | #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
291 | #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
292 | #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
293 | #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
294 | #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
7f2e60f1 ER |
295 | #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
296 | #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
cb13e46a MV |
297 | #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
298 | ||
299 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ | |
300 | #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
301 | #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
302 | #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
303 | #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
304 | #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
305 | #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
306 | #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
307 | #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
308 | #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
309 | #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
310 | #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
311 | #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
312 | #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
313 | #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
314 | #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
315 | #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
316 | #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
317 | #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
318 | #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
319 | #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
320 | #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
321 | #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
322 | #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
323 | #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
324 | #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
325 | #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
326 | #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
327 | #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
328 | #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
329 | #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
330 | #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
331 | #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
332 | ||
333 | #define PINMUX_GPSR \ | |
334 | \ | |
335 | \ | |
336 | \ | |
337 | \ | |
338 | \ | |
339 | \ | |
340 | \ | |
341 | GPSR2_25 \ | |
342 | GPSR2_24 \ | |
343 | GPSR2_23 \ | |
344 | GPSR1_22 GPSR2_22 \ | |
345 | GPSR1_21 GPSR2_21 \ | |
346 | GPSR1_20 GPSR2_20 \ | |
347 | GPSR1_19 GPSR2_19 GPSR5_19 \ | |
348 | GPSR1_18 GPSR2_18 GPSR5_18 \ | |
349 | GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \ | |
350 | GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \ | |
351 | GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \ | |
352 | GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \ | |
353 | GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \ | |
354 | GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \ | |
355 | GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \ | |
356 | GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ | |
357 | GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ | |
358 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ | |
359 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ | |
360 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ | |
361 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ | |
362 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ | |
363 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ | |
364 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ | |
365 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ | |
366 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 | |
367 | ||
368 | #define PINMUX_IPSR \ | |
369 | \ | |
370 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ | |
371 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ | |
372 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ | |
373 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ | |
374 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ | |
375 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ | |
376 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ | |
377 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ | |
378 | \ | |
379 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ | |
380 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ | |
381 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ | |
382 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ | |
383 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ | |
384 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ | |
385 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ | |
386 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ | |
387 | \ | |
388 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ | |
389 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ | |
390 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ | |
391 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ | |
392 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ | |
393 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ | |
394 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ | |
395 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ | |
396 | \ | |
397 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ | |
398 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ | |
399 | FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ | |
400 | FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ | |
401 | FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ | |
402 | FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ | |
403 | FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ | |
404 | FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 | |
405 | ||
8719ca81 MV |
406 | /* The bit numbering in MOD_SEL fields is reversed */ |
407 | #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 | |
408 | #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 | |
409 | ||
cb13e46a | 410 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ |
8719ca81 | 411 | #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0)) |
cb13e46a | 412 | #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) |
8719ca81 | 413 | #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0)) |
cb13e46a MV |
414 | #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) |
415 | #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) | |
416 | #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) | |
417 | #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) | |
8719ca81 MV |
418 | #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) |
419 | #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) | |
7f2e60f1 | 420 | #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) |
cb13e46a MV |
421 | #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) |
422 | #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) | |
8719ca81 MV |
423 | #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) |
424 | #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) | |
cb13e46a MV |
425 | #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) |
426 | #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) | |
427 | #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) | |
8719ca81 | 428 | #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0)) |
cb13e46a MV |
429 | #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) |
430 | #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) | |
431 | #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) | |
8719ca81 | 432 | #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) |
cb13e46a MV |
433 | |
434 | /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ | |
cb13e46a MV |
435 | #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) |
436 | #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) | |
437 | #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) | |
438 | #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) | |
8719ca81 MV |
439 | #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0)) |
440 | #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0)) | |
cb13e46a MV |
441 | #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) |
442 | #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) | |
443 | #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) | |
444 | #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) | |
8719ca81 MV |
445 | #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0)) |
446 | #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0)) | |
447 | #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0)) | |
cb13e46a MV |
448 | #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) |
449 | #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) | |
8719ca81 | 450 | #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0)) |
cb13e46a MV |
451 | #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) |
452 | ||
453 | #define PINMUX_MOD_SELS \ | |
454 | \ | |
7f2e60f1 | 455 | MOD_SEL0_30_29 \ |
cb13e46a MV |
456 | MOD_SEL1_29 \ |
457 | MOD_SEL0_28 MOD_SEL1_28 \ | |
458 | MOD_SEL0_27_26 \ | |
459 | MOD_SEL1_26 \ | |
460 | MOD_SEL0_25 MOD_SEL1_25 \ | |
461 | MOD_SEL0_24 MOD_SEL1_24_23_22 \ | |
462 | MOD_SEL0_23 \ | |
463 | MOD_SEL0_22 \ | |
464 | MOD_SEL0_21_20 MOD_SEL1_21_20_19 \ | |
465 | MOD_SEL0_19_18_17 MOD_SEL1_18 \ | |
466 | MOD_SEL1_17 \ | |
467 | MOD_SEL0_16 MOD_SEL1_16 \ | |
468 | MOD_SEL0_15 MOD_SEL1_15 \ | |
469 | MOD_SEL0_14 MOD_SEL1_14_13 \ | |
470 | MOD_SEL0_13_12 \ | |
471 | MOD_SEL1_12_11 \ | |
472 | MOD_SEL0_11_10 \ | |
473 | MOD_SEL1_10_9 \ | |
474 | MOD_SEL0_9 \ | |
475 | MOD_SEL0_8 MOD_SEL1_8 \ | |
476 | MOD_SEL0_7 MOD_SEL1_7 \ | |
477 | MOD_SEL0_6_5 MOD_SEL1_6_5 \ | |
478 | MOD_SEL0_4 MOD_SEL1_4 \ | |
479 | MOD_SEL0_3 \ | |
480 | MOD_SEL0_2 \ | |
481 | MOD_SEL0_1_0 | |
482 | ||
bf8d2dab MV |
483 | /* |
484 | * These pins are not able to be muxed but have other properties | |
485 | * that can be set, such as pull-up/pull-down enable. | |
486 | */ | |
487 | #define PINMUX_STATIC \ | |
488 | FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \ | |
489 | FM(AVB_TD3) \ | |
490 | FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \ | |
491 | FM(ASEBRK) \ | |
492 | FM(MLB_REF) | |
493 | ||
cb13e46a MV |
494 | enum { |
495 | PINMUX_RESERVED = 0, | |
496 | ||
497 | PINMUX_DATA_BEGIN, | |
498 | GP_ALL(DATA), | |
499 | PINMUX_DATA_END, | |
500 | ||
501 | #define F_(x, y) | |
502 | #define FM(x) FN_##x, | |
503 | PINMUX_FUNCTION_BEGIN, | |
504 | GP_ALL(FN), | |
505 | PINMUX_GPSR | |
506 | PINMUX_IPSR | |
507 | PINMUX_MOD_SELS | |
508 | PINMUX_FUNCTION_END, | |
509 | #undef F_ | |
510 | #undef FM | |
511 | ||
512 | #define F_(x, y) | |
513 | #define FM(x) x##_MARK, | |
514 | PINMUX_MARK_BEGIN, | |
515 | PINMUX_GPSR | |
516 | PINMUX_IPSR | |
517 | PINMUX_MOD_SELS | |
bf8d2dab | 518 | PINMUX_STATIC |
cb13e46a MV |
519 | PINMUX_MARK_END, |
520 | #undef F_ | |
521 | #undef FM | |
522 | }; | |
523 | ||
524 | static const u16 pinmux_data[] = { | |
525 | PINMUX_DATA_GP_ALL(), | |
526 | ||
bf8d2dab MV |
527 | PINMUX_SINGLE(CLKOUT), |
528 | PINMUX_SINGLE(AVB_PHY_INT), | |
529 | PINMUX_SINGLE(AVB_RD3), | |
530 | PINMUX_SINGLE(AVB_RXC), | |
531 | PINMUX_SINGLE(AVB_RX_CTL), | |
532 | PINMUX_SINGLE(QSPI0_SSL), | |
533 | ||
cb13e46a MV |
534 | /* IPSR0 */ |
535 | PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK), | |
536 | PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0), | |
537 | ||
538 | PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0), | |
539 | PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0), | |
540 | ||
541 | PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1), | |
542 | PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0), | |
543 | ||
544 | PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2), | |
545 | PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A), | |
546 | ||
547 | PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3), | |
548 | PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0), | |
549 | ||
550 | PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK), | |
551 | PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0), | |
552 | PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1), | |
553 | PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0), | |
554 | ||
555 | PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0), | |
556 | PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0), | |
557 | PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B), | |
558 | PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0), | |
559 | ||
560 | PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1), | |
561 | PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0), | |
562 | PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1), | |
563 | PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0), | |
564 | ||
565 | /* IPSR1 */ | |
566 | PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2), | |
567 | PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0), | |
568 | PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C), | |
569 | PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0), | |
570 | ||
571 | PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3), | |
572 | PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0), | |
573 | PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2), | |
574 | PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0), | |
575 | ||
576 | PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL), | |
577 | PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0), | |
578 | PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2), | |
579 | PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0), | |
580 | ||
581 | PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N), | |
582 | PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0), | |
583 | PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2), | |
584 | PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0), | |
585 | ||
586 | PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N), | |
587 | PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0), | |
588 | PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2), | |
589 | PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0), | |
590 | ||
591 | PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0), | |
592 | ||
593 | PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1), | |
594 | ||
595 | PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2), | |
596 | ||
597 | /* IPSR2 */ | |
598 | PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK), | |
599 | ||
600 | PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO), | |
601 | ||
602 | PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC), | |
603 | ||
604 | PINMUX_IPSR_GPSR(IP2_15_12, BS_N), | |
605 | PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0), | |
606 | PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC), | |
607 | PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK), | |
608 | PINMUX_IPSR_GPSR(IP2_15_12, TX3_C), | |
609 | PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1), | |
610 | ||
611 | PINMUX_IPSR_GPSR(IP2_19_16, RD_N), | |
612 | PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0), | |
613 | PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK), | |
614 | PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD), | |
615 | PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2), | |
616 | PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A), | |
617 | PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1), | |
618 | ||
619 | PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), | |
620 | PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), | |
621 | PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A), | |
622 | PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), | |
623 | PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), | |
624 | PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), | |
625 | PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0), | |
626 | ||
627 | PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), | |
628 | PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), | |
629 | PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A), | |
630 | PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), | |
631 | PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), | |
632 | PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), | |
633 | ||
634 | PINMUX_IPSR_GPSR(IP2_31_28, A0), | |
635 | PINMUX_IPSR_GPSR(IP2_31_28, IRQ0), | |
636 | PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0), | |
637 | PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1), | |
638 | PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0), | |
639 | PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE), | |
640 | PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3), | |
641 | PINMUX_IPSR_GPSR(IP2_31_28, IERX), | |
642 | PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE), | |
643 | ||
644 | /* IPSR3 */ | |
645 | PINMUX_IPSR_GPSR(IP3_3_0, A1), | |
646 | PINMUX_IPSR_GPSR(IP3_3_0, IRQ1), | |
647 | PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0), | |
648 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1), | |
649 | PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0), | |
650 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE), | |
651 | PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1), | |
652 | PINMUX_IPSR_GPSR(IP3_3_0, IETX), | |
653 | PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE), | |
654 | ||
655 | PINMUX_IPSR_GPSR(IP3_7_4, A2), | |
656 | PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), | |
657 | PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS), | |
658 | PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB), | |
659 | PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0), | |
660 | PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP), | |
661 | PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1), | |
662 | PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE), | |
663 | ||
664 | PINMUX_IPSR_GPSR(IP3_11_8, A3), | |
665 | PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0), | |
666 | PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0), | |
667 | PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12), | |
668 | PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0), | |
669 | PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D), | |
670 | PINMUX_IPSR_GPSR(IP3_11_8, IECLK), | |
671 | PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), | |
672 | ||
673 | PINMUX_IPSR_GPSR(IP3_15_12, A4), | |
7f2e60f1 | 674 | PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), |
cb13e46a MV |
675 | PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), |
676 | PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), | |
677 | PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), | |
678 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), | |
679 | PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1), | |
680 | ||
681 | PINMUX_IPSR_GPSR(IP3_19_16, A5), | |
682 | PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0), | |
683 | PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1), | |
684 | PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9), | |
685 | PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1), | |
686 | PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1), | |
687 | PINMUX_IPSR_GPSR(IP3_19_16, QPOLA), | |
688 | ||
689 | PINMUX_IPSR_GPSR(IP3_23_20, A6), | |
690 | PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0), | |
691 | PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1), | |
692 | PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10), | |
693 | PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1), | |
694 | ||
695 | PINMUX_IPSR_GPSR(IP3_27_24, A7), | |
696 | PINMUX_IPSR_GPSR(IP3_27_24, TX4_A), | |
697 | PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B), | |
698 | PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11), | |
699 | PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1), | |
700 | ||
701 | PINMUX_IPSR_GPSR(IP3_31_28, A8), | |
702 | PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0), | |
703 | PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1), | |
704 | PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2), | |
705 | PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0), | |
706 | PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC), | |
707 | PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1), | |
708 | PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS), | |
709 | ||
710 | /* IPSR4 */ | |
711 | PINMUX_IPSR_GPSR(IP4_3_0, A9), | |
712 | PINMUX_IPSR_GPSR(IP4_3_0, TX5_A), | |
713 | PINMUX_IPSR_GPSR(IP4_3_0, IRQ3), | |
714 | PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16), | |
715 | PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0), | |
716 | PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7), | |
717 | PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15), | |
718 | ||
719 | PINMUX_IPSR_GPSR(IP4_7_4, A10), | |
720 | PINMUX_IPSR_GPSR(IP4_7_4, IRQ4), | |
721 | PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1), | |
722 | PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13), | |
723 | PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0), | |
724 | PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5), | |
725 | PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B), | |
726 | PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13), | |
727 | ||
728 | PINMUX_IPSR_GPSR(IP4_11_8, A11), | |
729 | PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0), | |
730 | PINMUX_IPSR_GPSR(IP4_11_8, TX3_B), | |
731 | PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C), | |
732 | PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC), | |
733 | PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1), | |
734 | PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS), | |
735 | ||
736 | PINMUX_IPSR_GPSR(IP4_15_12, A12), | |
737 | PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0), | |
738 | PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B), | |
739 | PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17), | |
740 | PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0), | |
741 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6), | |
742 | PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14), | |
743 | ||
744 | PINMUX_IPSR_GPSR(IP4_19_16, A13), | |
745 | PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0), | |
746 | PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1), | |
747 | PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14), | |
748 | PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3), | |
749 | PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2), | |
750 | PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2), | |
751 | ||
752 | PINMUX_IPSR_GPSR(IP4_23_20, A14), | |
753 | PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1), | |
754 | PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1), | |
755 | PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15), | |
756 | PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D), | |
757 | PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3), | |
758 | PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3), | |
759 | ||
760 | PINMUX_IPSR_GPSR(IP4_27_24, A15), | |
761 | PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2), | |
762 | PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B), | |
763 | PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18), | |
764 | PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0), | |
765 | PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4), | |
766 | PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4), | |
767 | ||
768 | PINMUX_IPSR_GPSR(IP4_31_28, A16), | |
769 | PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC), | |
770 | PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B), | |
771 | PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19), | |
772 | PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0), | |
773 | PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5), | |
774 | PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5), | |
775 | ||
776 | /* IPSR5 */ | |
777 | PINMUX_IPSR_GPSR(IP5_3_0, A17), | |
778 | PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), | |
779 | PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20), | |
780 | PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0), | |
781 | PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6), | |
782 | PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6), | |
783 | ||
784 | PINMUX_IPSR_GPSR(IP5_7_4, A18), | |
785 | PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), | |
786 | PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21), | |
787 | PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0), | |
788 | PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0), | |
789 | PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4), | |
790 | PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0), | |
791 | ||
792 | PINMUX_IPSR_GPSR(IP5_11_8, A19), | |
793 | PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), | |
794 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22), | |
795 | PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0), | |
796 | PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1), | |
797 | PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E), | |
798 | PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1), | |
799 | ||
800 | PINMUX_IPSR_GPSR(IP5_15_12, CS0_N), | |
801 | PINMUX_IPSR_GPSR(IP5_15_12, SCL5), | |
802 | PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0), | |
803 | PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1), | |
804 | PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16), | |
805 | ||
806 | PINMUX_IPSR_GPSR(IP5_19_16, WE0_N), | |
807 | PINMUX_IPSR_GPSR(IP5_19_16, SDA5), | |
808 | PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1), | |
809 | PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1), | |
810 | PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17), | |
811 | ||
812 | PINMUX_IPSR_GPSR(IP5_23_20, D0), | |
813 | PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), | |
814 | PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2), | |
815 | PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2), | |
816 | PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18), | |
817 | ||
818 | PINMUX_IPSR_GPSR(IP5_27_24, D1), | |
819 | PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0), | |
820 | PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0), | |
821 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), | |
822 | PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), | |
823 | PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), | |
7f2e60f1 | 824 | PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), |
cb13e46a MV |
825 | PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), |
826 | ||
827 | PINMUX_IPSR_GPSR(IP5_31_28, D2), | |
828 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0), | |
829 | PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2), | |
830 | PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0), | |
831 | PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3), | |
832 | PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2), | |
833 | PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19), | |
834 | ||
835 | /* IPSR6 */ | |
836 | PINMUX_IPSR_GPSR(IP6_3_0, D3), | |
837 | PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A), | |
838 | PINMUX_IPSR_GPSR(IP6_3_0, TX5_C), | |
839 | PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0), | |
840 | PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4), | |
841 | PINMUX_IPSR_GPSR(IP6_3_0, TX4_C), | |
842 | PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20), | |
843 | ||
844 | PINMUX_IPSR_GPSR(IP6_7_4, D4), | |
845 | PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), | |
846 | PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), | |
847 | PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), | |
7f2e60f1 | 848 | PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), |
cb13e46a MV |
849 | PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), |
850 | PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), | |
851 | ||
852 | PINMUX_IPSR_GPSR(IP6_11_8, D5), | |
853 | PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0), | |
854 | PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1), | |
855 | PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5), | |
856 | PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1), | |
857 | PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21), | |
858 | ||
859 | PINMUX_IPSR_GPSR(IP6_15_12, D6), | |
860 | PINMUX_IPSR_GPSR(IP6_15_12, TX3_A), | |
861 | PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B), | |
862 | PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6), | |
863 | PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1), | |
864 | PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22), | |
865 | ||
866 | PINMUX_IPSR_GPSR(IP6_19_16, D7), | |
867 | PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX), | |
868 | PINMUX_IPSR_GPSR(IP6_19_16, IRQ5), | |
869 | PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX), | |
870 | PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0), | |
871 | PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1), | |
872 | ||
873 | PINMUX_IPSR_GPSR(IP6_23_20, D8), | |
874 | PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0), | |
875 | PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1), | |
876 | PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0), | |
877 | PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7), | |
878 | PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1), | |
879 | PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4), | |
880 | PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23), | |
881 | ||
882 | PINMUX_IPSR_GPSR(IP6_27_24, D9), | |
883 | PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0), | |
884 | PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0), | |
885 | PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0), | |
886 | PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1), | |
887 | PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4), | |
888 | PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8), | |
889 | ||
890 | PINMUX_IPSR_GPSR(IP6_31_28, D10), | |
891 | PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0), | |
892 | PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0), | |
893 | PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1), | |
894 | PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1), | |
895 | PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E), | |
896 | PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9), | |
897 | ||
898 | /* IPSR7 */ | |
899 | PINMUX_IPSR_GPSR(IP7_3_0, D11), | |
900 | PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A), | |
901 | PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0), | |
902 | PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2), | |
903 | PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1), | |
904 | PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4), | |
905 | PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10), | |
906 | ||
907 | PINMUX_IPSR_GPSR(IP7_7_4, D12), | |
908 | PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX), | |
909 | PINMUX_IPSR_GPSR(IP7_7_4, TX4_B), | |
910 | PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX), | |
911 | PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0), | |
912 | PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1), | |
913 | ||
914 | PINMUX_IPSR_GPSR(IP7_11_8, D13), | |
915 | PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX), | |
916 | PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1), | |
917 | PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX), | |
918 | PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0), | |
919 | PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1), | |
920 | PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1), | |
921 | ||
922 | PINMUX_IPSR_GPSR(IP7_15_12, D14), | |
923 | PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK), | |
924 | PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0), | |
925 | PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A), | |
926 | PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1), | |
927 | PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1), | |
928 | ||
929 | PINMUX_IPSR_GPSR(IP7_19_16, D15), | |
930 | PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A), | |
931 | PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A), | |
932 | PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A), | |
933 | PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3), | |
934 | PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11), | |
935 | ||
936 | PINMUX_IPSR_GPSR(IP7_23_20, SCL4), | |
937 | PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26), | |
938 | PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0), | |
939 | PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1), | |
940 | PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1), | |
941 | PINMUX_IPSR_GPSR(IP7_23_20, QCLK), | |
942 | ||
943 | PINMUX_IPSR_GPSR(IP7_27_24, SDA4), | |
944 | PINMUX_IPSR_GPSR(IP7_27_24, WE1_N), | |
945 | PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1), | |
946 | PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1), | |
947 | PINMUX_IPSR_GPSR(IP7_27_24, QPOLB), | |
948 | ||
949 | PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK), | |
950 | PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8), | |
951 | PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2), | |
952 | PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1), | |
953 | PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4), | |
954 | PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1), | |
955 | ||
956 | /* IPSR8 */ | |
957 | PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD), | |
958 | PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9), | |
959 | PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1), | |
960 | PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1), | |
961 | ||
962 | PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0), | |
963 | PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10), | |
964 | PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B), | |
965 | PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1), | |
966 | ||
967 | PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1), | |
968 | PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11), | |
969 | PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2), | |
970 | PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1), | |
971 | PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1), | |
972 | ||
973 | PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2), | |
974 | PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12), | |
975 | PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2), | |
976 | PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1), | |
977 | PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B), | |
978 | ||
979 | PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3), | |
980 | PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13), | |
981 | PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2), | |
982 | PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4), | |
983 | PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2), | |
984 | PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), | |
985 | ||
986 | PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), | |
7f2e60f1 | 987 | PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), |
cb13e46a MV |
988 | |
989 | PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), | |
7f2e60f1 | 990 | PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), |
cb13e46a MV |
991 | |
992 | PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), | |
7f2e60f1 | 993 | PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), |
cb13e46a MV |
994 | |
995 | /* IPSR9 */ | |
996 | PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), | |
7f2e60f1 | 997 | PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), |
cb13e46a MV |
998 | |
999 | PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), | |
7f2e60f1 | 1000 | PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), |
cb13e46a MV |
1001 | |
1002 | PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), | |
7f2e60f1 | 1003 | PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), |
cb13e46a MV |
1004 | |
1005 | PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), | |
1006 | PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), | |
1007 | ||
1008 | PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD), | |
1009 | PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N), | |
1010 | ||
1011 | PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0), | |
1012 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0), | |
1013 | ||
1014 | PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1), | |
1015 | PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1), | |
1016 | ||
1017 | PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2), | |
1018 | PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2), | |
1019 | ||
1020 | /* IPSR10 */ | |
1021 | PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3), | |
1022 | PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3), | |
1023 | ||
1024 | PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4), | |
1025 | PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4), | |
1026 | ||
1027 | PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5), | |
1028 | PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5), | |
1029 | ||
1030 | PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6), | |
1031 | PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6), | |
1032 | ||
1033 | PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7), | |
1034 | PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7), | |
1035 | ||
1036 | PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS), | |
1037 | PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), | |
1038 | ||
1039 | PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), | |
7f2e60f1 | 1040 | PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), |
cb13e46a MV |
1041 | PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), |
1042 | PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), | |
1043 | PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), | |
1044 | PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), | |
7f2e60f1 | 1045 | PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B), |
cb13e46a MV |
1046 | PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), |
1047 | ||
1048 | PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), | |
7f2e60f1 | 1049 | PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), |
cb13e46a MV |
1050 | PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), |
1051 | PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), | |
1052 | PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), | |
1053 | PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), | |
7f2e60f1 | 1054 | PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B), |
cb13e46a MV |
1055 | PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), |
1056 | ||
1057 | /* IPSR11 */ | |
1058 | PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), | |
7f2e60f1 | 1059 | PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), |
cb13e46a MV |
1060 | PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), |
1061 | PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), | |
1062 | PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), | |
1063 | ||
1064 | PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), | |
7f2e60f1 | 1065 | PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), |
cb13e46a MV |
1066 | PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), |
1067 | PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), | |
1068 | PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), | |
1069 | ||
1070 | PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), | |
1071 | PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), | |
7f2e60f1 | 1072 | PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A), |
cb13e46a MV |
1073 | PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), |
1074 | PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), | |
1075 | ||
bf93f24c | 1076 | PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), |
cb13e46a | 1077 | PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), |
7f2e60f1 | 1078 | PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A), |
cb13e46a MV |
1079 | PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), |
1080 | PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), | |
1081 | ||
1082 | PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), | |
7f2e60f1 | 1083 | PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), |
cb13e46a MV |
1084 | PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), |
1085 | PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), | |
1086 | PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), | |
1087 | PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), | |
1088 | ||
7f2e60f1 ER |
1089 | PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), |
1090 | PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), | |
cb13e46a MV |
1091 | PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), |
1092 | PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), | |
1093 | PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), | |
1094 | PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0), | |
1095 | ||
1096 | PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), | |
1097 | PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), | |
1098 | PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), | |
7f2e60f1 | 1099 | PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), |
cb13e46a MV |
1100 | PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), |
1101 | PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), | |
65eef78c | 1102 | PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), |
cb13e46a MV |
1103 | |
1104 | PINMUX_IPSR_GPSR(IP11_31_28, RX1), | |
1105 | PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1), | |
1106 | PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1), | |
1107 | PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B), | |
1108 | ||
1109 | /* IPSR12 */ | |
1110 | PINMUX_IPSR_GPSR(IP12_3_0, TX1), | |
1111 | PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B), | |
1112 | PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), | |
1113 | PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), | |
1114 | ||
ef083ecf | 1115 | PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0), |
cb13e46a MV |
1116 | PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), |
1117 | PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), | |
1118 | PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), | |
1119 | PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0), | |
1120 | PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), | |
1121 | PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), | |
1122 | ||
ef083ecf | 1123 | PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0), |
cb13e46a MV |
1124 | PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), |
1125 | PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), | |
1126 | PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), | |
1127 | PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), | |
1128 | PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), | |
1129 | ||
ef083ecf | 1130 | PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0), |
cb13e46a MV |
1131 | PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), |
1132 | PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), | |
1133 | PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), | |
1134 | PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0), | |
1135 | PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1), | |
1136 | ||
1137 | PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK), | |
1138 | PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78), | |
1139 | ||
1140 | PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), | |
1141 | PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), | |
ef083ecf | 1142 | PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1), |
cb13e46a MV |
1143 | |
1144 | PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), | |
1145 | PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), | |
ef083ecf | 1146 | PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1), |
cb13e46a MV |
1147 | |
1148 | PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), | |
1149 | PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), | |
1150 | PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8), | |
1151 | ||
1152 | /* IPSR13 */ | |
1153 | PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), | |
1154 | PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0), | |
1155 | PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4), | |
1156 | PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0), | |
1157 | PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C), | |
1158 | PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0), | |
1159 | ||
1160 | PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), | |
1161 | PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A), | |
1162 | PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4), | |
1163 | PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0), | |
1164 | PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2), | |
1165 | PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A), | |
1166 | ||
1167 | PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9), | |
1168 | PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0), | |
1169 | PINMUX_IPSR_GPSR(IP13_11_8, SCK1), | |
1170 | ||
1171 | PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK), | |
1172 | PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1), | |
1173 | PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0), | |
1174 | PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1), | |
1175 | PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1), | |
1176 | PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A), | |
1177 | ||
1178 | PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG), | |
1179 | PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1), | |
1180 | PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), | |
1181 | PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), | |
1182 | PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), | |
7f2e60f1 | 1183 | PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A), |
cb13e46a MV |
1184 | |
1185 | PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), | |
8719ca81 | 1186 | PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), |
cb13e46a MV |
1187 | PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), |
1188 | PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), | |
1189 | ||
1190 | PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239), | |
1191 | ||
1192 | PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239), | |
1193 | ||
1194 | /* IPSR14 */ | |
1195 | PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0), | |
1196 | ||
1197 | PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1), | |
1198 | PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1), | |
1199 | PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1), | |
1200 | ||
1201 | PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2), | |
1202 | PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B), | |
1203 | PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0), | |
1204 | PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1), | |
1205 | ||
1206 | PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349), | |
1207 | PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2), | |
1208 | ||
1209 | PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349), | |
1210 | PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2), | |
1211 | ||
1212 | PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3), | |
1213 | PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C), | |
1214 | PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1), | |
1215 | PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1), | |
1216 | ||
1217 | PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4), | |
1218 | PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0), | |
1219 | PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1), | |
1220 | ||
1221 | PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5), | |
1222 | PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1), | |
1223 | PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B), | |
1224 | PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3), | |
1225 | PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1), | |
1226 | ||
1227 | /* IPSR15 */ | |
1228 | PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5), | |
1229 | PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B), | |
1230 | PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1), | |
1231 | PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3), | |
1232 | ||
1233 | PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5), | |
1234 | PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1), | |
1235 | PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2), | |
1236 | PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0), | |
1237 | ||
1238 | PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6), | |
1239 | PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0), | |
1240 | PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2), | |
1241 | PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1), | |
1242 | PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1), | |
1243 | PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B), | |
1244 | ||
1245 | PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6), | |
1246 | PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), | |
1247 | PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C), | |
1248 | PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), | |
1249 | PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), | |
1250 | PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), | |
7f2e60f1 | 1251 | PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B), |
cb13e46a MV |
1252 | |
1253 | PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), | |
1254 | PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), | |
1255 | PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C), | |
1256 | PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3), | |
1257 | PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3), | |
1258 | PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1), | |
1259 | PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B), | |
1260 | ||
1261 | PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA), | |
1262 | ||
1263 | PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN), | |
1264 | PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A), | |
1265 | ||
1266 | PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC), | |
1267 | PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0), | |
bf8d2dab MV |
1268 | |
1269 | /* | |
1270 | * Static pins can not be muxed between different functions but | |
8719ca81 | 1271 | * still need mark entries in the pinmux list. Add each static |
bf8d2dab | 1272 | * pin to the list without an associated function. The sh-pfc |
8719ca81 MV |
1273 | * core will do the right thing and skip trying to mux the pin |
1274 | * while still applying configuration to it. | |
bf8d2dab MV |
1275 | */ |
1276 | #define FM(x) PINMUX_DATA(x##_MARK, 0), | |
1277 | PINMUX_STATIC | |
1278 | #undef FM | |
cb13e46a MV |
1279 | }; |
1280 | ||
bf8d2dab MV |
1281 | /* |
1282 | * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs. | |
1283 | * Physical layout rows: A - AE, cols: 1 - 25. | |
1284 | */ | |
1285 | #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) | |
1286 | #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300) | |
1287 | #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) | |
1288 | #define PIN_NONE U16_MAX | |
1289 | ||
cb13e46a MV |
1290 | static const struct sh_pfc_pin pinmux_pins[] = { |
1291 | PINMUX_GPIO_GP_ALL(), | |
bf8d2dab MV |
1292 | |
1293 | /* | |
1294 | * Pins not associated with a GPIO port. | |
1295 | * | |
1296 | * The pin positions are different between different R8A77990 | |
1297 | * packages, all that is needed for the pfc driver is a unique | |
1298 | * number for each pin. To this end use the pin layout from | |
1299 | * R8A77990 to calculate a unique number for each pin. | |
1300 | */ | |
1301 | SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS), | |
1302 | SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS), | |
1303 | SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS), | |
1304 | SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS), | |
1305 | SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS), | |
1306 | SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS), | |
1307 | SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS), | |
1308 | SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS), | |
1309 | SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS), | |
1310 | SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS), | |
1311 | SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS), | |
1312 | SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS), | |
1313 | SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS), | |
1314 | SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS), | |
1315 | SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS), | |
1316 | SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS), | |
cb13e46a MV |
1317 | }; |
1318 | ||
bf8d2dab MV |
1319 | /* - AUDIO CLOCK ------------------------------------------------------------ */ |
1320 | static const unsigned int audio_clk_a_pins[] = { | |
1321 | /* CLK A */ | |
1322 | RCAR_GP_PIN(6, 8), | |
1323 | }; | |
1324 | ||
1325 | static const unsigned int audio_clk_a_mux[] = { | |
1326 | AUDIO_CLKA_MARK, | |
1327 | }; | |
1328 | ||
1329 | static const unsigned int audio_clk_b_a_pins[] = { | |
1330 | /* CLK B_A */ | |
1331 | RCAR_GP_PIN(5, 7), | |
1332 | }; | |
1333 | ||
1334 | static const unsigned int audio_clk_b_a_mux[] = { | |
1335 | AUDIO_CLKB_A_MARK, | |
1336 | }; | |
1337 | ||
1338 | static const unsigned int audio_clk_b_b_pins[] = { | |
1339 | /* CLK B_B */ | |
1340 | RCAR_GP_PIN(6, 7), | |
1341 | }; | |
1342 | ||
1343 | static const unsigned int audio_clk_b_b_mux[] = { | |
1344 | AUDIO_CLKB_B_MARK, | |
1345 | }; | |
1346 | ||
1347 | static const unsigned int audio_clk_b_c_pins[] = { | |
1348 | /* CLK B_C */ | |
1349 | RCAR_GP_PIN(6, 13), | |
1350 | }; | |
1351 | ||
1352 | static const unsigned int audio_clk_b_c_mux[] = { | |
1353 | AUDIO_CLKB_C_MARK, | |
1354 | }; | |
1355 | ||
1356 | static const unsigned int audio_clk_c_a_pins[] = { | |
1357 | /* CLK C_A */ | |
1358 | RCAR_GP_PIN(5, 16), | |
1359 | }; | |
1360 | ||
1361 | static const unsigned int audio_clk_c_a_mux[] = { | |
1362 | AUDIO_CLKC_A_MARK, | |
1363 | }; | |
1364 | ||
1365 | static const unsigned int audio_clk_c_b_pins[] = { | |
1366 | /* CLK C_B */ | |
1367 | RCAR_GP_PIN(6, 3), | |
1368 | }; | |
1369 | ||
1370 | static const unsigned int audio_clk_c_b_mux[] = { | |
1371 | AUDIO_CLKC_B_MARK, | |
1372 | }; | |
1373 | ||
1374 | static const unsigned int audio_clk_c_c_pins[] = { | |
1375 | /* CLK C_C */ | |
1376 | RCAR_GP_PIN(6, 14), | |
1377 | }; | |
1378 | ||
1379 | static const unsigned int audio_clk_c_c_mux[] = { | |
1380 | AUDIO_CLKC_C_MARK, | |
1381 | }; | |
1382 | ||
1383 | static const unsigned int audio_clkout_a_pins[] = { | |
1384 | /* CLKOUT_A */ | |
1385 | RCAR_GP_PIN(5, 3), | |
1386 | }; | |
1387 | ||
1388 | static const unsigned int audio_clkout_a_mux[] = { | |
1389 | AUDIO_CLKOUT_A_MARK, | |
1390 | }; | |
1391 | ||
1392 | static const unsigned int audio_clkout_b_pins[] = { | |
1393 | /* CLKOUT_B */ | |
1394 | RCAR_GP_PIN(5, 13), | |
1395 | }; | |
1396 | ||
1397 | static const unsigned int audio_clkout_b_mux[] = { | |
1398 | AUDIO_CLKOUT_B_MARK, | |
1399 | }; | |
1400 | ||
1401 | static const unsigned int audio_clkout1_a_pins[] = { | |
1402 | /* CLKOUT1_A */ | |
1403 | RCAR_GP_PIN(5, 4), | |
1404 | }; | |
1405 | ||
1406 | static const unsigned int audio_clkout1_a_mux[] = { | |
1407 | AUDIO_CLKOUT1_A_MARK, | |
1408 | }; | |
1409 | ||
1410 | static const unsigned int audio_clkout1_b_pins[] = { | |
1411 | /* CLKOUT1_B */ | |
1412 | RCAR_GP_PIN(5, 5), | |
1413 | }; | |
1414 | ||
1415 | static const unsigned int audio_clkout1_b_mux[] = { | |
1416 | AUDIO_CLKOUT1_B_MARK, | |
1417 | }; | |
1418 | ||
1419 | static const unsigned int audio_clkout1_c_pins[] = { | |
1420 | /* CLKOUT1_C */ | |
1421 | RCAR_GP_PIN(6, 7), | |
1422 | }; | |
1423 | ||
1424 | static const unsigned int audio_clkout1_c_mux[] = { | |
1425 | AUDIO_CLKOUT1_C_MARK, | |
1426 | }; | |
1427 | ||
1428 | static const unsigned int audio_clkout2_a_pins[] = { | |
1429 | /* CLKOUT2_A */ | |
1430 | RCAR_GP_PIN(5, 8), | |
1431 | }; | |
1432 | ||
1433 | static const unsigned int audio_clkout2_a_mux[] = { | |
1434 | AUDIO_CLKOUT2_A_MARK, | |
1435 | }; | |
1436 | ||
1437 | static const unsigned int audio_clkout2_b_pins[] = { | |
1438 | /* CLKOUT2_B */ | |
1439 | RCAR_GP_PIN(6, 4), | |
1440 | }; | |
1441 | ||
1442 | static const unsigned int audio_clkout2_b_mux[] = { | |
1443 | AUDIO_CLKOUT2_B_MARK, | |
1444 | }; | |
1445 | ||
1446 | static const unsigned int audio_clkout2_c_pins[] = { | |
1447 | /* CLKOUT2_C */ | |
1448 | RCAR_GP_PIN(6, 15), | |
1449 | }; | |
1450 | ||
1451 | static const unsigned int audio_clkout2_c_mux[] = { | |
1452 | AUDIO_CLKOUT2_C_MARK, | |
1453 | }; | |
1454 | ||
1455 | static const unsigned int audio_clkout3_a_pins[] = { | |
1456 | /* CLKOUT3_A */ | |
1457 | RCAR_GP_PIN(5, 9), | |
1458 | }; | |
1459 | ||
1460 | static const unsigned int audio_clkout3_a_mux[] = { | |
1461 | AUDIO_CLKOUT3_A_MARK, | |
1462 | }; | |
1463 | ||
1464 | static const unsigned int audio_clkout3_b_pins[] = { | |
1465 | /* CLKOUT3_B */ | |
1466 | RCAR_GP_PIN(5, 6), | |
1467 | }; | |
1468 | ||
1469 | static const unsigned int audio_clkout3_b_mux[] = { | |
1470 | AUDIO_CLKOUT3_B_MARK, | |
1471 | }; | |
1472 | ||
1473 | static const unsigned int audio_clkout3_c_pins[] = { | |
1474 | /* CLKOUT3_C */ | |
1475 | RCAR_GP_PIN(6, 16), | |
1476 | }; | |
1477 | ||
1478 | static const unsigned int audio_clkout3_c_mux[] = { | |
1479 | AUDIO_CLKOUT3_C_MARK, | |
1480 | }; | |
1481 | ||
1482 | /* - EtherAVB --------------------------------------------------------------- */ | |
1483 | static const unsigned int avb_link_pins[] = { | |
1484 | /* AVB_LINK */ | |
1485 | RCAR_GP_PIN(2, 23), | |
1486 | }; | |
1487 | ||
1488 | static const unsigned int avb_link_mux[] = { | |
1489 | AVB_LINK_MARK, | |
1490 | }; | |
1491 | ||
1492 | static const unsigned int avb_magic_pins[] = { | |
1493 | /* AVB_MAGIC */ | |
1494 | RCAR_GP_PIN(2, 22), | |
1495 | }; | |
1496 | ||
1497 | static const unsigned int avb_magic_mux[] = { | |
1498 | AVB_MAGIC_MARK, | |
1499 | }; | |
1500 | ||
1501 | static const unsigned int avb_phy_int_pins[] = { | |
1502 | /* AVB_PHY_INT */ | |
1503 | RCAR_GP_PIN(2, 21), | |
1504 | }; | |
1505 | ||
1506 | static const unsigned int avb_phy_int_mux[] = { | |
1507 | AVB_PHY_INT_MARK, | |
1508 | }; | |
1509 | ||
1510 | static const unsigned int avb_mii_pins[] = { | |
1511 | /* | |
1512 | * AVB_RX_CTL, AVB_RXC, AVB_RD0, | |
1513 | * AVB_RD1, AVB_RD2, AVB_RD3, | |
1514 | * AVB_TXCREFCLK | |
1515 | */ | |
1516 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), | |
1517 | RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), | |
1518 | RCAR_GP_PIN(2, 20), | |
1519 | }; | |
1520 | ||
1521 | static const unsigned int avb_mii_mux[] = { | |
1522 | AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, | |
1523 | AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, | |
1524 | AVB_TXCREFCLK_MARK, | |
1525 | }; | |
1526 | ||
1527 | static const unsigned int avb_avtp_pps_pins[] = { | |
1528 | /* AVB_AVTP_PPS */ | |
1529 | RCAR_GP_PIN(1, 2), | |
1530 | }; | |
1531 | ||
1532 | static const unsigned int avb_avtp_pps_mux[] = { | |
1533 | AVB_AVTP_PPS_MARK, | |
1534 | }; | |
1535 | ||
1536 | static const unsigned int avb_avtp_match_a_pins[] = { | |
1537 | /* AVB_AVTP_MATCH_A */ | |
1538 | RCAR_GP_PIN(2, 24), | |
1539 | }; | |
1540 | ||
1541 | static const unsigned int avb_avtp_match_a_mux[] = { | |
1542 | AVB_AVTP_MATCH_A_MARK, | |
1543 | }; | |
1544 | ||
1545 | static const unsigned int avb_avtp_capture_a_pins[] = { | |
1546 | /* AVB_AVTP_CAPTURE_A */ | |
1547 | RCAR_GP_PIN(2, 25), | |
1548 | }; | |
1549 | ||
1550 | static const unsigned int avb_avtp_capture_a_mux[] = { | |
1551 | AVB_AVTP_CAPTURE_A_MARK, | |
1552 | }; | |
1553 | ||
1554 | /* - CAN ------------------------------------------------------------------ */ | |
1555 | static const unsigned int can0_data_pins[] = { | |
1556 | /* TX, RX */ | |
1557 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
1558 | }; | |
1559 | ||
1560 | static const unsigned int can0_data_mux[] = { | |
1561 | CAN0_TX_MARK, CAN0_RX_MARK, | |
1562 | }; | |
1563 | ||
1564 | static const unsigned int can1_data_pins[] = { | |
1565 | /* TX, RX */ | |
1566 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), | |
1567 | }; | |
1568 | ||
1569 | static const unsigned int can1_data_mux[] = { | |
1570 | CAN1_TX_MARK, CAN1_RX_MARK, | |
1571 | }; | |
1572 | ||
1573 | /* - CAN Clock -------------------------------------------------------------- */ | |
1574 | static const unsigned int can_clk_pins[] = { | |
1575 | /* CLK */ | |
1576 | RCAR_GP_PIN(0, 14), | |
1577 | }; | |
1578 | ||
1579 | static const unsigned int can_clk_mux[] = { | |
1580 | CAN_CLK_MARK, | |
1581 | }; | |
1582 | ||
1583 | /* - CAN FD --------------------------------------------------------------- */ | |
1584 | static const unsigned int canfd0_data_pins[] = { | |
1585 | /* TX, RX */ | |
1586 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
1587 | }; | |
1588 | ||
1589 | static const unsigned int canfd0_data_mux[] = { | |
1590 | CANFD0_TX_MARK, CANFD0_RX_MARK, | |
1591 | }; | |
1592 | ||
1593 | static const unsigned int canfd1_data_pins[] = { | |
1594 | /* TX, RX */ | |
1595 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), | |
1596 | }; | |
1597 | ||
1598 | static const unsigned int canfd1_data_mux[] = { | |
1599 | CANFD1_TX_MARK, CANFD1_RX_MARK, | |
1600 | }; | |
1601 | ||
1602 | /* - DRIF0 --------------------------------------------------------------- */ | |
1603 | static const unsigned int drif0_ctrl_a_pins[] = { | |
1604 | /* CLK, SYNC */ | |
1605 | RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19), | |
1606 | }; | |
1607 | ||
1608 | static const unsigned int drif0_ctrl_a_mux[] = { | |
1609 | RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, | |
1610 | }; | |
1611 | ||
1612 | static const unsigned int drif0_data0_a_pins[] = { | |
1613 | /* D0 */ | |
1614 | RCAR_GP_PIN(5, 17), | |
1615 | }; | |
1616 | ||
1617 | static const unsigned int drif0_data0_a_mux[] = { | |
1618 | RIF0_D0_A_MARK, | |
1619 | }; | |
1620 | ||
1621 | static const unsigned int drif0_data1_a_pins[] = { | |
1622 | /* D1 */ | |
1623 | RCAR_GP_PIN(5, 18), | |
1624 | }; | |
1625 | ||
1626 | static const unsigned int drif0_data1_a_mux[] = { | |
1627 | RIF0_D1_A_MARK, | |
1628 | }; | |
1629 | ||
1630 | static const unsigned int drif0_ctrl_b_pins[] = { | |
1631 | /* CLK, SYNC */ | |
1632 | RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), | |
1633 | }; | |
1634 | ||
1635 | static const unsigned int drif0_ctrl_b_mux[] = { | |
1636 | RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, | |
1637 | }; | |
1638 | ||
1639 | static const unsigned int drif0_data0_b_pins[] = { | |
1640 | /* D0 */ | |
1641 | RCAR_GP_PIN(3, 13), | |
1642 | }; | |
1643 | ||
1644 | static const unsigned int drif0_data0_b_mux[] = { | |
1645 | RIF0_D0_B_MARK, | |
1646 | }; | |
1647 | ||
1648 | static const unsigned int drif0_data1_b_pins[] = { | |
1649 | /* D1 */ | |
1650 | RCAR_GP_PIN(3, 14), | |
1651 | }; | |
1652 | ||
1653 | static const unsigned int drif0_data1_b_mux[] = { | |
1654 | RIF0_D1_B_MARK, | |
1655 | }; | |
1656 | ||
1657 | /* - DRIF1 --------------------------------------------------------------- */ | |
1658 | static const unsigned int drif1_ctrl_pins[] = { | |
1659 | /* CLK, SYNC */ | |
1660 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1), | |
1661 | }; | |
1662 | ||
1663 | static const unsigned int drif1_ctrl_mux[] = { | |
1664 | RIF1_CLK_MARK, RIF1_SYNC_MARK, | |
1665 | }; | |
1666 | ||
1667 | static const unsigned int drif1_data0_pins[] = { | |
1668 | /* D0 */ | |
1669 | RCAR_GP_PIN(5, 2), | |
1670 | }; | |
1671 | ||
1672 | static const unsigned int drif1_data0_mux[] = { | |
1673 | RIF1_D0_MARK, | |
1674 | }; | |
1675 | ||
1676 | static const unsigned int drif1_data1_pins[] = { | |
1677 | /* D1 */ | |
1678 | RCAR_GP_PIN(5, 3), | |
1679 | }; | |
1680 | ||
1681 | static const unsigned int drif1_data1_mux[] = { | |
1682 | RIF1_D1_MARK, | |
1683 | }; | |
1684 | ||
1685 | /* - DRIF2 --------------------------------------------------------------- */ | |
1686 | static const unsigned int drif2_ctrl_a_pins[] = { | |
1687 | /* CLK, SYNC */ | |
1688 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | |
1689 | }; | |
1690 | ||
1691 | static const unsigned int drif2_ctrl_a_mux[] = { | |
1692 | RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, | |
1693 | }; | |
1694 | ||
1695 | static const unsigned int drif2_data0_a_pins[] = { | |
1696 | /* D0 */ | |
1697 | RCAR_GP_PIN(2, 8), | |
1698 | }; | |
1699 | ||
1700 | static const unsigned int drif2_data0_a_mux[] = { | |
1701 | RIF2_D0_A_MARK, | |
1702 | }; | |
1703 | ||
1704 | static const unsigned int drif2_data1_a_pins[] = { | |
1705 | /* D1 */ | |
1706 | RCAR_GP_PIN(2, 9), | |
1707 | }; | |
1708 | ||
1709 | static const unsigned int drif2_data1_a_mux[] = { | |
1710 | RIF2_D1_A_MARK, | |
1711 | }; | |
1712 | ||
1713 | static const unsigned int drif2_ctrl_b_pins[] = { | |
1714 | /* CLK, SYNC */ | |
1715 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
1716 | }; | |
1717 | ||
1718 | static const unsigned int drif2_ctrl_b_mux[] = { | |
1719 | RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, | |
1720 | }; | |
1721 | ||
1722 | static const unsigned int drif2_data0_b_pins[] = { | |
1723 | /* D0 */ | |
1724 | RCAR_GP_PIN(1, 6), | |
1725 | }; | |
1726 | ||
1727 | static const unsigned int drif2_data0_b_mux[] = { | |
1728 | RIF2_D0_B_MARK, | |
1729 | }; | |
1730 | ||
1731 | static const unsigned int drif2_data1_b_pins[] = { | |
1732 | /* D1 */ | |
1733 | RCAR_GP_PIN(1, 7), | |
1734 | }; | |
1735 | ||
1736 | static const unsigned int drif2_data1_b_mux[] = { | |
1737 | RIF2_D1_B_MARK, | |
1738 | }; | |
1739 | ||
1740 | /* - DRIF3 --------------------------------------------------------------- */ | |
1741 | static const unsigned int drif3_ctrl_a_pins[] = { | |
1742 | /* CLK, SYNC */ | |
1743 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), | |
1744 | }; | |
1745 | ||
1746 | static const unsigned int drif3_ctrl_a_mux[] = { | |
1747 | RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, | |
1748 | }; | |
1749 | ||
1750 | static const unsigned int drif3_data0_a_pins[] = { | |
1751 | /* D0 */ | |
1752 | RCAR_GP_PIN(2, 12), | |
1753 | }; | |
1754 | ||
1755 | static const unsigned int drif3_data0_a_mux[] = { | |
1756 | RIF3_D0_A_MARK, | |
1757 | }; | |
1758 | ||
1759 | static const unsigned int drif3_data1_a_pins[] = { | |
1760 | /* D1 */ | |
1761 | RCAR_GP_PIN(2, 13), | |
1762 | }; | |
1763 | ||
1764 | static const unsigned int drif3_data1_a_mux[] = { | |
1765 | RIF3_D1_A_MARK, | |
1766 | }; | |
1767 | ||
1768 | static const unsigned int drif3_ctrl_b_pins[] = { | |
1769 | /* CLK, SYNC */ | |
1770 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | |
1771 | }; | |
1772 | ||
1773 | static const unsigned int drif3_ctrl_b_mux[] = { | |
1774 | RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, | |
1775 | }; | |
1776 | ||
1777 | static const unsigned int drif3_data0_b_pins[] = { | |
1778 | /* D0 */ | |
1779 | RCAR_GP_PIN(0, 10), | |
1780 | }; | |
1781 | ||
1782 | static const unsigned int drif3_data0_b_mux[] = { | |
1783 | RIF3_D0_B_MARK, | |
1784 | }; | |
1785 | ||
1786 | static const unsigned int drif3_data1_b_pins[] = { | |
1787 | /* D1 */ | |
1788 | RCAR_GP_PIN(0, 11), | |
1789 | }; | |
1790 | ||
1791 | static const unsigned int drif3_data1_b_mux[] = { | |
1792 | RIF3_D1_B_MARK, | |
1793 | }; | |
1794 | ||
1795 | /* - DU --------------------------------------------------------------------- */ | |
1796 | static const unsigned int du_rgb666_pins[] = { | |
1797 | /* R[7:2], G[7:2], B[7:2] */ | |
1798 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), | |
1799 | RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), | |
1800 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), | |
1801 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), | |
1802 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), | |
1803 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
1804 | }; | |
bf8d2dab MV |
1805 | static const unsigned int du_rgb666_mux[] = { |
1806 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
1807 | DU_DR3_MARK, DU_DR2_MARK, | |
1808 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
1809 | DU_DG3_MARK, DU_DG2_MARK, | |
1810 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
1811 | DU_DB3_MARK, DU_DB2_MARK, | |
1812 | }; | |
bf8d2dab MV |
1813 | static const unsigned int du_rgb888_pins[] = { |
1814 | /* R[7:0], G[7:0], B[7:0] */ | |
1815 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5), | |
1816 | RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0), | |
1817 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), | |
1818 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10), | |
1819 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), | |
1820 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), | |
1821 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), | |
1822 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
8719ca81 | 1823 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
bf8d2dab | 1824 | }; |
bf8d2dab MV |
1825 | static const unsigned int du_rgb888_mux[] = { |
1826 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
1827 | DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, | |
1828 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
1829 | DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, | |
1830 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
1831 | DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, | |
1832 | }; | |
8719ca81 MV |
1833 | static const unsigned int du_clk_in_0_pins[] = { |
1834 | /* CLKIN0 */ | |
1835 | RCAR_GP_PIN(0, 16), | |
1836 | }; | |
1837 | static const unsigned int du_clk_in_0_mux[] = { | |
1838 | DU_DOTCLKIN0_MARK | |
1839 | }; | |
1840 | static const unsigned int du_clk_in_1_pins[] = { | |
1841 | /* CLKIN1 */ | |
1842 | RCAR_GP_PIN(1, 1), | |
1843 | }; | |
1844 | static const unsigned int du_clk_in_1_mux[] = { | |
1845 | DU_DOTCLKIN1_MARK | |
1846 | }; | |
bf8d2dab MV |
1847 | static const unsigned int du_clk_out_0_pins[] = { |
1848 | /* CLKOUT */ | |
1849 | RCAR_GP_PIN(1, 3), | |
1850 | }; | |
bf8d2dab MV |
1851 | static const unsigned int du_clk_out_0_mux[] = { |
1852 | DU_DOTCLKOUT0_MARK | |
1853 | }; | |
bf8d2dab MV |
1854 | static const unsigned int du_sync_pins[] = { |
1855 | /* VSYNC, HSYNC */ | |
1856 | RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), | |
1857 | }; | |
bf8d2dab MV |
1858 | static const unsigned int du_sync_mux[] = { |
1859 | DU_VSYNC_MARK, DU_HSYNC_MARK | |
1860 | }; | |
8719ca81 MV |
1861 | static const unsigned int du_disp_cde_pins[] = { |
1862 | /* DISP_CDE */ | |
1863 | RCAR_GP_PIN(1, 1), | |
1864 | }; | |
1865 | static const unsigned int du_disp_cde_mux[] = { | |
1866 | DU_DISP_CDE_MARK, | |
1867 | }; | |
bf8d2dab MV |
1868 | static const unsigned int du_cde_pins[] = { |
1869 | /* CDE */ | |
1870 | RCAR_GP_PIN(1, 0), | |
1871 | }; | |
bf8d2dab MV |
1872 | static const unsigned int du_cde_mux[] = { |
1873 | DU_CDE_MARK, | |
1874 | }; | |
bf8d2dab MV |
1875 | static const unsigned int du_disp_pins[] = { |
1876 | /* DISP */ | |
1877 | RCAR_GP_PIN(1, 2), | |
1878 | }; | |
bf8d2dab MV |
1879 | static const unsigned int du_disp_mux[] = { |
1880 | DU_DISP_MARK, | |
1881 | }; | |
1882 | ||
bf8d2dab MV |
1883 | /* - HSCIF0 --------------------------------------------------*/ |
1884 | static const unsigned int hscif0_data_a_pins[] = { | |
1885 | /* RX, TX */ | |
1886 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), | |
1887 | }; | |
1888 | ||
1889 | static const unsigned int hscif0_data_a_mux[] = { | |
1890 | HRX0_A_MARK, HTX0_A_MARK, | |
1891 | }; | |
1892 | ||
1893 | static const unsigned int hscif0_clk_a_pins[] = { | |
1894 | /* SCK */ | |
1895 | RCAR_GP_PIN(5, 7), | |
1896 | }; | |
1897 | ||
1898 | static const unsigned int hscif0_clk_a_mux[] = { | |
1899 | HSCK0_A_MARK, | |
1900 | }; | |
1901 | ||
1902 | static const unsigned int hscif0_ctrl_a_pins[] = { | |
1903 | /* RTS, CTS */ | |
1904 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), | |
1905 | }; | |
1906 | ||
1907 | static const unsigned int hscif0_ctrl_a_mux[] = { | |
1908 | HRTS0_N_A_MARK, HCTS0_N_A_MARK, | |
1909 | }; | |
1910 | ||
1911 | static const unsigned int hscif0_data_b_pins[] = { | |
1912 | /* RX, TX */ | |
1913 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
1914 | }; | |
1915 | ||
1916 | static const unsigned int hscif0_data_b_mux[] = { | |
1917 | HRX0_B_MARK, HTX0_B_MARK, | |
1918 | }; | |
1919 | ||
1920 | static const unsigned int hscif0_clk_b_pins[] = { | |
1921 | /* SCK */ | |
1922 | RCAR_GP_PIN(6, 13), | |
1923 | }; | |
1924 | ||
1925 | static const unsigned int hscif0_clk_b_mux[] = { | |
1926 | HSCK0_B_MARK, | |
1927 | }; | |
1928 | ||
1929 | /* - HSCIF1 ------------------------------------------------- */ | |
1930 | static const unsigned int hscif1_data_a_pins[] = { | |
1931 | /* RX, TX */ | |
1932 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
1933 | }; | |
1934 | ||
1935 | static const unsigned int hscif1_data_a_mux[] = { | |
1936 | HRX1_A_MARK, HTX1_A_MARK, | |
1937 | }; | |
1938 | ||
1939 | static const unsigned int hscif1_clk_a_pins[] = { | |
1940 | /* SCK */ | |
1941 | RCAR_GP_PIN(5, 0), | |
1942 | }; | |
1943 | ||
1944 | static const unsigned int hscif1_clk_a_mux[] = { | |
1945 | HSCK1_A_MARK, | |
1946 | }; | |
1947 | ||
1948 | static const unsigned int hscif1_data_b_pins[] = { | |
1949 | /* RX, TX */ | |
1950 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), | |
1951 | }; | |
1952 | ||
1953 | static const unsigned int hscif1_data_b_mux[] = { | |
1954 | HRX1_B_MARK, HTX1_B_MARK, | |
1955 | }; | |
1956 | ||
1957 | static const unsigned int hscif1_clk_b_pins[] = { | |
1958 | /* SCK */ | |
1959 | RCAR_GP_PIN(3, 0), | |
1960 | }; | |
1961 | ||
1962 | static const unsigned int hscif1_clk_b_mux[] = { | |
1963 | HSCK1_B_MARK, | |
1964 | }; | |
1965 | ||
1966 | static const unsigned int hscif1_ctrl_b_pins[] = { | |
1967 | /* RTS, CTS */ | |
1968 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), | |
1969 | }; | |
1970 | ||
1971 | static const unsigned int hscif1_ctrl_b_mux[] = { | |
1972 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, | |
1973 | }; | |
1974 | ||
1975 | /* - HSCIF2 ------------------------------------------------- */ | |
1976 | static const unsigned int hscif2_data_a_pins[] = { | |
1977 | /* RX, TX */ | |
1978 | RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), | |
1979 | }; | |
1980 | ||
1981 | static const unsigned int hscif2_data_a_mux[] = { | |
1982 | HRX2_A_MARK, HTX2_A_MARK, | |
1983 | }; | |
1984 | ||
1985 | static const unsigned int hscif2_clk_a_pins[] = { | |
1986 | /* SCK */ | |
1987 | RCAR_GP_PIN(6, 14), | |
1988 | }; | |
1989 | ||
1990 | static const unsigned int hscif2_clk_a_mux[] = { | |
1991 | HSCK2_A_MARK, | |
1992 | }; | |
1993 | ||
1994 | static const unsigned int hscif2_ctrl_a_pins[] = { | |
1995 | /* RTS, CTS */ | |
1996 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), | |
1997 | }; | |
1998 | ||
1999 | static const unsigned int hscif2_ctrl_a_mux[] = { | |
2000 | HRTS2_N_A_MARK, HCTS2_N_A_MARK, | |
2001 | }; | |
2002 | ||
2003 | static const unsigned int hscif2_data_b_pins[] = { | |
2004 | /* RX, TX */ | |
2005 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2006 | }; | |
2007 | ||
2008 | static const unsigned int hscif2_data_b_mux[] = { | |
2009 | HRX2_B_MARK, HTX2_B_MARK, | |
2010 | }; | |
2011 | ||
2012 | /* - HSCIF3 ------------------------------------------------*/ | |
2013 | static const unsigned int hscif3_data_a_pins[] = { | |
2014 | /* RX, TX */ | |
2015 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
2016 | }; | |
2017 | ||
2018 | static const unsigned int hscif3_data_a_mux[] = { | |
2019 | HRX3_A_MARK, HTX3_A_MARK, | |
2020 | }; | |
2021 | ||
2022 | static const unsigned int hscif3_data_b_pins[] = { | |
2023 | /* RX, TX */ | |
2024 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
2025 | }; | |
2026 | ||
2027 | static const unsigned int hscif3_data_b_mux[] = { | |
2028 | HRX3_B_MARK, HTX3_B_MARK, | |
2029 | }; | |
2030 | ||
2031 | static const unsigned int hscif3_clk_b_pins[] = { | |
2032 | /* SCK */ | |
2033 | RCAR_GP_PIN(0, 4), | |
2034 | }; | |
2035 | ||
2036 | static const unsigned int hscif3_clk_b_mux[] = { | |
2037 | HSCK3_B_MARK, | |
2038 | }; | |
2039 | ||
2040 | static const unsigned int hscif3_data_c_pins[] = { | |
2041 | /* RX, TX */ | |
2042 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), | |
2043 | }; | |
2044 | ||
2045 | static const unsigned int hscif3_data_c_mux[] = { | |
2046 | HRX3_C_MARK, HTX3_C_MARK, | |
2047 | }; | |
2048 | ||
2049 | static const unsigned int hscif3_clk_c_pins[] = { | |
2050 | /* SCK */ | |
2051 | RCAR_GP_PIN(2, 11), | |
2052 | }; | |
2053 | ||
2054 | static const unsigned int hscif3_clk_c_mux[] = { | |
2055 | HSCK3_C_MARK, | |
2056 | }; | |
2057 | ||
2058 | static const unsigned int hscif3_ctrl_c_pins[] = { | |
2059 | /* RTS, CTS */ | |
2060 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), | |
2061 | }; | |
2062 | ||
2063 | static const unsigned int hscif3_ctrl_c_mux[] = { | |
2064 | HRTS3_N_C_MARK, HCTS3_N_C_MARK, | |
2065 | }; | |
2066 | ||
2067 | static const unsigned int hscif3_data_d_pins[] = { | |
2068 | /* RX, TX */ | |
8719ca81 | 2069 | RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), |
bf8d2dab MV |
2070 | }; |
2071 | ||
2072 | static const unsigned int hscif3_data_d_mux[] = { | |
2073 | HRX3_D_MARK, HTX3_D_MARK, | |
2074 | }; | |
2075 | ||
2076 | static const unsigned int hscif3_data_e_pins[] = { | |
2077 | /* RX, TX */ | |
2078 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
2079 | }; | |
2080 | ||
2081 | static const unsigned int hscif3_data_e_mux[] = { | |
2082 | HRX3_E_MARK, HTX3_E_MARK, | |
2083 | }; | |
2084 | ||
2085 | static const unsigned int hscif3_ctrl_e_pins[] = { | |
2086 | /* RTS, CTS */ | |
2087 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), | |
2088 | }; | |
2089 | ||
2090 | static const unsigned int hscif3_ctrl_e_mux[] = { | |
2091 | HRTS3_N_E_MARK, HCTS3_N_E_MARK, | |
2092 | }; | |
2093 | ||
2094 | /* - HSCIF4 -------------------------------------------------- */ | |
2095 | static const unsigned int hscif4_data_a_pins[] = { | |
2096 | /* RX, TX */ | |
2097 | RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), | |
2098 | }; | |
2099 | ||
2100 | static const unsigned int hscif4_data_a_mux[] = { | |
2101 | HRX4_A_MARK, HTX4_A_MARK, | |
2102 | }; | |
2103 | ||
2104 | static const unsigned int hscif4_clk_a_pins[] = { | |
2105 | /* SCK */ | |
2106 | RCAR_GP_PIN(2, 0), | |
2107 | }; | |
2108 | ||
2109 | static const unsigned int hscif4_clk_a_mux[] = { | |
2110 | HSCK4_A_MARK, | |
2111 | }; | |
2112 | ||
2113 | static const unsigned int hscif4_ctrl_a_pins[] = { | |
2114 | /* RTS, CTS */ | |
2115 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), | |
2116 | }; | |
2117 | ||
2118 | static const unsigned int hscif4_ctrl_a_mux[] = { | |
2119 | HRTS4_N_A_MARK, HCTS4_N_A_MARK, | |
2120 | }; | |
2121 | ||
2122 | static const unsigned int hscif4_data_b_pins[] = { | |
2123 | /* RX, TX */ | |
2124 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), | |
2125 | }; | |
2126 | ||
2127 | static const unsigned int hscif4_data_b_mux[] = { | |
2128 | HRX4_B_MARK, HTX4_B_MARK, | |
2129 | }; | |
2130 | ||
2131 | static const unsigned int hscif4_clk_b_pins[] = { | |
8719ca81 | 2132 | /* SCK */ |
bf8d2dab MV |
2133 | RCAR_GP_PIN(2, 6), |
2134 | }; | |
2135 | ||
2136 | static const unsigned int hscif4_clk_b_mux[] = { | |
2137 | HSCK4_B_MARK, | |
2138 | }; | |
2139 | ||
2140 | static const unsigned int hscif4_data_c_pins[] = { | |
2141 | /* RX, TX */ | |
2142 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
2143 | }; | |
2144 | ||
2145 | static const unsigned int hscif4_data_c_mux[] = { | |
2146 | HRX4_C_MARK, HTX4_C_MARK, | |
2147 | }; | |
2148 | ||
2149 | static const unsigned int hscif4_data_d_pins[] = { | |
2150 | /* RX, TX */ | |
2151 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
2152 | }; | |
2153 | ||
2154 | static const unsigned int hscif4_data_d_mux[] = { | |
2155 | HRX4_D_MARK, HTX4_D_MARK, | |
2156 | }; | |
2157 | ||
2158 | static const unsigned int hscif4_data_e_pins[] = { | |
2159 | /* RX, TX */ | |
2160 | RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), | |
2161 | }; | |
2162 | ||
2163 | static const unsigned int hscif4_data_e_mux[] = { | |
2164 | HRX4_E_MARK, HTX4_E_MARK, | |
2165 | }; | |
2166 | ||
2167 | /* - I2C -------------------------------------------------------------------- */ | |
2168 | static const unsigned int i2c1_a_pins[] = { | |
2169 | /* SCL, SDA */ | |
2170 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), | |
2171 | }; | |
2172 | ||
2173 | static const unsigned int i2c1_a_mux[] = { | |
2174 | SCL1_A_MARK, SDA1_A_MARK, | |
2175 | }; | |
2176 | ||
2177 | static const unsigned int i2c1_b_pins[] = { | |
2178 | /* SCL, SDA */ | |
2179 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), | |
2180 | }; | |
2181 | ||
2182 | static const unsigned int i2c1_b_mux[] = { | |
2183 | SCL1_B_MARK, SDA1_B_MARK, | |
2184 | }; | |
2185 | ||
2186 | static const unsigned int i2c1_c_pins[] = { | |
2187 | /* SCL, SDA */ | |
2188 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5), | |
2189 | }; | |
2190 | ||
2191 | static const unsigned int i2c1_c_mux[] = { | |
2192 | SCL1_C_MARK, SDA1_C_MARK, | |
2193 | }; | |
2194 | ||
2195 | static const unsigned int i2c1_d_pins[] = { | |
2196 | /* SCL, SDA */ | |
2197 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), | |
2198 | }; | |
2199 | ||
2200 | static const unsigned int i2c1_d_mux[] = { | |
2201 | SCL1_D_MARK, SDA1_D_MARK, | |
2202 | }; | |
2203 | ||
2204 | static const unsigned int i2c2_a_pins[] = { | |
2205 | /* SCL, SDA */ | |
2206 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0), | |
2207 | }; | |
2208 | ||
2209 | static const unsigned int i2c2_a_mux[] = { | |
2210 | SCL2_A_MARK, SDA2_A_MARK, | |
2211 | }; | |
2212 | ||
2213 | static const unsigned int i2c2_b_pins[] = { | |
2214 | /* SCL, SDA */ | |
2215 | RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), | |
2216 | }; | |
2217 | ||
2218 | static const unsigned int i2c2_b_mux[] = { | |
2219 | SCL2_B_MARK, SDA2_B_MARK, | |
2220 | }; | |
2221 | ||
2222 | static const unsigned int i2c2_c_pins[] = { | |
2223 | /* SCL, SDA */ | |
2224 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), | |
2225 | }; | |
2226 | ||
2227 | static const unsigned int i2c2_c_mux[] = { | |
2228 | SCL2_C_MARK, SDA2_C_MARK, | |
2229 | }; | |
2230 | ||
2231 | static const unsigned int i2c2_d_pins[] = { | |
2232 | /* SCL, SDA */ | |
2233 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
2234 | }; | |
2235 | ||
2236 | static const unsigned int i2c2_d_mux[] = { | |
2237 | SCL2_D_MARK, SDA2_D_MARK, | |
2238 | }; | |
2239 | ||
2240 | static const unsigned int i2c2_e_pins[] = { | |
2241 | /* SCL, SDA */ | |
2242 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), | |
2243 | }; | |
2244 | ||
2245 | static const unsigned int i2c2_e_mux[] = { | |
2246 | SCL2_E_MARK, SDA2_E_MARK, | |
2247 | }; | |
2248 | ||
2249 | static const unsigned int i2c4_pins[] = { | |
2250 | /* SCL, SDA */ | |
2251 | RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), | |
2252 | }; | |
2253 | ||
2254 | static const unsigned int i2c4_mux[] = { | |
2255 | SCL4_MARK, SDA4_MARK, | |
2256 | }; | |
2257 | ||
2258 | static const unsigned int i2c5_pins[] = { | |
2259 | /* SCL, SDA */ | |
2260 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), | |
2261 | }; | |
2262 | ||
2263 | static const unsigned int i2c5_mux[] = { | |
2264 | SCL5_MARK, SDA5_MARK, | |
2265 | }; | |
2266 | ||
2267 | static const unsigned int i2c6_a_pins[] = { | |
2268 | /* SCL, SDA */ | |
2269 | RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8), | |
2270 | }; | |
2271 | ||
2272 | static const unsigned int i2c6_a_mux[] = { | |
2273 | SCL6_A_MARK, SDA6_A_MARK, | |
2274 | }; | |
2275 | ||
2276 | static const unsigned int i2c6_b_pins[] = { | |
2277 | /* SCL, SDA */ | |
2278 | RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), | |
2279 | }; | |
2280 | ||
2281 | static const unsigned int i2c6_b_mux[] = { | |
2282 | SCL6_B_MARK, SDA6_B_MARK, | |
2283 | }; | |
2284 | ||
2285 | static const unsigned int i2c7_a_pins[] = { | |
2286 | /* SCL, SDA */ | |
2287 | RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25), | |
2288 | }; | |
2289 | ||
2290 | static const unsigned int i2c7_a_mux[] = { | |
2291 | SCL7_A_MARK, SDA7_A_MARK, | |
2292 | }; | |
2293 | ||
2294 | static const unsigned int i2c7_b_pins[] = { | |
2295 | /* SCL, SDA */ | |
2296 | RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), | |
2297 | }; | |
2298 | ||
2299 | static const unsigned int i2c7_b_mux[] = { | |
2300 | SCL7_B_MARK, SDA7_B_MARK, | |
2301 | }; | |
2302 | ||
2303 | /* - INTC-EX ---------------------------------------------------------------- */ | |
2304 | static const unsigned int intc_ex_irq0_pins[] = { | |
2305 | /* IRQ0 */ | |
2306 | RCAR_GP_PIN(1, 0), | |
2307 | }; | |
bf8d2dab MV |
2308 | static const unsigned int intc_ex_irq0_mux[] = { |
2309 | IRQ0_MARK, | |
2310 | }; | |
8719ca81 MV |
2311 | static const unsigned int intc_ex_irq1_pins[] = { |
2312 | /* IRQ1 */ | |
2313 | RCAR_GP_PIN(1, 1), | |
2314 | }; | |
2315 | static const unsigned int intc_ex_irq1_mux[] = { | |
2316 | IRQ1_MARK, | |
2317 | }; | |
2318 | static const unsigned int intc_ex_irq2_pins[] = { | |
2319 | /* IRQ2 */ | |
2320 | RCAR_GP_PIN(1, 2), | |
2321 | }; | |
2322 | static const unsigned int intc_ex_irq2_mux[] = { | |
2323 | IRQ2_MARK, | |
2324 | }; | |
2325 | static const unsigned int intc_ex_irq3_pins[] = { | |
2326 | /* IRQ3 */ | |
2327 | RCAR_GP_PIN(1, 9), | |
2328 | }; | |
2329 | static const unsigned int intc_ex_irq3_mux[] = { | |
2330 | IRQ3_MARK, | |
2331 | }; | |
2332 | static const unsigned int intc_ex_irq4_pins[] = { | |
2333 | /* IRQ4 */ | |
2334 | RCAR_GP_PIN(1, 10), | |
2335 | }; | |
2336 | static const unsigned int intc_ex_irq4_mux[] = { | |
2337 | IRQ4_MARK, | |
2338 | }; | |
2339 | static const unsigned int intc_ex_irq5_pins[] = { | |
2340 | /* IRQ5 */ | |
2341 | RCAR_GP_PIN(0, 7), | |
2342 | }; | |
2343 | static const unsigned int intc_ex_irq5_mux[] = { | |
2344 | IRQ5_MARK, | |
2345 | }; | |
bf8d2dab MV |
2346 | |
2347 | /* - MSIOF0 ----------------------------------------------------------------- */ | |
2348 | static const unsigned int msiof0_clk_pins[] = { | |
2349 | /* SCK */ | |
2350 | RCAR_GP_PIN(5, 10), | |
2351 | }; | |
2352 | ||
2353 | static const unsigned int msiof0_clk_mux[] = { | |
2354 | MSIOF0_SCK_MARK, | |
2355 | }; | |
2356 | ||
2357 | static const unsigned int msiof0_sync_pins[] = { | |
2358 | /* SYNC */ | |
2359 | RCAR_GP_PIN(5, 13), | |
2360 | }; | |
2361 | ||
2362 | static const unsigned int msiof0_sync_mux[] = { | |
2363 | MSIOF0_SYNC_MARK, | |
2364 | }; | |
2365 | ||
2366 | static const unsigned int msiof0_ss1_pins[] = { | |
2367 | /* SS1 */ | |
2368 | RCAR_GP_PIN(5, 14), | |
2369 | }; | |
2370 | ||
2371 | static const unsigned int msiof0_ss1_mux[] = { | |
2372 | MSIOF0_SS1_MARK, | |
2373 | }; | |
2374 | ||
2375 | static const unsigned int msiof0_ss2_pins[] = { | |
2376 | /* SS2 */ | |
2377 | RCAR_GP_PIN(5, 15), | |
2378 | }; | |
2379 | ||
2380 | static const unsigned int msiof0_ss2_mux[] = { | |
2381 | MSIOF0_SS2_MARK, | |
2382 | }; | |
2383 | ||
2384 | static const unsigned int msiof0_txd_pins[] = { | |
2385 | /* TXD */ | |
2386 | RCAR_GP_PIN(5, 12), | |
2387 | }; | |
2388 | ||
2389 | static const unsigned int msiof0_txd_mux[] = { | |
2390 | MSIOF0_TXD_MARK, | |
2391 | }; | |
2392 | ||
2393 | static const unsigned int msiof0_rxd_pins[] = { | |
2394 | /* RXD */ | |
2395 | RCAR_GP_PIN(5, 11), | |
2396 | }; | |
2397 | ||
2398 | static const unsigned int msiof0_rxd_mux[] = { | |
2399 | MSIOF0_RXD_MARK, | |
2400 | }; | |
2401 | ||
2402 | /* - MSIOF1 ----------------------------------------------------------------- */ | |
2403 | static const unsigned int msiof1_clk_pins[] = { | |
2404 | /* SCK */ | |
2405 | RCAR_GP_PIN(1, 19), | |
2406 | }; | |
2407 | ||
2408 | static const unsigned int msiof1_clk_mux[] = { | |
2409 | MSIOF1_SCK_MARK, | |
2410 | }; | |
2411 | ||
2412 | static const unsigned int msiof1_sync_pins[] = { | |
2413 | /* SYNC */ | |
2414 | RCAR_GP_PIN(1, 16), | |
2415 | }; | |
2416 | ||
2417 | static const unsigned int msiof1_sync_mux[] = { | |
2418 | MSIOF1_SYNC_MARK, | |
2419 | }; | |
2420 | ||
2421 | static const unsigned int msiof1_ss1_pins[] = { | |
2422 | /* SS1 */ | |
2423 | RCAR_GP_PIN(1, 14), | |
2424 | }; | |
2425 | ||
2426 | static const unsigned int msiof1_ss1_mux[] = { | |
2427 | MSIOF1_SS1_MARK, | |
2428 | }; | |
2429 | ||
2430 | static const unsigned int msiof1_ss2_pins[] = { | |
2431 | /* SS2 */ | |
2432 | RCAR_GP_PIN(1, 15), | |
2433 | }; | |
2434 | ||
2435 | static const unsigned int msiof1_ss2_mux[] = { | |
2436 | MSIOF1_SS2_MARK, | |
2437 | }; | |
2438 | ||
2439 | static const unsigned int msiof1_txd_pins[] = { | |
2440 | /* TXD */ | |
2441 | RCAR_GP_PIN(1, 18), | |
2442 | }; | |
2443 | ||
2444 | static const unsigned int msiof1_txd_mux[] = { | |
2445 | MSIOF1_TXD_MARK, | |
2446 | }; | |
2447 | ||
2448 | static const unsigned int msiof1_rxd_pins[] = { | |
2449 | /* RXD */ | |
2450 | RCAR_GP_PIN(1, 17), | |
2451 | }; | |
2452 | ||
2453 | static const unsigned int msiof1_rxd_mux[] = { | |
2454 | MSIOF1_RXD_MARK, | |
2455 | }; | |
2456 | ||
2457 | /* - MSIOF2 ----------------------------------------------------------------- */ | |
2458 | static const unsigned int msiof2_clk_a_pins[] = { | |
2459 | /* SCK */ | |
2460 | RCAR_GP_PIN(0, 8), | |
2461 | }; | |
2462 | ||
2463 | static const unsigned int msiof2_clk_a_mux[] = { | |
2464 | MSIOF2_SCK_A_MARK, | |
2465 | }; | |
2466 | ||
2467 | static const unsigned int msiof2_sync_a_pins[] = { | |
2468 | /* SYNC */ | |
2469 | RCAR_GP_PIN(0, 9), | |
2470 | }; | |
2471 | ||
2472 | static const unsigned int msiof2_sync_a_mux[] = { | |
2473 | MSIOF2_SYNC_A_MARK, | |
2474 | }; | |
2475 | ||
2476 | static const unsigned int msiof2_ss1_a_pins[] = { | |
2477 | /* SS1 */ | |
2478 | RCAR_GP_PIN(0, 15), | |
2479 | }; | |
2480 | ||
2481 | static const unsigned int msiof2_ss1_a_mux[] = { | |
2482 | MSIOF2_SS1_A_MARK, | |
2483 | }; | |
2484 | ||
2485 | static const unsigned int msiof2_ss2_a_pins[] = { | |
2486 | /* SS2 */ | |
2487 | RCAR_GP_PIN(0, 14), | |
2488 | }; | |
2489 | ||
2490 | static const unsigned int msiof2_ss2_a_mux[] = { | |
2491 | MSIOF2_SS2_A_MARK, | |
2492 | }; | |
2493 | ||
2494 | static const unsigned int msiof2_txd_a_pins[] = { | |
2495 | /* TXD */ | |
2496 | RCAR_GP_PIN(0, 11), | |
2497 | }; | |
2498 | ||
2499 | static const unsigned int msiof2_txd_a_mux[] = { | |
2500 | MSIOF2_TXD_A_MARK, | |
2501 | }; | |
2502 | ||
2503 | static const unsigned int msiof2_rxd_a_pins[] = { | |
2504 | /* RXD */ | |
2505 | RCAR_GP_PIN(0, 10), | |
2506 | }; | |
2507 | ||
2508 | static const unsigned int msiof2_rxd_a_mux[] = { | |
2509 | MSIOF2_RXD_A_MARK, | |
2510 | }; | |
2511 | ||
2512 | static const unsigned int msiof2_clk_b_pins[] = { | |
2513 | /* SCK */ | |
2514 | RCAR_GP_PIN(1, 13), | |
2515 | }; | |
2516 | ||
2517 | static const unsigned int msiof2_clk_b_mux[] = { | |
2518 | MSIOF2_SCK_B_MARK, | |
2519 | }; | |
2520 | ||
2521 | static const unsigned int msiof2_sync_b_pins[] = { | |
2522 | /* SYNC */ | |
2523 | RCAR_GP_PIN(1, 10), | |
2524 | }; | |
2525 | ||
2526 | static const unsigned int msiof2_sync_b_mux[] = { | |
2527 | MSIOF2_SYNC_B_MARK, | |
2528 | }; | |
2529 | ||
2530 | static const unsigned int msiof2_ss1_b_pins[] = { | |
2531 | /* SS1 */ | |
2532 | RCAR_GP_PIN(1, 16), | |
2533 | }; | |
2534 | ||
2535 | static const unsigned int msiof2_ss1_b_mux[] = { | |
2536 | MSIOF2_SS1_B_MARK, | |
2537 | }; | |
2538 | ||
2539 | static const unsigned int msiof2_ss2_b_pins[] = { | |
2540 | /* SS2 */ | |
2541 | RCAR_GP_PIN(1, 12), | |
2542 | }; | |
2543 | ||
2544 | static const unsigned int msiof2_ss2_b_mux[] = { | |
2545 | MSIOF2_SS2_B_MARK, | |
2546 | }; | |
2547 | ||
2548 | static const unsigned int msiof2_txd_b_pins[] = { | |
2549 | /* TXD */ | |
2550 | RCAR_GP_PIN(1, 15), | |
2551 | }; | |
2552 | ||
2553 | static const unsigned int msiof2_txd_b_mux[] = { | |
2554 | MSIOF2_TXD_B_MARK, | |
2555 | }; | |
2556 | ||
2557 | static const unsigned int msiof2_rxd_b_pins[] = { | |
2558 | /* RXD */ | |
2559 | RCAR_GP_PIN(1, 14), | |
2560 | }; | |
2561 | ||
2562 | static const unsigned int msiof2_rxd_b_mux[] = { | |
2563 | MSIOF2_RXD_B_MARK, | |
2564 | }; | |
2565 | ||
2566 | /* - MSIOF3 ----------------------------------------------------------------- */ | |
2567 | static const unsigned int msiof3_clk_a_pins[] = { | |
2568 | /* SCK */ | |
2569 | RCAR_GP_PIN(0, 0), | |
2570 | }; | |
2571 | ||
2572 | static const unsigned int msiof3_clk_a_mux[] = { | |
2573 | MSIOF3_SCK_A_MARK, | |
2574 | }; | |
2575 | ||
2576 | static const unsigned int msiof3_sync_a_pins[] = { | |
2577 | /* SYNC */ | |
2578 | RCAR_GP_PIN(0, 1), | |
2579 | }; | |
2580 | ||
2581 | static const unsigned int msiof3_sync_a_mux[] = { | |
2582 | MSIOF3_SYNC_A_MARK, | |
2583 | }; | |
2584 | ||
2585 | static const unsigned int msiof3_ss1_a_pins[] = { | |
2586 | /* SS1 */ | |
2587 | RCAR_GP_PIN(0, 15), | |
2588 | }; | |
2589 | ||
2590 | static const unsigned int msiof3_ss1_a_mux[] = { | |
2591 | MSIOF3_SS1_A_MARK, | |
2592 | }; | |
2593 | ||
2594 | static const unsigned int msiof3_ss2_a_pins[] = { | |
2595 | /* SS2 */ | |
2596 | RCAR_GP_PIN(0, 4), | |
2597 | }; | |
2598 | ||
2599 | static const unsigned int msiof3_ss2_a_mux[] = { | |
2600 | MSIOF3_SS2_A_MARK, | |
2601 | }; | |
2602 | ||
2603 | static const unsigned int msiof3_txd_a_pins[] = { | |
2604 | /* TXD */ | |
2605 | RCAR_GP_PIN(0, 3), | |
2606 | }; | |
2607 | ||
2608 | static const unsigned int msiof3_txd_a_mux[] = { | |
2609 | MSIOF3_TXD_A_MARK, | |
2610 | }; | |
2611 | ||
2612 | static const unsigned int msiof3_rxd_a_pins[] = { | |
2613 | /* RXD */ | |
2614 | RCAR_GP_PIN(0, 2), | |
2615 | }; | |
2616 | ||
2617 | static const unsigned int msiof3_rxd_a_mux[] = { | |
2618 | MSIOF3_RXD_A_MARK, | |
2619 | }; | |
2620 | ||
2621 | static const unsigned int msiof3_clk_b_pins[] = { | |
2622 | /* SCK */ | |
2623 | RCAR_GP_PIN(1, 5), | |
2624 | }; | |
2625 | ||
2626 | static const unsigned int msiof3_clk_b_mux[] = { | |
2627 | MSIOF3_SCK_B_MARK, | |
2628 | }; | |
2629 | ||
2630 | static const unsigned int msiof3_sync_b_pins[] = { | |
2631 | /* SYNC */ | |
2632 | RCAR_GP_PIN(1, 4), | |
2633 | }; | |
2634 | ||
2635 | static const unsigned int msiof3_sync_b_mux[] = { | |
2636 | MSIOF3_SYNC_B_MARK, | |
2637 | }; | |
2638 | ||
2639 | static const unsigned int msiof3_ss1_b_pins[] = { | |
2640 | /* SS1 */ | |
2641 | RCAR_GP_PIN(1, 0), | |
2642 | }; | |
2643 | ||
2644 | static const unsigned int msiof3_ss1_b_mux[] = { | |
2645 | MSIOF3_SS1_B_MARK, | |
2646 | }; | |
2647 | ||
2648 | static const unsigned int msiof3_txd_b_pins[] = { | |
2649 | /* TXD */ | |
2650 | RCAR_GP_PIN(1, 7), | |
2651 | }; | |
2652 | ||
2653 | static const unsigned int msiof3_txd_b_mux[] = { | |
2654 | MSIOF3_TXD_B_MARK, | |
2655 | }; | |
2656 | ||
2657 | static const unsigned int msiof3_rxd_b_pins[] = { | |
2658 | /* RXD */ | |
2659 | RCAR_GP_PIN(1, 6), | |
2660 | }; | |
2661 | ||
2662 | static const unsigned int msiof3_rxd_b_mux[] = { | |
2663 | MSIOF3_RXD_B_MARK, | |
2664 | }; | |
2665 | ||
2666 | /* - PWM0 --------------------------------------------------------------------*/ | |
2667 | static const unsigned int pwm0_a_pins[] = { | |
2668 | /* PWM */ | |
2669 | RCAR_GP_PIN(2, 22), | |
2670 | }; | |
2671 | ||
2672 | static const unsigned int pwm0_a_mux[] = { | |
2673 | PWM0_A_MARK, | |
2674 | }; | |
2675 | ||
2676 | static const unsigned int pwm0_b_pins[] = { | |
2677 | /* PWM */ | |
2678 | RCAR_GP_PIN(6, 3), | |
2679 | }; | |
2680 | ||
2681 | static const unsigned int pwm0_b_mux[] = { | |
2682 | PWM0_B_MARK, | |
2683 | }; | |
2684 | ||
2685 | /* - PWM1 --------------------------------------------------------------------*/ | |
2686 | static const unsigned int pwm1_a_pins[] = { | |
2687 | /* PWM */ | |
2688 | RCAR_GP_PIN(2, 23), | |
2689 | }; | |
2690 | ||
2691 | static const unsigned int pwm1_a_mux[] = { | |
2692 | PWM1_A_MARK, | |
2693 | }; | |
2694 | ||
2695 | static const unsigned int pwm1_b_pins[] = { | |
2696 | /* PWM */ | |
2697 | RCAR_GP_PIN(6, 4), | |
2698 | }; | |
2699 | ||
2700 | static const unsigned int pwm1_b_mux[] = { | |
2701 | PWM1_B_MARK, | |
2702 | }; | |
2703 | ||
2704 | /* - PWM2 --------------------------------------------------------------------*/ | |
2705 | static const unsigned int pwm2_a_pins[] = { | |
2706 | /* PWM */ | |
2707 | RCAR_GP_PIN(1, 0), | |
2708 | }; | |
2709 | ||
2710 | static const unsigned int pwm2_a_mux[] = { | |
2711 | PWM2_A_MARK, | |
2712 | }; | |
2713 | ||
2714 | static const unsigned int pwm2_b_pins[] = { | |
2715 | /* PWM */ | |
2716 | RCAR_GP_PIN(1, 4), | |
2717 | }; | |
2718 | ||
2719 | static const unsigned int pwm2_b_mux[] = { | |
2720 | PWM2_B_MARK, | |
2721 | }; | |
2722 | ||
2723 | static const unsigned int pwm2_c_pins[] = { | |
2724 | /* PWM */ | |
2725 | RCAR_GP_PIN(6, 5), | |
2726 | }; | |
2727 | ||
2728 | static const unsigned int pwm2_c_mux[] = { | |
2729 | PWM2_C_MARK, | |
2730 | }; | |
2731 | ||
2732 | /* - PWM3 --------------------------------------------------------------------*/ | |
2733 | static const unsigned int pwm3_a_pins[] = { | |
2734 | /* PWM */ | |
2735 | RCAR_GP_PIN(1, 1), | |
2736 | }; | |
2737 | ||
2738 | static const unsigned int pwm3_a_mux[] = { | |
2739 | PWM3_A_MARK, | |
2740 | }; | |
2741 | ||
2742 | static const unsigned int pwm3_b_pins[] = { | |
2743 | /* PWM */ | |
2744 | RCAR_GP_PIN(1, 5), | |
2745 | }; | |
2746 | ||
2747 | static const unsigned int pwm3_b_mux[] = { | |
2748 | PWM3_B_MARK, | |
2749 | }; | |
2750 | ||
2751 | static const unsigned int pwm3_c_pins[] = { | |
2752 | /* PWM */ | |
2753 | RCAR_GP_PIN(6, 6), | |
2754 | }; | |
2755 | ||
2756 | static const unsigned int pwm3_c_mux[] = { | |
2757 | PWM3_C_MARK, | |
2758 | }; | |
2759 | ||
2760 | /* - PWM4 --------------------------------------------------------------------*/ | |
2761 | static const unsigned int pwm4_a_pins[] = { | |
2762 | /* PWM */ | |
2763 | RCAR_GP_PIN(1, 3), | |
2764 | }; | |
2765 | ||
2766 | static const unsigned int pwm4_a_mux[] = { | |
2767 | PWM4_A_MARK, | |
2768 | }; | |
2769 | ||
2770 | static const unsigned int pwm4_b_pins[] = { | |
2771 | /* PWM */ | |
2772 | RCAR_GP_PIN(6, 7), | |
2773 | }; | |
2774 | ||
2775 | static const unsigned int pwm4_b_mux[] = { | |
2776 | PWM4_B_MARK, | |
2777 | }; | |
2778 | ||
2779 | /* - PWM5 --------------------------------------------------------------------*/ | |
2780 | static const unsigned int pwm5_a_pins[] = { | |
2781 | /* PWM */ | |
2782 | RCAR_GP_PIN(2, 24), | |
2783 | }; | |
2784 | ||
2785 | static const unsigned int pwm5_a_mux[] = { | |
2786 | PWM5_A_MARK, | |
2787 | }; | |
2788 | ||
2789 | static const unsigned int pwm5_b_pins[] = { | |
2790 | /* PWM */ | |
2791 | RCAR_GP_PIN(6, 10), | |
2792 | }; | |
2793 | ||
2794 | static const unsigned int pwm5_b_mux[] = { | |
2795 | PWM5_B_MARK, | |
2796 | }; | |
2797 | ||
2798 | /* - PWM6 --------------------------------------------------------------------*/ | |
2799 | static const unsigned int pwm6_a_pins[] = { | |
2800 | /* PWM */ | |
2801 | RCAR_GP_PIN(2, 25), | |
2802 | }; | |
2803 | ||
2804 | static const unsigned int pwm6_a_mux[] = { | |
2805 | PWM6_A_MARK, | |
2806 | }; | |
2807 | ||
2808 | static const unsigned int pwm6_b_pins[] = { | |
2809 | /* PWM */ | |
2810 | RCAR_GP_PIN(6, 11), | |
2811 | }; | |
2812 | ||
2813 | static const unsigned int pwm6_b_mux[] = { | |
2814 | PWM6_B_MARK, | |
2815 | }; | |
2816 | ||
2817 | /* - SCIF0 ------------------------------------------------------------------ */ | |
2818 | static const unsigned int scif0_data_a_pins[] = { | |
2819 | /* RX, TX */ | |
2820 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
2821 | }; | |
2822 | ||
2823 | static const unsigned int scif0_data_a_mux[] = { | |
2824 | RX0_A_MARK, TX0_A_MARK, | |
2825 | }; | |
2826 | ||
2827 | static const unsigned int scif0_clk_a_pins[] = { | |
2828 | /* SCK */ | |
2829 | RCAR_GP_PIN(5, 0), | |
2830 | }; | |
2831 | ||
2832 | static const unsigned int scif0_clk_a_mux[] = { | |
2833 | SCK0_A_MARK, | |
2834 | }; | |
2835 | ||
2836 | static const unsigned int scif0_ctrl_a_pins[] = { | |
2837 | /* RTS, CTS */ | |
2838 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), | |
2839 | }; | |
2840 | ||
2841 | static const unsigned int scif0_ctrl_a_mux[] = { | |
7f2e60f1 | 2842 | RTS0_N_A_MARK, CTS0_N_A_MARK, |
bf8d2dab MV |
2843 | }; |
2844 | ||
2845 | static const unsigned int scif0_data_b_pins[] = { | |
2846 | /* RX, TX */ | |
2847 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), | |
2848 | }; | |
2849 | ||
2850 | static const unsigned int scif0_data_b_mux[] = { | |
2851 | RX0_B_MARK, TX0_B_MARK, | |
2852 | }; | |
2853 | ||
2854 | static const unsigned int scif0_clk_b_pins[] = { | |
2855 | /* SCK */ | |
2856 | RCAR_GP_PIN(5, 18), | |
2857 | }; | |
2858 | ||
2859 | static const unsigned int scif0_clk_b_mux[] = { | |
2860 | SCK0_B_MARK, | |
2861 | }; | |
2862 | ||
2863 | /* - SCIF1 ------------------------------------------------------------------ */ | |
2864 | static const unsigned int scif1_data_pins[] = { | |
2865 | /* RX, TX */ | |
2866 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2867 | }; | |
2868 | ||
2869 | static const unsigned int scif1_data_mux[] = { | |
2870 | RX1_MARK, TX1_MARK, | |
2871 | }; | |
2872 | ||
2873 | static const unsigned int scif1_clk_pins[] = { | |
2874 | /* SCK */ | |
2875 | RCAR_GP_PIN(5, 16), | |
2876 | }; | |
2877 | ||
2878 | static const unsigned int scif1_clk_mux[] = { | |
2879 | SCK1_MARK, | |
2880 | }; | |
2881 | ||
2882 | static const unsigned int scif1_ctrl_pins[] = { | |
2883 | /* RTS, CTS */ | |
2884 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7), | |
2885 | }; | |
2886 | ||
2887 | static const unsigned int scif1_ctrl_mux[] = { | |
7f2e60f1 | 2888 | RTS1_N_MARK, CTS1_N_MARK, |
bf8d2dab MV |
2889 | }; |
2890 | ||
2891 | /* - SCIF2 ------------------------------------------------------------------ */ | |
2892 | static const unsigned int scif2_data_a_pins[] = { | |
2893 | /* RX, TX */ | |
2894 | RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), | |
2895 | }; | |
2896 | ||
2897 | static const unsigned int scif2_data_a_mux[] = { | |
2898 | RX2_A_MARK, TX2_A_MARK, | |
2899 | }; | |
2900 | ||
2901 | static const unsigned int scif2_clk_a_pins[] = { | |
2902 | /* SCK */ | |
2903 | RCAR_GP_PIN(5, 7), | |
2904 | }; | |
2905 | ||
2906 | static const unsigned int scif2_clk_a_mux[] = { | |
2907 | SCK2_A_MARK, | |
2908 | }; | |
2909 | ||
2910 | static const unsigned int scif2_data_b_pins[] = { | |
2911 | /* RX, TX */ | |
2912 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), | |
2913 | }; | |
2914 | ||
2915 | static const unsigned int scif2_data_b_mux[] = { | |
2916 | RX2_B_MARK, TX2_B_MARK, | |
2917 | }; | |
2918 | ||
2919 | /* - SCIF3 ------------------------------------------------------------------ */ | |
2920 | static const unsigned int scif3_data_a_pins[] = { | |
2921 | /* RX, TX */ | |
2922 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
2923 | }; | |
2924 | ||
2925 | static const unsigned int scif3_data_a_mux[] = { | |
2926 | RX3_A_MARK, TX3_A_MARK, | |
2927 | }; | |
2928 | ||
2929 | static const unsigned int scif3_clk_a_pins[] = { | |
2930 | /* SCK */ | |
2931 | RCAR_GP_PIN(0, 1), | |
2932 | }; | |
2933 | ||
2934 | static const unsigned int scif3_clk_a_mux[] = { | |
2935 | SCK3_A_MARK, | |
2936 | }; | |
2937 | ||
2938 | static const unsigned int scif3_ctrl_a_pins[] = { | |
2939 | /* RTS, CTS */ | |
2940 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7), | |
2941 | }; | |
2942 | ||
2943 | static const unsigned int scif3_ctrl_a_mux[] = { | |
7f2e60f1 | 2944 | RTS3_N_A_MARK, CTS3_N_A_MARK, |
bf8d2dab MV |
2945 | }; |
2946 | ||
2947 | static const unsigned int scif3_data_b_pins[] = { | |
2948 | /* RX, TX */ | |
2949 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
2950 | }; | |
2951 | ||
2952 | static const unsigned int scif3_data_b_mux[] = { | |
2953 | RX3_B_MARK, TX3_B_MARK, | |
2954 | }; | |
2955 | ||
2956 | static const unsigned int scif3_data_c_pins[] = { | |
2957 | /* RX, TX */ | |
2958 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), | |
2959 | }; | |
2960 | ||
2961 | static const unsigned int scif3_data_c_mux[] = { | |
2962 | RX3_C_MARK, TX3_C_MARK, | |
2963 | }; | |
2964 | ||
2965 | static const unsigned int scif3_clk_c_pins[] = { | |
2966 | /* SCK */ | |
2967 | RCAR_GP_PIN(2, 24), | |
2968 | }; | |
2969 | ||
2970 | static const unsigned int scif3_clk_c_mux[] = { | |
2971 | SCK3_C_MARK, | |
2972 | }; | |
2973 | ||
2974 | /* - SCIF4 ------------------------------------------------------------------ */ | |
2975 | static const unsigned int scif4_data_a_pins[] = { | |
2976 | /* RX, TX */ | |
2977 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
2978 | }; | |
2979 | ||
2980 | static const unsigned int scif4_data_a_mux[] = { | |
2981 | RX4_A_MARK, TX4_A_MARK, | |
2982 | }; | |
2983 | ||
2984 | static const unsigned int scif4_clk_a_pins[] = { | |
2985 | /* SCK */ | |
2986 | RCAR_GP_PIN(1, 5), | |
2987 | }; | |
2988 | ||
2989 | static const unsigned int scif4_clk_a_mux[] = { | |
2990 | SCK4_A_MARK, | |
2991 | }; | |
2992 | ||
2993 | static const unsigned int scif4_ctrl_a_pins[] = { | |
2994 | /* RTS, CTS */ | |
2995 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), | |
2996 | }; | |
2997 | ||
2998 | static const unsigned int scif4_ctrl_a_mux[] = { | |
7f2e60f1 | 2999 | RTS4_N_A_MARK, CTS4_N_A_MARK, |
bf8d2dab MV |
3000 | }; |
3001 | ||
3002 | static const unsigned int scif4_data_b_pins[] = { | |
3003 | /* RX, TX */ | |
3004 | RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), | |
3005 | }; | |
3006 | ||
3007 | static const unsigned int scif4_data_b_mux[] = { | |
3008 | RX4_B_MARK, TX4_B_MARK, | |
3009 | }; | |
3010 | ||
3011 | static const unsigned int scif4_clk_b_pins[] = { | |
3012 | /* SCK */ | |
3013 | RCAR_GP_PIN(0, 8), | |
3014 | }; | |
3015 | ||
3016 | static const unsigned int scif4_clk_b_mux[] = { | |
3017 | SCK4_B_MARK, | |
3018 | }; | |
3019 | ||
3020 | static const unsigned int scif4_data_c_pins[] = { | |
3021 | /* RX, TX */ | |
3022 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
3023 | }; | |
3024 | ||
3025 | static const unsigned int scif4_data_c_mux[] = { | |
3026 | RX4_C_MARK, TX4_C_MARK, | |
3027 | }; | |
3028 | ||
3029 | static const unsigned int scif4_ctrl_c_pins[] = { | |
3030 | /* RTS, CTS */ | |
3031 | RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), | |
3032 | }; | |
3033 | ||
3034 | static const unsigned int scif4_ctrl_c_mux[] = { | |
7f2e60f1 | 3035 | RTS4_N_C_MARK, CTS4_N_C_MARK, |
bf8d2dab MV |
3036 | }; |
3037 | ||
3038 | /* - SCIF5 ------------------------------------------------------------------ */ | |
3039 | static const unsigned int scif5_data_a_pins[] = { | |
3040 | /* RX, TX */ | |
3041 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9), | |
3042 | }; | |
3043 | ||
3044 | static const unsigned int scif5_data_a_mux[] = { | |
3045 | RX5_A_MARK, TX5_A_MARK, | |
3046 | }; | |
3047 | ||
3048 | static const unsigned int scif5_clk_a_pins[] = { | |
3049 | /* SCK */ | |
3050 | RCAR_GP_PIN(1, 13), | |
3051 | }; | |
3052 | ||
3053 | static const unsigned int scif5_clk_a_mux[] = { | |
3054 | SCK5_A_MARK, | |
3055 | }; | |
3056 | ||
3057 | static const unsigned int scif5_data_b_pins[] = { | |
3058 | /* RX, TX */ | |
3059 | RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), | |
3060 | }; | |
3061 | ||
3062 | static const unsigned int scif5_data_b_mux[] = { | |
3063 | RX5_B_MARK, TX5_B_MARK, | |
3064 | }; | |
3065 | ||
3066 | static const unsigned int scif5_data_c_pins[] = { | |
3067 | /* RX, TX */ | |
3068 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
3069 | }; | |
3070 | ||
3071 | static const unsigned int scif5_data_c_mux[] = { | |
3072 | RX5_C_MARK, TX5_C_MARK, | |
3073 | }; | |
3074 | ||
3075 | /* - SCIF Clock ------------------------------------------------------------- */ | |
3076 | static const unsigned int scif_clk_a_pins[] = { | |
3077 | /* SCIF_CLK */ | |
3078 | RCAR_GP_PIN(5, 3), | |
3079 | }; | |
3080 | ||
3081 | static const unsigned int scif_clk_a_mux[] = { | |
3082 | SCIF_CLK_A_MARK, | |
3083 | }; | |
3084 | ||
3085 | static const unsigned int scif_clk_b_pins[] = { | |
3086 | /* SCIF_CLK */ | |
3087 | RCAR_GP_PIN(5, 7), | |
3088 | }; | |
3089 | ||
3090 | static const unsigned int scif_clk_b_mux[] = { | |
3091 | SCIF_CLK_B_MARK, | |
3092 | }; | |
3093 | ||
3094 | /* - SDHI0 ------------------------------------------------------------------ */ | |
3095 | static const unsigned int sdhi0_data1_pins[] = { | |
3096 | /* D0 */ | |
3097 | RCAR_GP_PIN(3, 2), | |
3098 | }; | |
3099 | ||
3100 | static const unsigned int sdhi0_data1_mux[] = { | |
3101 | SD0_DAT0_MARK, | |
3102 | }; | |
3103 | ||
3104 | static const unsigned int sdhi0_data4_pins[] = { | |
3105 | /* D[0:3] */ | |
3106 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
3107 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
3108 | }; | |
3109 | ||
3110 | static const unsigned int sdhi0_data4_mux[] = { | |
3111 | SD0_DAT0_MARK, SD0_DAT1_MARK, | |
3112 | SD0_DAT2_MARK, SD0_DAT3_MARK, | |
3113 | }; | |
3114 | ||
3115 | static const unsigned int sdhi0_ctrl_pins[] = { | |
3116 | /* CLK, CMD */ | |
3117 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), | |
3118 | }; | |
3119 | ||
3120 | static const unsigned int sdhi0_ctrl_mux[] = { | |
3121 | SD0_CLK_MARK, SD0_CMD_MARK, | |
3122 | }; | |
3123 | ||
3124 | static const unsigned int sdhi0_cd_pins[] = { | |
3125 | /* CD */ | |
3126 | RCAR_GP_PIN(3, 12), | |
3127 | }; | |
3128 | ||
3129 | static const unsigned int sdhi0_cd_mux[] = { | |
3130 | SD0_CD_MARK, | |
3131 | }; | |
3132 | ||
3133 | static const unsigned int sdhi0_wp_pins[] = { | |
3134 | /* WP */ | |
3135 | RCAR_GP_PIN(3, 13), | |
3136 | }; | |
3137 | ||
3138 | static const unsigned int sdhi0_wp_mux[] = { | |
3139 | SD0_WP_MARK, | |
3140 | }; | |
3141 | ||
3142 | /* - SDHI1 ------------------------------------------------------------------ */ | |
3143 | static const unsigned int sdhi1_data1_pins[] = { | |
3144 | /* D0 */ | |
3145 | RCAR_GP_PIN(3, 8), | |
3146 | }; | |
3147 | ||
3148 | static const unsigned int sdhi1_data1_mux[] = { | |
3149 | SD1_DAT0_MARK, | |
3150 | }; | |
3151 | ||
3152 | static const unsigned int sdhi1_data4_pins[] = { | |
3153 | /* D[0:3] */ | |
3154 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
3155 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), | |
3156 | }; | |
3157 | ||
3158 | static const unsigned int sdhi1_data4_mux[] = { | |
3159 | SD1_DAT0_MARK, SD1_DAT1_MARK, | |
3160 | SD1_DAT2_MARK, SD1_DAT3_MARK, | |
3161 | }; | |
3162 | ||
3163 | static const unsigned int sdhi1_ctrl_pins[] = { | |
3164 | /* CLK, CMD */ | |
3165 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
3166 | }; | |
3167 | ||
3168 | static const unsigned int sdhi1_ctrl_mux[] = { | |
3169 | SD1_CLK_MARK, SD1_CMD_MARK, | |
3170 | }; | |
3171 | ||
3172 | static const unsigned int sdhi1_cd_pins[] = { | |
3173 | /* CD */ | |
3174 | RCAR_GP_PIN(3, 14), | |
3175 | }; | |
3176 | ||
3177 | static const unsigned int sdhi1_cd_mux[] = { | |
3178 | SD1_CD_MARK, | |
3179 | }; | |
3180 | ||
3181 | static const unsigned int sdhi1_wp_pins[] = { | |
3182 | /* WP */ | |
3183 | RCAR_GP_PIN(3, 15), | |
3184 | }; | |
3185 | ||
3186 | static const unsigned int sdhi1_wp_mux[] = { | |
3187 | SD1_WP_MARK, | |
3188 | }; | |
3189 | ||
3190 | /* - SDHI3 ------------------------------------------------------------------ */ | |
3191 | static const unsigned int sdhi3_data1_pins[] = { | |
3192 | /* D0 */ | |
3193 | RCAR_GP_PIN(4, 2), | |
3194 | }; | |
3195 | ||
3196 | static const unsigned int sdhi3_data1_mux[] = { | |
3197 | SD3_DAT0_MARK, | |
3198 | }; | |
3199 | ||
3200 | static const unsigned int sdhi3_data4_pins[] = { | |
3201 | /* D[0:3] */ | |
3202 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
3203 | RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), | |
3204 | }; | |
3205 | ||
3206 | static const unsigned int sdhi3_data4_mux[] = { | |
3207 | SD3_DAT0_MARK, SD3_DAT1_MARK, | |
3208 | SD3_DAT2_MARK, SD3_DAT3_MARK, | |
3209 | }; | |
3210 | ||
3211 | static const unsigned int sdhi3_data8_pins[] = { | |
3212 | /* D[0:7] */ | |
3213 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), | |
3214 | RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), | |
3215 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), | |
3216 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
3217 | }; | |
3218 | ||
3219 | static const unsigned int sdhi3_data8_mux[] = { | |
3220 | SD3_DAT0_MARK, SD3_DAT1_MARK, | |
3221 | SD3_DAT2_MARK, SD3_DAT3_MARK, | |
3222 | SD3_DAT4_MARK, SD3_DAT5_MARK, | |
3223 | SD3_DAT6_MARK, SD3_DAT7_MARK, | |
3224 | }; | |
3225 | ||
3226 | static const unsigned int sdhi3_ctrl_pins[] = { | |
3227 | /* CLK, CMD */ | |
3228 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
3229 | }; | |
3230 | ||
3231 | static const unsigned int sdhi3_ctrl_mux[] = { | |
3232 | SD3_CLK_MARK, SD3_CMD_MARK, | |
3233 | }; | |
3234 | ||
3235 | static const unsigned int sdhi3_cd_pins[] = { | |
3236 | /* CD */ | |
3237 | RCAR_GP_PIN(3, 12), | |
3238 | }; | |
3239 | ||
3240 | static const unsigned int sdhi3_cd_mux[] = { | |
3241 | SD3_CD_MARK, | |
3242 | }; | |
3243 | ||
3244 | static const unsigned int sdhi3_wp_pins[] = { | |
3245 | /* WP */ | |
3246 | RCAR_GP_PIN(3, 13), | |
3247 | }; | |
3248 | ||
3249 | static const unsigned int sdhi3_wp_mux[] = { | |
3250 | SD3_WP_MARK, | |
3251 | }; | |
3252 | ||
3253 | static const unsigned int sdhi3_ds_pins[] = { | |
3254 | /* DS */ | |
3255 | RCAR_GP_PIN(4, 10), | |
3256 | }; | |
3257 | ||
3258 | static const unsigned int sdhi3_ds_mux[] = { | |
3259 | SD3_DS_MARK, | |
3260 | }; | |
3261 | ||
3262 | /* - SSI -------------------------------------------------------------------- */ | |
3263 | static const unsigned int ssi0_data_pins[] = { | |
3264 | /* SDATA */ | |
3265 | RCAR_GP_PIN(6, 2), | |
3266 | }; | |
3267 | ||
3268 | static const unsigned int ssi0_data_mux[] = { | |
3269 | SSI_SDATA0_MARK, | |
3270 | }; | |
3271 | ||
3272 | static const unsigned int ssi01239_ctrl_pins[] = { | |
3273 | /* SCK, WS */ | |
3274 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), | |
3275 | }; | |
3276 | ||
3277 | static const unsigned int ssi01239_ctrl_mux[] = { | |
3278 | SSI_SCK01239_MARK, SSI_WS01239_MARK, | |
3279 | }; | |
3280 | ||
3281 | static const unsigned int ssi1_data_pins[] = { | |
3282 | /* SDATA */ | |
3283 | RCAR_GP_PIN(6, 3), | |
3284 | }; | |
3285 | ||
3286 | static const unsigned int ssi1_data_mux[] = { | |
3287 | SSI_SDATA1_MARK, | |
3288 | }; | |
3289 | ||
3290 | static const unsigned int ssi1_ctrl_pins[] = { | |
3291 | /* SCK, WS */ | |
3292 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | |
3293 | }; | |
3294 | ||
3295 | static const unsigned int ssi1_ctrl_mux[] = { | |
3296 | SSI_SCK1_MARK, SSI_WS1_MARK, | |
3297 | }; | |
3298 | ||
3299 | static const unsigned int ssi2_data_pins[] = { | |
3300 | /* SDATA */ | |
3301 | RCAR_GP_PIN(6, 4), | |
3302 | }; | |
3303 | ||
3304 | static const unsigned int ssi2_data_mux[] = { | |
3305 | SSI_SDATA2_MARK, | |
3306 | }; | |
3307 | ||
3308 | static const unsigned int ssi2_ctrl_a_pins[] = { | |
3309 | /* SCK, WS */ | |
3310 | RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), | |
3311 | }; | |
3312 | ||
3313 | static const unsigned int ssi2_ctrl_a_mux[] = { | |
3314 | SSI_SCK2_A_MARK, SSI_WS2_A_MARK, | |
3315 | }; | |
3316 | ||
3317 | static const unsigned int ssi2_ctrl_b_pins[] = { | |
3318 | /* SCK, WS */ | |
3319 | RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), | |
3320 | }; | |
3321 | ||
3322 | static const unsigned int ssi2_ctrl_b_mux[] = { | |
3323 | SSI_SCK2_B_MARK, SSI_WS2_B_MARK, | |
3324 | }; | |
3325 | ||
3326 | static const unsigned int ssi3_data_pins[] = { | |
3327 | /* SDATA */ | |
3328 | RCAR_GP_PIN(6, 7), | |
3329 | }; | |
3330 | ||
3331 | static const unsigned int ssi3_data_mux[] = { | |
3332 | SSI_SDATA3_MARK, | |
3333 | }; | |
3334 | ||
3335 | static const unsigned int ssi349_ctrl_pins[] = { | |
3336 | /* SCK, WS */ | |
3337 | RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), | |
3338 | }; | |
3339 | ||
3340 | static const unsigned int ssi349_ctrl_mux[] = { | |
3341 | SSI_SCK349_MARK, SSI_WS349_MARK, | |
3342 | }; | |
3343 | ||
3344 | static const unsigned int ssi4_data_pins[] = { | |
3345 | /* SDATA */ | |
3346 | RCAR_GP_PIN(6, 10), | |
3347 | }; | |
3348 | ||
3349 | static const unsigned int ssi4_data_mux[] = { | |
3350 | SSI_SDATA4_MARK, | |
3351 | }; | |
3352 | ||
3353 | static const unsigned int ssi4_ctrl_pins[] = { | |
3354 | /* SCK, WS */ | |
3355 | RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), | |
3356 | }; | |
3357 | ||
3358 | static const unsigned int ssi4_ctrl_mux[] = { | |
3359 | SSI_SCK4_MARK, SSI_WS4_MARK, | |
3360 | }; | |
3361 | ||
3362 | static const unsigned int ssi5_data_pins[] = { | |
3363 | /* SDATA */ | |
3364 | RCAR_GP_PIN(6, 13), | |
3365 | }; | |
3366 | ||
3367 | static const unsigned int ssi5_data_mux[] = { | |
3368 | SSI_SDATA5_MARK, | |
3369 | }; | |
3370 | ||
3371 | static const unsigned int ssi5_ctrl_pins[] = { | |
3372 | /* SCK, WS */ | |
3373 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
3374 | }; | |
3375 | ||
3376 | static const unsigned int ssi5_ctrl_mux[] = { | |
3377 | SSI_SCK5_MARK, SSI_WS5_MARK, | |
3378 | }; | |
3379 | ||
3380 | static const unsigned int ssi6_data_pins[] = { | |
3381 | /* SDATA */ | |
3382 | RCAR_GP_PIN(6, 16), | |
3383 | }; | |
3384 | ||
3385 | static const unsigned int ssi6_data_mux[] = { | |
3386 | SSI_SDATA6_MARK, | |
3387 | }; | |
3388 | ||
3389 | static const unsigned int ssi6_ctrl_pins[] = { | |
3390 | /* SCK, WS */ | |
3391 | RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), | |
3392 | }; | |
3393 | ||
3394 | static const unsigned int ssi6_ctrl_mux[] = { | |
3395 | SSI_SCK6_MARK, SSI_WS6_MARK, | |
3396 | }; | |
3397 | ||
3398 | static const unsigned int ssi7_data_pins[] = { | |
3399 | /* SDATA */ | |
3400 | RCAR_GP_PIN(5, 12), | |
3401 | }; | |
3402 | ||
3403 | static const unsigned int ssi7_data_mux[] = { | |
3404 | SSI_SDATA7_MARK, | |
3405 | }; | |
3406 | ||
3407 | static const unsigned int ssi78_ctrl_pins[] = { | |
3408 | /* SCK, WS */ | |
3409 | RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), | |
3410 | }; | |
3411 | ||
3412 | static const unsigned int ssi78_ctrl_mux[] = { | |
3413 | SSI_SCK78_MARK, SSI_WS78_MARK, | |
3414 | }; | |
3415 | ||
3416 | static const unsigned int ssi8_data_pins[] = { | |
3417 | /* SDATA */ | |
3418 | RCAR_GP_PIN(5, 13), | |
3419 | }; | |
3420 | ||
3421 | static const unsigned int ssi8_data_mux[] = { | |
3422 | SSI_SDATA8_MARK, | |
3423 | }; | |
3424 | ||
3425 | static const unsigned int ssi9_data_pins[] = { | |
3426 | /* SDATA */ | |
3427 | RCAR_GP_PIN(5, 16), | |
3428 | }; | |
3429 | ||
3430 | static const unsigned int ssi9_data_mux[] = { | |
3431 | SSI_SDATA9_MARK, | |
3432 | }; | |
3433 | ||
3434 | static const unsigned int ssi9_ctrl_a_pins[] = { | |
3435 | /* SCK, WS */ | |
3436 | RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10), | |
3437 | }; | |
3438 | ||
3439 | static const unsigned int ssi9_ctrl_a_mux[] = { | |
3440 | SSI_SCK9_A_MARK, SSI_WS9_A_MARK, | |
3441 | }; | |
3442 | ||
3443 | static const unsigned int ssi9_ctrl_b_pins[] = { | |
3444 | /* SCK, WS */ | |
3445 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
3446 | }; | |
3447 | ||
3448 | static const unsigned int ssi9_ctrl_b_mux[] = { | |
3449 | SSI_SCK9_B_MARK, SSI_WS9_B_MARK, | |
3450 | }; | |
3451 | ||
3452 | /* - TMU -------------------------------------------------------------------- */ | |
3453 | static const unsigned int tmu_tclk1_a_pins[] = { | |
3454 | /* TCLK */ | |
3455 | RCAR_GP_PIN(3, 12), | |
3456 | }; | |
3457 | ||
3458 | static const unsigned int tmu_tclk1_a_mux[] = { | |
3459 | TCLK1_A_MARK, | |
3460 | }; | |
3461 | ||
3462 | static const unsigned int tmu_tclk1_b_pins[] = { | |
3463 | /* TCLK */ | |
3464 | RCAR_GP_PIN(5, 17), | |
3465 | }; | |
3466 | ||
3467 | static const unsigned int tmu_tclk1_b_mux[] = { | |
3468 | TCLK1_B_MARK, | |
3469 | }; | |
3470 | ||
3471 | static const unsigned int tmu_tclk2_a_pins[] = { | |
3472 | /* TCLK */ | |
3473 | RCAR_GP_PIN(3, 13), | |
3474 | }; | |
3475 | ||
3476 | static const unsigned int tmu_tclk2_a_mux[] = { | |
3477 | TCLK2_A_MARK, | |
3478 | }; | |
3479 | ||
3480 | static const unsigned int tmu_tclk2_b_pins[] = { | |
3481 | /* TCLK */ | |
3482 | RCAR_GP_PIN(5, 18), | |
3483 | }; | |
3484 | ||
3485 | static const unsigned int tmu_tclk2_b_mux[] = { | |
3486 | TCLK2_B_MARK, | |
3487 | }; | |
3488 | ||
3489 | /* - USB0 ------------------------------------------------------------------- */ | |
3490 | static const unsigned int usb0_a_pins[] = { | |
3491 | /* PWEN, OVC */ | |
3492 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), | |
3493 | }; | |
3494 | ||
3495 | static const unsigned int usb0_a_mux[] = { | |
3496 | USB0_PWEN_A_MARK, USB0_OVC_A_MARK, | |
3497 | }; | |
3498 | ||
3499 | static const unsigned int usb0_b_pins[] = { | |
3500 | /* PWEN, OVC */ | |
3501 | RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), | |
3502 | }; | |
3503 | ||
3504 | static const unsigned int usb0_b_mux[] = { | |
3505 | USB0_PWEN_B_MARK, USB0_OVC_B_MARK, | |
3506 | }; | |
3507 | ||
3508 | static const unsigned int usb0_id_pins[] = { | |
3509 | /* ID */ | |
3510 | RCAR_GP_PIN(5, 0) | |
3511 | }; | |
3512 | ||
3513 | static const unsigned int usb0_id_mux[] = { | |
65eef78c | 3514 | USB0_ID_MARK, |
bf8d2dab MV |
3515 | }; |
3516 | ||
3517 | /* - USB30 ------------------------------------------------------------------ */ | |
3518 | static const unsigned int usb30_pins[] = { | |
3519 | /* PWEN, OVC */ | |
3520 | RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9), | |
3521 | }; | |
3522 | ||
3523 | static const unsigned int usb30_mux[] = { | |
3524 | USB30_PWEN_MARK, USB30_OVC_MARK, | |
3525 | }; | |
3526 | ||
3527 | static const unsigned int usb30_id_pins[] = { | |
3528 | /* ID */ | |
3529 | RCAR_GP_PIN(5, 0), | |
3530 | }; | |
3531 | ||
3532 | static const unsigned int usb30_id_mux[] = { | |
3533 | USB3HS0_ID_MARK, | |
3534 | }; | |
3535 | ||
3536 | /* - VIN4 ------------------------------------------------------------------- */ | |
8719ca81 | 3537 | static const unsigned int vin4_data18_a_pins[] = { |
bf8d2dab MV |
3538 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), |
3539 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), | |
3540 | RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), | |
bf8d2dab MV |
3541 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), |
3542 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), | |
3543 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
bf8d2dab MV |
3544 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), |
3545 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), | |
3546 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), | |
3547 | }; | |
3548 | ||
8719ca81 | 3549 | static const unsigned int vin4_data18_a_mux[] = { |
bf8d2dab MV |
3550 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, |
3551 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | |
3552 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | |
bf8d2dab MV |
3553 | VI4_DATA10_MARK, VI4_DATA11_MARK, |
3554 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
3555 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
bf8d2dab MV |
3556 | VI4_DATA18_MARK, VI4_DATA19_MARK, |
3557 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
3558 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
3559 | }; | |
3560 | ||
8719ca81 MV |
3561 | static const union vin_data vin4_data_a_pins = { |
3562 | .data24 = { | |
3563 | RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), | |
3564 | RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), | |
3565 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), | |
3566 | RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), | |
3567 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
3568 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
3569 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), | |
3570 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
3571 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), | |
3572 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), | |
3573 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), | |
3574 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), | |
3575 | }, | |
bf8d2dab MV |
3576 | }; |
3577 | ||
8719ca81 MV |
3578 | static const union vin_data vin4_data_a_mux = { |
3579 | .data24 = { | |
3580 | VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, | |
3581 | VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, | |
3582 | VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, | |
3583 | VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, | |
3584 | VI4_DATA8_MARK, VI4_DATA9_MARK, | |
3585 | VI4_DATA10_MARK, VI4_DATA11_MARK, | |
3586 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
3587 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
3588 | VI4_DATA16_MARK, VI4_DATA17_MARK, | |
3589 | VI4_DATA18_MARK, VI4_DATA19_MARK, | |
3590 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
3591 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
3592 | }, | |
bf8d2dab MV |
3593 | }; |
3594 | ||
8719ca81 | 3595 | static const unsigned int vin4_data18_b_pins[] = { |
bf8d2dab MV |
3596 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), |
3597 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
3598 | RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), | |
bf8d2dab MV |
3599 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), |
3600 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), | |
3601 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
bf8d2dab | 3602 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), |
bf8d2dab MV |
3603 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), |
3604 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), | |
3605 | }; | |
3606 | ||
8719ca81 | 3607 | static const unsigned int vin4_data18_b_mux[] = { |
bf8d2dab MV |
3608 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, |
3609 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | |
3610 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | |
bf8d2dab MV |
3611 | VI4_DATA10_MARK, VI4_DATA11_MARK, |
3612 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
3613 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
bf8d2dab MV |
3614 | VI4_DATA18_MARK, VI4_DATA19_MARK, |
3615 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
3616 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
3617 | }; | |
3618 | ||
8719ca81 MV |
3619 | static const union vin_data vin4_data_b_pins = { |
3620 | .data24 = { | |
3621 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), | |
3622 | RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), | |
3623 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), | |
3624 | RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), | |
3625 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
3626 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
3627 | RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), | |
3628 | RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), | |
3629 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), | |
3630 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), | |
3631 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), | |
3632 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), | |
3633 | }, | |
bf8d2dab MV |
3634 | }; |
3635 | ||
8719ca81 MV |
3636 | static const union vin_data vin4_data_b_mux = { |
3637 | .data24 = { | |
3638 | VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, | |
3639 | VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, | |
3640 | VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, | |
3641 | VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, | |
3642 | VI4_DATA8_MARK, VI4_DATA9_MARK, | |
3643 | VI4_DATA10_MARK, VI4_DATA11_MARK, | |
3644 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
3645 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
3646 | VI4_DATA16_MARK, VI4_DATA17_MARK, | |
3647 | VI4_DATA18_MARK, VI4_DATA19_MARK, | |
3648 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
3649 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
3650 | }, | |
bf8d2dab MV |
3651 | }; |
3652 | ||
3653 | static const unsigned int vin4_sync_pins[] = { | |
3654 | /* HSYNC, VSYNC */ | |
3655 | RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24), | |
3656 | }; | |
3657 | ||
3658 | static const unsigned int vin4_sync_mux[] = { | |
3659 | VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, | |
3660 | }; | |
3661 | ||
3662 | static const unsigned int vin4_field_pins[] = { | |
3663 | RCAR_GP_PIN(2, 23), | |
3664 | }; | |
3665 | ||
3666 | static const unsigned int vin4_field_mux[] = { | |
3667 | VI4_FIELD_MARK, | |
3668 | }; | |
3669 | ||
3670 | static const unsigned int vin4_clkenb_pins[] = { | |
3671 | RCAR_GP_PIN(1, 2), | |
3672 | }; | |
3673 | ||
3674 | static const unsigned int vin4_clkenb_mux[] = { | |
3675 | VI4_CLKENB_MARK, | |
3676 | }; | |
3677 | ||
3678 | static const unsigned int vin4_clk_pins[] = { | |
3679 | RCAR_GP_PIN(2, 22), | |
3680 | }; | |
3681 | ||
3682 | static const unsigned int vin4_clk_mux[] = { | |
3683 | VI4_CLK_MARK, | |
3684 | }; | |
3685 | ||
3686 | /* - VIN5 ------------------------------------------------------------------- */ | |
8719ca81 MV |
3687 | static const union vin_data16 vin5_data_a_pins = { |
3688 | .data16 = { | |
3689 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), | |
3690 | RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), | |
3691 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), | |
3692 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), | |
3693 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
3694 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), | |
3695 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), | |
3696 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
3697 | }, | |
bf8d2dab MV |
3698 | }; |
3699 | ||
8719ca81 MV |
3700 | static const union vin_data16 vin5_data_a_mux = { |
3701 | .data16 = { | |
3702 | VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, | |
3703 | VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, | |
3704 | VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, | |
3705 | VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, | |
3706 | VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, | |
3707 | VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, | |
3708 | VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, | |
3709 | VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, | |
3710 | }, | |
bf8d2dab MV |
3711 | }; |
3712 | ||
3713 | static const unsigned int vin5_data8_b_pins[] = { | |
3714 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4), | |
3715 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12), | |
3716 | RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), | |
3717 | RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), | |
3718 | }; | |
3719 | ||
3720 | static const unsigned int vin5_data8_b_mux[] = { | |
3721 | VI5_DATA0_B_MARK, VI5_DATA1_B_MARK, | |
3722 | VI5_DATA2_B_MARK, VI5_DATA3_B_MARK, | |
3723 | VI5_DATA4_B_MARK, VI5_DATA5_B_MARK, | |
3724 | VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, | |
3725 | }; | |
3726 | ||
3727 | static const unsigned int vin5_sync_a_pins[] = { | |
3728 | /* HSYNC_N, VSYNC_N */ | |
3729 | RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), | |
3730 | }; | |
3731 | ||
3732 | static const unsigned int vin5_sync_a_mux[] = { | |
3733 | VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK, | |
3734 | }; | |
3735 | ||
3736 | static const unsigned int vin5_field_a_pins[] = { | |
3737 | RCAR_GP_PIN(1, 10), | |
3738 | }; | |
3739 | ||
3740 | static const unsigned int vin5_field_a_mux[] = { | |
3741 | VI5_FIELD_A_MARK, | |
3742 | }; | |
3743 | ||
3744 | static const unsigned int vin5_clkenb_a_pins[] = { | |
3745 | RCAR_GP_PIN(0, 1), | |
3746 | }; | |
3747 | ||
3748 | static const unsigned int vin5_clkenb_a_mux[] = { | |
3749 | VI5_CLKENB_A_MARK, | |
3750 | }; | |
3751 | ||
3752 | static const unsigned int vin5_clk_a_pins[] = { | |
3753 | RCAR_GP_PIN(1, 0), | |
3754 | }; | |
3755 | ||
3756 | static const unsigned int vin5_clk_a_mux[] = { | |
3757 | VI5_CLK_A_MARK, | |
3758 | }; | |
3759 | ||
3760 | static const unsigned int vin5_clk_b_pins[] = { | |
3761 | RCAR_GP_PIN(2, 22), | |
3762 | }; | |
3763 | ||
3764 | static const unsigned int vin5_clk_b_mux[] = { | |
3765 | VI5_CLK_B_MARK, | |
3766 | }; | |
3767 | ||
8719ca81 | 3768 | static const struct { |
7f2e60f1 ER |
3769 | struct sh_pfc_pin_group common[247]; |
3770 | struct sh_pfc_pin_group automotive[21]; | |
8719ca81 MV |
3771 | } pinmux_groups = { |
3772 | .common = { | |
3773 | SH_PFC_PIN_GROUP(audio_clk_a), | |
3774 | SH_PFC_PIN_GROUP(audio_clk_b_a), | |
3775 | SH_PFC_PIN_GROUP(audio_clk_b_b), | |
3776 | SH_PFC_PIN_GROUP(audio_clk_b_c), | |
3777 | SH_PFC_PIN_GROUP(audio_clk_c_a), | |
3778 | SH_PFC_PIN_GROUP(audio_clk_c_b), | |
3779 | SH_PFC_PIN_GROUP(audio_clk_c_c), | |
3780 | SH_PFC_PIN_GROUP(audio_clkout_a), | |
3781 | SH_PFC_PIN_GROUP(audio_clkout_b), | |
3782 | SH_PFC_PIN_GROUP(audio_clkout1_a), | |
3783 | SH_PFC_PIN_GROUP(audio_clkout1_b), | |
3784 | SH_PFC_PIN_GROUP(audio_clkout1_c), | |
3785 | SH_PFC_PIN_GROUP(audio_clkout2_a), | |
3786 | SH_PFC_PIN_GROUP(audio_clkout2_b), | |
3787 | SH_PFC_PIN_GROUP(audio_clkout2_c), | |
3788 | SH_PFC_PIN_GROUP(audio_clkout3_a), | |
3789 | SH_PFC_PIN_GROUP(audio_clkout3_b), | |
3790 | SH_PFC_PIN_GROUP(audio_clkout3_c), | |
3791 | SH_PFC_PIN_GROUP(avb_link), | |
3792 | SH_PFC_PIN_GROUP(avb_magic), | |
3793 | SH_PFC_PIN_GROUP(avb_phy_int), | |
3794 | SH_PFC_PIN_GROUP(avb_mii), | |
3795 | SH_PFC_PIN_GROUP(avb_avtp_pps), | |
3796 | SH_PFC_PIN_GROUP(avb_avtp_match_a), | |
3797 | SH_PFC_PIN_GROUP(avb_avtp_capture_a), | |
3798 | SH_PFC_PIN_GROUP(can0_data), | |
3799 | SH_PFC_PIN_GROUP(can1_data), | |
3800 | SH_PFC_PIN_GROUP(can_clk), | |
7f2e60f1 ER |
3801 | SH_PFC_PIN_GROUP(canfd0_data), |
3802 | SH_PFC_PIN_GROUP(canfd1_data), | |
8719ca81 MV |
3803 | SH_PFC_PIN_GROUP(du_rgb666), |
3804 | SH_PFC_PIN_GROUP(du_rgb888), | |
3805 | SH_PFC_PIN_GROUP(du_clk_in_0), | |
3806 | SH_PFC_PIN_GROUP(du_clk_in_1), | |
3807 | SH_PFC_PIN_GROUP(du_clk_out_0), | |
3808 | SH_PFC_PIN_GROUP(du_sync), | |
3809 | SH_PFC_PIN_GROUP(du_disp_cde), | |
3810 | SH_PFC_PIN_GROUP(du_cde), | |
3811 | SH_PFC_PIN_GROUP(du_disp), | |
3812 | SH_PFC_PIN_GROUP(hscif0_data_a), | |
3813 | SH_PFC_PIN_GROUP(hscif0_clk_a), | |
3814 | SH_PFC_PIN_GROUP(hscif0_ctrl_a), | |
3815 | SH_PFC_PIN_GROUP(hscif0_data_b), | |
3816 | SH_PFC_PIN_GROUP(hscif0_clk_b), | |
3817 | SH_PFC_PIN_GROUP(hscif1_data_a), | |
3818 | SH_PFC_PIN_GROUP(hscif1_clk_a), | |
3819 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
3820 | SH_PFC_PIN_GROUP(hscif1_clk_b), | |
3821 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
3822 | SH_PFC_PIN_GROUP(hscif2_data_a), | |
3823 | SH_PFC_PIN_GROUP(hscif2_clk_a), | |
3824 | SH_PFC_PIN_GROUP(hscif2_ctrl_a), | |
3825 | SH_PFC_PIN_GROUP(hscif2_data_b), | |
3826 | SH_PFC_PIN_GROUP(hscif3_data_a), | |
3827 | SH_PFC_PIN_GROUP(hscif3_data_b), | |
3828 | SH_PFC_PIN_GROUP(hscif3_clk_b), | |
3829 | SH_PFC_PIN_GROUP(hscif3_data_c), | |
3830 | SH_PFC_PIN_GROUP(hscif3_clk_c), | |
3831 | SH_PFC_PIN_GROUP(hscif3_ctrl_c), | |
3832 | SH_PFC_PIN_GROUP(hscif3_data_d), | |
3833 | SH_PFC_PIN_GROUP(hscif3_data_e), | |
3834 | SH_PFC_PIN_GROUP(hscif3_ctrl_e), | |
3835 | SH_PFC_PIN_GROUP(hscif4_data_a), | |
3836 | SH_PFC_PIN_GROUP(hscif4_clk_a), | |
3837 | SH_PFC_PIN_GROUP(hscif4_ctrl_a), | |
3838 | SH_PFC_PIN_GROUP(hscif4_data_b), | |
3839 | SH_PFC_PIN_GROUP(hscif4_clk_b), | |
3840 | SH_PFC_PIN_GROUP(hscif4_data_c), | |
3841 | SH_PFC_PIN_GROUP(hscif4_data_d), | |
3842 | SH_PFC_PIN_GROUP(hscif4_data_e), | |
3843 | SH_PFC_PIN_GROUP(i2c1_a), | |
3844 | SH_PFC_PIN_GROUP(i2c1_b), | |
3845 | SH_PFC_PIN_GROUP(i2c1_c), | |
3846 | SH_PFC_PIN_GROUP(i2c1_d), | |
3847 | SH_PFC_PIN_GROUP(i2c2_a), | |
3848 | SH_PFC_PIN_GROUP(i2c2_b), | |
3849 | SH_PFC_PIN_GROUP(i2c2_c), | |
3850 | SH_PFC_PIN_GROUP(i2c2_d), | |
3851 | SH_PFC_PIN_GROUP(i2c2_e), | |
3852 | SH_PFC_PIN_GROUP(i2c4), | |
3853 | SH_PFC_PIN_GROUP(i2c5), | |
3854 | SH_PFC_PIN_GROUP(i2c6_a), | |
3855 | SH_PFC_PIN_GROUP(i2c6_b), | |
3856 | SH_PFC_PIN_GROUP(i2c7_a), | |
3857 | SH_PFC_PIN_GROUP(i2c7_b), | |
3858 | SH_PFC_PIN_GROUP(intc_ex_irq0), | |
3859 | SH_PFC_PIN_GROUP(intc_ex_irq1), | |
3860 | SH_PFC_PIN_GROUP(intc_ex_irq2), | |
3861 | SH_PFC_PIN_GROUP(intc_ex_irq3), | |
3862 | SH_PFC_PIN_GROUP(intc_ex_irq4), | |
3863 | SH_PFC_PIN_GROUP(intc_ex_irq5), | |
3864 | SH_PFC_PIN_GROUP(msiof0_clk), | |
3865 | SH_PFC_PIN_GROUP(msiof0_sync), | |
3866 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
3867 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
3868 | SH_PFC_PIN_GROUP(msiof0_txd), | |
3869 | SH_PFC_PIN_GROUP(msiof0_rxd), | |
3870 | SH_PFC_PIN_GROUP(msiof1_clk), | |
3871 | SH_PFC_PIN_GROUP(msiof1_sync), | |
3872 | SH_PFC_PIN_GROUP(msiof1_ss1), | |
3873 | SH_PFC_PIN_GROUP(msiof1_ss2), | |
3874 | SH_PFC_PIN_GROUP(msiof1_txd), | |
3875 | SH_PFC_PIN_GROUP(msiof1_rxd), | |
3876 | SH_PFC_PIN_GROUP(msiof2_clk_a), | |
3877 | SH_PFC_PIN_GROUP(msiof2_sync_a), | |
3878 | SH_PFC_PIN_GROUP(msiof2_ss1_a), | |
3879 | SH_PFC_PIN_GROUP(msiof2_ss2_a), | |
3880 | SH_PFC_PIN_GROUP(msiof2_txd_a), | |
3881 | SH_PFC_PIN_GROUP(msiof2_rxd_a), | |
3882 | SH_PFC_PIN_GROUP(msiof2_clk_b), | |
3883 | SH_PFC_PIN_GROUP(msiof2_sync_b), | |
3884 | SH_PFC_PIN_GROUP(msiof2_ss1_b), | |
3885 | SH_PFC_PIN_GROUP(msiof2_ss2_b), | |
3886 | SH_PFC_PIN_GROUP(msiof2_txd_b), | |
3887 | SH_PFC_PIN_GROUP(msiof2_rxd_b), | |
3888 | SH_PFC_PIN_GROUP(msiof3_clk_a), | |
3889 | SH_PFC_PIN_GROUP(msiof3_sync_a), | |
3890 | SH_PFC_PIN_GROUP(msiof3_ss1_a), | |
3891 | SH_PFC_PIN_GROUP(msiof3_ss2_a), | |
3892 | SH_PFC_PIN_GROUP(msiof3_txd_a), | |
3893 | SH_PFC_PIN_GROUP(msiof3_rxd_a), | |
3894 | SH_PFC_PIN_GROUP(msiof3_clk_b), | |
3895 | SH_PFC_PIN_GROUP(msiof3_sync_b), | |
3896 | SH_PFC_PIN_GROUP(msiof3_ss1_b), | |
3897 | SH_PFC_PIN_GROUP(msiof3_txd_b), | |
3898 | SH_PFC_PIN_GROUP(msiof3_rxd_b), | |
3899 | SH_PFC_PIN_GROUP(pwm0_a), | |
3900 | SH_PFC_PIN_GROUP(pwm0_b), | |
3901 | SH_PFC_PIN_GROUP(pwm1_a), | |
3902 | SH_PFC_PIN_GROUP(pwm1_b), | |
3903 | SH_PFC_PIN_GROUP(pwm2_a), | |
3904 | SH_PFC_PIN_GROUP(pwm2_b), | |
3905 | SH_PFC_PIN_GROUP(pwm2_c), | |
3906 | SH_PFC_PIN_GROUP(pwm3_a), | |
3907 | SH_PFC_PIN_GROUP(pwm3_b), | |
3908 | SH_PFC_PIN_GROUP(pwm3_c), | |
3909 | SH_PFC_PIN_GROUP(pwm4_a), | |
3910 | SH_PFC_PIN_GROUP(pwm4_b), | |
3911 | SH_PFC_PIN_GROUP(pwm5_a), | |
3912 | SH_PFC_PIN_GROUP(pwm5_b), | |
3913 | SH_PFC_PIN_GROUP(pwm6_a), | |
3914 | SH_PFC_PIN_GROUP(pwm6_b), | |
3915 | SH_PFC_PIN_GROUP(scif0_data_a), | |
3916 | SH_PFC_PIN_GROUP(scif0_clk_a), | |
3917 | SH_PFC_PIN_GROUP(scif0_ctrl_a), | |
3918 | SH_PFC_PIN_GROUP(scif0_data_b), | |
3919 | SH_PFC_PIN_GROUP(scif0_clk_b), | |
3920 | SH_PFC_PIN_GROUP(scif1_data), | |
3921 | SH_PFC_PIN_GROUP(scif1_clk), | |
3922 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
3923 | SH_PFC_PIN_GROUP(scif2_data_a), | |
3924 | SH_PFC_PIN_GROUP(scif2_clk_a), | |
3925 | SH_PFC_PIN_GROUP(scif2_data_b), | |
3926 | SH_PFC_PIN_GROUP(scif3_data_a), | |
3927 | SH_PFC_PIN_GROUP(scif3_clk_a), | |
3928 | SH_PFC_PIN_GROUP(scif3_ctrl_a), | |
3929 | SH_PFC_PIN_GROUP(scif3_data_b), | |
3930 | SH_PFC_PIN_GROUP(scif3_data_c), | |
3931 | SH_PFC_PIN_GROUP(scif3_clk_c), | |
3932 | SH_PFC_PIN_GROUP(scif4_data_a), | |
3933 | SH_PFC_PIN_GROUP(scif4_clk_a), | |
3934 | SH_PFC_PIN_GROUP(scif4_ctrl_a), | |
3935 | SH_PFC_PIN_GROUP(scif4_data_b), | |
3936 | SH_PFC_PIN_GROUP(scif4_clk_b), | |
3937 | SH_PFC_PIN_GROUP(scif4_data_c), | |
3938 | SH_PFC_PIN_GROUP(scif4_ctrl_c), | |
3939 | SH_PFC_PIN_GROUP(scif5_data_a), | |
3940 | SH_PFC_PIN_GROUP(scif5_clk_a), | |
3941 | SH_PFC_PIN_GROUP(scif5_data_b), | |
3942 | SH_PFC_PIN_GROUP(scif5_data_c), | |
3943 | SH_PFC_PIN_GROUP(scif_clk_a), | |
3944 | SH_PFC_PIN_GROUP(scif_clk_b), | |
3945 | SH_PFC_PIN_GROUP(sdhi0_data1), | |
3946 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
3947 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
3948 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
3949 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
3950 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
3951 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
3952 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
3953 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
3954 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
3955 | SH_PFC_PIN_GROUP(sdhi3_data1), | |
3956 | SH_PFC_PIN_GROUP(sdhi3_data4), | |
3957 | SH_PFC_PIN_GROUP(sdhi3_data8), | |
3958 | SH_PFC_PIN_GROUP(sdhi3_ctrl), | |
3959 | SH_PFC_PIN_GROUP(sdhi3_cd), | |
3960 | SH_PFC_PIN_GROUP(sdhi3_wp), | |
3961 | SH_PFC_PIN_GROUP(sdhi3_ds), | |
3962 | SH_PFC_PIN_GROUP(ssi0_data), | |
3963 | SH_PFC_PIN_GROUP(ssi01239_ctrl), | |
3964 | SH_PFC_PIN_GROUP(ssi1_data), | |
3965 | SH_PFC_PIN_GROUP(ssi1_ctrl), | |
3966 | SH_PFC_PIN_GROUP(ssi2_data), | |
3967 | SH_PFC_PIN_GROUP(ssi2_ctrl_a), | |
3968 | SH_PFC_PIN_GROUP(ssi2_ctrl_b), | |
3969 | SH_PFC_PIN_GROUP(ssi3_data), | |
3970 | SH_PFC_PIN_GROUP(ssi349_ctrl), | |
3971 | SH_PFC_PIN_GROUP(ssi4_data), | |
3972 | SH_PFC_PIN_GROUP(ssi4_ctrl), | |
3973 | SH_PFC_PIN_GROUP(ssi5_data), | |
3974 | SH_PFC_PIN_GROUP(ssi5_ctrl), | |
3975 | SH_PFC_PIN_GROUP(ssi6_data), | |
3976 | SH_PFC_PIN_GROUP(ssi6_ctrl), | |
3977 | SH_PFC_PIN_GROUP(ssi7_data), | |
3978 | SH_PFC_PIN_GROUP(ssi78_ctrl), | |
3979 | SH_PFC_PIN_GROUP(ssi8_data), | |
3980 | SH_PFC_PIN_GROUP(ssi9_data), | |
3981 | SH_PFC_PIN_GROUP(ssi9_ctrl_a), | |
3982 | SH_PFC_PIN_GROUP(ssi9_ctrl_b), | |
3983 | SH_PFC_PIN_GROUP(tmu_tclk1_a), | |
3984 | SH_PFC_PIN_GROUP(tmu_tclk1_b), | |
3985 | SH_PFC_PIN_GROUP(tmu_tclk2_a), | |
3986 | SH_PFC_PIN_GROUP(tmu_tclk2_b), | |
3987 | SH_PFC_PIN_GROUP(usb0_a), | |
3988 | SH_PFC_PIN_GROUP(usb0_b), | |
3989 | SH_PFC_PIN_GROUP(usb0_id), | |
3990 | SH_PFC_PIN_GROUP(usb30), | |
3991 | SH_PFC_PIN_GROUP(usb30_id), | |
3992 | VIN_DATA_PIN_GROUP(vin4_data, 8, _a), | |
3993 | VIN_DATA_PIN_GROUP(vin4_data, 10, _a), | |
3994 | VIN_DATA_PIN_GROUP(vin4_data, 12, _a), | |
3995 | VIN_DATA_PIN_GROUP(vin4_data, 16, _a), | |
3996 | SH_PFC_PIN_GROUP(vin4_data18_a), | |
3997 | VIN_DATA_PIN_GROUP(vin4_data, 20, _a), | |
3998 | VIN_DATA_PIN_GROUP(vin4_data, 24, _a), | |
3999 | VIN_DATA_PIN_GROUP(vin4_data, 8, _b), | |
4000 | VIN_DATA_PIN_GROUP(vin4_data, 10, _b), | |
4001 | VIN_DATA_PIN_GROUP(vin4_data, 12, _b), | |
4002 | VIN_DATA_PIN_GROUP(vin4_data, 16, _b), | |
4003 | SH_PFC_PIN_GROUP(vin4_data18_b), | |
4004 | VIN_DATA_PIN_GROUP(vin4_data, 20, _b), | |
4005 | VIN_DATA_PIN_GROUP(vin4_data, 24, _b), | |
4006 | SH_PFC_PIN_GROUP(vin4_sync), | |
4007 | SH_PFC_PIN_GROUP(vin4_field), | |
4008 | SH_PFC_PIN_GROUP(vin4_clkenb), | |
4009 | SH_PFC_PIN_GROUP(vin4_clk), | |
4010 | VIN_DATA_PIN_GROUP(vin5_data, 8, _a), | |
4011 | VIN_DATA_PIN_GROUP(vin5_data, 10, _a), | |
4012 | VIN_DATA_PIN_GROUP(vin5_data, 12, _a), | |
4013 | VIN_DATA_PIN_GROUP(vin5_data, 16, _a), | |
4014 | SH_PFC_PIN_GROUP(vin5_data8_b), | |
4015 | SH_PFC_PIN_GROUP(vin5_sync_a), | |
4016 | SH_PFC_PIN_GROUP(vin5_field_a), | |
4017 | SH_PFC_PIN_GROUP(vin5_clkenb_a), | |
4018 | SH_PFC_PIN_GROUP(vin5_clk_a), | |
4019 | SH_PFC_PIN_GROUP(vin5_clk_b), | |
4020 | }, | |
4021 | .automotive = { | |
8719ca81 MV |
4022 | SH_PFC_PIN_GROUP(drif0_ctrl_a), |
4023 | SH_PFC_PIN_GROUP(drif0_data0_a), | |
4024 | SH_PFC_PIN_GROUP(drif0_data1_a), | |
4025 | SH_PFC_PIN_GROUP(drif0_ctrl_b), | |
4026 | SH_PFC_PIN_GROUP(drif0_data0_b), | |
4027 | SH_PFC_PIN_GROUP(drif0_data1_b), | |
4028 | SH_PFC_PIN_GROUP(drif1_ctrl), | |
4029 | SH_PFC_PIN_GROUP(drif1_data0), | |
4030 | SH_PFC_PIN_GROUP(drif1_data1), | |
4031 | SH_PFC_PIN_GROUP(drif2_ctrl_a), | |
4032 | SH_PFC_PIN_GROUP(drif2_data0_a), | |
4033 | SH_PFC_PIN_GROUP(drif2_data1_a), | |
4034 | SH_PFC_PIN_GROUP(drif2_ctrl_b), | |
4035 | SH_PFC_PIN_GROUP(drif2_data0_b), | |
4036 | SH_PFC_PIN_GROUP(drif2_data1_b), | |
4037 | SH_PFC_PIN_GROUP(drif3_ctrl_a), | |
4038 | SH_PFC_PIN_GROUP(drif3_data0_a), | |
4039 | SH_PFC_PIN_GROUP(drif3_data1_a), | |
4040 | SH_PFC_PIN_GROUP(drif3_ctrl_b), | |
4041 | SH_PFC_PIN_GROUP(drif3_data0_b), | |
4042 | SH_PFC_PIN_GROUP(drif3_data1_b), | |
4043 | } | |
bf8d2dab MV |
4044 | }; |
4045 | ||
4046 | static const char * const audio_clk_groups[] = { | |
4047 | "audio_clk_a", | |
4048 | "audio_clk_b_a", | |
4049 | "audio_clk_b_b", | |
4050 | "audio_clk_b_c", | |
4051 | "audio_clk_c_a", | |
4052 | "audio_clk_c_b", | |
4053 | "audio_clk_c_c", | |
4054 | "audio_clkout_a", | |
4055 | "audio_clkout_b", | |
4056 | "audio_clkout1_a", | |
4057 | "audio_clkout1_b", | |
4058 | "audio_clkout1_c", | |
4059 | "audio_clkout2_a", | |
4060 | "audio_clkout2_b", | |
4061 | "audio_clkout2_c", | |
4062 | "audio_clkout3_a", | |
4063 | "audio_clkout3_b", | |
4064 | "audio_clkout3_c", | |
4065 | }; | |
4066 | ||
4067 | static const char * const avb_groups[] = { | |
4068 | "avb_link", | |
4069 | "avb_magic", | |
4070 | "avb_phy_int", | |
4071 | "avb_mii", | |
4072 | "avb_avtp_pps", | |
4073 | "avb_avtp_match_a", | |
4074 | "avb_avtp_capture_a", | |
4075 | }; | |
4076 | ||
4077 | static const char * const can0_groups[] = { | |
4078 | "can0_data", | |
4079 | }; | |
4080 | ||
4081 | static const char * const can1_groups[] = { | |
4082 | "can1_data", | |
4083 | }; | |
4084 | ||
4085 | static const char * const can_clk_groups[] = { | |
4086 | "can_clk", | |
4087 | }; | |
4088 | ||
4089 | static const char * const canfd0_groups[] = { | |
4090 | "canfd0_data", | |
4091 | }; | |
4092 | ||
4093 | static const char * const canfd1_groups[] = { | |
4094 | "canfd1_data", | |
4095 | }; | |
4096 | ||
4097 | static const char * const drif0_groups[] = { | |
4098 | "drif0_ctrl_a", | |
4099 | "drif0_data0_a", | |
4100 | "drif0_data1_a", | |
4101 | "drif0_ctrl_b", | |
4102 | "drif0_data0_b", | |
4103 | "drif0_data1_b", | |
4104 | }; | |
4105 | ||
4106 | static const char * const drif1_groups[] = { | |
4107 | "drif1_ctrl", | |
4108 | "drif1_data0", | |
4109 | "drif1_data1", | |
4110 | }; | |
4111 | ||
4112 | static const char * const drif2_groups[] = { | |
4113 | "drif2_ctrl_a", | |
4114 | "drif2_data0_a", | |
4115 | "drif2_data1_a", | |
4116 | "drif2_ctrl_b", | |
4117 | "drif2_data0_b", | |
4118 | "drif2_data1_b", | |
4119 | }; | |
4120 | ||
4121 | static const char * const drif3_groups[] = { | |
4122 | "drif3_ctrl_a", | |
4123 | "drif3_data0_a", | |
4124 | "drif3_data1_a", | |
4125 | "drif3_ctrl_b", | |
4126 | "drif3_data0_b", | |
4127 | "drif3_data1_b", | |
4128 | }; | |
4129 | ||
4130 | static const char * const du_groups[] = { | |
4131 | "du_rgb666", | |
4132 | "du_rgb888", | |
8719ca81 MV |
4133 | "du_clk_in_0", |
4134 | "du_clk_in_1", | |
bf8d2dab MV |
4135 | "du_clk_out_0", |
4136 | "du_sync", | |
8719ca81 | 4137 | "du_disp_cde", |
bf8d2dab MV |
4138 | "du_cde", |
4139 | "du_disp", | |
bf8d2dab MV |
4140 | }; |
4141 | ||
4142 | static const char * const hscif0_groups[] = { | |
4143 | "hscif0_data_a", | |
4144 | "hscif0_clk_a", | |
4145 | "hscif0_ctrl_a", | |
4146 | "hscif0_data_b", | |
4147 | "hscif0_clk_b", | |
4148 | }; | |
4149 | ||
4150 | static const char * const hscif1_groups[] = { | |
4151 | "hscif1_data_a", | |
4152 | "hscif1_clk_a", | |
4153 | "hscif1_data_b", | |
4154 | "hscif1_clk_b", | |
4155 | "hscif1_ctrl_b", | |
4156 | }; | |
4157 | ||
4158 | static const char * const hscif2_groups[] = { | |
4159 | "hscif2_data_a", | |
4160 | "hscif2_clk_a", | |
4161 | "hscif2_ctrl_a", | |
4162 | "hscif2_data_b", | |
4163 | }; | |
4164 | ||
4165 | static const char * const hscif3_groups[] = { | |
4166 | "hscif3_data_a", | |
4167 | "hscif3_data_b", | |
4168 | "hscif3_clk_b", | |
4169 | "hscif3_data_c", | |
4170 | "hscif3_clk_c", | |
4171 | "hscif3_ctrl_c", | |
4172 | "hscif3_data_d", | |
4173 | "hscif3_data_e", | |
4174 | "hscif3_ctrl_e", | |
4175 | }; | |
4176 | ||
4177 | static const char * const hscif4_groups[] = { | |
4178 | "hscif4_data_a", | |
4179 | "hscif4_clk_a", | |
4180 | "hscif4_ctrl_a", | |
4181 | "hscif4_data_b", | |
4182 | "hscif4_clk_b", | |
4183 | "hscif4_data_c", | |
4184 | "hscif4_data_d", | |
4185 | "hscif4_data_e", | |
4186 | }; | |
4187 | ||
4188 | static const char * const i2c1_groups[] = { | |
4189 | "i2c1_a", | |
4190 | "i2c1_b", | |
4191 | "i2c1_c", | |
4192 | "i2c1_d", | |
4193 | }; | |
4194 | ||
4195 | static const char * const i2c2_groups[] = { | |
4196 | "i2c2_a", | |
4197 | "i2c2_b", | |
4198 | "i2c2_c", | |
4199 | "i2c2_d", | |
4200 | "i2c2_e", | |
4201 | }; | |
4202 | ||
4203 | static const char * const i2c4_groups[] = { | |
4204 | "i2c4", | |
4205 | }; | |
4206 | ||
4207 | static const char * const i2c5_groups[] = { | |
4208 | "i2c5", | |
4209 | }; | |
4210 | ||
4211 | static const char * const i2c6_groups[] = { | |
4212 | "i2c6_a", | |
4213 | "i2c6_b", | |
4214 | }; | |
4215 | ||
4216 | static const char * const i2c7_groups[] = { | |
4217 | "i2c7_a", | |
4218 | "i2c7_b", | |
4219 | }; | |
4220 | ||
4221 | static const char * const intc_ex_groups[] = { | |
4222 | "intc_ex_irq0", | |
8719ca81 MV |
4223 | "intc_ex_irq1", |
4224 | "intc_ex_irq2", | |
4225 | "intc_ex_irq3", | |
4226 | "intc_ex_irq4", | |
4227 | "intc_ex_irq5", | |
bf8d2dab MV |
4228 | }; |
4229 | ||
4230 | static const char * const msiof0_groups[] = { | |
4231 | "msiof0_clk", | |
4232 | "msiof0_sync", | |
4233 | "msiof0_ss1", | |
4234 | "msiof0_ss2", | |
4235 | "msiof0_txd", | |
4236 | "msiof0_rxd", | |
4237 | }; | |
4238 | ||
4239 | static const char * const msiof1_groups[] = { | |
4240 | "msiof1_clk", | |
4241 | "msiof1_sync", | |
4242 | "msiof1_ss1", | |
4243 | "msiof1_ss2", | |
4244 | "msiof1_txd", | |
4245 | "msiof1_rxd", | |
4246 | }; | |
4247 | ||
4248 | static const char * const msiof2_groups[] = { | |
4249 | "msiof2_clk_a", | |
4250 | "msiof2_sync_a", | |
4251 | "msiof2_ss1_a", | |
4252 | "msiof2_ss2_a", | |
4253 | "msiof2_txd_a", | |
4254 | "msiof2_rxd_a", | |
4255 | "msiof2_clk_b", | |
4256 | "msiof2_sync_b", | |
4257 | "msiof2_ss1_b", | |
4258 | "msiof2_ss2_b", | |
4259 | "msiof2_txd_b", | |
4260 | "msiof2_rxd_b", | |
4261 | }; | |
4262 | ||
4263 | static const char * const msiof3_groups[] = { | |
4264 | "msiof3_clk_a", | |
4265 | "msiof3_sync_a", | |
4266 | "msiof3_ss1_a", | |
4267 | "msiof3_ss2_a", | |
4268 | "msiof3_txd_a", | |
4269 | "msiof3_rxd_a", | |
4270 | "msiof3_clk_b", | |
4271 | "msiof3_sync_b", | |
4272 | "msiof3_ss1_b", | |
4273 | "msiof3_txd_b", | |
4274 | "msiof3_rxd_b", | |
4275 | }; | |
4276 | ||
4277 | static const char * const pwm0_groups[] = { | |
4278 | "pwm0_a", | |
4279 | "pwm0_b", | |
4280 | }; | |
4281 | ||
4282 | static const char * const pwm1_groups[] = { | |
4283 | "pwm1_a", | |
4284 | "pwm1_b", | |
4285 | }; | |
4286 | ||
4287 | static const char * const pwm2_groups[] = { | |
4288 | "pwm2_a", | |
4289 | "pwm2_b", | |
4290 | "pwm2_c", | |
4291 | }; | |
4292 | ||
4293 | static const char * const pwm3_groups[] = { | |
4294 | "pwm3_a", | |
4295 | "pwm3_b", | |
4296 | "pwm3_c", | |
4297 | }; | |
4298 | ||
4299 | static const char * const pwm4_groups[] = { | |
4300 | "pwm4_a", | |
4301 | "pwm4_b", | |
4302 | }; | |
4303 | ||
4304 | static const char * const pwm5_groups[] = { | |
4305 | "pwm5_a", | |
4306 | "pwm5_b", | |
4307 | }; | |
4308 | ||
4309 | static const char * const pwm6_groups[] = { | |
4310 | "pwm6_a", | |
4311 | "pwm6_b", | |
4312 | }; | |
4313 | ||
4314 | static const char * const scif0_groups[] = { | |
4315 | "scif0_data_a", | |
4316 | "scif0_clk_a", | |
4317 | "scif0_ctrl_a", | |
4318 | "scif0_data_b", | |
4319 | "scif0_clk_b", | |
4320 | }; | |
4321 | ||
4322 | static const char * const scif1_groups[] = { | |
4323 | "scif1_data", | |
4324 | "scif1_clk", | |
4325 | "scif1_ctrl", | |
4326 | }; | |
4327 | ||
4328 | static const char * const scif2_groups[] = { | |
4329 | "scif2_data_a", | |
4330 | "scif2_clk_a", | |
4331 | "scif2_data_b", | |
4332 | }; | |
4333 | ||
4334 | static const char * const scif3_groups[] = { | |
4335 | "scif3_data_a", | |
4336 | "scif3_clk_a", | |
4337 | "scif3_ctrl_a", | |
4338 | "scif3_data_b", | |
4339 | "scif3_data_c", | |
4340 | "scif3_clk_c", | |
4341 | }; | |
4342 | ||
4343 | static const char * const scif4_groups[] = { | |
4344 | "scif4_data_a", | |
4345 | "scif4_clk_a", | |
4346 | "scif4_ctrl_a", | |
4347 | "scif4_data_b", | |
4348 | "scif4_clk_b", | |
4349 | "scif4_data_c", | |
4350 | "scif4_ctrl_c", | |
4351 | }; | |
4352 | ||
4353 | static const char * const scif5_groups[] = { | |
4354 | "scif5_data_a", | |
4355 | "scif5_clk_a", | |
4356 | "scif5_data_b", | |
4357 | "scif5_data_c", | |
4358 | }; | |
4359 | ||
4360 | static const char * const scif_clk_groups[] = { | |
4361 | "scif_clk_a", | |
4362 | "scif_clk_b", | |
4363 | }; | |
4364 | ||
4365 | static const char * const sdhi0_groups[] = { | |
4366 | "sdhi0_data1", | |
4367 | "sdhi0_data4", | |
4368 | "sdhi0_ctrl", | |
4369 | "sdhi0_cd", | |
4370 | "sdhi0_wp", | |
4371 | }; | |
4372 | ||
4373 | static const char * const sdhi1_groups[] = { | |
4374 | "sdhi1_data1", | |
4375 | "sdhi1_data4", | |
4376 | "sdhi1_ctrl", | |
4377 | "sdhi1_cd", | |
4378 | "sdhi1_wp", | |
4379 | }; | |
4380 | ||
4381 | static const char * const sdhi3_groups[] = { | |
4382 | "sdhi3_data1", | |
4383 | "sdhi3_data4", | |
4384 | "sdhi3_data8", | |
4385 | "sdhi3_ctrl", | |
4386 | "sdhi3_cd", | |
4387 | "sdhi3_wp", | |
4388 | "sdhi3_ds", | |
4389 | }; | |
4390 | ||
4391 | static const char * const ssi_groups[] = { | |
4392 | "ssi0_data", | |
4393 | "ssi01239_ctrl", | |
4394 | "ssi1_data", | |
4395 | "ssi1_ctrl", | |
4396 | "ssi2_data", | |
4397 | "ssi2_ctrl_a", | |
4398 | "ssi2_ctrl_b", | |
4399 | "ssi3_data", | |
4400 | "ssi349_ctrl", | |
4401 | "ssi4_data", | |
4402 | "ssi4_ctrl", | |
4403 | "ssi5_data", | |
4404 | "ssi5_ctrl", | |
4405 | "ssi6_data", | |
4406 | "ssi6_ctrl", | |
4407 | "ssi7_data", | |
4408 | "ssi78_ctrl", | |
4409 | "ssi8_data", | |
4410 | "ssi9_data", | |
4411 | "ssi9_ctrl_a", | |
4412 | "ssi9_ctrl_b", | |
4413 | }; | |
4414 | ||
4415 | static const char * const tmu_groups[] = { | |
4416 | "tmu_tclk1_a", | |
4417 | "tmu_tclk1_b", | |
4418 | "tmu_tclk2_a", | |
4419 | "tmu_tclk2_b", | |
4420 | }; | |
4421 | ||
4422 | static const char * const usb0_groups[] = { | |
4423 | "usb0_a", | |
4424 | "usb0_b", | |
4425 | "usb0_id", | |
4426 | }; | |
4427 | ||
4428 | static const char * const usb30_groups[] = { | |
4429 | "usb30", | |
4430 | "usb30_id", | |
4431 | }; | |
4432 | ||
4433 | static const char * const vin4_groups[] = { | |
4434 | "vin4_data8_a", | |
4435 | "vin4_data10_a", | |
4436 | "vin4_data12_a", | |
4437 | "vin4_data16_a", | |
8719ca81 | 4438 | "vin4_data18_a", |
bf8d2dab MV |
4439 | "vin4_data20_a", |
4440 | "vin4_data24_a", | |
4441 | "vin4_data8_b", | |
4442 | "vin4_data10_b", | |
4443 | "vin4_data12_b", | |
4444 | "vin4_data16_b", | |
8719ca81 | 4445 | "vin4_data18_b", |
bf8d2dab MV |
4446 | "vin4_data20_b", |
4447 | "vin4_data24_b", | |
bf8d2dab MV |
4448 | "vin4_sync", |
4449 | "vin4_field", | |
4450 | "vin4_clkenb", | |
4451 | "vin4_clk", | |
4452 | }; | |
4453 | ||
4454 | static const char * const vin5_groups[] = { | |
4455 | "vin5_data8_a", | |
bf8d2dab MV |
4456 | "vin5_data10_a", |
4457 | "vin5_data12_a", | |
4458 | "vin5_data16_a", | |
4459 | "vin5_data8_b", | |
4460 | "vin5_sync_a", | |
4461 | "vin5_field_a", | |
4462 | "vin5_clkenb_a", | |
4463 | "vin5_clk_a", | |
4464 | "vin5_clk_b", | |
cb13e46a MV |
4465 | }; |
4466 | ||
8719ca81 | 4467 | static const struct { |
7f2e60f1 ER |
4468 | struct sh_pfc_function common[47]; |
4469 | struct sh_pfc_function automotive[4]; | |
8719ca81 MV |
4470 | } pinmux_functions = { |
4471 | .common = { | |
4472 | SH_PFC_FUNCTION(audio_clk), | |
4473 | SH_PFC_FUNCTION(avb), | |
4474 | SH_PFC_FUNCTION(can0), | |
4475 | SH_PFC_FUNCTION(can1), | |
4476 | SH_PFC_FUNCTION(can_clk), | |
7f2e60f1 ER |
4477 | SH_PFC_FUNCTION(canfd0), |
4478 | SH_PFC_FUNCTION(canfd1), | |
8719ca81 MV |
4479 | SH_PFC_FUNCTION(du), |
4480 | SH_PFC_FUNCTION(hscif0), | |
4481 | SH_PFC_FUNCTION(hscif1), | |
4482 | SH_PFC_FUNCTION(hscif2), | |
4483 | SH_PFC_FUNCTION(hscif3), | |
4484 | SH_PFC_FUNCTION(hscif4), | |
4485 | SH_PFC_FUNCTION(i2c1), | |
4486 | SH_PFC_FUNCTION(i2c2), | |
4487 | SH_PFC_FUNCTION(i2c4), | |
4488 | SH_PFC_FUNCTION(i2c5), | |
4489 | SH_PFC_FUNCTION(i2c6), | |
4490 | SH_PFC_FUNCTION(i2c7), | |
4491 | SH_PFC_FUNCTION(intc_ex), | |
4492 | SH_PFC_FUNCTION(msiof0), | |
4493 | SH_PFC_FUNCTION(msiof1), | |
4494 | SH_PFC_FUNCTION(msiof2), | |
4495 | SH_PFC_FUNCTION(msiof3), | |
4496 | SH_PFC_FUNCTION(pwm0), | |
4497 | SH_PFC_FUNCTION(pwm1), | |
4498 | SH_PFC_FUNCTION(pwm2), | |
4499 | SH_PFC_FUNCTION(pwm3), | |
4500 | SH_PFC_FUNCTION(pwm4), | |
4501 | SH_PFC_FUNCTION(pwm5), | |
4502 | SH_PFC_FUNCTION(pwm6), | |
4503 | SH_PFC_FUNCTION(scif0), | |
4504 | SH_PFC_FUNCTION(scif1), | |
4505 | SH_PFC_FUNCTION(scif2), | |
4506 | SH_PFC_FUNCTION(scif3), | |
4507 | SH_PFC_FUNCTION(scif4), | |
4508 | SH_PFC_FUNCTION(scif5), | |
4509 | SH_PFC_FUNCTION(scif_clk), | |
4510 | SH_PFC_FUNCTION(sdhi0), | |
4511 | SH_PFC_FUNCTION(sdhi1), | |
4512 | SH_PFC_FUNCTION(sdhi3), | |
4513 | SH_PFC_FUNCTION(ssi), | |
4514 | SH_PFC_FUNCTION(tmu), | |
4515 | SH_PFC_FUNCTION(usb0), | |
4516 | SH_PFC_FUNCTION(usb30), | |
4517 | SH_PFC_FUNCTION(vin4), | |
4518 | SH_PFC_FUNCTION(vin5), | |
4519 | }, | |
4520 | .automotive = { | |
8719ca81 MV |
4521 | SH_PFC_FUNCTION(drif0), |
4522 | SH_PFC_FUNCTION(drif1), | |
4523 | SH_PFC_FUNCTION(drif2), | |
4524 | SH_PFC_FUNCTION(drif3), | |
4525 | } | |
cb13e46a MV |
4526 | }; |
4527 | ||
4528 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
4529 | #define F_(x, y) FN_##y | |
4530 | #define FM(x) FN_##x | |
7f2e60f1 | 4531 | { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( |
cb13e46a MV |
4532 | 0, 0, |
4533 | 0, 0, | |
4534 | 0, 0, | |
4535 | 0, 0, | |
4536 | 0, 0, | |
4537 | 0, 0, | |
4538 | 0, 0, | |
4539 | 0, 0, | |
4540 | 0, 0, | |
4541 | 0, 0, | |
4542 | 0, 0, | |
4543 | 0, 0, | |
4544 | 0, 0, | |
4545 | 0, 0, | |
4546 | GP_0_17_FN, GPSR0_17, | |
4547 | GP_0_16_FN, GPSR0_16, | |
4548 | GP_0_15_FN, GPSR0_15, | |
4549 | GP_0_14_FN, GPSR0_14, | |
4550 | GP_0_13_FN, GPSR0_13, | |
4551 | GP_0_12_FN, GPSR0_12, | |
4552 | GP_0_11_FN, GPSR0_11, | |
4553 | GP_0_10_FN, GPSR0_10, | |
4554 | GP_0_9_FN, GPSR0_9, | |
4555 | GP_0_8_FN, GPSR0_8, | |
4556 | GP_0_7_FN, GPSR0_7, | |
4557 | GP_0_6_FN, GPSR0_6, | |
4558 | GP_0_5_FN, GPSR0_5, | |
4559 | GP_0_4_FN, GPSR0_4, | |
4560 | GP_0_3_FN, GPSR0_3, | |
4561 | GP_0_2_FN, GPSR0_2, | |
4562 | GP_0_1_FN, GPSR0_1, | |
7f2e60f1 | 4563 | GP_0_0_FN, GPSR0_0, )) |
cb13e46a | 4564 | }, |
7f2e60f1 | 4565 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( |
cb13e46a MV |
4566 | 0, 0, |
4567 | 0, 0, | |
4568 | 0, 0, | |
4569 | 0, 0, | |
4570 | 0, 0, | |
4571 | 0, 0, | |
4572 | 0, 0, | |
4573 | 0, 0, | |
4574 | 0, 0, | |
4575 | GP_1_22_FN, GPSR1_22, | |
4576 | GP_1_21_FN, GPSR1_21, | |
4577 | GP_1_20_FN, GPSR1_20, | |
4578 | GP_1_19_FN, GPSR1_19, | |
4579 | GP_1_18_FN, GPSR1_18, | |
4580 | GP_1_17_FN, GPSR1_17, | |
4581 | GP_1_16_FN, GPSR1_16, | |
4582 | GP_1_15_FN, GPSR1_15, | |
4583 | GP_1_14_FN, GPSR1_14, | |
4584 | GP_1_13_FN, GPSR1_13, | |
4585 | GP_1_12_FN, GPSR1_12, | |
4586 | GP_1_11_FN, GPSR1_11, | |
4587 | GP_1_10_FN, GPSR1_10, | |
4588 | GP_1_9_FN, GPSR1_9, | |
4589 | GP_1_8_FN, GPSR1_8, | |
4590 | GP_1_7_FN, GPSR1_7, | |
4591 | GP_1_6_FN, GPSR1_6, | |
4592 | GP_1_5_FN, GPSR1_5, | |
4593 | GP_1_4_FN, GPSR1_4, | |
4594 | GP_1_3_FN, GPSR1_3, | |
4595 | GP_1_2_FN, GPSR1_2, | |
4596 | GP_1_1_FN, GPSR1_1, | |
7f2e60f1 | 4597 | GP_1_0_FN, GPSR1_0, )) |
cb13e46a | 4598 | }, |
7f2e60f1 | 4599 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( |
cb13e46a MV |
4600 | 0, 0, |
4601 | 0, 0, | |
4602 | 0, 0, | |
4603 | 0, 0, | |
4604 | 0, 0, | |
4605 | 0, 0, | |
4606 | GP_2_25_FN, GPSR2_25, | |
4607 | GP_2_24_FN, GPSR2_24, | |
4608 | GP_2_23_FN, GPSR2_23, | |
4609 | GP_2_22_FN, GPSR2_22, | |
4610 | GP_2_21_FN, GPSR2_21, | |
4611 | GP_2_20_FN, GPSR2_20, | |
4612 | GP_2_19_FN, GPSR2_19, | |
4613 | GP_2_18_FN, GPSR2_18, | |
4614 | GP_2_17_FN, GPSR2_17, | |
4615 | GP_2_16_FN, GPSR2_16, | |
4616 | GP_2_15_FN, GPSR2_15, | |
4617 | GP_2_14_FN, GPSR2_14, | |
4618 | GP_2_13_FN, GPSR2_13, | |
4619 | GP_2_12_FN, GPSR2_12, | |
4620 | GP_2_11_FN, GPSR2_11, | |
4621 | GP_2_10_FN, GPSR2_10, | |
4622 | GP_2_9_FN, GPSR2_9, | |
4623 | GP_2_8_FN, GPSR2_8, | |
4624 | GP_2_7_FN, GPSR2_7, | |
4625 | GP_2_6_FN, GPSR2_6, | |
4626 | GP_2_5_FN, GPSR2_5, | |
4627 | GP_2_4_FN, GPSR2_4, | |
4628 | GP_2_3_FN, GPSR2_3, | |
4629 | GP_2_2_FN, GPSR2_2, | |
4630 | GP_2_1_FN, GPSR2_1, | |
7f2e60f1 | 4631 | GP_2_0_FN, GPSR2_0, )) |
cb13e46a | 4632 | }, |
7f2e60f1 | 4633 | { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( |
cb13e46a MV |
4634 | 0, 0, |
4635 | 0, 0, | |
4636 | 0, 0, | |
4637 | 0, 0, | |
4638 | 0, 0, | |
4639 | 0, 0, | |
4640 | 0, 0, | |
4641 | 0, 0, | |
4642 | 0, 0, | |
4643 | 0, 0, | |
4644 | 0, 0, | |
4645 | 0, 0, | |
4646 | 0, 0, | |
4647 | 0, 0, | |
4648 | 0, 0, | |
4649 | 0, 0, | |
4650 | GP_3_15_FN, GPSR3_15, | |
4651 | GP_3_14_FN, GPSR3_14, | |
4652 | GP_3_13_FN, GPSR3_13, | |
4653 | GP_3_12_FN, GPSR3_12, | |
4654 | GP_3_11_FN, GPSR3_11, | |
4655 | GP_3_10_FN, GPSR3_10, | |
4656 | GP_3_9_FN, GPSR3_9, | |
4657 | GP_3_8_FN, GPSR3_8, | |
4658 | GP_3_7_FN, GPSR3_7, | |
4659 | GP_3_6_FN, GPSR3_6, | |
4660 | GP_3_5_FN, GPSR3_5, | |
4661 | GP_3_4_FN, GPSR3_4, | |
4662 | GP_3_3_FN, GPSR3_3, | |
4663 | GP_3_2_FN, GPSR3_2, | |
4664 | GP_3_1_FN, GPSR3_1, | |
7f2e60f1 | 4665 | GP_3_0_FN, GPSR3_0, )) |
cb13e46a | 4666 | }, |
7f2e60f1 | 4667 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( |
cb13e46a MV |
4668 | 0, 0, |
4669 | 0, 0, | |
4670 | 0, 0, | |
4671 | 0, 0, | |
4672 | 0, 0, | |
4673 | 0, 0, | |
4674 | 0, 0, | |
4675 | 0, 0, | |
4676 | 0, 0, | |
4677 | 0, 0, | |
4678 | 0, 0, | |
4679 | 0, 0, | |
4680 | 0, 0, | |
4681 | 0, 0, | |
4682 | 0, 0, | |
4683 | 0, 0, | |
4684 | 0, 0, | |
4685 | 0, 0, | |
4686 | 0, 0, | |
4687 | 0, 0, | |
4688 | 0, 0, | |
4689 | GP_4_10_FN, GPSR4_10, | |
4690 | GP_4_9_FN, GPSR4_9, | |
4691 | GP_4_8_FN, GPSR4_8, | |
4692 | GP_4_7_FN, GPSR4_7, | |
4693 | GP_4_6_FN, GPSR4_6, | |
4694 | GP_4_5_FN, GPSR4_5, | |
4695 | GP_4_4_FN, GPSR4_4, | |
4696 | GP_4_3_FN, GPSR4_3, | |
4697 | GP_4_2_FN, GPSR4_2, | |
4698 | GP_4_1_FN, GPSR4_1, | |
7f2e60f1 | 4699 | GP_4_0_FN, GPSR4_0, )) |
cb13e46a | 4700 | }, |
7f2e60f1 | 4701 | { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( |
cb13e46a MV |
4702 | 0, 0, |
4703 | 0, 0, | |
4704 | 0, 0, | |
4705 | 0, 0, | |
4706 | 0, 0, | |
4707 | 0, 0, | |
4708 | 0, 0, | |
4709 | 0, 0, | |
4710 | 0, 0, | |
4711 | 0, 0, | |
4712 | 0, 0, | |
4713 | 0, 0, | |
4714 | GP_5_19_FN, GPSR5_19, | |
4715 | GP_5_18_FN, GPSR5_18, | |
4716 | GP_5_17_FN, GPSR5_17, | |
4717 | GP_5_16_FN, GPSR5_16, | |
4718 | GP_5_15_FN, GPSR5_15, | |
4719 | GP_5_14_FN, GPSR5_14, | |
4720 | GP_5_13_FN, GPSR5_13, | |
4721 | GP_5_12_FN, GPSR5_12, | |
4722 | GP_5_11_FN, GPSR5_11, | |
4723 | GP_5_10_FN, GPSR5_10, | |
4724 | GP_5_9_FN, GPSR5_9, | |
4725 | GP_5_8_FN, GPSR5_8, | |
4726 | GP_5_7_FN, GPSR5_7, | |
4727 | GP_5_6_FN, GPSR5_6, | |
4728 | GP_5_5_FN, GPSR5_5, | |
4729 | GP_5_4_FN, GPSR5_4, | |
4730 | GP_5_3_FN, GPSR5_3, | |
4731 | GP_5_2_FN, GPSR5_2, | |
4732 | GP_5_1_FN, GPSR5_1, | |
7f2e60f1 | 4733 | GP_5_0_FN, GPSR5_0, )) |
cb13e46a | 4734 | }, |
7f2e60f1 | 4735 | { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( |
cb13e46a MV |
4736 | 0, 0, |
4737 | 0, 0, | |
4738 | 0, 0, | |
4739 | 0, 0, | |
4740 | 0, 0, | |
4741 | 0, 0, | |
4742 | 0, 0, | |
4743 | 0, 0, | |
4744 | 0, 0, | |
4745 | 0, 0, | |
4746 | 0, 0, | |
4747 | 0, 0, | |
4748 | 0, 0, | |
4749 | 0, 0, | |
4750 | GP_6_17_FN, GPSR6_17, | |
4751 | GP_6_16_FN, GPSR6_16, | |
4752 | GP_6_15_FN, GPSR6_15, | |
4753 | GP_6_14_FN, GPSR6_14, | |
4754 | GP_6_13_FN, GPSR6_13, | |
4755 | GP_6_12_FN, GPSR6_12, | |
4756 | GP_6_11_FN, GPSR6_11, | |
4757 | GP_6_10_FN, GPSR6_10, | |
4758 | GP_6_9_FN, GPSR6_9, | |
4759 | GP_6_8_FN, GPSR6_8, | |
4760 | GP_6_7_FN, GPSR6_7, | |
4761 | GP_6_6_FN, GPSR6_6, | |
4762 | GP_6_5_FN, GPSR6_5, | |
4763 | GP_6_4_FN, GPSR6_4, | |
4764 | GP_6_3_FN, GPSR6_3, | |
4765 | GP_6_2_FN, GPSR6_2, | |
4766 | GP_6_1_FN, GPSR6_1, | |
7f2e60f1 | 4767 | GP_6_0_FN, GPSR6_0, )) |
cb13e46a MV |
4768 | }, |
4769 | #undef F_ | |
4770 | #undef FM | |
4771 | ||
4772 | #define F_(x, y) x, | |
4773 | #define FM(x) FN_##x, | |
7f2e60f1 | 4774 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( |
cb13e46a MV |
4775 | IP0_31_28 |
4776 | IP0_27_24 | |
4777 | IP0_23_20 | |
4778 | IP0_19_16 | |
4779 | IP0_15_12 | |
4780 | IP0_11_8 | |
4781 | IP0_7_4 | |
7f2e60f1 | 4782 | IP0_3_0 )) |
cb13e46a | 4783 | }, |
7f2e60f1 | 4784 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( |
cb13e46a MV |
4785 | IP1_31_28 |
4786 | IP1_27_24 | |
4787 | IP1_23_20 | |
4788 | IP1_19_16 | |
4789 | IP1_15_12 | |
4790 | IP1_11_8 | |
4791 | IP1_7_4 | |
7f2e60f1 | 4792 | IP1_3_0 )) |
cb13e46a | 4793 | }, |
7f2e60f1 | 4794 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( |
cb13e46a MV |
4795 | IP2_31_28 |
4796 | IP2_27_24 | |
4797 | IP2_23_20 | |
4798 | IP2_19_16 | |
4799 | IP2_15_12 | |
4800 | IP2_11_8 | |
4801 | IP2_7_4 | |
7f2e60f1 | 4802 | IP2_3_0 )) |
cb13e46a | 4803 | }, |
7f2e60f1 | 4804 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( |
cb13e46a MV |
4805 | IP3_31_28 |
4806 | IP3_27_24 | |
4807 | IP3_23_20 | |
4808 | IP3_19_16 | |
4809 | IP3_15_12 | |
4810 | IP3_11_8 | |
4811 | IP3_7_4 | |
7f2e60f1 | 4812 | IP3_3_0 )) |
cb13e46a | 4813 | }, |
7f2e60f1 | 4814 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( |
cb13e46a MV |
4815 | IP4_31_28 |
4816 | IP4_27_24 | |
4817 | IP4_23_20 | |
4818 | IP4_19_16 | |
4819 | IP4_15_12 | |
4820 | IP4_11_8 | |
4821 | IP4_7_4 | |
7f2e60f1 | 4822 | IP4_3_0 )) |
cb13e46a | 4823 | }, |
7f2e60f1 | 4824 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( |
cb13e46a MV |
4825 | IP5_31_28 |
4826 | IP5_27_24 | |
4827 | IP5_23_20 | |
4828 | IP5_19_16 | |
4829 | IP5_15_12 | |
4830 | IP5_11_8 | |
4831 | IP5_7_4 | |
7f2e60f1 | 4832 | IP5_3_0 )) |
cb13e46a | 4833 | }, |
7f2e60f1 | 4834 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( |
cb13e46a MV |
4835 | IP6_31_28 |
4836 | IP6_27_24 | |
4837 | IP6_23_20 | |
4838 | IP6_19_16 | |
4839 | IP6_15_12 | |
4840 | IP6_11_8 | |
4841 | IP6_7_4 | |
7f2e60f1 | 4842 | IP6_3_0 )) |
cb13e46a | 4843 | }, |
7f2e60f1 | 4844 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( |
cb13e46a MV |
4845 | IP7_31_28 |
4846 | IP7_27_24 | |
4847 | IP7_23_20 | |
4848 | IP7_19_16 | |
4849 | IP7_15_12 | |
4850 | IP7_11_8 | |
4851 | IP7_7_4 | |
7f2e60f1 | 4852 | IP7_3_0 )) |
cb13e46a | 4853 | }, |
7f2e60f1 | 4854 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( |
cb13e46a MV |
4855 | IP8_31_28 |
4856 | IP8_27_24 | |
4857 | IP8_23_20 | |
4858 | IP8_19_16 | |
4859 | IP8_15_12 | |
4860 | IP8_11_8 | |
4861 | IP8_7_4 | |
7f2e60f1 | 4862 | IP8_3_0 )) |
cb13e46a | 4863 | }, |
7f2e60f1 | 4864 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( |
cb13e46a MV |
4865 | IP9_31_28 |
4866 | IP9_27_24 | |
4867 | IP9_23_20 | |
4868 | IP9_19_16 | |
4869 | IP9_15_12 | |
4870 | IP9_11_8 | |
4871 | IP9_7_4 | |
7f2e60f1 | 4872 | IP9_3_0 )) |
cb13e46a | 4873 | }, |
7f2e60f1 | 4874 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( |
cb13e46a MV |
4875 | IP10_31_28 |
4876 | IP10_27_24 | |
4877 | IP10_23_20 | |
4878 | IP10_19_16 | |
4879 | IP10_15_12 | |
4880 | IP10_11_8 | |
4881 | IP10_7_4 | |
7f2e60f1 | 4882 | IP10_3_0 )) |
cb13e46a | 4883 | }, |
7f2e60f1 | 4884 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( |
cb13e46a MV |
4885 | IP11_31_28 |
4886 | IP11_27_24 | |
4887 | IP11_23_20 | |
4888 | IP11_19_16 | |
4889 | IP11_15_12 | |
4890 | IP11_11_8 | |
4891 | IP11_7_4 | |
7f2e60f1 | 4892 | IP11_3_0 )) |
cb13e46a | 4893 | }, |
7f2e60f1 | 4894 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( |
cb13e46a MV |
4895 | IP12_31_28 |
4896 | IP12_27_24 | |
4897 | IP12_23_20 | |
4898 | IP12_19_16 | |
4899 | IP12_15_12 | |
4900 | IP12_11_8 | |
4901 | IP12_7_4 | |
7f2e60f1 | 4902 | IP12_3_0 )) |
cb13e46a | 4903 | }, |
7f2e60f1 | 4904 | { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( |
cb13e46a MV |
4905 | IP13_31_28 |
4906 | IP13_27_24 | |
4907 | IP13_23_20 | |
4908 | IP13_19_16 | |
4909 | IP13_15_12 | |
4910 | IP13_11_8 | |
4911 | IP13_7_4 | |
7f2e60f1 | 4912 | IP13_3_0 )) |
cb13e46a | 4913 | }, |
7f2e60f1 | 4914 | { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( |
cb13e46a MV |
4915 | IP14_31_28 |
4916 | IP14_27_24 | |
4917 | IP14_23_20 | |
4918 | IP14_19_16 | |
4919 | IP14_15_12 | |
4920 | IP14_11_8 | |
4921 | IP14_7_4 | |
7f2e60f1 | 4922 | IP14_3_0 )) |
cb13e46a | 4923 | }, |
7f2e60f1 | 4924 | { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( |
cb13e46a MV |
4925 | IP15_31_28 |
4926 | IP15_27_24 | |
4927 | IP15_23_20 | |
4928 | IP15_19_16 | |
4929 | IP15_15_12 | |
4930 | IP15_11_8 | |
4931 | IP15_7_4 | |
7f2e60f1 | 4932 | IP15_3_0 )) |
cb13e46a MV |
4933 | }, |
4934 | #undef F_ | |
4935 | #undef FM | |
4936 | ||
4937 | #define F_(x, y) x, | |
4938 | #define FM(x) FN_##x, | |
4939 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, | |
7f2e60f1 ER |
4940 | GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, |
4941 | 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), | |
4942 | GROUP( | |
cb13e46a MV |
4943 | /* RESERVED 31 */ |
4944 | 0, 0, | |
4945 | MOD_SEL0_30_29 | |
4946 | MOD_SEL0_28 | |
4947 | MOD_SEL0_27_26 | |
4948 | MOD_SEL0_25 | |
4949 | MOD_SEL0_24 | |
4950 | MOD_SEL0_23 | |
4951 | MOD_SEL0_22 | |
4952 | MOD_SEL0_21_20 | |
4953 | MOD_SEL0_19_18_17 | |
4954 | MOD_SEL0_16 | |
4955 | MOD_SEL0_15 | |
4956 | MOD_SEL0_14 | |
4957 | MOD_SEL0_13_12 | |
4958 | MOD_SEL0_11_10 | |
4959 | MOD_SEL0_9 | |
4960 | MOD_SEL0_8 | |
4961 | MOD_SEL0_7 | |
4962 | MOD_SEL0_6_5 | |
4963 | MOD_SEL0_4 | |
4964 | MOD_SEL0_3 | |
4965 | MOD_SEL0_2 | |
7f2e60f1 | 4966 | MOD_SEL0_1_0 )) |
cb13e46a MV |
4967 | }, |
4968 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, | |
7f2e60f1 ER |
4969 | GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, |
4970 | 2, 2, 2, 1, 1, 2, 1, 4), | |
4971 | GROUP( | |
4972 | /* RESERVED 31, 30 */ | |
4973 | 0, 0, 0, 0, | |
cb13e46a MV |
4974 | MOD_SEL1_29 |
4975 | MOD_SEL1_28 | |
4976 | /* RESERVED 27 */ | |
4977 | 0, 0, | |
4978 | MOD_SEL1_26 | |
4979 | MOD_SEL1_25 | |
4980 | MOD_SEL1_24_23_22 | |
4981 | MOD_SEL1_21_20_19 | |
4982 | MOD_SEL1_18 | |
4983 | MOD_SEL1_17 | |
4984 | MOD_SEL1_16 | |
4985 | MOD_SEL1_15 | |
4986 | MOD_SEL1_14_13 | |
4987 | MOD_SEL1_12_11 | |
4988 | MOD_SEL1_10_9 | |
4989 | MOD_SEL1_8 | |
4990 | MOD_SEL1_7 | |
4991 | MOD_SEL1_6_5 | |
4992 | MOD_SEL1_4 | |
4993 | /* RESERVED 3, 2, 1, 0 */ | |
7f2e60f1 | 4994 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) |
cb13e46a MV |
4995 | }, |
4996 | { }, | |
4997 | }; | |
4998 | ||
5dbdd3a6 | 4999 | enum ioctrl_regs { |
7f2e60f1 ER |
5000 | POCCTRL0, |
5001 | TDSELCTRL, | |
5dbdd3a6 MV |
5002 | }; |
5003 | ||
5004 | static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { | |
7f2e60f1 ER |
5005 | [POCCTRL0] = { 0xe6060380, }, |
5006 | [TDSELCTRL] = { 0xe60603c0, }, | |
5dbdd3a6 MV |
5007 | { /* sentinel */ }, |
5008 | }; | |
5009 | ||
8719ca81 MV |
5010 | static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, |
5011 | u32 *pocctrl) | |
5dbdd3a6 MV |
5012 | { |
5013 | int bit = -EINVAL; | |
5014 | ||
7f2e60f1 | 5015 | *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; |
5dbdd3a6 MV |
5016 | |
5017 | if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) | |
5018 | bit = pin & 0x1f; | |
5019 | ||
5020 | if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10)) | |
5021 | bit = (pin & 0x1f) + 19; | |
5022 | ||
5023 | return bit; | |
5024 | } | |
5025 | ||
8719ca81 MV |
5026 | static const struct pinmux_bias_reg pinmux_bias_regs[] = { |
5027 | { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { | |
5028 | [0] = RCAR_GP_PIN(2, 23), /* RD# */ | |
5029 | [1] = RCAR_GP_PIN(2, 22), /* BS# */ | |
5030 | [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */ | |
5031 | [3] = PIN_NUMBER('P', 5), /* AVB_MDC */ | |
5032 | [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */ | |
5033 | [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */ | |
5034 | [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */ | |
5035 | [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */ | |
5036 | [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */ | |
5037 | [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */ | |
5038 | [10] = PIN_NUMBER('N', 1), /* AVB_TXC */ | |
5039 | [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */ | |
5040 | [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */ | |
5041 | [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */ | |
5042 | [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */ | |
5043 | [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */ | |
5044 | [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */ | |
5045 | [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */ | |
5046 | [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */ | |
5047 | [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */ | |
5048 | [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */ | |
5049 | [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */ | |
5050 | [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */ | |
5051 | [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */ | |
5052 | [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */ | |
5053 | [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */ | |
5054 | [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */ | |
5055 | [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */ | |
5056 | [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */ | |
5057 | [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */ | |
5058 | [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */ | |
5059 | [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */ | |
5060 | } }, | |
5061 | { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { | |
5062 | [0] = RCAR_GP_PIN(0, 4), /* D4 */ | |
5063 | [1] = RCAR_GP_PIN(0, 3), /* D3 */ | |
5064 | [2] = RCAR_GP_PIN(0, 2), /* D2 */ | |
5065 | [3] = RCAR_GP_PIN(0, 1), /* D1 */ | |
5066 | [4] = RCAR_GP_PIN(0, 0), /* D0 */ | |
5067 | [5] = RCAR_GP_PIN(1, 22), /* WE0# */ | |
5068 | [6] = RCAR_GP_PIN(1, 21), /* CS0# */ | |
5069 | [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */ | |
5070 | [8] = RCAR_GP_PIN(1, 19), /* A19 */ | |
5071 | [9] = RCAR_GP_PIN(1, 18), /* A18 */ | |
5072 | [10] = RCAR_GP_PIN(1, 17), /* A17 */ | |
5073 | [11] = RCAR_GP_PIN(1, 16), /* A16 */ | |
5074 | [12] = RCAR_GP_PIN(1, 15), /* A15 */ | |
5075 | [13] = RCAR_GP_PIN(1, 14), /* A14 */ | |
5076 | [14] = RCAR_GP_PIN(1, 13), /* A13 */ | |
5077 | [15] = RCAR_GP_PIN(1, 12), /* A12 */ | |
5078 | [16] = RCAR_GP_PIN(1, 11), /* A11 */ | |
5079 | [17] = RCAR_GP_PIN(1, 10), /* A10 */ | |
5080 | [18] = RCAR_GP_PIN(1, 9), /* A9 */ | |
5081 | [19] = RCAR_GP_PIN(1, 8), /* A8 */ | |
5082 | [20] = RCAR_GP_PIN(1, 7), /* A7 */ | |
5083 | [21] = RCAR_GP_PIN(1, 6), /* A6 */ | |
5084 | [22] = RCAR_GP_PIN(1, 5), /* A5 */ | |
5085 | [23] = RCAR_GP_PIN(1, 4), /* A4 */ | |
5086 | [24] = RCAR_GP_PIN(1, 3), /* A3 */ | |
5087 | [25] = RCAR_GP_PIN(1, 2), /* A2 */ | |
5088 | [26] = RCAR_GP_PIN(1, 1), /* A1 */ | |
5089 | [27] = RCAR_GP_PIN(1, 0), /* A0 */ | |
5090 | [28] = PIN_NONE, | |
5091 | [29] = PIN_NONE, | |
5092 | [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ | |
5093 | [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ | |
5094 | } }, | |
5095 | { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { | |
5096 | [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ | |
5097 | [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ | |
5098 | [2] = PIN_NUMBER('H', 1), /* ASEBRK */ | |
5099 | [3] = PIN_NONE, | |
5100 | [4] = PIN_NUMBER('G', 2), /* TDI */ | |
5101 | [5] = PIN_NUMBER('F', 3), /* TMS */ | |
5102 | [6] = PIN_NUMBER('F', 4), /* TCK */ | |
5103 | [7] = PIN_NUMBER('F', 1), /* TRST# */ | |
5104 | [8] = PIN_NONE, | |
5105 | [9] = PIN_NONE, | |
5106 | [10] = PIN_NONE, | |
5107 | [11] = PIN_NONE, | |
5108 | [12] = PIN_NONE, | |
5109 | [13] = PIN_NONE, | |
5110 | [14] = PIN_NONE, | |
5111 | [15] = PIN_NUMBER('G', 3), /* FSCLKST# */ | |
5112 | [16] = RCAR_GP_PIN(0, 17), /* SDA4 */ | |
5113 | [17] = RCAR_GP_PIN(0, 16), /* SCL4 */ | |
5114 | [18] = PIN_NONE, | |
5115 | [19] = PIN_NONE, | |
5116 | [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */ | |
5117 | [21] = RCAR_GP_PIN(0, 15), /* D15 */ | |
5118 | [22] = RCAR_GP_PIN(0, 14), /* D14 */ | |
5119 | [23] = RCAR_GP_PIN(0, 13), /* D13 */ | |
5120 | [24] = RCAR_GP_PIN(0, 12), /* D12 */ | |
5121 | [25] = RCAR_GP_PIN(0, 11), /* D11 */ | |
5122 | [26] = RCAR_GP_PIN(0, 10), /* D10 */ | |
5123 | [27] = RCAR_GP_PIN(0, 9), /* D9 */ | |
5124 | [28] = RCAR_GP_PIN(0, 8), /* D8 */ | |
5125 | [29] = RCAR_GP_PIN(0, 7), /* D7 */ | |
5126 | [30] = RCAR_GP_PIN(0, 6), /* D6 */ | |
5127 | [31] = RCAR_GP_PIN(0, 5), /* D5 */ | |
5128 | } }, | |
5129 | { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { | |
5130 | [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ | |
7f2e60f1 | 5131 | [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ |
8719ca81 MV |
5132 | [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ |
5133 | [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ | |
5134 | [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ | |
5135 | [5] = PIN_NONE, | |
5136 | [6] = PIN_NONE, | |
5137 | [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */ | |
5138 | [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */ | |
5139 | [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ | |
5140 | [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */ | |
5141 | [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */ | |
5142 | [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */ | |
5143 | [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */ | |
5144 | [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */ | |
5145 | [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */ | |
5146 | [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */ | |
5147 | [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */ | |
5148 | [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */ | |
5149 | [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */ | |
5150 | [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */ | |
5151 | [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */ | |
5152 | [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ | |
5153 | [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ | |
5154 | [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ | |
5155 | [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ | |
5156 | [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ | |
5157 | [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ | |
5158 | [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ | |
5159 | [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ | |
5160 | [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ | |
5161 | [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ | |
5162 | } }, | |
5163 | { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { | |
5164 | [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */ | |
5165 | [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ | |
5166 | [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ | |
5167 | [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ | |
5168 | [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ | |
5169 | [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ | |
5170 | [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ | |
5171 | [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ | |
5172 | [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ | |
5173 | [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ | |
5174 | [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ | |
5175 | [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */ | |
5176 | [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */ | |
5177 | [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ | |
5178 | [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ | |
5179 | [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ | |
5180 | [16] = PIN_NUMBER('T', 21), /* MLB_REF */ | |
5181 | [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */ | |
5182 | [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */ | |
5183 | [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */ | |
5184 | [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */ | |
5185 | [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */ | |
5186 | [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ | |
5187 | [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ | |
5188 | [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */ | |
5189 | [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */ | |
5190 | [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */ | |
5191 | [27] = RCAR_GP_PIN(5, 9), /* RX2_A */ | |
5192 | [28] = RCAR_GP_PIN(5, 8), /* TX2_A */ | |
5193 | [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */ | |
5194 | [30] = RCAR_GP_PIN(5, 6), /* TX1 */ | |
5195 | [31] = RCAR_GP_PIN(5, 5), /* RX1 */ | |
5196 | } }, | |
5197 | { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { | |
5198 | [0] = PIN_NONE, | |
5199 | [1] = PIN_NONE, | |
5200 | [2] = PIN_NONE, | |
5201 | [3] = PIN_NONE, | |
5202 | [4] = PIN_NONE, | |
5203 | [5] = PIN_NONE, | |
5204 | [6] = PIN_NONE, | |
5205 | [7] = PIN_NONE, | |
5206 | [8] = PIN_NONE, | |
5207 | [9] = PIN_NONE, | |
5208 | [10] = PIN_NONE, | |
5209 | [11] = PIN_NONE, | |
5210 | [12] = PIN_NONE, | |
5211 | [13] = PIN_NONE, | |
5212 | [14] = PIN_NONE, | |
5213 | [15] = PIN_NONE, | |
5214 | [16] = PIN_NONE, | |
5215 | [17] = PIN_NONE, | |
5216 | [18] = PIN_NONE, | |
5217 | [19] = PIN_NONE, | |
5218 | [20] = PIN_NONE, | |
5219 | [21] = PIN_NONE, | |
5220 | [22] = PIN_NONE, | |
5221 | [23] = PIN_NONE, | |
5222 | [24] = PIN_NONE, | |
5223 | [25] = PIN_NONE, | |
5224 | [26] = PIN_NONE, | |
5225 | [27] = PIN_NONE, | |
5226 | [28] = PIN_NONE, | |
5227 | [29] = PIN_NONE, | |
5228 | [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ | |
5229 | [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ | |
5230 | } }, | |
5231 | { /* sentinel */ }, | |
5232 | }; | |
5233 | ||
5234 | static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, | |
5235 | unsigned int pin) | |
5236 | { | |
5237 | const struct pinmux_bias_reg *reg; | |
5238 | unsigned int bit; | |
5239 | ||
5240 | reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); | |
5241 | if (!reg) | |
5242 | return PIN_CONFIG_BIAS_DISABLE; | |
5243 | ||
5244 | if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) | |
5245 | return PIN_CONFIG_BIAS_DISABLE; | |
5246 | else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) | |
5247 | return PIN_CONFIG_BIAS_PULL_UP; | |
5248 | else | |
5249 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
5250 | } | |
5251 | ||
5252 | static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, | |
5253 | unsigned int bias) | |
5254 | { | |
5255 | const struct pinmux_bias_reg *reg; | |
5256 | u32 enable, updown; | |
5257 | unsigned int bit; | |
5258 | ||
5259 | reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); | |
5260 | if (!reg) | |
5261 | return; | |
5262 | ||
5263 | enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); | |
5264 | if (bias != PIN_CONFIG_BIAS_DISABLE) | |
5265 | enable |= BIT(bit); | |
5266 | ||
5267 | updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); | |
5268 | if (bias == PIN_CONFIG_BIAS_PULL_UP) | |
5269 | updown |= BIT(bit); | |
5270 | ||
5271 | sh_pfc_write(pfc, reg->pud, updown); | |
5272 | sh_pfc_write(pfc, reg->puen, enable); | |
5273 | } | |
5274 | ||
5dbdd3a6 MV |
5275 | static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { |
5276 | .pin_to_pocctrl = r8a77990_pin_to_pocctrl, | |
8719ca81 MV |
5277 | .get_bias = r8a77990_pinmux_get_bias, |
5278 | .set_bias = r8a77990_pinmux_set_bias, | |
5279 | }; | |
5280 | ||
5281 | #ifdef CONFIG_PINCTRL_PFC_R8A774C0 | |
5282 | const struct sh_pfc_soc_info r8a774c0_pinmux_info = { | |
5283 | .name = "r8a774c0_pfc", | |
5284 | .ops = &r8a77990_pinmux_ops, | |
5285 | .unlock_reg = 0xe6060000, /* PMMR */ | |
5286 | ||
5287 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
5288 | ||
5289 | .pins = pinmux_pins, | |
5290 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
5291 | .groups = pinmux_groups.common, | |
5292 | .nr_groups = ARRAY_SIZE(pinmux_groups.common), | |
5293 | .functions = pinmux_functions.common, | |
5294 | .nr_functions = ARRAY_SIZE(pinmux_functions.common), | |
5295 | ||
5296 | .cfg_regs = pinmux_config_regs, | |
5297 | .bias_regs = pinmux_bias_regs, | |
5298 | .ioctrl_regs = pinmux_ioctrl_regs, | |
5299 | ||
5300 | .pinmux_data = pinmux_data, | |
5301 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
5dbdd3a6 | 5302 | }; |
8719ca81 | 5303 | #endif |
5dbdd3a6 | 5304 | |
8719ca81 | 5305 | #ifdef CONFIG_PINCTRL_PFC_R8A77990 |
cb13e46a MV |
5306 | const struct sh_pfc_soc_info r8a77990_pinmux_info = { |
5307 | .name = "r8a77990_pfc", | |
5dbdd3a6 | 5308 | .ops = &r8a77990_pinmux_ops, |
cb13e46a MV |
5309 | .unlock_reg = 0xe6060000, /* PMMR */ |
5310 | ||
5311 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
5312 | ||
5313 | .pins = pinmux_pins, | |
5314 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
8719ca81 MV |
5315 | .groups = pinmux_groups.common, |
5316 | .nr_groups = ARRAY_SIZE(pinmux_groups.common) + | |
5317 | ARRAY_SIZE(pinmux_groups.automotive), | |
5318 | .functions = pinmux_functions.common, | |
5319 | .nr_functions = ARRAY_SIZE(pinmux_functions.common) + | |
5320 | ARRAY_SIZE(pinmux_functions.automotive), | |
cb13e46a MV |
5321 | |
5322 | .cfg_regs = pinmux_config_regs, | |
8719ca81 | 5323 | .bias_regs = pinmux_bias_regs, |
5dbdd3a6 | 5324 | .ioctrl_regs = pinmux_ioctrl_regs, |
cb13e46a MV |
5325 | |
5326 | .pinmux_data = pinmux_data, | |
5327 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
5328 | }; | |
8719ca81 | 5329 | #endif |