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a59e6976 MV |
1 | /* |
2 | * R8A77995 processor support - PFC hardware block. | |
3 | * | |
4 | * Copyright (C) 2017 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c | |
7 | * | |
8 | * R-Car Gen3 processor support - PFC hardware block. | |
9 | * | |
10 | * Copyright (C) 2015 Renesas Electronics Corporation | |
11 | * | |
12 | * SPDX-License-Identifier: GPL-2.0 | |
13 | */ | |
14 | ||
15 | #include <common.h> | |
16 | #include <dm.h> | |
17 | #include <errno.h> | |
18 | #include <dm/pinctrl.h> | |
19 | #include <linux/kernel.h> | |
20 | ||
21 | #include "sh_pfc.h" | |
22 | ||
23 | #define CPU_ALL_PORT(fn, sfx) \ | |
24 | PORT_GP_9(0, fn, sfx), \ | |
25 | PORT_GP_32(1, fn, sfx), \ | |
26 | PORT_GP_32(2, fn, sfx), \ | |
27 | PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
28 | PORT_GP_32(4, fn, sfx), \ | |
29 | PORT_GP_21(5, fn, sfx), \ | |
30 | PORT_GP_14(6, fn, sfx) | |
31 | ||
32 | /* | |
33 | * F_() : just information | |
34 | * FM() : macro for FN_xxx / xxx_MARK | |
35 | */ | |
36 | ||
37 | /* GPSR0 */ | |
38 | #define GPSR0_8 F_(MLB_SIG, IP0_27_24) | |
39 | #define GPSR0_7 F_(MLB_DAT, IP0_23_20) | |
40 | #define GPSR0_6 F_(MLB_CLK, IP0_19_16) | |
41 | #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) | |
42 | #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) | |
43 | #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) | |
44 | #define GPSR0_2 F_(IRQ0_A, IP0_3_0) | |
45 | #define GPSR0_1 FM(USB0_OVC) | |
46 | #define GPSR0_0 FM(USB0_PWEN) | |
47 | ||
48 | /* GPSR1 */ | |
49 | #define GPSR1_31 F_(QPOLB, IP4_27_24) | |
50 | #define GPSR1_30 F_(QPOLA, IP4_23_20) | |
51 | #define GPSR1_29 F_(DU_CDE, IP4_19_16) | |
52 | #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) | |
53 | #define GPSR1_27 F_(DU_DISP, IP4_11_8) | |
54 | #define GPSR1_26 F_(DU_VSYNC, IP4_7_4) | |
55 | #define GPSR1_25 F_(DU_HSYNC, IP4_3_0) | |
56 | #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) | |
57 | #define GPSR1_23 F_(DU_DR7, IP3_27_24) | |
58 | #define GPSR1_22 F_(DU_DR6, IP3_23_20) | |
59 | #define GPSR1_21 F_(DU_DR5, IP3_19_16) | |
60 | #define GPSR1_20 F_(DU_DR4, IP3_15_12) | |
61 | #define GPSR1_19 F_(DU_DR3, IP3_11_8) | |
62 | #define GPSR1_18 F_(DU_DR2, IP3_7_4) | |
63 | #define GPSR1_17 F_(DU_DR1, IP3_3_0) | |
64 | #define GPSR1_16 F_(DU_DR0, IP2_31_28) | |
65 | #define GPSR1_15 F_(DU_DG7, IP2_27_24) | |
66 | #define GPSR1_14 F_(DU_DG6, IP2_23_20) | |
67 | #define GPSR1_13 F_(DU_DG5, IP2_19_16) | |
68 | #define GPSR1_12 F_(DU_DG4, IP2_15_12) | |
69 | #define GPSR1_11 F_(DU_DG3, IP2_11_8) | |
70 | #define GPSR1_10 F_(DU_DG2, IP2_7_4) | |
71 | #define GPSR1_9 F_(DU_DG1, IP2_3_0) | |
72 | #define GPSR1_8 F_(DU_DG0, IP1_31_28) | |
73 | #define GPSR1_7 F_(DU_DB7, IP1_27_24) | |
74 | #define GPSR1_6 F_(DU_DB6, IP1_23_20) | |
75 | #define GPSR1_5 F_(DU_DB5, IP1_19_16) | |
76 | #define GPSR1_4 F_(DU_DB4, IP1_15_12) | |
77 | #define GPSR1_3 F_(DU_DB3, IP1_11_8) | |
78 | #define GPSR1_2 F_(DU_DB2, IP1_7_4) | |
79 | #define GPSR1_1 F_(DU_DB1, IP1_3_0) | |
80 | #define GPSR1_0 F_(DU_DB0, IP0_31_28) | |
81 | ||
82 | /* GPSR2 */ | |
83 | #define GPSR2_31 F_(NFCE_N, IP8_19_16) | |
84 | #define GPSR2_30 F_(NFCLE, IP8_15_12) | |
85 | #define GPSR2_29 F_(NFALE, IP8_11_8) | |
86 | #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) | |
87 | #define GPSR2_27 F_(VI4_FIELD, IP8_3_0) | |
88 | #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) | |
89 | #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) | |
90 | #define GPSR2_24 F_(VI4_DATA23, IP7_23_20) | |
91 | #define GPSR2_23 F_(VI4_DATA22, IP7_19_16) | |
92 | #define GPSR2_22 F_(VI4_DATA21, IP7_15_12) | |
93 | #define GPSR2_21 F_(VI4_DATA20, IP7_11_8) | |
94 | #define GPSR2_20 F_(VI4_DATA19, IP7_7_4) | |
95 | #define GPSR2_19 F_(VI4_DATA18, IP7_3_0) | |
96 | #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) | |
97 | #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) | |
98 | #define GPSR2_16 F_(VI4_DATA15, IP6_23_20) | |
99 | #define GPSR2_15 F_(VI4_DATA14, IP6_19_16) | |
100 | #define GPSR2_14 F_(VI4_DATA13, IP6_15_12) | |
101 | #define GPSR2_13 F_(VI4_DATA12, IP6_11_8) | |
102 | #define GPSR2_12 F_(VI4_DATA11, IP6_7_4) | |
103 | #define GPSR2_11 F_(VI4_DATA10, IP6_3_0) | |
104 | #define GPSR2_10 F_(VI4_DATA9, IP5_31_28) | |
105 | #define GPSR2_9 F_(VI4_DATA8, IP5_27_24) | |
106 | #define GPSR2_8 F_(VI4_DATA7, IP5_23_20) | |
107 | #define GPSR2_7 F_(VI4_DATA6, IP5_19_16) | |
108 | #define GPSR2_6 F_(VI4_DATA5, IP5_15_12) | |
109 | #define GPSR2_5 FM(VI4_DATA4) | |
110 | #define GPSR2_4 F_(VI4_DATA3, IP5_11_8) | |
111 | #define GPSR2_3 F_(VI4_DATA2, IP5_7_4) | |
112 | #define GPSR2_2 F_(VI4_DATA1, IP5_3_0) | |
113 | #define GPSR2_1 F_(VI4_DATA0, IP4_31_28) | |
114 | #define GPSR2_0 FM(VI4_CLK) | |
115 | ||
116 | /* GPSR3 */ | |
117 | #define GPSR3_9 F_(NFDATA7, IP9_31_28) | |
118 | #define GPSR3_8 F_(NFDATA6, IP9_27_24) | |
119 | #define GPSR3_7 F_(NFDATA5, IP9_23_20) | |
120 | #define GPSR3_6 F_(NFDATA4, IP9_19_16) | |
121 | #define GPSR3_5 F_(NFDATA3, IP9_15_12) | |
122 | #define GPSR3_4 F_(NFDATA2, IP9_11_8) | |
123 | #define GPSR3_3 F_(NFDATA1, IP9_7_4) | |
124 | #define GPSR3_2 F_(NFDATA0, IP9_3_0) | |
125 | #define GPSR3_1 F_(NFWE_N, IP8_31_28) | |
126 | #define GPSR3_0 F_(NFRE_N, IP8_27_24) | |
127 | ||
128 | /* GPSR4 */ | |
129 | #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) | |
130 | #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) | |
131 | #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) | |
132 | #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) | |
133 | #define GPSR4_27 FM(TX2) | |
134 | #define GPSR4_26 FM(RX2) | |
135 | #define GPSR4_25 F_(SCK2, IP12_11_8) | |
136 | #define GPSR4_24 F_(TX1_A, IP12_7_4) | |
137 | #define GPSR4_23 F_(RX1_A, IP12_3_0) | |
138 | #define GPSR4_22 F_(SCK1_A, IP11_31_28) | |
139 | #define GPSR4_21 F_(TX0_A, IP11_27_24) | |
140 | #define GPSR4_20 F_(RX0_A, IP11_23_20) | |
141 | #define GPSR4_19 F_(SCK0_A, IP11_19_16) | |
142 | #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) | |
143 | #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) | |
144 | #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) | |
145 | #define GPSR4_15 FM(MSIOF0_RXD) | |
146 | #define GPSR4_14 FM(MSIOF0_TXD) | |
147 | #define GPSR4_13 FM(MSIOF0_SYNC) | |
148 | #define GPSR4_12 FM(MSIOF0_SCK) | |
149 | #define GPSR4_11 F_(SDA1, IP11_3_0) | |
150 | #define GPSR4_10 F_(SCL1, IP10_31_28) | |
151 | #define GPSR4_9 FM(SDA0) | |
152 | #define GPSR4_8 FM(SCL0) | |
153 | #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) | |
154 | #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) | |
155 | #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) | |
156 | #define GPSR4_4 F_(SSI_WS34, IP10_15_12) | |
157 | #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) | |
158 | #define GPSR4_2 F_(SSI_SCK34, IP10_7_4) | |
159 | #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) | |
160 | #define GPSR4_0 F_(NFRB_N, IP8_23_20) | |
161 | ||
162 | /* GPSR5 */ | |
163 | #define GPSR5_20 FM(AVB0_LINK) | |
164 | #define GPSR5_19 FM(AVB0_PHY_INT) | |
165 | #define GPSR5_18 FM(AVB0_MAGIC) | |
166 | #define GPSR5_17 FM(AVB0_MDC) | |
167 | #define GPSR5_16 FM(AVB0_MDIO) | |
168 | #define GPSR5_15 FM(AVB0_TXCREFCLK) | |
169 | #define GPSR5_14 FM(AVB0_TD3) | |
170 | #define GPSR5_13 FM(AVB0_TD2) | |
171 | #define GPSR5_12 FM(AVB0_TD1) | |
172 | #define GPSR5_11 FM(AVB0_TD0) | |
173 | #define GPSR5_10 FM(AVB0_TXC) | |
174 | #define GPSR5_9 FM(AVB0_TX_CTL) | |
175 | #define GPSR5_8 FM(AVB0_RD3) | |
176 | #define GPSR5_7 FM(AVB0_RD2) | |
177 | #define GPSR5_6 FM(AVB0_RD1) | |
178 | #define GPSR5_5 FM(AVB0_RD0) | |
179 | #define GPSR5_4 FM(AVB0_RXC) | |
180 | #define GPSR5_3 FM(AVB0_RX_CTL) | |
181 | #define GPSR5_2 F_(CAN_CLK, IP12_23_20) | |
182 | #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) | |
183 | #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) | |
184 | ||
185 | /* GPSR6 */ | |
186 | #define GPSR6_13 FM(RPC_INT_N) | |
187 | #define GPSR6_12 FM(RPC_RESET_N) | |
188 | #define GPSR6_11 FM(QSPI1_SSL) | |
189 | #define GPSR6_10 FM(QSPI1_IO3) | |
190 | #define GPSR6_9 FM(QSPI1_IO2) | |
191 | #define GPSR6_8 FM(QSPI1_MISO_IO1) | |
192 | #define GPSR6_7 FM(QSPI1_MOSI_IO0) | |
193 | #define GPSR6_6 FM(QSPI1_SPCLK) | |
194 | #define GPSR6_5 FM(QSPI0_SSL) | |
195 | #define GPSR6_4 FM(QSPI0_IO3) | |
196 | #define GPSR6_3 FM(QSPI0_IO2) | |
197 | #define GPSR6_2 FM(QSPI0_MISO_IO1) | |
198 | #define GPSR6_1 FM(QSPI0_MOSI_IO0) | |
199 | #define GPSR6_0 FM(QSPI0_SPCLK) | |
200 | ||
201 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
202 | #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
203 | #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
204 | #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
205 | #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
206 | #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
207 | #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
208 | #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
209 | #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
210 | #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
211 | #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
212 | #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
213 | #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
214 | #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
215 | #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
216 | #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
217 | #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
218 | #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
219 | #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
220 | #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
221 | #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
222 | #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
223 | #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
224 | #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
225 | #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
226 | #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
227 | #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
228 | #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
229 | #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
230 | #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
231 | #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
232 | #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
233 | #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
234 | ||
235 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
236 | #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
237 | #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
238 | #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
239 | #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
240 | #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
241 | #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
242 | #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
243 | #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
244 | #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
245 | #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
246 | #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
247 | #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
248 | #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
249 | #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
250 | #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
251 | #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
252 | #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
253 | #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
254 | #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
255 | #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
256 | #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
257 | #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
258 | #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
259 | #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
260 | #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
261 | #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
262 | #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
263 | #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
264 | #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
265 | #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
266 | #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
267 | #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
268 | ||
269 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
270 | #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
271 | #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
272 | #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
273 | #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
274 | #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
275 | #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
276 | #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
277 | #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
278 | #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
279 | #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
280 | #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
281 | #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
282 | #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
283 | #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
284 | #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
285 | #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
286 | #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
287 | #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
288 | #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
289 | #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
290 | #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
291 | #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
292 | #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
293 | #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
294 | #define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
295 | #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
296 | #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
297 | #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
298 | #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
299 | #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
300 | #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
301 | #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
302 | ||
303 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
304 | #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
305 | #define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
306 | #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
307 | #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
308 | #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
309 | #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
310 | #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
311 | #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
312 | #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
313 | #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
314 | ||
315 | #define PINMUX_GPSR \ | |
316 | \ | |
317 | GPSR1_31 GPSR2_31 GPSR4_31 \ | |
318 | GPSR1_30 GPSR2_30 GPSR4_30 \ | |
319 | GPSR1_29 GPSR2_29 GPSR4_29 \ | |
320 | GPSR1_28 GPSR2_28 GPSR4_28 \ | |
321 | GPSR1_27 GPSR2_27 GPSR4_27 \ | |
322 | GPSR1_26 GPSR2_26 GPSR4_26 \ | |
323 | GPSR1_25 GPSR2_25 GPSR4_25 \ | |
324 | GPSR1_24 GPSR2_24 GPSR4_24 \ | |
325 | GPSR1_23 GPSR2_23 GPSR4_23 \ | |
326 | GPSR1_22 GPSR2_22 GPSR4_22 \ | |
327 | GPSR1_21 GPSR2_21 GPSR4_21 \ | |
328 | GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ | |
329 | GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ | |
330 | GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ | |
331 | GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ | |
332 | GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ | |
333 | GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ | |
334 | GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ | |
335 | GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ | |
336 | GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ | |
337 | GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ | |
338 | GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ | |
339 | GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ | |
340 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ | |
341 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ | |
342 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ | |
343 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ | |
344 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ | |
345 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ | |
346 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ | |
347 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ | |
348 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 | |
349 | ||
350 | #define PINMUX_IPSR \ | |
351 | \ | |
352 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ | |
353 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ | |
354 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ | |
355 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ | |
356 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ | |
357 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ | |
358 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ | |
359 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ | |
360 | \ | |
361 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ | |
362 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ | |
363 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ | |
364 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ | |
365 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ | |
366 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ | |
367 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ | |
368 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ | |
369 | \ | |
370 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ | |
371 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ | |
372 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ | |
373 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ | |
374 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ | |
375 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ | |
376 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ | |
377 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ | |
378 | \ | |
379 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ | |
380 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ | |
381 | FM(IP12_11_8) IP12_11_8 \ | |
382 | FM(IP12_15_12) IP12_15_12 \ | |
383 | FM(IP12_19_16) IP12_19_16 \ | |
384 | FM(IP12_23_20) IP12_23_20 \ | |
385 | FM(IP12_27_24) IP12_27_24 \ | |
386 | FM(IP12_31_28) IP12_31_28 \ | |
387 | ||
388 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ | |
389 | #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) | |
390 | #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) | |
391 | #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) | |
392 | #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) | |
393 | #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) | |
394 | #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) | |
395 | #define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3) | |
396 | #define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3) | |
397 | #define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3) | |
398 | #define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3) | |
399 | #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) | |
400 | #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) | |
401 | #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) | |
402 | #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) | |
403 | #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) | |
404 | #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) | |
405 | #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) | |
406 | #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) | |
407 | #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) | |
408 | #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) | |
409 | #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) | |
410 | #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) | |
411 | ||
412 | #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) | |
413 | #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) | |
414 | #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) | |
415 | #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) | |
416 | #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) | |
417 | #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) | |
418 | ||
419 | ||
420 | #define PINMUX_MOD_SELS \ | |
421 | \ | |
422 | MOD_SEL1_31 \ | |
423 | MOD_SEL0_30 MOD_SEL1_30 \ | |
424 | MOD_SEL0_29 MOD_SEL1_29 \ | |
425 | MOD_SEL0_28 MOD_SEL1_28 \ | |
426 | MOD_SEL0_27 MOD_SEL1_27 \ | |
427 | MOD_SEL0_26 MOD_SEL1_26 \ | |
428 | MOD_SEL0_25 \ | |
429 | MOD_SEL0_24_23 \ | |
430 | MOD_SEL0_22_21 \ | |
431 | MOD_SEL0_20_19 \ | |
432 | MOD_SEL0_18_17 \ | |
433 | MOD_SEL0_15 \ | |
434 | MOD_SEL0_14 \ | |
435 | MOD_SEL0_13 \ | |
436 | MOD_SEL0_12 \ | |
437 | MOD_SEL0_11 \ | |
438 | MOD_SEL0_10 \ | |
439 | MOD_SEL0_5 \ | |
440 | MOD_SEL0_4 \ | |
441 | MOD_SEL0_3 \ | |
442 | MOD_SEL0_2 \ | |
443 | MOD_SEL0_1 \ | |
444 | MOD_SEL0_0 | |
445 | ||
446 | enum { | |
447 | PINMUX_RESERVED = 0, | |
448 | ||
449 | PINMUX_DATA_BEGIN, | |
450 | GP_ALL(DATA), | |
451 | PINMUX_DATA_END, | |
452 | ||
453 | #define F_(x, y) | |
454 | #define FM(x) FN_##x, | |
455 | PINMUX_FUNCTION_BEGIN, | |
456 | GP_ALL(FN), | |
457 | PINMUX_GPSR | |
458 | PINMUX_IPSR | |
459 | PINMUX_MOD_SELS | |
460 | PINMUX_FUNCTION_END, | |
461 | #undef F_ | |
462 | #undef FM | |
463 | ||
464 | #define F_(x, y) | |
465 | #define FM(x) x##_MARK, | |
466 | PINMUX_MARK_BEGIN, | |
467 | PINMUX_GPSR | |
468 | PINMUX_IPSR | |
469 | PINMUX_MOD_SELS | |
470 | PINMUX_MARK_END, | |
471 | #undef F_ | |
472 | #undef FM | |
473 | }; | |
474 | ||
475 | #define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ | |
476 | PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr) | |
477 | ||
478 | #define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ | |
479 | PINMUX_DATA(fn##_MARK, FN_##msel) | |
480 | ||
481 | static const u16 pinmux_data[] = { | |
482 | PINMUX_DATA_GP_ALL(), | |
483 | ||
484 | PINMUX_SINGLE(USB0_OVC), | |
485 | PINMUX_SINGLE(USB0_PWEN), | |
486 | PINMUX_SINGLE(VI4_DATA4), | |
487 | PINMUX_SINGLE(VI4_CLK), | |
488 | PINMUX_SINGLE(TX2), | |
489 | PINMUX_SINGLE(RX2), | |
490 | PINMUX_SINGLE(AVB0_LINK), | |
491 | PINMUX_SINGLE(AVB0_PHY_INT), | |
492 | PINMUX_SINGLE(AVB0_MAGIC), | |
493 | PINMUX_SINGLE(AVB0_MDC), | |
494 | PINMUX_SINGLE(AVB0_MDIO), | |
495 | PINMUX_SINGLE(AVB0_TXCREFCLK), | |
496 | PINMUX_SINGLE(AVB0_TD3), | |
497 | PINMUX_SINGLE(AVB0_TD2), | |
498 | PINMUX_SINGLE(AVB0_TD1), | |
499 | PINMUX_SINGLE(AVB0_TD0), | |
500 | PINMUX_SINGLE(AVB0_TXC), | |
501 | PINMUX_SINGLE(AVB0_TX_CTL), | |
502 | PINMUX_SINGLE(AVB0_RD3), | |
503 | PINMUX_SINGLE(AVB0_RD2), | |
504 | PINMUX_SINGLE(AVB0_RD1), | |
505 | PINMUX_SINGLE(AVB0_RD0), | |
506 | PINMUX_SINGLE(AVB0_RXC), | |
507 | PINMUX_SINGLE(AVB0_RX_CTL), | |
508 | PINMUX_SINGLE(RPC_INT_N), | |
509 | PINMUX_SINGLE(RPC_RESET_N), | |
510 | PINMUX_SINGLE(QSPI1_SSL), | |
511 | PINMUX_SINGLE(QSPI1_IO3), | |
512 | PINMUX_SINGLE(QSPI1_IO2), | |
513 | PINMUX_SINGLE(QSPI1_MISO_IO1), | |
514 | PINMUX_SINGLE(QSPI1_MOSI_IO0), | |
515 | PINMUX_SINGLE(QSPI1_SPCLK), | |
516 | PINMUX_SINGLE(QSPI0_SSL), | |
517 | PINMUX_SINGLE(QSPI0_IO3), | |
518 | PINMUX_SINGLE(QSPI0_IO2), | |
519 | PINMUX_SINGLE(QSPI0_MISO_IO1), | |
520 | PINMUX_SINGLE(QSPI0_MOSI_IO0), | |
521 | PINMUX_SINGLE(QSPI0_SPCLK), | |
522 | ||
523 | /* IPSR0 */ | |
524 | PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), | |
525 | PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), | |
526 | PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN), | |
527 | ||
528 | PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), | |
529 | PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU), | |
530 | ||
531 | PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), | |
532 | PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), | |
533 | ||
534 | PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), | |
535 | PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), | |
536 | ||
537 | PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), | |
538 | PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), | |
539 | PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), | |
540 | ||
541 | PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), | |
542 | PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), | |
543 | PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), | |
544 | PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), | |
545 | ||
546 | PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), | |
547 | PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), | |
548 | PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), | |
549 | PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), | |
550 | ||
551 | PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), | |
552 | PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), | |
553 | PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), | |
554 | ||
555 | /* IPSR1 */ | |
556 | PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), | |
557 | PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), | |
558 | PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), | |
559 | ||
560 | PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), | |
561 | PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), | |
562 | PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), | |
563 | ||
564 | PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), | |
565 | PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), | |
566 | PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), | |
567 | ||
568 | PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), | |
569 | PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), | |
570 | PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), | |
571 | ||
572 | PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), | |
573 | PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), | |
574 | PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), | |
575 | ||
576 | PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), | |
577 | PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), | |
578 | PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), | |
579 | ||
580 | PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), | |
581 | PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), | |
582 | PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), | |
583 | ||
584 | PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), | |
585 | PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), | |
586 | PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), | |
587 | ||
588 | /* IPSR2 */ | |
589 | PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), | |
590 | PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), | |
591 | PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), | |
592 | ||
593 | PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), | |
594 | PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), | |
595 | ||
596 | PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), | |
597 | PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), | |
598 | PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), | |
599 | ||
600 | PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), | |
601 | PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), | |
602 | PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), | |
603 | ||
604 | PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), | |
605 | PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), | |
606 | PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), | |
607 | ||
608 | PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), | |
609 | PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), | |
610 | PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), | |
611 | ||
612 | PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), | |
613 | PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), | |
614 | PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), | |
615 | ||
616 | PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), | |
617 | PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), | |
618 | PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), | |
619 | ||
620 | /* IPSR3 */ | |
621 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), | |
622 | PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), | |
623 | PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), | |
624 | ||
625 | PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), | |
626 | PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), | |
627 | PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), | |
628 | ||
629 | PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), | |
630 | PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), | |
631 | PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), | |
632 | ||
633 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), | |
634 | PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), | |
635 | PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), | |
636 | ||
637 | PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), | |
638 | PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), | |
639 | PINMUX_IPSR_GPSR(IP3_19_16, NMI), | |
640 | ||
641 | PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), | |
642 | PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), | |
643 | PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), | |
644 | ||
645 | PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), | |
646 | PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), | |
647 | PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), | |
648 | ||
649 | PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), | |
650 | PINMUX_IPSR_GPSR(IP3_31_28, QCLK), | |
651 | ||
652 | /* IPSR4 */ | |
653 | PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), | |
654 | PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), | |
655 | PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), | |
656 | ||
657 | PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), | |
658 | PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), | |
659 | PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), | |
660 | ||
661 | PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), | |
662 | PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), | |
663 | PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), | |
664 | ||
665 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), | |
666 | PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), | |
667 | PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), | |
668 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), | |
669 | ||
670 | PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), | |
671 | PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), | |
672 | PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), | |
673 | ||
674 | PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), | |
675 | PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), | |
676 | ||
677 | PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), | |
678 | PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), | |
679 | ||
680 | PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), | |
681 | PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), | |
682 | ||
683 | /* IPSR5 */ | |
684 | PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), | |
685 | PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), | |
686 | ||
687 | PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), | |
688 | PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), | |
689 | ||
690 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), | |
691 | PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), | |
692 | ||
693 | PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), | |
694 | PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), | |
695 | ||
696 | PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), | |
697 | PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), | |
698 | ||
699 | PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), | |
700 | PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), | |
701 | ||
702 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), | |
703 | ||
704 | PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), | |
705 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), | |
706 | PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), | |
707 | ||
708 | /* IPSR6 */ | |
709 | PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), | |
710 | PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), | |
711 | ||
712 | PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), | |
713 | PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), | |
714 | ||
715 | PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), | |
716 | PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), | |
717 | ||
718 | PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), | |
719 | PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), | |
720 | PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), | |
721 | ||
722 | PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), | |
723 | PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), | |
724 | PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), | |
725 | ||
726 | PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), | |
727 | PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), | |
728 | ||
729 | PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), | |
730 | PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), | |
731 | ||
732 | PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), | |
733 | PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), | |
734 | ||
735 | /* IPSR7 */ | |
736 | PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), | |
737 | PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), | |
738 | ||
739 | PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), | |
740 | PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), | |
741 | PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), | |
742 | ||
743 | PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), | |
744 | PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), | |
745 | PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), | |
746 | ||
747 | PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), | |
748 | PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), | |
749 | ||
750 | PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), | |
751 | PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), | |
752 | PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), | |
753 | ||
754 | PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), | |
755 | PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), | |
756 | PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), | |
757 | ||
758 | PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), | |
759 | ||
760 | PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), | |
761 | PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), | |
762 | PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), | |
763 | ||
764 | PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), | |
765 | PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), | |
766 | PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), | |
767 | ||
768 | /* IPSR8 */ | |
769 | PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), | |
770 | PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), | |
771 | PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), | |
772 | PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), | |
773 | PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), | |
774 | ||
775 | PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), | |
776 | PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), | |
777 | PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), | |
778 | PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), | |
779 | ||
780 | PINMUX_IPSR_GPSR(IP8_11_8, NFALE), | |
781 | PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), | |
782 | PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), | |
783 | PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), | |
784 | ||
785 | PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), | |
786 | PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), | |
787 | PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), | |
788 | PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), | |
789 | ||
790 | PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), | |
791 | PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), | |
792 | PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), | |
793 | ||
794 | PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), | |
795 | PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), | |
796 | PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), | |
797 | ||
798 | PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), | |
799 | PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), | |
800 | ||
801 | PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), | |
802 | PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), | |
803 | ||
804 | /* IPSR9 */ | |
805 | PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), | |
806 | PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), | |
807 | ||
808 | PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), | |
809 | PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), | |
810 | ||
811 | PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), | |
812 | PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), | |
813 | ||
814 | PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), | |
815 | PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), | |
816 | ||
817 | PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), | |
818 | PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), | |
819 | ||
820 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), | |
821 | PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), | |
822 | ||
823 | PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), | |
824 | PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), | |
825 | ||
826 | PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), | |
827 | PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), | |
828 | ||
829 | /* IPSR10 */ | |
830 | PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), | |
831 | PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), | |
832 | ||
833 | PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), | |
834 | PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), | |
835 | ||
836 | PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), | |
837 | PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), | |
838 | ||
839 | PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), | |
840 | PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), | |
841 | ||
842 | PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), | |
843 | PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), | |
844 | PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), | |
845 | PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), | |
846 | PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), | |
847 | ||
848 | PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), | |
849 | PINMUX_IPSR_GPSR(IP10_23_20, HTX0), | |
850 | PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), | |
851 | PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), | |
852 | ||
853 | PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), | |
854 | PINMUX_IPSR_GPSR(IP10_27_24, HRX0), | |
855 | PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), | |
856 | PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), | |
857 | ||
858 | PINMUX_IPSR_GPSR(IP10_31_28, SCL1), | |
859 | PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), | |
860 | ||
861 | /* IPSR11 */ | |
862 | PINMUX_IPSR_GPSR(IP11_3_0, SDA1), | |
863 | PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), | |
864 | ||
865 | PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), | |
866 | PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), | |
867 | ||
868 | PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), | |
869 | PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), | |
870 | ||
871 | PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), | |
872 | PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), | |
873 | ||
874 | PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), | |
875 | PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), | |
876 | PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), | |
877 | ||
878 | PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), | |
879 | PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), | |
880 | PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), | |
881 | ||
882 | PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), | |
883 | PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), | |
884 | PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), | |
885 | ||
886 | PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), | |
887 | PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), | |
888 | PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), | |
889 | PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), | |
890 | PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), | |
891 | ||
892 | /* IPSR12 */ | |
893 | PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), | |
894 | PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), | |
895 | PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), | |
896 | ||
897 | PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), | |
898 | PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), | |
899 | PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), | |
900 | ||
901 | PINMUX_IPSR_GPSR(IP12_11_8, SCK2), | |
902 | PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), | |
903 | PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), | |
904 | ||
905 | PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), | |
906 | PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), | |
907 | PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), | |
908 | ||
909 | PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), | |
910 | PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), | |
911 | PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), | |
912 | ||
913 | PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), | |
914 | PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), | |
915 | PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), | |
916 | PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), | |
917 | ||
918 | PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), | |
919 | PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), | |
920 | PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), | |
921 | ||
922 | PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), | |
923 | PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), | |
924 | PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), | |
925 | ||
926 | /* IPSR13 */ | |
927 | PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), | |
928 | PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), | |
929 | PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), | |
930 | ||
931 | PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), | |
932 | PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), | |
933 | PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), | |
934 | }; | |
935 | ||
936 | static const struct sh_pfc_pin pinmux_pins[] = { | |
937 | PINMUX_GPIO_GP_ALL(), | |
938 | }; | |
939 | ||
940 | /* - I2C -------------------------------------------------------------------- */ | |
941 | static const unsigned int i2c0_pins[] = { | |
942 | /* SCL, SDA */ | |
943 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
944 | }; | |
945 | static const unsigned int i2c0_mux[] = { | |
946 | SCL0_MARK, SDA0_MARK, | |
947 | }; | |
948 | static const unsigned int i2c1_pins[] = { | |
949 | /* SCL, SDA */ | |
950 | RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), | |
951 | }; | |
952 | static const unsigned int i2c1_mux[] = { | |
953 | SCL1_MARK, SDA1_MARK, | |
954 | }; | |
955 | static const unsigned int i2c2_a_pins[] = { | |
956 | /* SCL, SDA */ | |
957 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), | |
958 | }; | |
959 | static const unsigned int i2c2_a_mux[] = { | |
960 | SCL2_A_MARK, SDA2_A_MARK, | |
961 | }; | |
962 | static const unsigned int i2c2_b_pins[] = { | |
963 | /* SCL, SDA */ | |
964 | RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), | |
965 | }; | |
966 | static const unsigned int i2c2_b_mux[] = { | |
967 | SCL2_B_MARK, SDA2_B_MARK, | |
968 | }; | |
969 | static const unsigned int i2c3_a_pins[] = { | |
970 | /* SCL, SDA */ | |
971 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
972 | }; | |
973 | static const unsigned int i2c3_a_mux[] = { | |
974 | SCL3_A_MARK, SDA3_A_MARK, | |
975 | }; | |
976 | static const unsigned int i2c3_b_pins[] = { | |
977 | /* SCL, SDA */ | |
978 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), | |
979 | }; | |
980 | static const unsigned int i2c3_b_mux[] = { | |
981 | SCL3_B_MARK, SDA3_B_MARK, | |
982 | }; | |
983 | ||
984 | /* - MMC ------------------------------------------------------------------- */ | |
985 | static const unsigned int mmc_data1_pins[] = { | |
986 | /* D0 */ | |
987 | RCAR_GP_PIN(3, 2), | |
988 | }; | |
989 | static const unsigned int mmc_data1_mux[] = { | |
990 | MMC_D0_MARK, | |
991 | }; | |
992 | static const unsigned int mmc_data4_pins[] = { | |
993 | /* D[0:3] */ | |
994 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
995 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
996 | }; | |
997 | static const unsigned int mmc_data4_mux[] = { | |
998 | MMC_D0_MARK, MMC_D1_MARK, | |
999 | MMC_D2_MARK, MMC_D3_MARK, | |
1000 | }; | |
1001 | static const unsigned int mmc_data8_pins[] = { | |
1002 | /* D[0:7] */ | |
1003 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
1004 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
1005 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
1006 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
1007 | }; | |
1008 | static const unsigned int mmc_data8_mux[] = { | |
1009 | MMC_D0_MARK, MMC_D1_MARK, | |
1010 | MMC_D2_MARK, MMC_D3_MARK, | |
1011 | MMC_D4_MARK, MMC_D5_MARK, | |
1012 | MMC_D6_MARK, MMC_D7_MARK, | |
1013 | }; | |
1014 | static const unsigned int mmc_ctrl_pins[] = { | |
1015 | /* CLK, CMD */ | |
1016 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), | |
1017 | }; | |
1018 | static const unsigned int mmc_ctrl_mux[] = { | |
1019 | MMC_CLK_MARK, MMC_CMD_MARK, | |
1020 | }; | |
1021 | ||
1022 | /* - SCIF0 ------------------------------------------------------------------ */ | |
1023 | static const unsigned int scif0_data_a_pins[] = { | |
1024 | /* RX, TX */ | |
1025 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), | |
1026 | }; | |
1027 | static const unsigned int scif0_data_a_mux[] = { | |
1028 | RX0_A_MARK, TX0_A_MARK, | |
1029 | }; | |
1030 | static const unsigned int scif0_clk_a_pins[] = { | |
1031 | /* SCK */ | |
1032 | RCAR_GP_PIN(4, 19), | |
1033 | }; | |
1034 | static const unsigned int scif0_clk_a_mux[] = { | |
1035 | SCK0_A_MARK, | |
1036 | }; | |
1037 | static const unsigned int scif0_data_b_pins[] = { | |
1038 | /* RX, TX */ | |
1039 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), | |
1040 | }; | |
1041 | static const unsigned int scif0_data_b_mux[] = { | |
1042 | RX0_B_MARK, TX0_B_MARK, | |
1043 | }; | |
1044 | static const unsigned int scif0_clk_b_pins[] = { | |
1045 | /* SCK */ | |
1046 | RCAR_GP_PIN(5, 2), | |
1047 | }; | |
1048 | static const unsigned int scif0_clk_b_mux[] = { | |
1049 | SCK0_B_MARK, | |
1050 | }; | |
1051 | static const unsigned int scif0_ctrl_pins[] = { | |
1052 | /* RTS, CTS */ | |
1053 | RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), | |
1054 | }; | |
1055 | static const unsigned int scif0_ctrl_mux[] = { | |
1056 | RTS0_N_TANS_MARK, CTS0_N_MARK, | |
1057 | }; | |
1058 | /* - SCIF1 ------------------------------------------------------------------ */ | |
1059 | static const unsigned int scif1_data_a_pins[] = { | |
1060 | /* RX, TX */ | |
1061 | RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), | |
1062 | }; | |
1063 | static const unsigned int scif1_data_a_mux[] = { | |
1064 | RX1_A_MARK, TX1_A_MARK, | |
1065 | }; | |
1066 | static const unsigned int scif1_clk_a_pins[] = { | |
1067 | /* SCK */ | |
1068 | RCAR_GP_PIN(4, 22), | |
1069 | }; | |
1070 | static const unsigned int scif1_clk_a_mux[] = { | |
1071 | SCK1_A_MARK, | |
1072 | }; | |
1073 | static const unsigned int scif1_data_b_pins[] = { | |
1074 | /* RX, TX */ | |
1075 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), | |
1076 | }; | |
1077 | static const unsigned int scif1_data_b_mux[] = { | |
1078 | RX1_B_MARK, TX1_B_MARK, | |
1079 | }; | |
1080 | static const unsigned int scif1_clk_b_pins[] = { | |
1081 | /* SCK */ | |
1082 | RCAR_GP_PIN(2, 25), | |
1083 | }; | |
1084 | static const unsigned int scif1_clk_b_mux[] = { | |
1085 | SCK1_B_MARK, | |
1086 | }; | |
1087 | static const unsigned int scif1_ctrl_pins[] = { | |
1088 | /* RTS, CTS */ | |
1089 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), | |
1090 | }; | |
1091 | static const unsigned int scif1_ctrl_mux[] = { | |
1092 | RTS1_N_TANS_MARK, CTS1_N_MARK, | |
1093 | }; | |
1094 | ||
1095 | /* - SCIF2 ------------------------------------------------------------------ */ | |
1096 | static const unsigned int scif2_data_pins[] = { | |
1097 | /* RX, TX */ | |
1098 | RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), | |
1099 | }; | |
1100 | static const unsigned int scif2_data_mux[] = { | |
1101 | RX2_MARK, TX2_MARK, | |
1102 | }; | |
1103 | static const unsigned int scif2_clk_pins[] = { | |
1104 | /* SCK */ | |
1105 | RCAR_GP_PIN(4, 25), | |
1106 | }; | |
1107 | static const unsigned int scif2_clk_mux[] = { | |
1108 | SCK2_MARK, | |
1109 | }; | |
1110 | /* - SCIF3 ------------------------------------------------------------------ */ | |
1111 | static const unsigned int scif3_data_a_pins[] = { | |
1112 | /* RX, TX */ | |
1113 | RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), | |
1114 | }; | |
1115 | static const unsigned int scif3_data_a_mux[] = { | |
1116 | RX3_A_MARK, TX3_A_MARK, | |
1117 | }; | |
1118 | static const unsigned int scif3_clk_a_pins[] = { | |
1119 | /* SCK */ | |
1120 | RCAR_GP_PIN(2, 30), | |
1121 | }; | |
1122 | static const unsigned int scif3_clk_a_mux[] = { | |
1123 | SCK3_A_MARK, | |
1124 | }; | |
1125 | static const unsigned int scif3_data_b_pins[] = { | |
1126 | /* RX, TX */ | |
1127 | RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), | |
1128 | }; | |
1129 | static const unsigned int scif3_data_b_mux[] = { | |
1130 | RX3_B_MARK, TX3_B_MARK, | |
1131 | }; | |
1132 | static const unsigned int scif3_clk_b_pins[] = { | |
1133 | /* SCK */ | |
1134 | RCAR_GP_PIN(1, 29), | |
1135 | }; | |
1136 | static const unsigned int scif3_clk_b_mux[] = { | |
1137 | SCK3_B_MARK, | |
1138 | }; | |
1139 | /* - SCIF4 ------------------------------------------------------------------ */ | |
1140 | static const unsigned int scif4_data_a_pins[] = { | |
1141 | /* RX, TX */ | |
1142 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
1143 | }; | |
1144 | static const unsigned int scif4_data_a_mux[] = { | |
1145 | RX4_A_MARK, TX4_A_MARK, | |
1146 | }; | |
1147 | static const unsigned int scif4_clk_a_pins[] = { | |
1148 | /* SCK */ | |
1149 | RCAR_GP_PIN(2, 6), | |
1150 | }; | |
1151 | static const unsigned int scif4_clk_a_mux[] = { | |
1152 | SCK4_A_MARK, | |
1153 | }; | |
1154 | static const unsigned int scif4_data_b_pins[] = { | |
1155 | /* RX, TX */ | |
1156 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
1157 | }; | |
1158 | static const unsigned int scif4_data_b_mux[] = { | |
1159 | RX4_B_MARK, TX4_B_MARK, | |
1160 | }; | |
1161 | static const unsigned int scif4_clk_b_pins[] = { | |
1162 | /* SCK */ | |
1163 | RCAR_GP_PIN(1, 15), | |
1164 | }; | |
1165 | static const unsigned int scif4_clk_b_mux[] = { | |
1166 | SCK4_B_MARK, | |
1167 | }; | |
1168 | /* - SCIF5 ------------------------------------------------------------------ */ | |
1169 | static const unsigned int scif5_data_a_pins[] = { | |
1170 | /* RX, TX */ | |
1171 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), | |
1172 | }; | |
1173 | static const unsigned int scif5_data_a_mux[] = { | |
1174 | RX5_A_MARK, TX5_A_MARK, | |
1175 | }; | |
1176 | static const unsigned int scif5_clk_a_pins[] = { | |
1177 | /* SCK */ | |
1178 | RCAR_GP_PIN(0, 6), | |
1179 | }; | |
1180 | static const unsigned int scif5_clk_a_mux[] = { | |
1181 | SCK5_A_MARK, | |
1182 | }; | |
1183 | static const unsigned int scif5_data_b_pins[] = { | |
1184 | /* RX, TX */ | |
1185 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
1186 | }; | |
1187 | static const unsigned int scif5_data_b_mux[] = { | |
1188 | RX5_B_MARK, TX5_B_MARK, | |
1189 | }; | |
1190 | static const unsigned int scif5_clk_b_pins[] = { | |
1191 | /* SCK */ | |
1192 | RCAR_GP_PIN(1, 3), | |
1193 | }; | |
1194 | static const unsigned int scif5_clk_b_mux[] = { | |
1195 | SCK5_B_MARK, | |
1196 | }; | |
1197 | /* - SCIF Clock ------------------------------------------------------------- */ | |
1198 | static const unsigned int scif_clk_pins[] = { | |
1199 | /* SCIF_CLK */ | |
1200 | RCAR_GP_PIN(2, 27), | |
1201 | }; | |
1202 | static const unsigned int scif_clk_mux[] = { | |
1203 | SCIF_CLK_MARK, | |
1204 | }; | |
1205 | ||
1206 | static const struct sh_pfc_pin_group pinmux_groups[] = { | |
1207 | SH_PFC_PIN_GROUP(i2c0), | |
1208 | SH_PFC_PIN_GROUP(i2c1), | |
1209 | SH_PFC_PIN_GROUP(i2c2_a), | |
1210 | SH_PFC_PIN_GROUP(i2c2_b), | |
1211 | SH_PFC_PIN_GROUP(i2c3_a), | |
1212 | SH_PFC_PIN_GROUP(i2c3_b), | |
1213 | SH_PFC_PIN_GROUP(mmc_data1), | |
1214 | SH_PFC_PIN_GROUP(mmc_data4), | |
1215 | SH_PFC_PIN_GROUP(mmc_data8), | |
1216 | SH_PFC_PIN_GROUP(mmc_ctrl), | |
1217 | SH_PFC_PIN_GROUP(scif0_data_a), | |
1218 | SH_PFC_PIN_GROUP(scif0_clk_a), | |
1219 | SH_PFC_PIN_GROUP(scif0_data_b), | |
1220 | SH_PFC_PIN_GROUP(scif0_clk_b), | |
1221 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
1222 | SH_PFC_PIN_GROUP(scif1_data_a), | |
1223 | SH_PFC_PIN_GROUP(scif1_clk_a), | |
1224 | SH_PFC_PIN_GROUP(scif1_data_b), | |
1225 | SH_PFC_PIN_GROUP(scif1_clk_b), | |
1226 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
1227 | SH_PFC_PIN_GROUP(scif2_data), | |
1228 | SH_PFC_PIN_GROUP(scif2_clk), | |
1229 | SH_PFC_PIN_GROUP(scif3_data_a), | |
1230 | SH_PFC_PIN_GROUP(scif3_clk_a), | |
1231 | SH_PFC_PIN_GROUP(scif3_data_b), | |
1232 | SH_PFC_PIN_GROUP(scif3_clk_b), | |
1233 | SH_PFC_PIN_GROUP(scif4_data_a), | |
1234 | SH_PFC_PIN_GROUP(scif4_clk_a), | |
1235 | SH_PFC_PIN_GROUP(scif4_data_b), | |
1236 | SH_PFC_PIN_GROUP(scif4_clk_b), | |
1237 | SH_PFC_PIN_GROUP(scif5_data_a), | |
1238 | SH_PFC_PIN_GROUP(scif5_clk_a), | |
1239 | SH_PFC_PIN_GROUP(scif5_data_b), | |
1240 | SH_PFC_PIN_GROUP(scif5_clk_b), | |
1241 | SH_PFC_PIN_GROUP(scif_clk), | |
1242 | }; | |
1243 | ||
1244 | static const char * const i2c0_groups[] = { | |
1245 | "i2c0", | |
1246 | }; | |
1247 | static const char * const i2c1_groups[] = { | |
1248 | "i2c1", | |
1249 | }; | |
1250 | ||
1251 | static const char * const i2c2_groups[] = { | |
1252 | "i2c2_a", | |
1253 | "i2c2_b", | |
1254 | }; | |
1255 | ||
1256 | static const char * const i2c3_groups[] = { | |
1257 | "i2c3_a", | |
1258 | "i2c3_b", | |
1259 | }; | |
1260 | ||
1261 | static const char * const mmc_groups[] = { | |
1262 | "mmc_data1", | |
1263 | "mmc_data4", | |
1264 | "mmc_data8", | |
1265 | "mmc_ctrl", | |
1266 | }; | |
1267 | ||
1268 | static const char * const scif0_groups[] = { | |
1269 | "scif0_data_a", | |
1270 | "scif0_clk_a", | |
1271 | "scif0_data_b", | |
1272 | "scif0_clk_b", | |
1273 | "scif0_ctrl", | |
1274 | }; | |
1275 | ||
1276 | static const char * const scif1_groups[] = { | |
1277 | "scif1_data_a", | |
1278 | "scif1_clk_a", | |
1279 | "scif1_data_b", | |
1280 | "scif1_clk_b", | |
1281 | "scif1_ctrl", | |
1282 | }; | |
1283 | ||
1284 | static const char * const scif2_groups[] = { | |
1285 | "scif2_data", | |
1286 | "scif2_clk", | |
1287 | }; | |
1288 | ||
1289 | static const char * const scif3_groups[] = { | |
1290 | "scif3_data_a", | |
1291 | "scif3_clk_a", | |
1292 | "scif3_data_b", | |
1293 | "scif3_clk_b", | |
1294 | }; | |
1295 | ||
1296 | static const char * const scif4_groups[] = { | |
1297 | "scif4_data_a", | |
1298 | "scif4_clk_a", | |
1299 | "scif4_data_b", | |
1300 | "scif4_clk_b", | |
1301 | }; | |
1302 | ||
1303 | static const char * const scif5_groups[] = { | |
1304 | "scif5_data_a", | |
1305 | "scif5_clk_a", | |
1306 | "scif5_data_b", | |
1307 | "scif5_clk_b", | |
1308 | }; | |
1309 | ||
1310 | static const char * const scif_clk_groups[] = { | |
1311 | "scif_clk", | |
1312 | }; | |
1313 | ||
1314 | static const struct sh_pfc_function pinmux_functions[] = { | |
1315 | SH_PFC_FUNCTION(i2c0), | |
1316 | SH_PFC_FUNCTION(i2c1), | |
1317 | SH_PFC_FUNCTION(i2c2), | |
1318 | SH_PFC_FUNCTION(i2c3), | |
1319 | SH_PFC_FUNCTION(mmc), | |
1320 | SH_PFC_FUNCTION(scif0), | |
1321 | SH_PFC_FUNCTION(scif1), | |
1322 | SH_PFC_FUNCTION(scif2), | |
1323 | SH_PFC_FUNCTION(scif3), | |
1324 | SH_PFC_FUNCTION(scif4), | |
1325 | SH_PFC_FUNCTION(scif5), | |
1326 | SH_PFC_FUNCTION(scif_clk), | |
1327 | }; | |
1328 | ||
1329 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
1330 | #define F_(x, y) FN_##y | |
1331 | #define FM(x) FN_##x | |
1332 | { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { | |
1333 | 0, 0, | |
1334 | 0, 0, | |
1335 | 0, 0, | |
1336 | 0, 0, | |
1337 | 0, 0, | |
1338 | 0, 0, | |
1339 | 0, 0, | |
1340 | 0, 0, | |
1341 | 0, 0, | |
1342 | 0, 0, | |
1343 | 0, 0, | |
1344 | 0, 0, | |
1345 | 0, 0, | |
1346 | 0, 0, | |
1347 | 0, 0, | |
1348 | 0, 0, | |
1349 | 0, 0, | |
1350 | 0, 0, | |
1351 | 0, 0, | |
1352 | 0, 0, | |
1353 | 0, 0, | |
1354 | 0, 0, | |
1355 | 0, 0, | |
1356 | GP_0_8_FN, GPSR0_8, | |
1357 | GP_0_7_FN, GPSR0_7, | |
1358 | GP_0_6_FN, GPSR0_6, | |
1359 | GP_0_5_FN, GPSR0_5, | |
1360 | GP_0_4_FN, GPSR0_4, | |
1361 | GP_0_3_FN, GPSR0_3, | |
1362 | GP_0_2_FN, GPSR0_2, | |
1363 | GP_0_1_FN, GPSR0_1, | |
1364 | GP_0_0_FN, GPSR0_0, } | |
1365 | }, | |
1366 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { | |
1367 | GP_1_31_FN, GPSR1_31, | |
1368 | GP_1_30_FN, GPSR1_30, | |
1369 | GP_1_29_FN, GPSR1_29, | |
1370 | GP_1_28_FN, GPSR1_28, | |
1371 | GP_1_27_FN, GPSR1_27, | |
1372 | GP_1_26_FN, GPSR1_26, | |
1373 | GP_1_25_FN, GPSR1_25, | |
1374 | GP_1_24_FN, GPSR1_24, | |
1375 | GP_1_23_FN, GPSR1_23, | |
1376 | GP_1_22_FN, GPSR1_22, | |
1377 | GP_1_21_FN, GPSR1_21, | |
1378 | GP_1_20_FN, GPSR1_20, | |
1379 | GP_1_19_FN, GPSR1_19, | |
1380 | GP_1_18_FN, GPSR1_18, | |
1381 | GP_1_17_FN, GPSR1_17, | |
1382 | GP_1_16_FN, GPSR1_16, | |
1383 | GP_1_15_FN, GPSR1_15, | |
1384 | GP_1_14_FN, GPSR1_14, | |
1385 | GP_1_13_FN, GPSR1_13, | |
1386 | GP_1_12_FN, GPSR1_12, | |
1387 | GP_1_11_FN, GPSR1_11, | |
1388 | GP_1_10_FN, GPSR1_10, | |
1389 | GP_1_9_FN, GPSR1_9, | |
1390 | GP_1_8_FN, GPSR1_8, | |
1391 | GP_1_7_FN, GPSR1_7, | |
1392 | GP_1_6_FN, GPSR1_6, | |
1393 | GP_1_5_FN, GPSR1_5, | |
1394 | GP_1_4_FN, GPSR1_4, | |
1395 | GP_1_3_FN, GPSR1_3, | |
1396 | GP_1_2_FN, GPSR1_2, | |
1397 | GP_1_1_FN, GPSR1_1, | |
1398 | GP_1_0_FN, GPSR1_0, } | |
1399 | }, | |
1400 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { | |
1401 | GP_2_31_FN, GPSR2_31, | |
1402 | GP_2_30_FN, GPSR2_30, | |
1403 | GP_2_29_FN, GPSR2_29, | |
1404 | GP_2_28_FN, GPSR2_28, | |
1405 | GP_2_27_FN, GPSR2_27, | |
1406 | GP_2_26_FN, GPSR2_26, | |
1407 | GP_2_25_FN, GPSR2_25, | |
1408 | GP_2_24_FN, GPSR2_24, | |
1409 | GP_2_23_FN, GPSR2_23, | |
1410 | GP_2_22_FN, GPSR2_22, | |
1411 | GP_2_21_FN, GPSR2_21, | |
1412 | GP_2_20_FN, GPSR2_20, | |
1413 | GP_2_19_FN, GPSR2_19, | |
1414 | GP_2_18_FN, GPSR2_18, | |
1415 | GP_2_17_FN, GPSR2_17, | |
1416 | GP_2_16_FN, GPSR2_16, | |
1417 | GP_2_15_FN, GPSR2_15, | |
1418 | GP_2_14_FN, GPSR2_14, | |
1419 | GP_2_13_FN, GPSR2_13, | |
1420 | GP_2_12_FN, GPSR2_12, | |
1421 | GP_2_11_FN, GPSR2_11, | |
1422 | GP_2_10_FN, GPSR2_10, | |
1423 | GP_2_9_FN, GPSR2_9, | |
1424 | GP_2_8_FN, GPSR2_8, | |
1425 | GP_2_7_FN, GPSR2_7, | |
1426 | GP_2_6_FN, GPSR2_6, | |
1427 | GP_2_5_FN, GPSR2_5, | |
1428 | GP_2_4_FN, GPSR2_4, | |
1429 | GP_2_3_FN, GPSR2_3, | |
1430 | GP_2_2_FN, GPSR2_2, | |
1431 | GP_2_1_FN, GPSR2_1, | |
1432 | GP_2_0_FN, GPSR2_0, } | |
1433 | }, | |
1434 | { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { | |
1435 | 0, 0, | |
1436 | 0, 0, | |
1437 | 0, 0, | |
1438 | 0, 0, | |
1439 | 0, 0, | |
1440 | 0, 0, | |
1441 | 0, 0, | |
1442 | 0, 0, | |
1443 | 0, 0, | |
1444 | 0, 0, | |
1445 | 0, 0, | |
1446 | 0, 0, | |
1447 | 0, 0, | |
1448 | 0, 0, | |
1449 | 0, 0, | |
1450 | 0, 0, | |
1451 | 0, 0, | |
1452 | 0, 0, | |
1453 | 0, 0, | |
1454 | 0, 0, | |
1455 | 0, 0, | |
1456 | 0, 0, | |
1457 | GP_3_9_FN, GPSR3_9, | |
1458 | GP_3_8_FN, GPSR3_8, | |
1459 | GP_3_7_FN, GPSR3_7, | |
1460 | GP_3_6_FN, GPSR3_6, | |
1461 | GP_3_5_FN, GPSR3_5, | |
1462 | GP_3_4_FN, GPSR3_4, | |
1463 | GP_3_3_FN, GPSR3_3, | |
1464 | GP_3_2_FN, GPSR3_2, | |
1465 | GP_3_1_FN, GPSR3_1, | |
1466 | GP_3_0_FN, GPSR3_0, } | |
1467 | }, | |
1468 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { | |
1469 | GP_4_31_FN, GPSR4_31, | |
1470 | GP_4_30_FN, GPSR4_30, | |
1471 | GP_4_29_FN, GPSR4_29, | |
1472 | GP_4_28_FN, GPSR4_28, | |
1473 | GP_4_27_FN, GPSR4_27, | |
1474 | GP_4_26_FN, GPSR4_26, | |
1475 | GP_4_25_FN, GPSR4_25, | |
1476 | GP_4_24_FN, GPSR4_24, | |
1477 | GP_4_23_FN, GPSR4_23, | |
1478 | GP_4_22_FN, GPSR4_22, | |
1479 | GP_4_21_FN, GPSR4_21, | |
1480 | GP_4_20_FN, GPSR4_20, | |
1481 | GP_4_19_FN, GPSR4_19, | |
1482 | GP_4_18_FN, GPSR4_18, | |
1483 | GP_4_17_FN, GPSR4_17, | |
1484 | GP_4_16_FN, GPSR4_16, | |
1485 | GP_4_15_FN, GPSR4_15, | |
1486 | GP_4_14_FN, GPSR4_14, | |
1487 | GP_4_13_FN, GPSR4_13, | |
1488 | GP_4_12_FN, GPSR4_12, | |
1489 | GP_4_11_FN, GPSR4_11, | |
1490 | GP_4_10_FN, GPSR4_10, | |
1491 | GP_4_9_FN, GPSR4_9, | |
1492 | GP_4_8_FN, GPSR4_8, | |
1493 | GP_4_7_FN, GPSR4_7, | |
1494 | GP_4_6_FN, GPSR4_6, | |
1495 | GP_4_5_FN, GPSR4_5, | |
1496 | GP_4_4_FN, GPSR4_4, | |
1497 | GP_4_3_FN, GPSR4_3, | |
1498 | GP_4_2_FN, GPSR4_2, | |
1499 | GP_4_1_FN, GPSR4_1, | |
1500 | GP_4_0_FN, GPSR4_0, } | |
1501 | }, | |
1502 | { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { | |
1503 | 0, 0, | |
1504 | 0, 0, | |
1505 | 0, 0, | |
1506 | 0, 0, | |
1507 | 0, 0, | |
1508 | 0, 0, | |
1509 | 0, 0, | |
1510 | 0, 0, | |
1511 | 0, 0, | |
1512 | 0, 0, | |
1513 | 0, 0, | |
1514 | GP_5_20_FN, GPSR5_20, | |
1515 | GP_5_19_FN, GPSR5_19, | |
1516 | GP_5_18_FN, GPSR5_18, | |
1517 | GP_5_17_FN, GPSR5_17, | |
1518 | GP_5_16_FN, GPSR5_16, | |
1519 | GP_5_15_FN, GPSR5_15, | |
1520 | GP_5_14_FN, GPSR5_14, | |
1521 | GP_5_13_FN, GPSR5_13, | |
1522 | GP_5_12_FN, GPSR5_12, | |
1523 | GP_5_11_FN, GPSR5_11, | |
1524 | GP_5_10_FN, GPSR5_10, | |
1525 | GP_5_9_FN, GPSR5_9, | |
1526 | GP_5_8_FN, GPSR5_8, | |
1527 | GP_5_7_FN, GPSR5_7, | |
1528 | GP_5_6_FN, GPSR5_6, | |
1529 | GP_5_5_FN, GPSR5_5, | |
1530 | GP_5_4_FN, GPSR5_4, | |
1531 | GP_5_3_FN, GPSR5_3, | |
1532 | GP_5_2_FN, GPSR5_2, | |
1533 | GP_5_1_FN, GPSR5_1, | |
1534 | GP_5_0_FN, GPSR5_0, } | |
1535 | }, | |
1536 | { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { | |
1537 | 0, 0, | |
1538 | 0, 0, | |
1539 | 0, 0, | |
1540 | 0, 0, | |
1541 | 0, 0, | |
1542 | 0, 0, | |
1543 | 0, 0, | |
1544 | 0, 0, | |
1545 | 0, 0, | |
1546 | 0, 0, | |
1547 | 0, 0, | |
1548 | 0, 0, | |
1549 | 0, 0, | |
1550 | 0, 0, | |
1551 | 0, 0, | |
1552 | 0, 0, | |
1553 | 0, 0, | |
1554 | 0, 0, | |
1555 | GP_6_13_FN, GPSR6_13, | |
1556 | GP_6_12_FN, GPSR6_12, | |
1557 | GP_6_11_FN, GPSR6_11, | |
1558 | GP_6_10_FN, GPSR6_10, | |
1559 | GP_6_9_FN, GPSR6_9, | |
1560 | GP_6_8_FN, GPSR6_8, | |
1561 | GP_6_7_FN, GPSR6_7, | |
1562 | GP_6_6_FN, GPSR6_6, | |
1563 | GP_6_5_FN, GPSR6_5, | |
1564 | GP_6_4_FN, GPSR6_4, | |
1565 | GP_6_3_FN, GPSR6_3, | |
1566 | GP_6_2_FN, GPSR6_2, | |
1567 | GP_6_1_FN, GPSR6_1, | |
1568 | GP_6_0_FN, GPSR6_0, } | |
1569 | }, | |
1570 | #undef F_ | |
1571 | #undef FM | |
1572 | ||
1573 | #define F_(x, y) x, | |
1574 | #define FM(x) FN_##x, | |
1575 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { | |
1576 | IP0_31_28 | |
1577 | IP0_27_24 | |
1578 | IP0_23_20 | |
1579 | IP0_19_16 | |
1580 | IP0_15_12 | |
1581 | IP0_11_8 | |
1582 | IP0_7_4 | |
1583 | IP0_3_0 } | |
1584 | }, | |
1585 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { | |
1586 | IP1_31_28 | |
1587 | IP1_27_24 | |
1588 | IP1_23_20 | |
1589 | IP1_19_16 | |
1590 | IP1_15_12 | |
1591 | IP1_11_8 | |
1592 | IP1_7_4 | |
1593 | IP1_3_0 } | |
1594 | }, | |
1595 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { | |
1596 | IP2_31_28 | |
1597 | IP2_27_24 | |
1598 | IP2_23_20 | |
1599 | IP2_19_16 | |
1600 | IP2_15_12 | |
1601 | IP2_11_8 | |
1602 | IP2_7_4 | |
1603 | IP2_3_0 } | |
1604 | }, | |
1605 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { | |
1606 | IP3_31_28 | |
1607 | IP3_27_24 | |
1608 | IP3_23_20 | |
1609 | IP3_19_16 | |
1610 | IP3_15_12 | |
1611 | IP3_11_8 | |
1612 | IP3_7_4 | |
1613 | IP3_3_0 } | |
1614 | }, | |
1615 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { | |
1616 | IP4_31_28 | |
1617 | IP4_27_24 | |
1618 | IP4_23_20 | |
1619 | IP4_19_16 | |
1620 | IP4_15_12 | |
1621 | IP4_11_8 | |
1622 | IP4_7_4 | |
1623 | IP4_3_0 } | |
1624 | }, | |
1625 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { | |
1626 | IP5_31_28 | |
1627 | IP5_27_24 | |
1628 | IP5_23_20 | |
1629 | IP5_19_16 | |
1630 | IP5_15_12 | |
1631 | IP5_11_8 | |
1632 | IP5_7_4 | |
1633 | IP5_3_0 } | |
1634 | }, | |
1635 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { | |
1636 | IP6_31_28 | |
1637 | IP6_27_24 | |
1638 | IP6_23_20 | |
1639 | IP6_19_16 | |
1640 | IP6_15_12 | |
1641 | IP6_11_8 | |
1642 | IP6_7_4 | |
1643 | IP6_3_0 } | |
1644 | }, | |
1645 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { | |
1646 | IP7_31_28 | |
1647 | IP7_27_24 | |
1648 | IP7_23_20 | |
1649 | IP7_19_16 | |
1650 | IP7_15_12 | |
1651 | IP7_11_8 | |
1652 | IP7_7_4 | |
1653 | IP7_3_0 } | |
1654 | }, | |
1655 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { | |
1656 | IP8_31_28 | |
1657 | IP8_27_24 | |
1658 | IP8_23_20 | |
1659 | IP8_19_16 | |
1660 | IP8_15_12 | |
1661 | IP8_11_8 | |
1662 | IP8_7_4 | |
1663 | IP8_3_0 } | |
1664 | }, | |
1665 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { | |
1666 | IP9_31_28 | |
1667 | IP9_27_24 | |
1668 | IP9_23_20 | |
1669 | IP9_19_16 | |
1670 | IP9_15_12 | |
1671 | IP9_11_8 | |
1672 | IP9_7_4 | |
1673 | IP9_3_0 } | |
1674 | }, | |
1675 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { | |
1676 | IP10_31_28 | |
1677 | IP10_27_24 | |
1678 | IP10_23_20 | |
1679 | IP10_19_16 | |
1680 | IP10_15_12 | |
1681 | IP10_11_8 | |
1682 | IP10_7_4 | |
1683 | IP10_3_0 } | |
1684 | }, | |
1685 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { | |
1686 | IP11_31_28 | |
1687 | IP11_27_24 | |
1688 | IP11_23_20 | |
1689 | IP11_19_16 | |
1690 | IP11_15_12 | |
1691 | IP11_11_8 | |
1692 | IP11_7_4 | |
1693 | IP11_3_0 } | |
1694 | }, | |
1695 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { | |
1696 | IP12_31_28 | |
1697 | IP12_27_24 | |
1698 | IP12_23_20 | |
1699 | IP12_19_16 | |
1700 | IP12_15_12 | |
1701 | IP12_11_8 | |
1702 | IP12_7_4 | |
1703 | IP12_3_0 } | |
1704 | }, | |
1705 | { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { | |
1706 | /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1707 | /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1708 | /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1709 | /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1710 | /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1711 | /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1712 | IP13_7_4 | |
1713 | IP13_3_0 } | |
1714 | }, | |
1715 | #undef F_ | |
1716 | #undef FM | |
1717 | ||
1718 | #define F_(x, y) x, | |
1719 | #define FM(x) FN_##x, | |
1720 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, | |
1721 | 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, | |
1722 | 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { | |
1723 | /* RESERVED 31 */ | |
1724 | 0, 0, | |
1725 | MOD_SEL0_30 | |
1726 | MOD_SEL0_29 | |
1727 | MOD_SEL0_28 | |
1728 | MOD_SEL0_27 | |
1729 | MOD_SEL0_26 | |
1730 | MOD_SEL0_25 | |
1731 | MOD_SEL0_24_23 | |
1732 | MOD_SEL0_22_21 | |
1733 | MOD_SEL0_20_19 | |
1734 | MOD_SEL0_18_17 | |
1735 | /* RESERVED 16 */ | |
1736 | 0, 0, | |
1737 | MOD_SEL0_15 | |
1738 | MOD_SEL0_14 | |
1739 | MOD_SEL0_13 | |
1740 | MOD_SEL0_12 | |
1741 | MOD_SEL0_11 | |
1742 | MOD_SEL0_10 | |
1743 | /* RESERVED 9, 8, 7, 6 */ | |
1744 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1745 | MOD_SEL0_5 | |
1746 | MOD_SEL0_4 | |
1747 | MOD_SEL0_3 | |
1748 | MOD_SEL0_2 | |
1749 | MOD_SEL0_1 | |
1750 | MOD_SEL0_0 } | |
1751 | }, | |
1752 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, | |
1753 | 1, 1, 1, 1, 1, 1, 2, 4, 4, | |
1754 | 4, 4, 4, 4) { | |
1755 | MOD_SEL1_31 | |
1756 | MOD_SEL1_30 | |
1757 | MOD_SEL1_29 | |
1758 | MOD_SEL1_28 | |
1759 | MOD_SEL1_27 | |
1760 | MOD_SEL1_26 | |
1761 | /* RESERVED 25, 24 */ | |
1762 | 0, 0, 0, 0, | |
1763 | /* RESERVED 23, 22, 21, 20 */ | |
1764 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1765 | /* RESERVED 19, 18, 17, 16 */ | |
1766 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1767 | /* RESERVED 15, 14, 13, 12 */ | |
1768 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1769 | /* RESERVED 11, 10, 9, 8 */ | |
1770 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1771 | /* RESERVED 7, 6, 5, 4 */ | |
1772 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
1773 | /* RESERVED 3, 2, 1, 0 */ | |
1774 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | |
1775 | }, | |
1776 | { }, | |
1777 | }; | |
1778 | ||
1779 | static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) | |
1780 | { | |
1781 | int bit = -EINVAL; | |
1782 | ||
1783 | *pocctrl = 0xe6060380; | |
1784 | ||
1785 | if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) | |
1786 | bit = 29 - (pin - RCAR_GP_PIN(3, 0)); | |
1787 | ||
1788 | return bit; | |
1789 | } | |
1790 | ||
1791 | static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { | |
1792 | .pin_to_pocctrl = r8a77995_pin_to_pocctrl, | |
1793 | }; | |
1794 | ||
1795 | const struct sh_pfc_soc_info r8a77995_pinmux_info = { | |
1796 | .name = "r8a77995_pfc", | |
1797 | .ops = &r8a77995_pinmux_ops, | |
1798 | .unlock_reg = 0xe6060000, /* PMMR */ | |
1799 | ||
1800 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
1801 | ||
1802 | .pins = pinmux_pins, | |
1803 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
1804 | .groups = pinmux_groups, | |
1805 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
1806 | .functions = pinmux_functions, | |
1807 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
1808 | ||
1809 | .cfg_regs = pinmux_config_regs, | |
1810 | ||
1811 | .pinmux_data = pinmux_data, | |
1812 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
1813 | }; |