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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
a59e6976 MV |
2 | /* |
3 | * R8A77995 processor support - PFC hardware block. | |
4 | * | |
5 | * Copyright (C) 2017 Renesas Electronics Corp. | |
6 | * | |
7 | * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c | |
8 | * | |
9 | * R-Car Gen3 processor support - PFC hardware block. | |
10 | * | |
11 | * Copyright (C) 2015 Renesas Electronics Corporation | |
a59e6976 MV |
12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <dm.h> | |
16 | #include <errno.h> | |
17 | #include <dm/pinctrl.h> | |
18 | #include <linux/kernel.h> | |
19 | ||
20 | #include "sh_pfc.h" | |
21 | ||
22 | #define CPU_ALL_PORT(fn, sfx) \ | |
23 | PORT_GP_9(0, fn, sfx), \ | |
24 | PORT_GP_32(1, fn, sfx), \ | |
25 | PORT_GP_32(2, fn, sfx), \ | |
26 | PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ | |
27 | PORT_GP_32(4, fn, sfx), \ | |
28 | PORT_GP_21(5, fn, sfx), \ | |
29 | PORT_GP_14(6, fn, sfx) | |
30 | ||
31 | /* | |
32 | * F_() : just information | |
33 | * FM() : macro for FN_xxx / xxx_MARK | |
34 | */ | |
35 | ||
36 | /* GPSR0 */ | |
37 | #define GPSR0_8 F_(MLB_SIG, IP0_27_24) | |
38 | #define GPSR0_7 F_(MLB_DAT, IP0_23_20) | |
39 | #define GPSR0_6 F_(MLB_CLK, IP0_19_16) | |
40 | #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) | |
41 | #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) | |
42 | #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) | |
43 | #define GPSR0_2 F_(IRQ0_A, IP0_3_0) | |
44 | #define GPSR0_1 FM(USB0_OVC) | |
45 | #define GPSR0_0 FM(USB0_PWEN) | |
46 | ||
47 | /* GPSR1 */ | |
48 | #define GPSR1_31 F_(QPOLB, IP4_27_24) | |
49 | #define GPSR1_30 F_(QPOLA, IP4_23_20) | |
50 | #define GPSR1_29 F_(DU_CDE, IP4_19_16) | |
51 | #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) | |
52 | #define GPSR1_27 F_(DU_DISP, IP4_11_8) | |
53 | #define GPSR1_26 F_(DU_VSYNC, IP4_7_4) | |
54 | #define GPSR1_25 F_(DU_HSYNC, IP4_3_0) | |
55 | #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) | |
56 | #define GPSR1_23 F_(DU_DR7, IP3_27_24) | |
57 | #define GPSR1_22 F_(DU_DR6, IP3_23_20) | |
58 | #define GPSR1_21 F_(DU_DR5, IP3_19_16) | |
59 | #define GPSR1_20 F_(DU_DR4, IP3_15_12) | |
60 | #define GPSR1_19 F_(DU_DR3, IP3_11_8) | |
61 | #define GPSR1_18 F_(DU_DR2, IP3_7_4) | |
62 | #define GPSR1_17 F_(DU_DR1, IP3_3_0) | |
63 | #define GPSR1_16 F_(DU_DR0, IP2_31_28) | |
64 | #define GPSR1_15 F_(DU_DG7, IP2_27_24) | |
65 | #define GPSR1_14 F_(DU_DG6, IP2_23_20) | |
66 | #define GPSR1_13 F_(DU_DG5, IP2_19_16) | |
67 | #define GPSR1_12 F_(DU_DG4, IP2_15_12) | |
68 | #define GPSR1_11 F_(DU_DG3, IP2_11_8) | |
69 | #define GPSR1_10 F_(DU_DG2, IP2_7_4) | |
70 | #define GPSR1_9 F_(DU_DG1, IP2_3_0) | |
71 | #define GPSR1_8 F_(DU_DG0, IP1_31_28) | |
72 | #define GPSR1_7 F_(DU_DB7, IP1_27_24) | |
73 | #define GPSR1_6 F_(DU_DB6, IP1_23_20) | |
74 | #define GPSR1_5 F_(DU_DB5, IP1_19_16) | |
75 | #define GPSR1_4 F_(DU_DB4, IP1_15_12) | |
76 | #define GPSR1_3 F_(DU_DB3, IP1_11_8) | |
77 | #define GPSR1_2 F_(DU_DB2, IP1_7_4) | |
78 | #define GPSR1_1 F_(DU_DB1, IP1_3_0) | |
79 | #define GPSR1_0 F_(DU_DB0, IP0_31_28) | |
80 | ||
81 | /* GPSR2 */ | |
82 | #define GPSR2_31 F_(NFCE_N, IP8_19_16) | |
83 | #define GPSR2_30 F_(NFCLE, IP8_15_12) | |
84 | #define GPSR2_29 F_(NFALE, IP8_11_8) | |
85 | #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) | |
86 | #define GPSR2_27 F_(VI4_FIELD, IP8_3_0) | |
87 | #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) | |
88 | #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) | |
89 | #define GPSR2_24 F_(VI4_DATA23, IP7_23_20) | |
90 | #define GPSR2_23 F_(VI4_DATA22, IP7_19_16) | |
91 | #define GPSR2_22 F_(VI4_DATA21, IP7_15_12) | |
92 | #define GPSR2_21 F_(VI4_DATA20, IP7_11_8) | |
93 | #define GPSR2_20 F_(VI4_DATA19, IP7_7_4) | |
94 | #define GPSR2_19 F_(VI4_DATA18, IP7_3_0) | |
95 | #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) | |
96 | #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) | |
97 | #define GPSR2_16 F_(VI4_DATA15, IP6_23_20) | |
98 | #define GPSR2_15 F_(VI4_DATA14, IP6_19_16) | |
99 | #define GPSR2_14 F_(VI4_DATA13, IP6_15_12) | |
100 | #define GPSR2_13 F_(VI4_DATA12, IP6_11_8) | |
101 | #define GPSR2_12 F_(VI4_DATA11, IP6_7_4) | |
102 | #define GPSR2_11 F_(VI4_DATA10, IP6_3_0) | |
103 | #define GPSR2_10 F_(VI4_DATA9, IP5_31_28) | |
104 | #define GPSR2_9 F_(VI4_DATA8, IP5_27_24) | |
105 | #define GPSR2_8 F_(VI4_DATA7, IP5_23_20) | |
106 | #define GPSR2_7 F_(VI4_DATA6, IP5_19_16) | |
107 | #define GPSR2_6 F_(VI4_DATA5, IP5_15_12) | |
108 | #define GPSR2_5 FM(VI4_DATA4) | |
109 | #define GPSR2_4 F_(VI4_DATA3, IP5_11_8) | |
110 | #define GPSR2_3 F_(VI4_DATA2, IP5_7_4) | |
111 | #define GPSR2_2 F_(VI4_DATA1, IP5_3_0) | |
112 | #define GPSR2_1 F_(VI4_DATA0, IP4_31_28) | |
113 | #define GPSR2_0 FM(VI4_CLK) | |
114 | ||
115 | /* GPSR3 */ | |
116 | #define GPSR3_9 F_(NFDATA7, IP9_31_28) | |
117 | #define GPSR3_8 F_(NFDATA6, IP9_27_24) | |
118 | #define GPSR3_7 F_(NFDATA5, IP9_23_20) | |
119 | #define GPSR3_6 F_(NFDATA4, IP9_19_16) | |
120 | #define GPSR3_5 F_(NFDATA3, IP9_15_12) | |
121 | #define GPSR3_4 F_(NFDATA2, IP9_11_8) | |
122 | #define GPSR3_3 F_(NFDATA1, IP9_7_4) | |
123 | #define GPSR3_2 F_(NFDATA0, IP9_3_0) | |
124 | #define GPSR3_1 F_(NFWE_N, IP8_31_28) | |
125 | #define GPSR3_0 F_(NFRE_N, IP8_27_24) | |
126 | ||
127 | /* GPSR4 */ | |
128 | #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) | |
129 | #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) | |
130 | #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) | |
131 | #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) | |
132 | #define GPSR4_27 FM(TX2) | |
133 | #define GPSR4_26 FM(RX2) | |
134 | #define GPSR4_25 F_(SCK2, IP12_11_8) | |
135 | #define GPSR4_24 F_(TX1_A, IP12_7_4) | |
136 | #define GPSR4_23 F_(RX1_A, IP12_3_0) | |
137 | #define GPSR4_22 F_(SCK1_A, IP11_31_28) | |
138 | #define GPSR4_21 F_(TX0_A, IP11_27_24) | |
139 | #define GPSR4_20 F_(RX0_A, IP11_23_20) | |
140 | #define GPSR4_19 F_(SCK0_A, IP11_19_16) | |
141 | #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) | |
142 | #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) | |
143 | #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) | |
144 | #define GPSR4_15 FM(MSIOF0_RXD) | |
145 | #define GPSR4_14 FM(MSIOF0_TXD) | |
146 | #define GPSR4_13 FM(MSIOF0_SYNC) | |
147 | #define GPSR4_12 FM(MSIOF0_SCK) | |
148 | #define GPSR4_11 F_(SDA1, IP11_3_0) | |
149 | #define GPSR4_10 F_(SCL1, IP10_31_28) | |
150 | #define GPSR4_9 FM(SDA0) | |
151 | #define GPSR4_8 FM(SCL0) | |
152 | #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) | |
153 | #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) | |
154 | #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) | |
155 | #define GPSR4_4 F_(SSI_WS34, IP10_15_12) | |
156 | #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) | |
157 | #define GPSR4_2 F_(SSI_SCK34, IP10_7_4) | |
158 | #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) | |
159 | #define GPSR4_0 F_(NFRB_N, IP8_23_20) | |
160 | ||
161 | /* GPSR5 */ | |
162 | #define GPSR5_20 FM(AVB0_LINK) | |
163 | #define GPSR5_19 FM(AVB0_PHY_INT) | |
164 | #define GPSR5_18 FM(AVB0_MAGIC) | |
165 | #define GPSR5_17 FM(AVB0_MDC) | |
166 | #define GPSR5_16 FM(AVB0_MDIO) | |
167 | #define GPSR5_15 FM(AVB0_TXCREFCLK) | |
168 | #define GPSR5_14 FM(AVB0_TD3) | |
169 | #define GPSR5_13 FM(AVB0_TD2) | |
170 | #define GPSR5_12 FM(AVB0_TD1) | |
171 | #define GPSR5_11 FM(AVB0_TD0) | |
172 | #define GPSR5_10 FM(AVB0_TXC) | |
173 | #define GPSR5_9 FM(AVB0_TX_CTL) | |
174 | #define GPSR5_8 FM(AVB0_RD3) | |
175 | #define GPSR5_7 FM(AVB0_RD2) | |
176 | #define GPSR5_6 FM(AVB0_RD1) | |
177 | #define GPSR5_5 FM(AVB0_RD0) | |
178 | #define GPSR5_4 FM(AVB0_RXC) | |
179 | #define GPSR5_3 FM(AVB0_RX_CTL) | |
180 | #define GPSR5_2 F_(CAN_CLK, IP12_23_20) | |
181 | #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) | |
182 | #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) | |
183 | ||
184 | /* GPSR6 */ | |
185 | #define GPSR6_13 FM(RPC_INT_N) | |
186 | #define GPSR6_12 FM(RPC_RESET_N) | |
187 | #define GPSR6_11 FM(QSPI1_SSL) | |
188 | #define GPSR6_10 FM(QSPI1_IO3) | |
189 | #define GPSR6_9 FM(QSPI1_IO2) | |
190 | #define GPSR6_8 FM(QSPI1_MISO_IO1) | |
191 | #define GPSR6_7 FM(QSPI1_MOSI_IO0) | |
192 | #define GPSR6_6 FM(QSPI1_SPCLK) | |
193 | #define GPSR6_5 FM(QSPI0_SSL) | |
194 | #define GPSR6_4 FM(QSPI0_IO3) | |
195 | #define GPSR6_3 FM(QSPI0_IO2) | |
196 | #define GPSR6_2 FM(QSPI0_MISO_IO1) | |
197 | #define GPSR6_1 FM(QSPI0_MOSI_IO0) | |
198 | #define GPSR6_0 FM(QSPI0_SPCLK) | |
199 | ||
200 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
bf8d2dab MV |
201 | #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
202 | #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
a59e6976 MV |
203 | #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
204 | #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
205 | #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
206 | #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
207 | #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
208 | #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
209 | #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
210 | #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
211 | #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
212 | #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
213 | #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
214 | #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
215 | #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
216 | #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
217 | #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
218 | #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
219 | #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
220 | #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
221 | #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
222 | #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
223 | #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
224 | #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
225 | #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
226 | #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
227 | #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
228 | #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
229 | #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
230 | #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
231 | #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
232 | #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
233 | ||
234 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
235 | #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
236 | #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
237 | #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
238 | #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
239 | #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
240 | #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
241 | #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
242 | #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
243 | #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
244 | #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
245 | #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
246 | #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
247 | #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
248 | #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
249 | #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
250 | #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
251 | #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
252 | #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
253 | #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
254 | #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
255 | #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
256 | #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
257 | #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
258 | #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
259 | #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
260 | #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
261 | #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
262 | #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
263 | #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
264 | #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
265 | #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
266 | #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
267 | ||
268 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
269 | #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
270 | #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
271 | #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
272 | #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
273 | #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
274 | #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
275 | #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
276 | #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
277 | #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
278 | #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
279 | #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
280 | #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
281 | #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
282 | #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
283 | #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
284 | #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
285 | #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
286 | #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
287 | #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
288 | #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
289 | #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
290 | #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
291 | #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
292 | #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
293 | #define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
294 | #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
295 | #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
296 | #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
297 | #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
298 | #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
299 | #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
300 | #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
301 | ||
302 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ | |
303 | #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
304 | #define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
305 | #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
306 | #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
307 | #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
308 | #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
309 | #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
310 | #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
311 | #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
312 | #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) | |
313 | ||
314 | #define PINMUX_GPSR \ | |
315 | \ | |
316 | GPSR1_31 GPSR2_31 GPSR4_31 \ | |
317 | GPSR1_30 GPSR2_30 GPSR4_30 \ | |
318 | GPSR1_29 GPSR2_29 GPSR4_29 \ | |
319 | GPSR1_28 GPSR2_28 GPSR4_28 \ | |
320 | GPSR1_27 GPSR2_27 GPSR4_27 \ | |
321 | GPSR1_26 GPSR2_26 GPSR4_26 \ | |
322 | GPSR1_25 GPSR2_25 GPSR4_25 \ | |
323 | GPSR1_24 GPSR2_24 GPSR4_24 \ | |
324 | GPSR1_23 GPSR2_23 GPSR4_23 \ | |
325 | GPSR1_22 GPSR2_22 GPSR4_22 \ | |
326 | GPSR1_21 GPSR2_21 GPSR4_21 \ | |
327 | GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ | |
328 | GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ | |
329 | GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ | |
330 | GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ | |
331 | GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ | |
332 | GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ | |
333 | GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ | |
334 | GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ | |
335 | GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ | |
336 | GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ | |
337 | GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ | |
338 | GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ | |
339 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ | |
340 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ | |
341 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ | |
342 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ | |
343 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ | |
344 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ | |
345 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ | |
346 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ | |
347 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 | |
348 | ||
349 | #define PINMUX_IPSR \ | |
350 | \ | |
351 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ | |
352 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ | |
353 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ | |
354 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ | |
355 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ | |
356 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ | |
357 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ | |
358 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ | |
359 | \ | |
360 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ | |
361 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ | |
362 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ | |
363 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ | |
364 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ | |
365 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ | |
366 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ | |
367 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ | |
368 | \ | |
369 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ | |
370 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ | |
371 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ | |
372 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ | |
373 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ | |
374 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ | |
375 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ | |
376 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ | |
377 | \ | |
378 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ | |
379 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ | |
380 | FM(IP12_11_8) IP12_11_8 \ | |
381 | FM(IP12_15_12) IP12_15_12 \ | |
382 | FM(IP12_19_16) IP12_19_16 \ | |
383 | FM(IP12_23_20) IP12_23_20 \ | |
384 | FM(IP12_27_24) IP12_27_24 \ | |
385 | FM(IP12_31_28) IP12_31_28 \ | |
386 | ||
8719ca81 MV |
387 | /* The bit numbering in MOD_SEL fields is reversed */ |
388 | #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 | |
389 | ||
a59e6976 MV |
390 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ |
391 | #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) | |
392 | #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) | |
393 | #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) | |
394 | #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) | |
395 | #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) | |
396 | #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) | |
8719ca81 MV |
397 | #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0)) |
398 | #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0)) | |
399 | #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) | |
400 | #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) | |
a59e6976 MV |
401 | #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) |
402 | #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) | |
403 | #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) | |
404 | #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) | |
405 | #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) | |
406 | #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) | |
407 | #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) | |
408 | #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) | |
409 | #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) | |
410 | #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) | |
411 | #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) | |
412 | #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) | |
413 | ||
414 | #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) | |
415 | #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) | |
416 | #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) | |
417 | #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) | |
418 | #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) | |
419 | #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) | |
420 | ||
421 | ||
422 | #define PINMUX_MOD_SELS \ | |
423 | \ | |
424 | MOD_SEL1_31 \ | |
425 | MOD_SEL0_30 MOD_SEL1_30 \ | |
426 | MOD_SEL0_29 MOD_SEL1_29 \ | |
427 | MOD_SEL0_28 MOD_SEL1_28 \ | |
428 | MOD_SEL0_27 MOD_SEL1_27 \ | |
429 | MOD_SEL0_26 MOD_SEL1_26 \ | |
430 | MOD_SEL0_25 \ | |
431 | MOD_SEL0_24_23 \ | |
432 | MOD_SEL0_22_21 \ | |
433 | MOD_SEL0_20_19 \ | |
434 | MOD_SEL0_18_17 \ | |
435 | MOD_SEL0_15 \ | |
436 | MOD_SEL0_14 \ | |
437 | MOD_SEL0_13 \ | |
438 | MOD_SEL0_12 \ | |
439 | MOD_SEL0_11 \ | |
440 | MOD_SEL0_10 \ | |
441 | MOD_SEL0_5 \ | |
442 | MOD_SEL0_4 \ | |
443 | MOD_SEL0_3 \ | |
444 | MOD_SEL0_2 \ | |
445 | MOD_SEL0_1 \ | |
446 | MOD_SEL0_0 | |
447 | ||
448 | enum { | |
449 | PINMUX_RESERVED = 0, | |
450 | ||
451 | PINMUX_DATA_BEGIN, | |
452 | GP_ALL(DATA), | |
453 | PINMUX_DATA_END, | |
454 | ||
455 | #define F_(x, y) | |
456 | #define FM(x) FN_##x, | |
457 | PINMUX_FUNCTION_BEGIN, | |
458 | GP_ALL(FN), | |
459 | PINMUX_GPSR | |
460 | PINMUX_IPSR | |
461 | PINMUX_MOD_SELS | |
462 | PINMUX_FUNCTION_END, | |
463 | #undef F_ | |
464 | #undef FM | |
465 | ||
466 | #define F_(x, y) | |
467 | #define FM(x) x##_MARK, | |
468 | PINMUX_MARK_BEGIN, | |
469 | PINMUX_GPSR | |
470 | PINMUX_IPSR | |
471 | PINMUX_MOD_SELS | |
472 | PINMUX_MARK_END, | |
473 | #undef F_ | |
474 | #undef FM | |
475 | }; | |
476 | ||
a59e6976 MV |
477 | static const u16 pinmux_data[] = { |
478 | PINMUX_DATA_GP_ALL(), | |
479 | ||
480 | PINMUX_SINGLE(USB0_OVC), | |
481 | PINMUX_SINGLE(USB0_PWEN), | |
482 | PINMUX_SINGLE(VI4_DATA4), | |
483 | PINMUX_SINGLE(VI4_CLK), | |
484 | PINMUX_SINGLE(TX2), | |
485 | PINMUX_SINGLE(RX2), | |
486 | PINMUX_SINGLE(AVB0_LINK), | |
487 | PINMUX_SINGLE(AVB0_PHY_INT), | |
488 | PINMUX_SINGLE(AVB0_MAGIC), | |
489 | PINMUX_SINGLE(AVB0_MDC), | |
490 | PINMUX_SINGLE(AVB0_MDIO), | |
491 | PINMUX_SINGLE(AVB0_TXCREFCLK), | |
492 | PINMUX_SINGLE(AVB0_TD3), | |
493 | PINMUX_SINGLE(AVB0_TD2), | |
494 | PINMUX_SINGLE(AVB0_TD1), | |
495 | PINMUX_SINGLE(AVB0_TD0), | |
496 | PINMUX_SINGLE(AVB0_TXC), | |
497 | PINMUX_SINGLE(AVB0_TX_CTL), | |
498 | PINMUX_SINGLE(AVB0_RD3), | |
499 | PINMUX_SINGLE(AVB0_RD2), | |
500 | PINMUX_SINGLE(AVB0_RD1), | |
501 | PINMUX_SINGLE(AVB0_RD0), | |
502 | PINMUX_SINGLE(AVB0_RXC), | |
503 | PINMUX_SINGLE(AVB0_RX_CTL), | |
504 | PINMUX_SINGLE(RPC_INT_N), | |
505 | PINMUX_SINGLE(RPC_RESET_N), | |
506 | PINMUX_SINGLE(QSPI1_SSL), | |
507 | PINMUX_SINGLE(QSPI1_IO3), | |
508 | PINMUX_SINGLE(QSPI1_IO2), | |
509 | PINMUX_SINGLE(QSPI1_MISO_IO1), | |
510 | PINMUX_SINGLE(QSPI1_MOSI_IO0), | |
511 | PINMUX_SINGLE(QSPI1_SPCLK), | |
512 | PINMUX_SINGLE(QSPI0_SSL), | |
513 | PINMUX_SINGLE(QSPI0_IO3), | |
514 | PINMUX_SINGLE(QSPI0_IO2), | |
515 | PINMUX_SINGLE(QSPI0_MISO_IO1), | |
516 | PINMUX_SINGLE(QSPI0_MOSI_IO0), | |
517 | PINMUX_SINGLE(QSPI0_SPCLK), | |
bf8d2dab MV |
518 | PINMUX_SINGLE(SCL0), |
519 | PINMUX_SINGLE(SDA0), | |
8719ca81 MV |
520 | PINMUX_SINGLE(MSIOF0_RXD), |
521 | PINMUX_SINGLE(MSIOF0_TXD), | |
522 | PINMUX_SINGLE(MSIOF0_SYNC), | |
523 | PINMUX_SINGLE(MSIOF0_SCK), | |
a59e6976 MV |
524 | |
525 | /* IPSR0 */ | |
526 | PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), | |
527 | PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), | |
a59e6976 MV |
528 | |
529 | PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), | |
a59e6976 MV |
530 | |
531 | PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), | |
532 | PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), | |
533 | ||
534 | PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), | |
535 | PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), | |
536 | ||
537 | PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), | |
538 | PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), | |
539 | PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), | |
540 | ||
541 | PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), | |
542 | PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), | |
543 | PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), | |
544 | PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), | |
545 | ||
546 | PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), | |
547 | PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), | |
548 | PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), | |
549 | PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), | |
550 | ||
551 | PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), | |
552 | PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), | |
553 | PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), | |
554 | ||
555 | /* IPSR1 */ | |
556 | PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), | |
557 | PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), | |
558 | PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), | |
559 | ||
560 | PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), | |
561 | PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), | |
562 | PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), | |
563 | ||
564 | PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), | |
565 | PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), | |
566 | PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), | |
567 | ||
568 | PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), | |
569 | PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), | |
570 | PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), | |
571 | ||
572 | PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), | |
573 | PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), | |
574 | PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), | |
575 | ||
576 | PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), | |
577 | PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), | |
578 | PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), | |
579 | ||
580 | PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), | |
581 | PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), | |
582 | PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), | |
583 | ||
584 | PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), | |
585 | PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), | |
586 | PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), | |
587 | ||
588 | /* IPSR2 */ | |
589 | PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), | |
590 | PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), | |
591 | PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), | |
592 | ||
593 | PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), | |
594 | PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), | |
595 | ||
596 | PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), | |
597 | PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), | |
598 | PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), | |
599 | ||
600 | PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), | |
601 | PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), | |
602 | PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), | |
603 | ||
604 | PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), | |
605 | PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), | |
606 | PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), | |
607 | ||
608 | PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), | |
609 | PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), | |
610 | PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), | |
611 | ||
612 | PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), | |
613 | PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), | |
614 | PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), | |
615 | ||
616 | PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), | |
617 | PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), | |
618 | PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), | |
619 | ||
620 | /* IPSR3 */ | |
621 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), | |
622 | PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), | |
623 | PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), | |
624 | ||
625 | PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), | |
626 | PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), | |
627 | PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), | |
628 | ||
629 | PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), | |
630 | PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), | |
631 | PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), | |
632 | ||
633 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), | |
634 | PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), | |
635 | PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), | |
636 | ||
637 | PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), | |
638 | PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), | |
639 | PINMUX_IPSR_GPSR(IP3_19_16, NMI), | |
640 | ||
641 | PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), | |
642 | PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), | |
643 | PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), | |
644 | ||
645 | PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), | |
646 | PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), | |
647 | PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), | |
648 | ||
649 | PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), | |
650 | PINMUX_IPSR_GPSR(IP3_31_28, QCLK), | |
651 | ||
652 | /* IPSR4 */ | |
653 | PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), | |
654 | PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), | |
655 | PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), | |
656 | ||
657 | PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), | |
658 | PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), | |
659 | PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), | |
660 | ||
661 | PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), | |
662 | PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), | |
663 | PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), | |
664 | ||
665 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), | |
666 | PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), | |
667 | PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), | |
668 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), | |
669 | ||
670 | PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), | |
671 | PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), | |
672 | PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), | |
673 | ||
674 | PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), | |
675 | PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), | |
676 | ||
677 | PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), | |
678 | PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), | |
679 | ||
680 | PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), | |
681 | PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), | |
682 | ||
683 | /* IPSR5 */ | |
684 | PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), | |
685 | PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), | |
686 | ||
687 | PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), | |
688 | PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), | |
689 | ||
690 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), | |
691 | PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), | |
692 | ||
693 | PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), | |
694 | PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), | |
695 | ||
696 | PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), | |
697 | PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), | |
698 | ||
699 | PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), | |
700 | PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), | |
701 | ||
702 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), | |
703 | ||
704 | PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), | |
705 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), | |
706 | PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), | |
707 | ||
708 | /* IPSR6 */ | |
709 | PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), | |
710 | PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), | |
711 | ||
712 | PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), | |
713 | PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), | |
714 | ||
715 | PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), | |
716 | PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), | |
717 | ||
718 | PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), | |
719 | PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), | |
720 | PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), | |
721 | ||
722 | PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), | |
723 | PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), | |
724 | PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), | |
725 | ||
726 | PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), | |
727 | PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), | |
728 | ||
729 | PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), | |
730 | PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), | |
731 | ||
732 | PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), | |
733 | PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), | |
734 | ||
735 | /* IPSR7 */ | |
736 | PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), | |
737 | PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), | |
738 | ||
739 | PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), | |
740 | PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), | |
741 | PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), | |
742 | ||
743 | PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), | |
744 | PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), | |
745 | PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), | |
746 | ||
747 | PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), | |
748 | PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), | |
749 | ||
750 | PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), | |
751 | PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), | |
752 | PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), | |
753 | ||
754 | PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), | |
755 | PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), | |
756 | PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), | |
757 | ||
758 | PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), | |
759 | ||
760 | PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), | |
761 | PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), | |
762 | PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), | |
763 | ||
764 | PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), | |
765 | PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), | |
766 | PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), | |
767 | ||
768 | /* IPSR8 */ | |
769 | PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), | |
770 | PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), | |
771 | PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), | |
772 | PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), | |
773 | PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), | |
774 | ||
775 | PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), | |
776 | PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), | |
777 | PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), | |
778 | PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), | |
779 | ||
780 | PINMUX_IPSR_GPSR(IP8_11_8, NFALE), | |
781 | PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), | |
782 | PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), | |
783 | PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), | |
784 | ||
785 | PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), | |
786 | PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), | |
787 | PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), | |
788 | PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), | |
789 | ||
790 | PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), | |
791 | PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), | |
792 | PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), | |
793 | ||
794 | PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), | |
795 | PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), | |
796 | PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), | |
797 | ||
798 | PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), | |
799 | PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), | |
800 | ||
801 | PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), | |
802 | PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), | |
803 | ||
804 | /* IPSR9 */ | |
805 | PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), | |
806 | PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), | |
807 | ||
808 | PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), | |
809 | PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), | |
810 | ||
811 | PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), | |
812 | PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), | |
813 | ||
814 | PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), | |
815 | PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), | |
816 | ||
817 | PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), | |
818 | PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), | |
819 | ||
820 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), | |
821 | PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), | |
822 | ||
823 | PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), | |
824 | PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), | |
825 | ||
826 | PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), | |
827 | PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), | |
828 | ||
829 | /* IPSR10 */ | |
830 | PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), | |
831 | PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), | |
832 | ||
833 | PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), | |
834 | PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), | |
835 | ||
836 | PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), | |
837 | PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), | |
838 | ||
839 | PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), | |
840 | PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), | |
841 | ||
842 | PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), | |
843 | PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), | |
844 | PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), | |
845 | PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), | |
846 | PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), | |
847 | ||
848 | PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), | |
849 | PINMUX_IPSR_GPSR(IP10_23_20, HTX0), | |
850 | PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), | |
851 | PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), | |
852 | ||
853 | PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), | |
854 | PINMUX_IPSR_GPSR(IP10_27_24, HRX0), | |
855 | PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), | |
856 | PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), | |
857 | ||
858 | PINMUX_IPSR_GPSR(IP10_31_28, SCL1), | |
859 | PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), | |
860 | ||
861 | /* IPSR11 */ | |
862 | PINMUX_IPSR_GPSR(IP11_3_0, SDA1), | |
863 | PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), | |
864 | ||
865 | PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), | |
866 | PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), | |
867 | ||
868 | PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), | |
869 | PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), | |
870 | ||
871 | PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), | |
872 | PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), | |
873 | ||
874 | PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), | |
875 | PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), | |
876 | PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), | |
877 | ||
878 | PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), | |
879 | PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), | |
880 | PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), | |
881 | ||
882 | PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), | |
883 | PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), | |
884 | PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), | |
885 | ||
886 | PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), | |
887 | PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), | |
888 | PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), | |
889 | PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), | |
890 | PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), | |
891 | ||
892 | /* IPSR12 */ | |
893 | PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), | |
894 | PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), | |
895 | PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), | |
896 | ||
897 | PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), | |
898 | PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), | |
899 | PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), | |
900 | ||
901 | PINMUX_IPSR_GPSR(IP12_11_8, SCK2), | |
902 | PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), | |
903 | PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), | |
904 | ||
905 | PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), | |
906 | PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), | |
907 | PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), | |
908 | ||
909 | PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), | |
910 | PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), | |
911 | PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), | |
912 | ||
913 | PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), | |
914 | PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), | |
915 | PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), | |
916 | PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), | |
917 | ||
918 | PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), | |
919 | PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), | |
920 | PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), | |
921 | ||
922 | PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), | |
923 | PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), | |
924 | PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), | |
925 | ||
926 | /* IPSR13 */ | |
927 | PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), | |
928 | PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), | |
929 | PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), | |
930 | ||
931 | PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), | |
932 | PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), | |
933 | PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), | |
934 | }; | |
935 | ||
936 | static const struct sh_pfc_pin pinmux_pins[] = { | |
937 | PINMUX_GPIO_GP_ALL(), | |
938 | }; | |
939 | ||
bf8d2dab MV |
940 | /* - AUDIO CLOCK ------------------------------------------------------------- */ |
941 | static const unsigned int audio_clk_a_pins[] = { | |
942 | /* CLK A */ | |
943 | RCAR_GP_PIN(4, 1), | |
944 | }; | |
945 | static const unsigned int audio_clk_a_mux[] = { | |
946 | AUDIO_CLKA_MARK, | |
947 | }; | |
948 | static const unsigned int audio_clk_b_pins[] = { | |
949 | /* CLK B */ | |
950 | RCAR_GP_PIN(2, 27), | |
951 | }; | |
952 | static const unsigned int audio_clk_b_mux[] = { | |
953 | AUDIO_CLKB_MARK, | |
954 | }; | |
955 | static const unsigned int audio_clkout_pins[] = { | |
956 | /* CLKOUT */ | |
957 | RCAR_GP_PIN(4, 5), | |
958 | }; | |
959 | static const unsigned int audio_clkout_mux[] = { | |
960 | AUDIO_CLKOUT_MARK, | |
961 | }; | |
962 | static const unsigned int audio_clkout1_pins[] = { | |
963 | /* CLKOUT1 */ | |
964 | RCAR_GP_PIN(4, 22), | |
965 | }; | |
966 | static const unsigned int audio_clkout1_mux[] = { | |
967 | AUDIO_CLKOUT1_MARK, | |
968 | }; | |
969 | ||
970 | /* - EtherAVB --------------------------------------------------------------- */ | |
971 | static const unsigned int avb0_link_pins[] = { | |
972 | /* AVB0_LINK */ | |
973 | RCAR_GP_PIN(5, 20), | |
974 | }; | |
975 | static const unsigned int avb0_link_mux[] = { | |
976 | AVB0_LINK_MARK, | |
977 | }; | |
978 | static const unsigned int avb0_magic_pins[] = { | |
979 | /* AVB0_MAGIC */ | |
980 | RCAR_GP_PIN(5, 18), | |
981 | }; | |
982 | static const unsigned int avb0_magic_mux[] = { | |
983 | AVB0_MAGIC_MARK, | |
984 | }; | |
985 | static const unsigned int avb0_phy_int_pins[] = { | |
986 | /* AVB0_PHY_INT */ | |
987 | RCAR_GP_PIN(5, 19), | |
988 | }; | |
989 | static const unsigned int avb0_phy_int_mux[] = { | |
990 | AVB0_PHY_INT_MARK, | |
991 | }; | |
992 | static const unsigned int avb0_mdio_pins[] = { | |
993 | /* AVB0_MDC, AVB0_MDIO */ | |
994 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16), | |
995 | }; | |
996 | static const unsigned int avb0_mdio_mux[] = { | |
997 | AVB0_MDC_MARK, AVB0_MDIO_MARK, | |
998 | }; | |
999 | static const unsigned int avb0_mii_pins[] = { | |
1000 | /* | |
1001 | * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, | |
1002 | * AVB0_TD1, AVB0_TD2, AVB0_TD3, | |
1003 | * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, | |
1004 | * AVB0_RD1, AVB0_RD2, AVB0_RD3, | |
1005 | * AVB0_TXCREFCLK | |
1006 | */ | |
1007 | RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), | |
1008 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), | |
1009 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), | |
1010 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), | |
1011 | RCAR_GP_PIN(5, 15), | |
1012 | }; | |
1013 | static const unsigned int avb0_mii_mux[] = { | |
1014 | AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK, | |
1015 | AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, | |
1016 | AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK, | |
1017 | AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, | |
1018 | AVB0_TXCREFCLK_MARK, | |
1019 | }; | |
1020 | static const unsigned int avb0_avtp_pps_a_pins[] = { | |
1021 | /* AVB0_AVTP_PPS_A */ | |
1022 | RCAR_GP_PIN(5, 2), | |
1023 | }; | |
1024 | static const unsigned int avb0_avtp_pps_a_mux[] = { | |
1025 | AVB0_AVTP_PPS_A_MARK, | |
1026 | }; | |
1027 | static const unsigned int avb0_avtp_match_a_pins[] = { | |
1028 | /* AVB0_AVTP_MATCH_A */ | |
1029 | RCAR_GP_PIN(5, 1), | |
1030 | }; | |
1031 | static const unsigned int avb0_avtp_match_a_mux[] = { | |
1032 | AVB0_AVTP_MATCH_A_MARK, | |
1033 | }; | |
1034 | static const unsigned int avb0_avtp_capture_a_pins[] = { | |
1035 | /* AVB0_AVTP_CAPTURE_A */ | |
1036 | RCAR_GP_PIN(5, 0), | |
1037 | }; | |
1038 | static const unsigned int avb0_avtp_capture_a_mux[] = { | |
1039 | AVB0_AVTP_CAPTURE_A_MARK, | |
1040 | }; | |
1041 | static const unsigned int avb0_avtp_pps_b_pins[] = { | |
1042 | /* AVB0_AVTP_PPS_B */ | |
1043 | RCAR_GP_PIN(4, 16), | |
1044 | }; | |
1045 | static const unsigned int avb0_avtp_pps_b_mux[] = { | |
1046 | AVB0_AVTP_PPS_B_MARK, | |
1047 | }; | |
1048 | static const unsigned int avb0_avtp_match_b_pins[] = { | |
1049 | /* AVB0_AVTP_MATCH_B */ | |
1050 | RCAR_GP_PIN(4, 18), | |
1051 | }; | |
1052 | static const unsigned int avb0_avtp_match_b_mux[] = { | |
1053 | AVB0_AVTP_MATCH_B_MARK, | |
1054 | }; | |
1055 | static const unsigned int avb0_avtp_capture_b_pins[] = { | |
1056 | /* AVB0_AVTP_CAPTURE_B */ | |
1057 | RCAR_GP_PIN(4, 17), | |
1058 | }; | |
1059 | static const unsigned int avb0_avtp_capture_b_mux[] = { | |
1060 | AVB0_AVTP_CAPTURE_B_MARK, | |
1061 | }; | |
1062 | ||
1063 | /* - CAN ------------------------------------------------------------------ */ | |
1064 | static const unsigned int can0_data_a_pins[] = { | |
1065 | /* TX, RX */ | |
1066 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), | |
1067 | }; | |
1068 | static const unsigned int can0_data_a_mux[] = { | |
1069 | CAN0_TX_A_MARK, CAN0_RX_A_MARK, | |
1070 | }; | |
1071 | static const unsigned int can0_data_b_pins[] = { | |
1072 | /* TX, RX */ | |
1073 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5), | |
1074 | }; | |
1075 | static const unsigned int can0_data_b_mux[] = { | |
1076 | CAN0_TX_B_MARK, CAN0_RX_B_MARK, | |
1077 | }; | |
1078 | static const unsigned int can1_data_a_pins[] = { | |
1079 | /* TX, RX */ | |
1080 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), | |
1081 | }; | |
1082 | static const unsigned int can1_data_a_mux[] = { | |
1083 | CAN1_TX_A_MARK, CAN1_RX_A_MARK, | |
1084 | }; | |
1085 | static const unsigned int can1_data_b_pins[] = { | |
1086 | /* TX, RX */ | |
1087 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), | |
1088 | }; | |
1089 | static const unsigned int can1_data_b_mux[] = { | |
1090 | CAN1_TX_B_MARK, CAN1_RX_B_MARK, | |
1091 | }; | |
1092 | ||
1093 | /* - CAN Clock -------------------------------------------------------------- */ | |
1094 | static const unsigned int can_clk_pins[] = { | |
1095 | /* CLK */ | |
1096 | RCAR_GP_PIN(5, 2), | |
1097 | }; | |
1098 | static const unsigned int can_clk_mux[] = { | |
1099 | CAN_CLK_MARK, | |
1100 | }; | |
1101 | ||
1102 | /* - CAN FD ----------------------------------------------------------------- */ | |
1103 | static const unsigned int canfd0_data_pins[] = { | |
1104 | /* TX, RX */ | |
1105 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), | |
1106 | }; | |
1107 | static const unsigned int canfd0_data_mux[] = { | |
1108 | CANFD0_TX_MARK, CANFD0_RX_MARK, | |
1109 | }; | |
1110 | static const unsigned int canfd1_data_pins[] = { | |
1111 | /* TX, RX */ | |
1112 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), | |
1113 | }; | |
1114 | static const unsigned int canfd1_data_mux[] = { | |
1115 | CANFD1_TX_MARK, CANFD1_RX_MARK, | |
1116 | }; | |
1117 | ||
1118 | /* - DU --------------------------------------------------------------------- */ | |
1119 | static const unsigned int du_rgb666_pins[] = { | |
1120 | /* R[7:2], G[7:2], B[7:2] */ | |
1121 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), | |
1122 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), | |
1123 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
1124 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), | |
1125 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), | |
1126 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), | |
1127 | }; | |
1128 | static const unsigned int du_rgb666_mux[] = { | |
1129 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
1130 | DU_DR3_MARK, DU_DR2_MARK, | |
1131 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
1132 | DU_DG3_MARK, DU_DG2_MARK, | |
1133 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
1134 | DU_DB3_MARK, DU_DB2_MARK, | |
1135 | }; | |
1136 | static const unsigned int du_rgb888_pins[] = { | |
1137 | /* R[7:0], G[7:0], B[7:0] */ | |
1138 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), | |
1139 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), | |
1140 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), | |
1141 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
1142 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), | |
1143 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), | |
1144 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), | |
1145 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), | |
1146 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), | |
1147 | }; | |
1148 | static const unsigned int du_rgb888_mux[] = { | |
1149 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, | |
1150 | DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, | |
1151 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, | |
1152 | DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, | |
1153 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, | |
1154 | DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, | |
1155 | }; | |
1156 | static const unsigned int du_clk_in_1_pins[] = { | |
1157 | /* CLKIN */ | |
1158 | RCAR_GP_PIN(1, 28), | |
1159 | }; | |
1160 | static const unsigned int du_clk_in_1_mux[] = { | |
1161 | DU_DOTCLKIN1_MARK | |
1162 | }; | |
1163 | static const unsigned int du_clk_out_0_pins[] = { | |
1164 | /* CLKOUT */ | |
1165 | RCAR_GP_PIN(1, 24), | |
1166 | }; | |
1167 | static const unsigned int du_clk_out_0_mux[] = { | |
1168 | DU_DOTCLKOUT0_MARK | |
1169 | }; | |
1170 | static const unsigned int du_sync_pins[] = { | |
1171 | /* VSYNC, HSYNC */ | |
1172 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), | |
1173 | }; | |
1174 | static const unsigned int du_sync_mux[] = { | |
1175 | DU_VSYNC_MARK, DU_HSYNC_MARK | |
1176 | }; | |
1177 | static const unsigned int du_disp_cde_pins[] = { | |
1178 | /* DISP_CDE */ | |
1179 | RCAR_GP_PIN(1, 28), | |
1180 | }; | |
1181 | static const unsigned int du_disp_cde_mux[] = { | |
1182 | DU_DISP_CDE_MARK, | |
1183 | }; | |
1184 | static const unsigned int du_cde_pins[] = { | |
1185 | /* CDE */ | |
1186 | RCAR_GP_PIN(1, 29), | |
1187 | }; | |
1188 | static const unsigned int du_cde_mux[] = { | |
1189 | DU_CDE_MARK, | |
1190 | }; | |
1191 | static const unsigned int du_disp_pins[] = { | |
1192 | /* DISP */ | |
1193 | RCAR_GP_PIN(1, 27), | |
1194 | }; | |
1195 | static const unsigned int du_disp_mux[] = { | |
1196 | DU_DISP_MARK, | |
1197 | }; | |
1198 | ||
a59e6976 MV |
1199 | /* - I2C -------------------------------------------------------------------- */ |
1200 | static const unsigned int i2c0_pins[] = { | |
1201 | /* SCL, SDA */ | |
1202 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
1203 | }; | |
1204 | static const unsigned int i2c0_mux[] = { | |
1205 | SCL0_MARK, SDA0_MARK, | |
1206 | }; | |
1207 | static const unsigned int i2c1_pins[] = { | |
1208 | /* SCL, SDA */ | |
1209 | RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), | |
1210 | }; | |
1211 | static const unsigned int i2c1_mux[] = { | |
1212 | SCL1_MARK, SDA1_MARK, | |
1213 | }; | |
1214 | static const unsigned int i2c2_a_pins[] = { | |
1215 | /* SCL, SDA */ | |
1216 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), | |
1217 | }; | |
1218 | static const unsigned int i2c2_a_mux[] = { | |
1219 | SCL2_A_MARK, SDA2_A_MARK, | |
1220 | }; | |
1221 | static const unsigned int i2c2_b_pins[] = { | |
1222 | /* SCL, SDA */ | |
1223 | RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), | |
1224 | }; | |
1225 | static const unsigned int i2c2_b_mux[] = { | |
1226 | SCL2_B_MARK, SDA2_B_MARK, | |
1227 | }; | |
1228 | static const unsigned int i2c3_a_pins[] = { | |
1229 | /* SCL, SDA */ | |
1230 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
1231 | }; | |
1232 | static const unsigned int i2c3_a_mux[] = { | |
1233 | SCL3_A_MARK, SDA3_A_MARK, | |
1234 | }; | |
1235 | static const unsigned int i2c3_b_pins[] = { | |
1236 | /* SCL, SDA */ | |
1237 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), | |
1238 | }; | |
1239 | static const unsigned int i2c3_b_mux[] = { | |
1240 | SCL3_B_MARK, SDA3_B_MARK, | |
1241 | }; | |
1242 | ||
1243 | /* - MMC ------------------------------------------------------------------- */ | |
1244 | static const unsigned int mmc_data1_pins[] = { | |
1245 | /* D0 */ | |
1246 | RCAR_GP_PIN(3, 2), | |
1247 | }; | |
1248 | static const unsigned int mmc_data1_mux[] = { | |
1249 | MMC_D0_MARK, | |
1250 | }; | |
1251 | static const unsigned int mmc_data4_pins[] = { | |
1252 | /* D[0:3] */ | |
1253 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
1254 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
1255 | }; | |
1256 | static const unsigned int mmc_data4_mux[] = { | |
1257 | MMC_D0_MARK, MMC_D1_MARK, | |
1258 | MMC_D2_MARK, MMC_D3_MARK, | |
1259 | }; | |
1260 | static const unsigned int mmc_data8_pins[] = { | |
1261 | /* D[0:7] */ | |
1262 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
1263 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
1264 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
1265 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
1266 | }; | |
1267 | static const unsigned int mmc_data8_mux[] = { | |
1268 | MMC_D0_MARK, MMC_D1_MARK, | |
1269 | MMC_D2_MARK, MMC_D3_MARK, | |
1270 | MMC_D4_MARK, MMC_D5_MARK, | |
1271 | MMC_D6_MARK, MMC_D7_MARK, | |
1272 | }; | |
1273 | static const unsigned int mmc_ctrl_pins[] = { | |
1274 | /* CLK, CMD */ | |
1275 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), | |
1276 | }; | |
1277 | static const unsigned int mmc_ctrl_mux[] = { | |
1278 | MMC_CLK_MARK, MMC_CMD_MARK, | |
1279 | }; | |
1280 | ||
8719ca81 MV |
1281 | /* - MSIOF0 ----------------------------------------------------------------- */ |
1282 | static const unsigned int msiof0_clk_pins[] = { | |
1283 | /* SCK */ | |
1284 | RCAR_GP_PIN(4, 12), | |
1285 | }; | |
1286 | ||
1287 | static const unsigned int msiof0_clk_mux[] = { | |
1288 | MSIOF0_SCK_MARK, | |
1289 | }; | |
1290 | ||
1291 | static const unsigned int msiof0_sync_pins[] = { | |
1292 | /* SYNC */ | |
1293 | RCAR_GP_PIN(4, 13), | |
1294 | }; | |
1295 | ||
1296 | static const unsigned int msiof0_sync_mux[] = { | |
1297 | MSIOF0_SYNC_MARK, | |
1298 | }; | |
1299 | ||
1300 | static const unsigned int msiof0_ss1_pins[] = { | |
1301 | /* SS1 */ | |
1302 | RCAR_GP_PIN(4, 20), | |
1303 | }; | |
1304 | ||
1305 | static const unsigned int msiof0_ss1_mux[] = { | |
1306 | MSIOF0_SS1_MARK, | |
1307 | }; | |
1308 | ||
1309 | static const unsigned int msiof0_ss2_pins[] = { | |
1310 | /* SS2 */ | |
1311 | RCAR_GP_PIN(4, 21), | |
1312 | }; | |
1313 | ||
1314 | static const unsigned int msiof0_ss2_mux[] = { | |
1315 | MSIOF0_SS2_MARK, | |
1316 | }; | |
1317 | ||
1318 | static const unsigned int msiof0_txd_pins[] = { | |
1319 | /* TXD */ | |
1320 | RCAR_GP_PIN(4, 14), | |
1321 | }; | |
1322 | ||
1323 | static const unsigned int msiof0_txd_mux[] = { | |
1324 | MSIOF0_TXD_MARK, | |
1325 | }; | |
1326 | ||
1327 | static const unsigned int msiof0_rxd_pins[] = { | |
1328 | /* RXD */ | |
1329 | RCAR_GP_PIN(4, 15), | |
1330 | }; | |
1331 | ||
1332 | static const unsigned int msiof0_rxd_mux[] = { | |
1333 | MSIOF0_RXD_MARK, | |
1334 | }; | |
1335 | ||
1336 | /* - MSIOF1 ----------------------------------------------------------------- */ | |
1337 | static const unsigned int msiof1_clk_pins[] = { | |
1338 | /* SCK */ | |
1339 | RCAR_GP_PIN(4, 16), | |
1340 | }; | |
1341 | ||
1342 | static const unsigned int msiof1_clk_mux[] = { | |
1343 | MSIOF1_SCK_MARK, | |
1344 | }; | |
1345 | ||
1346 | static const unsigned int msiof1_sync_pins[] = { | |
1347 | /* SYNC */ | |
1348 | RCAR_GP_PIN(4, 19), | |
1349 | }; | |
1350 | ||
1351 | static const unsigned int msiof1_sync_mux[] = { | |
1352 | MSIOF1_SYNC_MARK, | |
1353 | }; | |
1354 | ||
1355 | static const unsigned int msiof1_ss1_pins[] = { | |
1356 | /* SS1 */ | |
1357 | RCAR_GP_PIN(4, 25), | |
1358 | }; | |
1359 | ||
1360 | static const unsigned int msiof1_ss1_mux[] = { | |
1361 | MSIOF1_SS1_MARK, | |
1362 | }; | |
1363 | ||
1364 | static const unsigned int msiof1_ss2_pins[] = { | |
1365 | /* SS2 */ | |
1366 | RCAR_GP_PIN(4, 22), | |
1367 | }; | |
1368 | ||
1369 | static const unsigned int msiof1_ss2_mux[] = { | |
1370 | MSIOF1_SS2_MARK, | |
1371 | }; | |
1372 | ||
1373 | static const unsigned int msiof1_txd_pins[] = { | |
1374 | /* TXD */ | |
1375 | RCAR_GP_PIN(4, 17), | |
1376 | }; | |
1377 | ||
1378 | static const unsigned int msiof1_txd_mux[] = { | |
1379 | MSIOF1_TXD_MARK, | |
1380 | }; | |
1381 | ||
1382 | static const unsigned int msiof1_rxd_pins[] = { | |
1383 | /* RXD */ | |
1384 | RCAR_GP_PIN(4, 18), | |
1385 | }; | |
1386 | ||
1387 | static const unsigned int msiof1_rxd_mux[] = { | |
1388 | MSIOF1_RXD_MARK, | |
1389 | }; | |
1390 | ||
1391 | /* - MSIOF2 ----------------------------------------------------------------- */ | |
1392 | static const unsigned int msiof2_clk_pins[] = { | |
1393 | /* SCK */ | |
1394 | RCAR_GP_PIN(0, 3), | |
1395 | }; | |
1396 | ||
1397 | static const unsigned int msiof2_clk_mux[] = { | |
1398 | MSIOF2_SCK_MARK, | |
1399 | }; | |
1400 | ||
1401 | static const unsigned int msiof2_sync_a_pins[] = { | |
1402 | /* SYNC */ | |
1403 | RCAR_GP_PIN(0, 6), | |
1404 | }; | |
1405 | ||
1406 | static const unsigned int msiof2_sync_a_mux[] = { | |
1407 | MSIOF2_SYNC_A_MARK, | |
1408 | }; | |
1409 | ||
1410 | static const unsigned int msiof2_sync_b_pins[] = { | |
1411 | /* SYNC */ | |
1412 | RCAR_GP_PIN(0, 2), | |
1413 | }; | |
1414 | ||
1415 | static const unsigned int msiof2_sync_b_mux[] = { | |
1416 | MSIOF2_SYNC_B_MARK, | |
1417 | }; | |
1418 | ||
1419 | static const unsigned int msiof2_ss1_pins[] = { | |
1420 | /* SS1 */ | |
1421 | RCAR_GP_PIN(0, 7), | |
1422 | }; | |
1423 | ||
1424 | static const unsigned int msiof2_ss1_mux[] = { | |
1425 | MSIOF2_SS1_MARK, | |
1426 | }; | |
1427 | ||
1428 | static const unsigned int msiof2_ss2_pins[] = { | |
1429 | /* SS2 */ | |
1430 | RCAR_GP_PIN(0, 8), | |
1431 | }; | |
1432 | ||
1433 | static const unsigned int msiof2_ss2_mux[] = { | |
1434 | MSIOF2_SS2_MARK, | |
1435 | }; | |
1436 | ||
1437 | static const unsigned int msiof2_txd_pins[] = { | |
1438 | /* TXD */ | |
1439 | RCAR_GP_PIN(0, 4), | |
1440 | }; | |
1441 | ||
1442 | static const unsigned int msiof2_txd_mux[] = { | |
1443 | MSIOF2_TXD_MARK, | |
1444 | }; | |
1445 | ||
1446 | static const unsigned int msiof2_rxd_pins[] = { | |
1447 | /* RXD */ | |
1448 | RCAR_GP_PIN(0, 5), | |
1449 | }; | |
1450 | ||
1451 | static const unsigned int msiof2_rxd_mux[] = { | |
1452 | MSIOF2_RXD_MARK, | |
1453 | }; | |
1454 | ||
1455 | /* - MSIOF3 ----------------------------------------------------------------- */ | |
1456 | static const unsigned int msiof3_clk_a_pins[] = { | |
1457 | /* SCK */ | |
1458 | RCAR_GP_PIN(2, 24), | |
1459 | }; | |
1460 | ||
1461 | static const unsigned int msiof3_clk_a_mux[] = { | |
1462 | MSIOF3_SCK_A_MARK, | |
1463 | }; | |
1464 | ||
1465 | static const unsigned int msiof3_sync_a_pins[] = { | |
1466 | /* SYNC */ | |
1467 | RCAR_GP_PIN(2, 21), | |
1468 | }; | |
1469 | ||
1470 | static const unsigned int msiof3_sync_a_mux[] = { | |
1471 | MSIOF3_SYNC_A_MARK, | |
1472 | }; | |
1473 | ||
1474 | static const unsigned int msiof3_ss1_a_pins[] = { | |
1475 | /* SS1 */ | |
1476 | RCAR_GP_PIN(2, 14), | |
1477 | }; | |
1478 | ||
1479 | static const unsigned int msiof3_ss1_a_mux[] = { | |
1480 | MSIOF3_SS1_A_MARK, | |
1481 | }; | |
1482 | ||
1483 | static const unsigned int msiof3_ss2_a_pins[] = { | |
1484 | /* SS2 */ | |
1485 | RCAR_GP_PIN(2, 10), | |
1486 | }; | |
1487 | ||
1488 | static const unsigned int msiof3_ss2_a_mux[] = { | |
1489 | MSIOF3_SS2_A_MARK, | |
1490 | }; | |
1491 | ||
1492 | static const unsigned int msiof3_txd_a_pins[] = { | |
1493 | /* TXD */ | |
1494 | RCAR_GP_PIN(2, 22), | |
1495 | }; | |
1496 | ||
1497 | static const unsigned int msiof3_txd_a_mux[] = { | |
1498 | MSIOF3_TXD_A_MARK, | |
1499 | }; | |
1500 | ||
1501 | static const unsigned int msiof3_rxd_a_pins[] = { | |
1502 | /* RXD */ | |
1503 | RCAR_GP_PIN(2, 23), | |
1504 | }; | |
1505 | ||
1506 | static const unsigned int msiof3_rxd_a_mux[] = { | |
1507 | MSIOF3_RXD_A_MARK, | |
1508 | }; | |
1509 | ||
1510 | static const unsigned int msiof3_clk_b_pins[] = { | |
1511 | /* SCK */ | |
1512 | RCAR_GP_PIN(1, 8), | |
1513 | }; | |
1514 | ||
1515 | static const unsigned int msiof3_clk_b_mux[] = { | |
1516 | MSIOF3_SCK_B_MARK, | |
1517 | }; | |
1518 | ||
1519 | static const unsigned int msiof3_sync_b_pins[] = { | |
1520 | /* SYNC */ | |
1521 | RCAR_GP_PIN(1, 9), | |
1522 | }; | |
1523 | ||
1524 | static const unsigned int msiof3_sync_b_mux[] = { | |
1525 | MSIOF3_SYNC_B_MARK, | |
1526 | }; | |
1527 | ||
1528 | static const unsigned int msiof3_ss1_b_pins[] = { | |
1529 | /* SS1 */ | |
1530 | RCAR_GP_PIN(1, 6), | |
1531 | }; | |
1532 | ||
1533 | static const unsigned int msiof3_ss1_b_mux[] = { | |
1534 | MSIOF3_SS1_B_MARK, | |
1535 | }; | |
1536 | ||
1537 | static const unsigned int msiof3_ss2_b_pins[] = { | |
1538 | /* SS2 */ | |
1539 | RCAR_GP_PIN(1, 7), | |
1540 | }; | |
1541 | ||
1542 | static const unsigned int msiof3_ss2_b_mux[] = { | |
1543 | MSIOF3_SS2_B_MARK, | |
1544 | }; | |
1545 | ||
1546 | static const unsigned int msiof3_txd_b_pins[] = { | |
1547 | /* TXD */ | |
1548 | RCAR_GP_PIN(1, 0), | |
1549 | }; | |
1550 | ||
1551 | static const unsigned int msiof3_txd_b_mux[] = { | |
1552 | MSIOF3_TXD_B_MARK, | |
1553 | }; | |
1554 | ||
1555 | static const unsigned int msiof3_rxd_b_pins[] = { | |
1556 | /* RXD */ | |
1557 | RCAR_GP_PIN(1, 1), | |
1558 | }; | |
1559 | ||
1560 | static const unsigned int msiof3_rxd_b_mux[] = { | |
1561 | MSIOF3_RXD_B_MARK, | |
1562 | }; | |
1563 | ||
bf8d2dab MV |
1564 | /* - PWM0 ------------------------------------------------------------------ */ |
1565 | static const unsigned int pwm0_a_pins[] = { | |
1566 | /* PWM */ | |
1567 | RCAR_GP_PIN(2, 1), | |
1568 | }; | |
1569 | ||
1570 | static const unsigned int pwm0_a_mux[] = { | |
1571 | PWM0_A_MARK, | |
1572 | }; | |
1573 | ||
1574 | static const unsigned int pwm0_b_pins[] = { | |
1575 | /* PWM */ | |
1576 | RCAR_GP_PIN(1, 18), | |
1577 | }; | |
1578 | ||
1579 | static const unsigned int pwm0_b_mux[] = { | |
1580 | PWM0_B_MARK, | |
1581 | }; | |
1582 | ||
1583 | static const unsigned int pwm0_c_pins[] = { | |
1584 | /* PWM */ | |
1585 | RCAR_GP_PIN(2, 29), | |
1586 | }; | |
1587 | ||
1588 | static const unsigned int pwm0_c_mux[] = { | |
1589 | PWM0_C_MARK, | |
1590 | }; | |
1591 | ||
1592 | /* - PWM1 ------------------------------------------------------------------ */ | |
1593 | static const unsigned int pwm1_a_pins[] = { | |
1594 | /* PWM */ | |
1595 | RCAR_GP_PIN(2, 2), | |
1596 | }; | |
1597 | ||
1598 | static const unsigned int pwm1_a_mux[] = { | |
1599 | PWM1_A_MARK, | |
1600 | }; | |
1601 | ||
1602 | static const unsigned int pwm1_b_pins[] = { | |
1603 | /* PWM */ | |
1604 | RCAR_GP_PIN(1, 19), | |
1605 | }; | |
1606 | ||
1607 | static const unsigned int pwm1_b_mux[] = { | |
1608 | PWM1_B_MARK, | |
1609 | }; | |
1610 | ||
1611 | static const unsigned int pwm1_c_pins[] = { | |
1612 | /* PWM */ | |
1613 | RCAR_GP_PIN(2, 30), | |
1614 | }; | |
1615 | ||
1616 | static const unsigned int pwm1_c_mux[] = { | |
1617 | PWM1_C_MARK, | |
1618 | }; | |
1619 | ||
1620 | /* - PWM2 ------------------------------------------------------------------ */ | |
1621 | static const unsigned int pwm2_a_pins[] = { | |
1622 | /* PWM */ | |
1623 | RCAR_GP_PIN(2, 3), | |
1624 | }; | |
1625 | ||
1626 | static const unsigned int pwm2_a_mux[] = { | |
1627 | PWM2_A_MARK, | |
1628 | }; | |
1629 | ||
1630 | static const unsigned int pwm2_b_pins[] = { | |
1631 | /* PWM */ | |
1632 | RCAR_GP_PIN(1, 22), | |
1633 | }; | |
1634 | ||
1635 | static const unsigned int pwm2_b_mux[] = { | |
1636 | PWM2_B_MARK, | |
1637 | }; | |
1638 | ||
1639 | static const unsigned int pwm2_c_pins[] = { | |
1640 | /* PWM */ | |
1641 | RCAR_GP_PIN(2, 31), | |
1642 | }; | |
1643 | ||
1644 | static const unsigned int pwm2_c_mux[] = { | |
1645 | PWM2_C_MARK, | |
1646 | }; | |
1647 | ||
1648 | /* - PWM3 ------------------------------------------------------------------ */ | |
1649 | static const unsigned int pwm3_a_pins[] = { | |
1650 | /* PWM */ | |
1651 | RCAR_GP_PIN(2, 4), | |
1652 | }; | |
1653 | ||
1654 | static const unsigned int pwm3_a_mux[] = { | |
1655 | PWM3_A_MARK, | |
1656 | }; | |
1657 | ||
1658 | static const unsigned int pwm3_b_pins[] = { | |
1659 | /* PWM */ | |
1660 | RCAR_GP_PIN(1, 27), | |
1661 | }; | |
1662 | ||
1663 | static const unsigned int pwm3_b_mux[] = { | |
1664 | PWM3_B_MARK, | |
1665 | }; | |
1666 | ||
1667 | static const unsigned int pwm3_c_pins[] = { | |
1668 | /* PWM */ | |
1669 | RCAR_GP_PIN(4, 0), | |
1670 | }; | |
1671 | ||
1672 | static const unsigned int pwm3_c_mux[] = { | |
1673 | PWM3_C_MARK, | |
1674 | }; | |
1675 | ||
a59e6976 MV |
1676 | /* - SCIF0 ------------------------------------------------------------------ */ |
1677 | static const unsigned int scif0_data_a_pins[] = { | |
1678 | /* RX, TX */ | |
1679 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), | |
1680 | }; | |
1681 | static const unsigned int scif0_data_a_mux[] = { | |
1682 | RX0_A_MARK, TX0_A_MARK, | |
1683 | }; | |
1684 | static const unsigned int scif0_clk_a_pins[] = { | |
1685 | /* SCK */ | |
1686 | RCAR_GP_PIN(4, 19), | |
1687 | }; | |
1688 | static const unsigned int scif0_clk_a_mux[] = { | |
1689 | SCK0_A_MARK, | |
1690 | }; | |
1691 | static const unsigned int scif0_data_b_pins[] = { | |
1692 | /* RX, TX */ | |
1693 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), | |
1694 | }; | |
1695 | static const unsigned int scif0_data_b_mux[] = { | |
1696 | RX0_B_MARK, TX0_B_MARK, | |
1697 | }; | |
1698 | static const unsigned int scif0_clk_b_pins[] = { | |
1699 | /* SCK */ | |
1700 | RCAR_GP_PIN(5, 2), | |
1701 | }; | |
1702 | static const unsigned int scif0_clk_b_mux[] = { | |
1703 | SCK0_B_MARK, | |
1704 | }; | |
1705 | static const unsigned int scif0_ctrl_pins[] = { | |
1706 | /* RTS, CTS */ | |
1707 | RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), | |
1708 | }; | |
1709 | static const unsigned int scif0_ctrl_mux[] = { | |
1710 | RTS0_N_TANS_MARK, CTS0_N_MARK, | |
1711 | }; | |
1712 | /* - SCIF1 ------------------------------------------------------------------ */ | |
1713 | static const unsigned int scif1_data_a_pins[] = { | |
1714 | /* RX, TX */ | |
1715 | RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), | |
1716 | }; | |
1717 | static const unsigned int scif1_data_a_mux[] = { | |
1718 | RX1_A_MARK, TX1_A_MARK, | |
1719 | }; | |
1720 | static const unsigned int scif1_clk_a_pins[] = { | |
1721 | /* SCK */ | |
1722 | RCAR_GP_PIN(4, 22), | |
1723 | }; | |
1724 | static const unsigned int scif1_clk_a_mux[] = { | |
1725 | SCK1_A_MARK, | |
1726 | }; | |
1727 | static const unsigned int scif1_data_b_pins[] = { | |
1728 | /* RX, TX */ | |
1729 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), | |
1730 | }; | |
1731 | static const unsigned int scif1_data_b_mux[] = { | |
1732 | RX1_B_MARK, TX1_B_MARK, | |
1733 | }; | |
1734 | static const unsigned int scif1_clk_b_pins[] = { | |
1735 | /* SCK */ | |
1736 | RCAR_GP_PIN(2, 25), | |
1737 | }; | |
1738 | static const unsigned int scif1_clk_b_mux[] = { | |
1739 | SCK1_B_MARK, | |
1740 | }; | |
1741 | static const unsigned int scif1_ctrl_pins[] = { | |
1742 | /* RTS, CTS */ | |
1743 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), | |
1744 | }; | |
1745 | static const unsigned int scif1_ctrl_mux[] = { | |
1746 | RTS1_N_TANS_MARK, CTS1_N_MARK, | |
1747 | }; | |
1748 | ||
1749 | /* - SCIF2 ------------------------------------------------------------------ */ | |
1750 | static const unsigned int scif2_data_pins[] = { | |
1751 | /* RX, TX */ | |
1752 | RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), | |
1753 | }; | |
1754 | static const unsigned int scif2_data_mux[] = { | |
1755 | RX2_MARK, TX2_MARK, | |
1756 | }; | |
1757 | static const unsigned int scif2_clk_pins[] = { | |
1758 | /* SCK */ | |
1759 | RCAR_GP_PIN(4, 25), | |
1760 | }; | |
1761 | static const unsigned int scif2_clk_mux[] = { | |
1762 | SCK2_MARK, | |
1763 | }; | |
1764 | /* - SCIF3 ------------------------------------------------------------------ */ | |
1765 | static const unsigned int scif3_data_a_pins[] = { | |
1766 | /* RX, TX */ | |
1767 | RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), | |
1768 | }; | |
1769 | static const unsigned int scif3_data_a_mux[] = { | |
1770 | RX3_A_MARK, TX3_A_MARK, | |
1771 | }; | |
1772 | static const unsigned int scif3_clk_a_pins[] = { | |
1773 | /* SCK */ | |
1774 | RCAR_GP_PIN(2, 30), | |
1775 | }; | |
1776 | static const unsigned int scif3_clk_a_mux[] = { | |
1777 | SCK3_A_MARK, | |
1778 | }; | |
1779 | static const unsigned int scif3_data_b_pins[] = { | |
1780 | /* RX, TX */ | |
1781 | RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), | |
1782 | }; | |
1783 | static const unsigned int scif3_data_b_mux[] = { | |
1784 | RX3_B_MARK, TX3_B_MARK, | |
1785 | }; | |
1786 | static const unsigned int scif3_clk_b_pins[] = { | |
1787 | /* SCK */ | |
1788 | RCAR_GP_PIN(1, 29), | |
1789 | }; | |
1790 | static const unsigned int scif3_clk_b_mux[] = { | |
1791 | SCK3_B_MARK, | |
1792 | }; | |
1793 | /* - SCIF4 ------------------------------------------------------------------ */ | |
1794 | static const unsigned int scif4_data_a_pins[] = { | |
1795 | /* RX, TX */ | |
1796 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
1797 | }; | |
1798 | static const unsigned int scif4_data_a_mux[] = { | |
1799 | RX4_A_MARK, TX4_A_MARK, | |
1800 | }; | |
1801 | static const unsigned int scif4_clk_a_pins[] = { | |
1802 | /* SCK */ | |
1803 | RCAR_GP_PIN(2, 6), | |
1804 | }; | |
1805 | static const unsigned int scif4_clk_a_mux[] = { | |
1806 | SCK4_A_MARK, | |
1807 | }; | |
1808 | static const unsigned int scif4_data_b_pins[] = { | |
1809 | /* RX, TX */ | |
1810 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
1811 | }; | |
1812 | static const unsigned int scif4_data_b_mux[] = { | |
1813 | RX4_B_MARK, TX4_B_MARK, | |
1814 | }; | |
1815 | static const unsigned int scif4_clk_b_pins[] = { | |
1816 | /* SCK */ | |
1817 | RCAR_GP_PIN(1, 15), | |
1818 | }; | |
1819 | static const unsigned int scif4_clk_b_mux[] = { | |
1820 | SCK4_B_MARK, | |
1821 | }; | |
1822 | /* - SCIF5 ------------------------------------------------------------------ */ | |
1823 | static const unsigned int scif5_data_a_pins[] = { | |
1824 | /* RX, TX */ | |
1825 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), | |
1826 | }; | |
1827 | static const unsigned int scif5_data_a_mux[] = { | |
1828 | RX5_A_MARK, TX5_A_MARK, | |
1829 | }; | |
1830 | static const unsigned int scif5_clk_a_pins[] = { | |
1831 | /* SCK */ | |
1832 | RCAR_GP_PIN(0, 6), | |
1833 | }; | |
1834 | static const unsigned int scif5_clk_a_mux[] = { | |
1835 | SCK5_A_MARK, | |
1836 | }; | |
1837 | static const unsigned int scif5_data_b_pins[] = { | |
1838 | /* RX, TX */ | |
1839 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
1840 | }; | |
1841 | static const unsigned int scif5_data_b_mux[] = { | |
1842 | RX5_B_MARK, TX5_B_MARK, | |
1843 | }; | |
1844 | static const unsigned int scif5_clk_b_pins[] = { | |
1845 | /* SCK */ | |
1846 | RCAR_GP_PIN(1, 3), | |
1847 | }; | |
1848 | static const unsigned int scif5_clk_b_mux[] = { | |
1849 | SCK5_B_MARK, | |
1850 | }; | |
1851 | /* - SCIF Clock ------------------------------------------------------------- */ | |
1852 | static const unsigned int scif_clk_pins[] = { | |
1853 | /* SCIF_CLK */ | |
1854 | RCAR_GP_PIN(2, 27), | |
1855 | }; | |
1856 | static const unsigned int scif_clk_mux[] = { | |
1857 | SCIF_CLK_MARK, | |
1858 | }; | |
1859 | ||
bf8d2dab MV |
1860 | /* - SSI ---------------------------------------------------------------*/ |
1861 | static const unsigned int ssi3_data_pins[] = { | |
1862 | /* SDATA */ | |
1863 | RCAR_GP_PIN(4, 3), | |
1864 | }; | |
1865 | static const unsigned int ssi3_data_mux[] = { | |
1866 | SSI_SDATA3_MARK, | |
1867 | }; | |
1868 | static const unsigned int ssi34_ctrl_pins[] = { | |
1869 | /* SCK, WS */ | |
1870 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4), | |
1871 | }; | |
1872 | static const unsigned int ssi34_ctrl_mux[] = { | |
1873 | SSI_SCK34_MARK, SSI_WS34_MARK, | |
1874 | }; | |
1875 | static const unsigned int ssi4_ctrl_a_pins[] = { | |
1876 | /* SCK, WS */ | |
1877 | RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), | |
1878 | }; | |
1879 | static const unsigned int ssi4_ctrl_a_mux[] = { | |
1880 | SSI_SCK4_A_MARK, SSI_WS4_A_MARK, | |
1881 | }; | |
1882 | static const unsigned int ssi4_data_a_pins[] = { | |
1883 | /* SDATA */ | |
1884 | RCAR_GP_PIN(4, 6), | |
1885 | }; | |
1886 | static const unsigned int ssi4_data_a_mux[] = { | |
1887 | SSI_SDATA4_A_MARK, | |
1888 | }; | |
1889 | static const unsigned int ssi4_ctrl_b_pins[] = { | |
1890 | /* SCK, WS */ | |
1891 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20), | |
1892 | }; | |
1893 | static const unsigned int ssi4_ctrl_b_mux[] = { | |
1894 | SSI_SCK4_B_MARK, SSI_WS4_B_MARK, | |
1895 | }; | |
1896 | static const unsigned int ssi4_data_b_pins[] = { | |
1897 | /* SDATA */ | |
1898 | RCAR_GP_PIN(2, 16), | |
1899 | }; | |
1900 | static const unsigned int ssi4_data_b_mux[] = { | |
1901 | SSI_SDATA4_B_MARK, | |
1902 | }; | |
1903 | ||
1904 | /* - USB0 ------------------------------------------------------------------- */ | |
1905 | static const unsigned int usb0_pins[] = { | |
1906 | /* PWEN, OVC */ | |
1907 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | |
1908 | }; | |
1909 | static const unsigned int usb0_mux[] = { | |
1910 | USB0_PWEN_MARK, USB0_OVC_MARK, | |
1911 | }; | |
1912 | ||
1913 | /* - VIN4 ------------------------------------------------------------------- */ | |
1914 | static const unsigned int vin4_data18_pins[] = { | |
1915 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), | |
1916 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
1917 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
1918 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
1919 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), | |
1920 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), | |
1921 | RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), | |
1922 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
1923 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), | |
1924 | }; | |
1925 | static const unsigned int vin4_data18_mux[] = { | |
1926 | VI4_DATA2_MARK, VI4_DATA3_MARK, | |
1927 | VI4_DATA4_MARK, VI4_DATA5_MARK, | |
1928 | VI4_DATA6_MARK, VI4_DATA7_MARK, | |
1929 | VI4_DATA10_MARK, VI4_DATA11_MARK, | |
1930 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
1931 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
1932 | VI4_DATA18_MARK, VI4_DATA19_MARK, | |
1933 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
1934 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
1935 | }; | |
1936 | static const union vin_data vin4_data_pins = { | |
1937 | .data24 = { | |
1938 | RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), | |
1939 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), | |
1940 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
1941 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
1942 | RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), | |
1943 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
1944 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), | |
1945 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), | |
1946 | RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), | |
1947 | RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), | |
1948 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
1949 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), | |
1950 | }, | |
1951 | }; | |
1952 | static const union vin_data vin4_data_mux = { | |
1953 | .data24 = { | |
1954 | VI4_DATA0_MARK, VI4_DATA1_MARK, | |
1955 | VI4_DATA2_MARK, VI4_DATA3_MARK, | |
1956 | VI4_DATA4_MARK, VI4_DATA5_MARK, | |
1957 | VI4_DATA6_MARK, VI4_DATA7_MARK, | |
1958 | VI4_DATA8_MARK, VI4_DATA9_MARK, | |
1959 | VI4_DATA10_MARK, VI4_DATA11_MARK, | |
1960 | VI4_DATA12_MARK, VI4_DATA13_MARK, | |
1961 | VI4_DATA14_MARK, VI4_DATA15_MARK, | |
1962 | VI4_DATA16_MARK, VI4_DATA17_MARK, | |
1963 | VI4_DATA18_MARK, VI4_DATA19_MARK, | |
1964 | VI4_DATA20_MARK, VI4_DATA21_MARK, | |
1965 | VI4_DATA22_MARK, VI4_DATA23_MARK, | |
1966 | }, | |
1967 | }; | |
1968 | static const unsigned int vin4_sync_pins[] = { | |
1969 | /* HSYNC#, VSYNC# */ | |
1970 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), | |
1971 | }; | |
1972 | static const unsigned int vin4_sync_mux[] = { | |
1973 | VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, | |
1974 | }; | |
1975 | static const unsigned int vin4_field_pins[] = { | |
1976 | /* FIELD */ | |
1977 | RCAR_GP_PIN(2, 27), | |
1978 | }; | |
1979 | static const unsigned int vin4_field_mux[] = { | |
1980 | VI4_FIELD_MARK, | |
1981 | }; | |
1982 | static const unsigned int vin4_clkenb_pins[] = { | |
1983 | /* CLKENB */ | |
1984 | RCAR_GP_PIN(2, 28), | |
1985 | }; | |
1986 | static const unsigned int vin4_clkenb_mux[] = { | |
1987 | VI4_CLKENB_MARK, | |
1988 | }; | |
1989 | static const unsigned int vin4_clk_pins[] = { | |
1990 | /* CLK */ | |
1991 | RCAR_GP_PIN(2, 0), | |
1992 | }; | |
1993 | static const unsigned int vin4_clk_mux[] = { | |
1994 | VI4_CLK_MARK, | |
1995 | }; | |
1996 | ||
a59e6976 | 1997 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
bf8d2dab MV |
1998 | SH_PFC_PIN_GROUP(audio_clk_a), |
1999 | SH_PFC_PIN_GROUP(audio_clk_b), | |
2000 | SH_PFC_PIN_GROUP(audio_clkout), | |
2001 | SH_PFC_PIN_GROUP(audio_clkout1), | |
2002 | SH_PFC_PIN_GROUP(avb0_link), | |
2003 | SH_PFC_PIN_GROUP(avb0_magic), | |
2004 | SH_PFC_PIN_GROUP(avb0_phy_int), | |
2005 | SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */ | |
2006 | SH_PFC_PIN_GROUP(avb0_mdio), | |
2007 | SH_PFC_PIN_GROUP(avb0_mii), | |
2008 | SH_PFC_PIN_GROUP(avb0_avtp_pps_a), | |
2009 | SH_PFC_PIN_GROUP(avb0_avtp_match_a), | |
2010 | SH_PFC_PIN_GROUP(avb0_avtp_capture_a), | |
2011 | SH_PFC_PIN_GROUP(avb0_avtp_pps_b), | |
2012 | SH_PFC_PIN_GROUP(avb0_avtp_match_b), | |
2013 | SH_PFC_PIN_GROUP(avb0_avtp_capture_b), | |
2014 | SH_PFC_PIN_GROUP(can0_data_a), | |
2015 | SH_PFC_PIN_GROUP(can0_data_b), | |
2016 | SH_PFC_PIN_GROUP(can1_data_a), | |
2017 | SH_PFC_PIN_GROUP(can1_data_b), | |
2018 | SH_PFC_PIN_GROUP(can_clk), | |
2019 | SH_PFC_PIN_GROUP(canfd0_data), | |
2020 | SH_PFC_PIN_GROUP(canfd1_data), | |
2021 | SH_PFC_PIN_GROUP(du_rgb666), | |
2022 | SH_PFC_PIN_GROUP(du_rgb888), | |
2023 | SH_PFC_PIN_GROUP(du_clk_in_1), | |
2024 | SH_PFC_PIN_GROUP(du_clk_out_0), | |
2025 | SH_PFC_PIN_GROUP(du_sync), | |
2026 | SH_PFC_PIN_GROUP(du_disp_cde), | |
2027 | SH_PFC_PIN_GROUP(du_cde), | |
2028 | SH_PFC_PIN_GROUP(du_disp), | |
a59e6976 MV |
2029 | SH_PFC_PIN_GROUP(i2c0), |
2030 | SH_PFC_PIN_GROUP(i2c1), | |
2031 | SH_PFC_PIN_GROUP(i2c2_a), | |
2032 | SH_PFC_PIN_GROUP(i2c2_b), | |
2033 | SH_PFC_PIN_GROUP(i2c3_a), | |
2034 | SH_PFC_PIN_GROUP(i2c3_b), | |
2035 | SH_PFC_PIN_GROUP(mmc_data1), | |
2036 | SH_PFC_PIN_GROUP(mmc_data4), | |
2037 | SH_PFC_PIN_GROUP(mmc_data8), | |
2038 | SH_PFC_PIN_GROUP(mmc_ctrl), | |
8719ca81 MV |
2039 | SH_PFC_PIN_GROUP(msiof0_clk), |
2040 | SH_PFC_PIN_GROUP(msiof0_sync), | |
2041 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
2042 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
2043 | SH_PFC_PIN_GROUP(msiof0_txd), | |
2044 | SH_PFC_PIN_GROUP(msiof0_rxd), | |
2045 | SH_PFC_PIN_GROUP(msiof1_clk), | |
2046 | SH_PFC_PIN_GROUP(msiof1_sync), | |
2047 | SH_PFC_PIN_GROUP(msiof1_ss1), | |
2048 | SH_PFC_PIN_GROUP(msiof1_ss2), | |
2049 | SH_PFC_PIN_GROUP(msiof1_txd), | |
2050 | SH_PFC_PIN_GROUP(msiof1_rxd), | |
2051 | SH_PFC_PIN_GROUP(msiof2_clk), | |
2052 | SH_PFC_PIN_GROUP(msiof2_sync_a), | |
2053 | SH_PFC_PIN_GROUP(msiof2_sync_b), | |
2054 | SH_PFC_PIN_GROUP(msiof2_ss1), | |
2055 | SH_PFC_PIN_GROUP(msiof2_ss2), | |
2056 | SH_PFC_PIN_GROUP(msiof2_txd), | |
2057 | SH_PFC_PIN_GROUP(msiof2_rxd), | |
2058 | SH_PFC_PIN_GROUP(msiof3_clk_a), | |
2059 | SH_PFC_PIN_GROUP(msiof3_sync_a), | |
2060 | SH_PFC_PIN_GROUP(msiof3_ss1_a), | |
2061 | SH_PFC_PIN_GROUP(msiof3_ss2_a), | |
2062 | SH_PFC_PIN_GROUP(msiof3_txd_a), | |
2063 | SH_PFC_PIN_GROUP(msiof3_rxd_a), | |
2064 | SH_PFC_PIN_GROUP(msiof3_clk_b), | |
2065 | SH_PFC_PIN_GROUP(msiof3_sync_b), | |
2066 | SH_PFC_PIN_GROUP(msiof3_ss1_b), | |
2067 | SH_PFC_PIN_GROUP(msiof3_ss2_b), | |
2068 | SH_PFC_PIN_GROUP(msiof3_txd_b), | |
2069 | SH_PFC_PIN_GROUP(msiof3_rxd_b), | |
bf8d2dab MV |
2070 | SH_PFC_PIN_GROUP(pwm0_a), |
2071 | SH_PFC_PIN_GROUP(pwm0_b), | |
2072 | SH_PFC_PIN_GROUP(pwm0_c), | |
2073 | SH_PFC_PIN_GROUP(pwm1_a), | |
2074 | SH_PFC_PIN_GROUP(pwm1_b), | |
2075 | SH_PFC_PIN_GROUP(pwm1_c), | |
2076 | SH_PFC_PIN_GROUP(pwm2_a), | |
2077 | SH_PFC_PIN_GROUP(pwm2_b), | |
2078 | SH_PFC_PIN_GROUP(pwm2_c), | |
2079 | SH_PFC_PIN_GROUP(pwm3_a), | |
2080 | SH_PFC_PIN_GROUP(pwm3_b), | |
2081 | SH_PFC_PIN_GROUP(pwm3_c), | |
a59e6976 MV |
2082 | SH_PFC_PIN_GROUP(scif0_data_a), |
2083 | SH_PFC_PIN_GROUP(scif0_clk_a), | |
2084 | SH_PFC_PIN_GROUP(scif0_data_b), | |
2085 | SH_PFC_PIN_GROUP(scif0_clk_b), | |
2086 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
2087 | SH_PFC_PIN_GROUP(scif1_data_a), | |
2088 | SH_PFC_PIN_GROUP(scif1_clk_a), | |
2089 | SH_PFC_PIN_GROUP(scif1_data_b), | |
2090 | SH_PFC_PIN_GROUP(scif1_clk_b), | |
2091 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
2092 | SH_PFC_PIN_GROUP(scif2_data), | |
2093 | SH_PFC_PIN_GROUP(scif2_clk), | |
2094 | SH_PFC_PIN_GROUP(scif3_data_a), | |
2095 | SH_PFC_PIN_GROUP(scif3_clk_a), | |
2096 | SH_PFC_PIN_GROUP(scif3_data_b), | |
2097 | SH_PFC_PIN_GROUP(scif3_clk_b), | |
2098 | SH_PFC_PIN_GROUP(scif4_data_a), | |
2099 | SH_PFC_PIN_GROUP(scif4_clk_a), | |
2100 | SH_PFC_PIN_GROUP(scif4_data_b), | |
2101 | SH_PFC_PIN_GROUP(scif4_clk_b), | |
2102 | SH_PFC_PIN_GROUP(scif5_data_a), | |
2103 | SH_PFC_PIN_GROUP(scif5_clk_a), | |
2104 | SH_PFC_PIN_GROUP(scif5_data_b), | |
2105 | SH_PFC_PIN_GROUP(scif5_clk_b), | |
2106 | SH_PFC_PIN_GROUP(scif_clk), | |
bf8d2dab MV |
2107 | SH_PFC_PIN_GROUP(ssi3_data), |
2108 | SH_PFC_PIN_GROUP(ssi34_ctrl), | |
2109 | SH_PFC_PIN_GROUP(ssi4_ctrl_a), | |
2110 | SH_PFC_PIN_GROUP(ssi4_data_a), | |
2111 | SH_PFC_PIN_GROUP(ssi4_ctrl_b), | |
2112 | SH_PFC_PIN_GROUP(ssi4_data_b), | |
2113 | SH_PFC_PIN_GROUP(usb0), | |
2114 | VIN_DATA_PIN_GROUP(vin4_data, 8), | |
2115 | VIN_DATA_PIN_GROUP(vin4_data, 10), | |
2116 | VIN_DATA_PIN_GROUP(vin4_data, 12), | |
2117 | VIN_DATA_PIN_GROUP(vin4_data, 16), | |
2118 | SH_PFC_PIN_GROUP(vin4_data18), | |
2119 | VIN_DATA_PIN_GROUP(vin4_data, 20), | |
2120 | VIN_DATA_PIN_GROUP(vin4_data, 24), | |
2121 | SH_PFC_PIN_GROUP(vin4_sync), | |
2122 | SH_PFC_PIN_GROUP(vin4_field), | |
2123 | SH_PFC_PIN_GROUP(vin4_clkenb), | |
2124 | SH_PFC_PIN_GROUP(vin4_clk), | |
2125 | }; | |
2126 | ||
2127 | static const char * const audio_clk_groups[] = { | |
2128 | "audio_clk_a", | |
2129 | "audio_clk_b", | |
2130 | "audio_clkout", | |
2131 | "audio_clkout1", | |
2132 | }; | |
2133 | ||
2134 | static const char * const avb0_groups[] = { | |
2135 | "avb0_link", | |
2136 | "avb0_magic", | |
2137 | "avb0_phy_int", | |
2138 | "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */ | |
2139 | "avb0_mdio", | |
2140 | "avb0_mii", | |
2141 | "avb0_avtp_pps_a", | |
2142 | "avb0_avtp_match_a", | |
2143 | "avb0_avtp_capture_a", | |
2144 | "avb0_avtp_pps_b", | |
2145 | "avb0_avtp_match_b", | |
2146 | "avb0_avtp_capture_b", | |
2147 | }; | |
2148 | ||
2149 | static const char * const can0_groups[] = { | |
2150 | "can0_data_a", | |
2151 | "can0_data_b", | |
2152 | }; | |
2153 | static const char * const can1_groups[] = { | |
2154 | "can1_data_a", | |
2155 | "can1_data_b", | |
2156 | }; | |
2157 | static const char * const can_clk_groups[] = { | |
2158 | "can_clk", | |
2159 | }; | |
2160 | ||
2161 | static const char * const canfd0_groups[] = { | |
2162 | "canfd0_data", | |
2163 | }; | |
2164 | static const char * const canfd1_groups[] = { | |
2165 | "canfd1_data", | |
2166 | }; | |
2167 | ||
2168 | static const char * const du_groups[] = { | |
2169 | "du_rgb666", | |
2170 | "du_rgb888", | |
2171 | "du_clk_in_1", | |
2172 | "du_clk_out_0", | |
2173 | "du_sync", | |
2174 | "du_disp_cde", | |
2175 | "du_cde", | |
2176 | "du_disp", | |
a59e6976 MV |
2177 | }; |
2178 | ||
2179 | static const char * const i2c0_groups[] = { | |
2180 | "i2c0", | |
2181 | }; | |
2182 | static const char * const i2c1_groups[] = { | |
2183 | "i2c1", | |
2184 | }; | |
2185 | ||
2186 | static const char * const i2c2_groups[] = { | |
2187 | "i2c2_a", | |
2188 | "i2c2_b", | |
2189 | }; | |
2190 | ||
2191 | static const char * const i2c3_groups[] = { | |
2192 | "i2c3_a", | |
2193 | "i2c3_b", | |
2194 | }; | |
2195 | ||
2196 | static const char * const mmc_groups[] = { | |
2197 | "mmc_data1", | |
2198 | "mmc_data4", | |
2199 | "mmc_data8", | |
2200 | "mmc_ctrl", | |
2201 | }; | |
2202 | ||
bf8d2dab MV |
2203 | static const char * const pwm0_groups[] = { |
2204 | "pwm0_a", | |
2205 | "pwm0_b", | |
2206 | "pwm0_c", | |
2207 | }; | |
2208 | ||
2209 | static const char * const pwm1_groups[] = { | |
2210 | "pwm1_a", | |
2211 | "pwm1_b", | |
2212 | "pwm1_c", | |
2213 | }; | |
2214 | ||
2215 | static const char * const pwm2_groups[] = { | |
2216 | "pwm2_a", | |
2217 | "pwm2_b", | |
2218 | "pwm2_c", | |
2219 | }; | |
2220 | ||
2221 | static const char * const pwm3_groups[] = { | |
2222 | "pwm3_a", | |
2223 | "pwm3_b", | |
2224 | "pwm3_c", | |
2225 | }; | |
2226 | ||
a59e6976 MV |
2227 | static const char * const scif0_groups[] = { |
2228 | "scif0_data_a", | |
2229 | "scif0_clk_a", | |
2230 | "scif0_data_b", | |
2231 | "scif0_clk_b", | |
2232 | "scif0_ctrl", | |
2233 | }; | |
2234 | ||
2235 | static const char * const scif1_groups[] = { | |
2236 | "scif1_data_a", | |
2237 | "scif1_clk_a", | |
2238 | "scif1_data_b", | |
2239 | "scif1_clk_b", | |
2240 | "scif1_ctrl", | |
2241 | }; | |
2242 | ||
2243 | static const char * const scif2_groups[] = { | |
2244 | "scif2_data", | |
2245 | "scif2_clk", | |
2246 | }; | |
2247 | ||
2248 | static const char * const scif3_groups[] = { | |
2249 | "scif3_data_a", | |
2250 | "scif3_clk_a", | |
2251 | "scif3_data_b", | |
2252 | "scif3_clk_b", | |
2253 | }; | |
2254 | ||
2255 | static const char * const scif4_groups[] = { | |
2256 | "scif4_data_a", | |
2257 | "scif4_clk_a", | |
2258 | "scif4_data_b", | |
2259 | "scif4_clk_b", | |
2260 | }; | |
2261 | ||
2262 | static const char * const scif5_groups[] = { | |
2263 | "scif5_data_a", | |
2264 | "scif5_clk_a", | |
2265 | "scif5_data_b", | |
2266 | "scif5_clk_b", | |
2267 | }; | |
2268 | ||
2269 | static const char * const scif_clk_groups[] = { | |
2270 | "scif_clk", | |
2271 | }; | |
2272 | ||
bf8d2dab MV |
2273 | static const char * const ssi_groups[] = { |
2274 | "ssi3_data", | |
2275 | "ssi34_ctrl", | |
2276 | "ssi4_ctrl_a", | |
2277 | "ssi4_data_a", | |
2278 | "ssi4_ctrl_b", | |
2279 | "ssi4_data_b", | |
2280 | }; | |
2281 | ||
2282 | static const char * const usb0_groups[] = { | |
2283 | "usb0", | |
2284 | }; | |
2285 | ||
2286 | static const char * const vin4_groups[] = { | |
2287 | "vin4_data8", | |
2288 | "vin4_data10", | |
2289 | "vin4_data12", | |
2290 | "vin4_data16", | |
2291 | "vin4_data18", | |
2292 | "vin4_data20", | |
2293 | "vin4_data24", | |
2294 | "vin4_sync", | |
2295 | "vin4_field", | |
2296 | "vin4_clkenb", | |
2297 | "vin4_clk", | |
2298 | }; | |
2299 | ||
8719ca81 MV |
2300 | static const char * const msiof0_groups[] = { |
2301 | "msiof0_clk", | |
2302 | "msiof0_sync", | |
2303 | "msiof0_ss1", | |
2304 | "msiof0_ss2", | |
2305 | "msiof0_txd", | |
2306 | "msiof0_rxd", | |
2307 | }; | |
2308 | ||
2309 | static const char * const msiof1_groups[] = { | |
2310 | "msiof1_clk", | |
2311 | "msiof1_sync", | |
2312 | "msiof1_ss1", | |
2313 | "msiof1_ss2", | |
2314 | "msiof1_txd", | |
2315 | "msiof1_rxd", | |
2316 | }; | |
2317 | ||
2318 | static const char * const msiof2_groups[] = { | |
2319 | "msiof2_clk", | |
2320 | "msiof2_sync_a", | |
2321 | "msiof2_sync_b", | |
2322 | "msiof2_ss1", | |
2323 | "msiof2_ss2", | |
2324 | "msiof2_txd", | |
2325 | "msiof2_rxd", | |
2326 | }; | |
2327 | ||
2328 | static const char * const msiof3_groups[] = { | |
2329 | "msiof3_clk_a", | |
2330 | "msiof3_sync_a", | |
2331 | "msiof3_ss1_a", | |
2332 | "msiof3_ss2_a", | |
2333 | "msiof3_txd_a", | |
2334 | "msiof3_rxd_a", | |
2335 | "msiof3_clk_b", | |
2336 | "msiof3_sync_b", | |
2337 | "msiof3_ss1_b", | |
2338 | "msiof3_ss2_b", | |
2339 | "msiof3_txd_b", | |
2340 | "msiof3_rxd_b", | |
2341 | }; | |
2342 | ||
a59e6976 | 2343 | static const struct sh_pfc_function pinmux_functions[] = { |
bf8d2dab MV |
2344 | SH_PFC_FUNCTION(audio_clk), |
2345 | SH_PFC_FUNCTION(avb0), | |
2346 | SH_PFC_FUNCTION(can0), | |
2347 | SH_PFC_FUNCTION(can1), | |
2348 | SH_PFC_FUNCTION(can_clk), | |
2349 | SH_PFC_FUNCTION(canfd0), | |
2350 | SH_PFC_FUNCTION(canfd1), | |
2351 | SH_PFC_FUNCTION(du), | |
a59e6976 MV |
2352 | SH_PFC_FUNCTION(i2c0), |
2353 | SH_PFC_FUNCTION(i2c1), | |
2354 | SH_PFC_FUNCTION(i2c2), | |
2355 | SH_PFC_FUNCTION(i2c3), | |
2356 | SH_PFC_FUNCTION(mmc), | |
8719ca81 MV |
2357 | SH_PFC_FUNCTION(msiof0), |
2358 | SH_PFC_FUNCTION(msiof1), | |
2359 | SH_PFC_FUNCTION(msiof2), | |
2360 | SH_PFC_FUNCTION(msiof3), | |
bf8d2dab MV |
2361 | SH_PFC_FUNCTION(pwm0), |
2362 | SH_PFC_FUNCTION(pwm1), | |
2363 | SH_PFC_FUNCTION(pwm2), | |
2364 | SH_PFC_FUNCTION(pwm3), | |
a59e6976 MV |
2365 | SH_PFC_FUNCTION(scif0), |
2366 | SH_PFC_FUNCTION(scif1), | |
2367 | SH_PFC_FUNCTION(scif2), | |
2368 | SH_PFC_FUNCTION(scif3), | |
2369 | SH_PFC_FUNCTION(scif4), | |
2370 | SH_PFC_FUNCTION(scif5), | |
2371 | SH_PFC_FUNCTION(scif_clk), | |
bf8d2dab MV |
2372 | SH_PFC_FUNCTION(ssi), |
2373 | SH_PFC_FUNCTION(usb0), | |
2374 | SH_PFC_FUNCTION(vin4), | |
a59e6976 MV |
2375 | }; |
2376 | ||
2377 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | |
2378 | #define F_(x, y) FN_##y | |
2379 | #define FM(x) FN_##x | |
2380 | { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { | |
2381 | 0, 0, | |
2382 | 0, 0, | |
2383 | 0, 0, | |
2384 | 0, 0, | |
2385 | 0, 0, | |
2386 | 0, 0, | |
2387 | 0, 0, | |
2388 | 0, 0, | |
2389 | 0, 0, | |
2390 | 0, 0, | |
2391 | 0, 0, | |
2392 | 0, 0, | |
2393 | 0, 0, | |
2394 | 0, 0, | |
2395 | 0, 0, | |
2396 | 0, 0, | |
2397 | 0, 0, | |
2398 | 0, 0, | |
2399 | 0, 0, | |
2400 | 0, 0, | |
2401 | 0, 0, | |
2402 | 0, 0, | |
2403 | 0, 0, | |
2404 | GP_0_8_FN, GPSR0_8, | |
2405 | GP_0_7_FN, GPSR0_7, | |
2406 | GP_0_6_FN, GPSR0_6, | |
2407 | GP_0_5_FN, GPSR0_5, | |
2408 | GP_0_4_FN, GPSR0_4, | |
2409 | GP_0_3_FN, GPSR0_3, | |
2410 | GP_0_2_FN, GPSR0_2, | |
2411 | GP_0_1_FN, GPSR0_1, | |
2412 | GP_0_0_FN, GPSR0_0, } | |
2413 | }, | |
2414 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { | |
2415 | GP_1_31_FN, GPSR1_31, | |
2416 | GP_1_30_FN, GPSR1_30, | |
2417 | GP_1_29_FN, GPSR1_29, | |
2418 | GP_1_28_FN, GPSR1_28, | |
2419 | GP_1_27_FN, GPSR1_27, | |
2420 | GP_1_26_FN, GPSR1_26, | |
2421 | GP_1_25_FN, GPSR1_25, | |
2422 | GP_1_24_FN, GPSR1_24, | |
2423 | GP_1_23_FN, GPSR1_23, | |
2424 | GP_1_22_FN, GPSR1_22, | |
2425 | GP_1_21_FN, GPSR1_21, | |
2426 | GP_1_20_FN, GPSR1_20, | |
2427 | GP_1_19_FN, GPSR1_19, | |
2428 | GP_1_18_FN, GPSR1_18, | |
2429 | GP_1_17_FN, GPSR1_17, | |
2430 | GP_1_16_FN, GPSR1_16, | |
2431 | GP_1_15_FN, GPSR1_15, | |
2432 | GP_1_14_FN, GPSR1_14, | |
2433 | GP_1_13_FN, GPSR1_13, | |
2434 | GP_1_12_FN, GPSR1_12, | |
2435 | GP_1_11_FN, GPSR1_11, | |
2436 | GP_1_10_FN, GPSR1_10, | |
2437 | GP_1_9_FN, GPSR1_9, | |
2438 | GP_1_8_FN, GPSR1_8, | |
2439 | GP_1_7_FN, GPSR1_7, | |
2440 | GP_1_6_FN, GPSR1_6, | |
2441 | GP_1_5_FN, GPSR1_5, | |
2442 | GP_1_4_FN, GPSR1_4, | |
2443 | GP_1_3_FN, GPSR1_3, | |
2444 | GP_1_2_FN, GPSR1_2, | |
2445 | GP_1_1_FN, GPSR1_1, | |
2446 | GP_1_0_FN, GPSR1_0, } | |
2447 | }, | |
2448 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { | |
2449 | GP_2_31_FN, GPSR2_31, | |
2450 | GP_2_30_FN, GPSR2_30, | |
2451 | GP_2_29_FN, GPSR2_29, | |
2452 | GP_2_28_FN, GPSR2_28, | |
2453 | GP_2_27_FN, GPSR2_27, | |
2454 | GP_2_26_FN, GPSR2_26, | |
2455 | GP_2_25_FN, GPSR2_25, | |
2456 | GP_2_24_FN, GPSR2_24, | |
2457 | GP_2_23_FN, GPSR2_23, | |
2458 | GP_2_22_FN, GPSR2_22, | |
2459 | GP_2_21_FN, GPSR2_21, | |
2460 | GP_2_20_FN, GPSR2_20, | |
2461 | GP_2_19_FN, GPSR2_19, | |
2462 | GP_2_18_FN, GPSR2_18, | |
2463 | GP_2_17_FN, GPSR2_17, | |
2464 | GP_2_16_FN, GPSR2_16, | |
2465 | GP_2_15_FN, GPSR2_15, | |
2466 | GP_2_14_FN, GPSR2_14, | |
2467 | GP_2_13_FN, GPSR2_13, | |
2468 | GP_2_12_FN, GPSR2_12, | |
2469 | GP_2_11_FN, GPSR2_11, | |
2470 | GP_2_10_FN, GPSR2_10, | |
2471 | GP_2_9_FN, GPSR2_9, | |
2472 | GP_2_8_FN, GPSR2_8, | |
2473 | GP_2_7_FN, GPSR2_7, | |
2474 | GP_2_6_FN, GPSR2_6, | |
2475 | GP_2_5_FN, GPSR2_5, | |
2476 | GP_2_4_FN, GPSR2_4, | |
2477 | GP_2_3_FN, GPSR2_3, | |
2478 | GP_2_2_FN, GPSR2_2, | |
2479 | GP_2_1_FN, GPSR2_1, | |
2480 | GP_2_0_FN, GPSR2_0, } | |
2481 | }, | |
2482 | { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { | |
2483 | 0, 0, | |
2484 | 0, 0, | |
2485 | 0, 0, | |
2486 | 0, 0, | |
2487 | 0, 0, | |
2488 | 0, 0, | |
2489 | 0, 0, | |
2490 | 0, 0, | |
2491 | 0, 0, | |
2492 | 0, 0, | |
2493 | 0, 0, | |
2494 | 0, 0, | |
2495 | 0, 0, | |
2496 | 0, 0, | |
2497 | 0, 0, | |
2498 | 0, 0, | |
2499 | 0, 0, | |
2500 | 0, 0, | |
2501 | 0, 0, | |
2502 | 0, 0, | |
2503 | 0, 0, | |
2504 | 0, 0, | |
2505 | GP_3_9_FN, GPSR3_9, | |
2506 | GP_3_8_FN, GPSR3_8, | |
2507 | GP_3_7_FN, GPSR3_7, | |
2508 | GP_3_6_FN, GPSR3_6, | |
2509 | GP_3_5_FN, GPSR3_5, | |
2510 | GP_3_4_FN, GPSR3_4, | |
2511 | GP_3_3_FN, GPSR3_3, | |
2512 | GP_3_2_FN, GPSR3_2, | |
2513 | GP_3_1_FN, GPSR3_1, | |
2514 | GP_3_0_FN, GPSR3_0, } | |
2515 | }, | |
2516 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { | |
2517 | GP_4_31_FN, GPSR4_31, | |
2518 | GP_4_30_FN, GPSR4_30, | |
2519 | GP_4_29_FN, GPSR4_29, | |
2520 | GP_4_28_FN, GPSR4_28, | |
2521 | GP_4_27_FN, GPSR4_27, | |
2522 | GP_4_26_FN, GPSR4_26, | |
2523 | GP_4_25_FN, GPSR4_25, | |
2524 | GP_4_24_FN, GPSR4_24, | |
2525 | GP_4_23_FN, GPSR4_23, | |
2526 | GP_4_22_FN, GPSR4_22, | |
2527 | GP_4_21_FN, GPSR4_21, | |
2528 | GP_4_20_FN, GPSR4_20, | |
2529 | GP_4_19_FN, GPSR4_19, | |
2530 | GP_4_18_FN, GPSR4_18, | |
2531 | GP_4_17_FN, GPSR4_17, | |
2532 | GP_4_16_FN, GPSR4_16, | |
2533 | GP_4_15_FN, GPSR4_15, | |
2534 | GP_4_14_FN, GPSR4_14, | |
2535 | GP_4_13_FN, GPSR4_13, | |
2536 | GP_4_12_FN, GPSR4_12, | |
2537 | GP_4_11_FN, GPSR4_11, | |
2538 | GP_4_10_FN, GPSR4_10, | |
2539 | GP_4_9_FN, GPSR4_9, | |
2540 | GP_4_8_FN, GPSR4_8, | |
2541 | GP_4_7_FN, GPSR4_7, | |
2542 | GP_4_6_FN, GPSR4_6, | |
2543 | GP_4_5_FN, GPSR4_5, | |
2544 | GP_4_4_FN, GPSR4_4, | |
2545 | GP_4_3_FN, GPSR4_3, | |
2546 | GP_4_2_FN, GPSR4_2, | |
2547 | GP_4_1_FN, GPSR4_1, | |
2548 | GP_4_0_FN, GPSR4_0, } | |
2549 | }, | |
2550 | { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { | |
2551 | 0, 0, | |
2552 | 0, 0, | |
2553 | 0, 0, | |
2554 | 0, 0, | |
2555 | 0, 0, | |
2556 | 0, 0, | |
2557 | 0, 0, | |
2558 | 0, 0, | |
2559 | 0, 0, | |
2560 | 0, 0, | |
2561 | 0, 0, | |
2562 | GP_5_20_FN, GPSR5_20, | |
2563 | GP_5_19_FN, GPSR5_19, | |
2564 | GP_5_18_FN, GPSR5_18, | |
2565 | GP_5_17_FN, GPSR5_17, | |
2566 | GP_5_16_FN, GPSR5_16, | |
2567 | GP_5_15_FN, GPSR5_15, | |
2568 | GP_5_14_FN, GPSR5_14, | |
2569 | GP_5_13_FN, GPSR5_13, | |
2570 | GP_5_12_FN, GPSR5_12, | |
2571 | GP_5_11_FN, GPSR5_11, | |
2572 | GP_5_10_FN, GPSR5_10, | |
2573 | GP_5_9_FN, GPSR5_9, | |
2574 | GP_5_8_FN, GPSR5_8, | |
2575 | GP_5_7_FN, GPSR5_7, | |
2576 | GP_5_6_FN, GPSR5_6, | |
2577 | GP_5_5_FN, GPSR5_5, | |
2578 | GP_5_4_FN, GPSR5_4, | |
2579 | GP_5_3_FN, GPSR5_3, | |
2580 | GP_5_2_FN, GPSR5_2, | |
2581 | GP_5_1_FN, GPSR5_1, | |
2582 | GP_5_0_FN, GPSR5_0, } | |
2583 | }, | |
2584 | { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { | |
2585 | 0, 0, | |
2586 | 0, 0, | |
2587 | 0, 0, | |
2588 | 0, 0, | |
2589 | 0, 0, | |
2590 | 0, 0, | |
2591 | 0, 0, | |
2592 | 0, 0, | |
2593 | 0, 0, | |
2594 | 0, 0, | |
2595 | 0, 0, | |
2596 | 0, 0, | |
2597 | 0, 0, | |
2598 | 0, 0, | |
2599 | 0, 0, | |
2600 | 0, 0, | |
2601 | 0, 0, | |
2602 | 0, 0, | |
2603 | GP_6_13_FN, GPSR6_13, | |
2604 | GP_6_12_FN, GPSR6_12, | |
2605 | GP_6_11_FN, GPSR6_11, | |
2606 | GP_6_10_FN, GPSR6_10, | |
2607 | GP_6_9_FN, GPSR6_9, | |
2608 | GP_6_8_FN, GPSR6_8, | |
2609 | GP_6_7_FN, GPSR6_7, | |
2610 | GP_6_6_FN, GPSR6_6, | |
2611 | GP_6_5_FN, GPSR6_5, | |
2612 | GP_6_4_FN, GPSR6_4, | |
2613 | GP_6_3_FN, GPSR6_3, | |
2614 | GP_6_2_FN, GPSR6_2, | |
2615 | GP_6_1_FN, GPSR6_1, | |
2616 | GP_6_0_FN, GPSR6_0, } | |
2617 | }, | |
2618 | #undef F_ | |
2619 | #undef FM | |
2620 | ||
2621 | #define F_(x, y) x, | |
2622 | #define FM(x) FN_##x, | |
2623 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { | |
2624 | IP0_31_28 | |
2625 | IP0_27_24 | |
2626 | IP0_23_20 | |
2627 | IP0_19_16 | |
2628 | IP0_15_12 | |
2629 | IP0_11_8 | |
2630 | IP0_7_4 | |
2631 | IP0_3_0 } | |
2632 | }, | |
2633 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { | |
2634 | IP1_31_28 | |
2635 | IP1_27_24 | |
2636 | IP1_23_20 | |
2637 | IP1_19_16 | |
2638 | IP1_15_12 | |
2639 | IP1_11_8 | |
2640 | IP1_7_4 | |
2641 | IP1_3_0 } | |
2642 | }, | |
2643 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { | |
2644 | IP2_31_28 | |
2645 | IP2_27_24 | |
2646 | IP2_23_20 | |
2647 | IP2_19_16 | |
2648 | IP2_15_12 | |
2649 | IP2_11_8 | |
2650 | IP2_7_4 | |
2651 | IP2_3_0 } | |
2652 | }, | |
2653 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { | |
2654 | IP3_31_28 | |
2655 | IP3_27_24 | |
2656 | IP3_23_20 | |
2657 | IP3_19_16 | |
2658 | IP3_15_12 | |
2659 | IP3_11_8 | |
2660 | IP3_7_4 | |
2661 | IP3_3_0 } | |
2662 | }, | |
2663 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { | |
2664 | IP4_31_28 | |
2665 | IP4_27_24 | |
2666 | IP4_23_20 | |
2667 | IP4_19_16 | |
2668 | IP4_15_12 | |
2669 | IP4_11_8 | |
2670 | IP4_7_4 | |
2671 | IP4_3_0 } | |
2672 | }, | |
2673 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { | |
2674 | IP5_31_28 | |
2675 | IP5_27_24 | |
2676 | IP5_23_20 | |
2677 | IP5_19_16 | |
2678 | IP5_15_12 | |
2679 | IP5_11_8 | |
2680 | IP5_7_4 | |
2681 | IP5_3_0 } | |
2682 | }, | |
2683 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { | |
2684 | IP6_31_28 | |
2685 | IP6_27_24 | |
2686 | IP6_23_20 | |
2687 | IP6_19_16 | |
2688 | IP6_15_12 | |
2689 | IP6_11_8 | |
2690 | IP6_7_4 | |
2691 | IP6_3_0 } | |
2692 | }, | |
2693 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { | |
2694 | IP7_31_28 | |
2695 | IP7_27_24 | |
2696 | IP7_23_20 | |
2697 | IP7_19_16 | |
2698 | IP7_15_12 | |
2699 | IP7_11_8 | |
2700 | IP7_7_4 | |
2701 | IP7_3_0 } | |
2702 | }, | |
2703 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { | |
2704 | IP8_31_28 | |
2705 | IP8_27_24 | |
2706 | IP8_23_20 | |
2707 | IP8_19_16 | |
2708 | IP8_15_12 | |
2709 | IP8_11_8 | |
2710 | IP8_7_4 | |
2711 | IP8_3_0 } | |
2712 | }, | |
2713 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { | |
2714 | IP9_31_28 | |
2715 | IP9_27_24 | |
2716 | IP9_23_20 | |
2717 | IP9_19_16 | |
2718 | IP9_15_12 | |
2719 | IP9_11_8 | |
2720 | IP9_7_4 | |
2721 | IP9_3_0 } | |
2722 | }, | |
2723 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { | |
2724 | IP10_31_28 | |
2725 | IP10_27_24 | |
2726 | IP10_23_20 | |
2727 | IP10_19_16 | |
2728 | IP10_15_12 | |
2729 | IP10_11_8 | |
2730 | IP10_7_4 | |
2731 | IP10_3_0 } | |
2732 | }, | |
2733 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { | |
2734 | IP11_31_28 | |
2735 | IP11_27_24 | |
2736 | IP11_23_20 | |
2737 | IP11_19_16 | |
2738 | IP11_15_12 | |
2739 | IP11_11_8 | |
2740 | IP11_7_4 | |
2741 | IP11_3_0 } | |
2742 | }, | |
2743 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { | |
2744 | IP12_31_28 | |
2745 | IP12_27_24 | |
2746 | IP12_23_20 | |
2747 | IP12_19_16 | |
2748 | IP12_15_12 | |
2749 | IP12_11_8 | |
2750 | IP12_7_4 | |
2751 | IP12_3_0 } | |
2752 | }, | |
2753 | { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { | |
2754 | /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2755 | /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2756 | /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2757 | /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2758 | /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2759 | /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2760 | IP13_7_4 | |
2761 | IP13_3_0 } | |
2762 | }, | |
2763 | #undef F_ | |
2764 | #undef FM | |
2765 | ||
2766 | #define F_(x, y) x, | |
2767 | #define FM(x) FN_##x, | |
2768 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, | |
2769 | 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, | |
2770 | 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { | |
2771 | /* RESERVED 31 */ | |
2772 | 0, 0, | |
2773 | MOD_SEL0_30 | |
2774 | MOD_SEL0_29 | |
2775 | MOD_SEL0_28 | |
2776 | MOD_SEL0_27 | |
2777 | MOD_SEL0_26 | |
2778 | MOD_SEL0_25 | |
2779 | MOD_SEL0_24_23 | |
2780 | MOD_SEL0_22_21 | |
2781 | MOD_SEL0_20_19 | |
2782 | MOD_SEL0_18_17 | |
2783 | /* RESERVED 16 */ | |
2784 | 0, 0, | |
2785 | MOD_SEL0_15 | |
2786 | MOD_SEL0_14 | |
2787 | MOD_SEL0_13 | |
2788 | MOD_SEL0_12 | |
2789 | MOD_SEL0_11 | |
2790 | MOD_SEL0_10 | |
2791 | /* RESERVED 9, 8, 7, 6 */ | |
2792 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2793 | MOD_SEL0_5 | |
2794 | MOD_SEL0_4 | |
2795 | MOD_SEL0_3 | |
2796 | MOD_SEL0_2 | |
2797 | MOD_SEL0_1 | |
2798 | MOD_SEL0_0 } | |
2799 | }, | |
2800 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, | |
2801 | 1, 1, 1, 1, 1, 1, 2, 4, 4, | |
2802 | 4, 4, 4, 4) { | |
2803 | MOD_SEL1_31 | |
2804 | MOD_SEL1_30 | |
2805 | MOD_SEL1_29 | |
2806 | MOD_SEL1_28 | |
2807 | MOD_SEL1_27 | |
2808 | MOD_SEL1_26 | |
2809 | /* RESERVED 25, 24 */ | |
2810 | 0, 0, 0, 0, | |
2811 | /* RESERVED 23, 22, 21, 20 */ | |
2812 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2813 | /* RESERVED 19, 18, 17, 16 */ | |
2814 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2815 | /* RESERVED 15, 14, 13, 12 */ | |
2816 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2817 | /* RESERVED 11, 10, 9, 8 */ | |
2818 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2819 | /* RESERVED 7, 6, 5, 4 */ | |
2820 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2821 | /* RESERVED 3, 2, 1, 0 */ | |
2822 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } | |
2823 | }, | |
2824 | { }, | |
2825 | }; | |
2826 | ||
2827 | static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) | |
2828 | { | |
2829 | int bit = -EINVAL; | |
2830 | ||
2831 | *pocctrl = 0xe6060380; | |
2832 | ||
2833 | if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) | |
2834 | bit = 29 - (pin - RCAR_GP_PIN(3, 0)); | |
2835 | ||
2836 | return bit; | |
2837 | } | |
2838 | ||
2839 | static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { | |
2840 | .pin_to_pocctrl = r8a77995_pin_to_pocctrl, | |
2841 | }; | |
2842 | ||
2843 | const struct sh_pfc_soc_info r8a77995_pinmux_info = { | |
2844 | .name = "r8a77995_pfc", | |
2845 | .ops = &r8a77995_pinmux_ops, | |
2846 | .unlock_reg = 0xe6060000, /* PMMR */ | |
2847 | ||
2848 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
2849 | ||
2850 | .pins = pinmux_pins, | |
2851 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
2852 | .groups = pinmux_groups, | |
2853 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
2854 | .functions = pinmux_functions, | |
2855 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
2856 | ||
2857 | .cfg_regs = pinmux_config_regs, | |
2858 | ||
2859 | .pinmux_data = pinmux_data, | |
2860 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
2861 | }; |